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| user?s manual all information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by renesas electronics corp. without notice. please review the latest information published by renesas electronics corp. through various m eans, including the renesas electronics corp. website (http://www.renesas.com). v850es/jh3-e, v850es/jj3-e user?s manual: hardware rev.3.00 sep, 2011 32 renesas mcu v850es/jx3-e microcontrollers www.renesas.com v850es/jh3-e v850es/jh3-h pd70f3778 pd70f3784 pd70f3779 pd70f3785 pd70f3780 pd70f3786 pd70f3781 pd70f3782 pd70f3783
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 how to use this manual readers this manual is intended for users who wish to understand the functions of the v850es/jh3-e and v850es/jj3-e and des ign application systems using the v850es/jh3-e and v850es/jj3-e. purpose this manual is intended to give users an understanding of the hardwar e functions of the v850es/jh3-e and v850es/jj3-e shown in the organization below. organization the manual of these products is divided into two volumes: hardware (this volume) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the overall functions of the v850es/jh3-e and v850es/jj3-e read this manual according to the contents . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. to know the electrical specificati ons of the v850es/jh3-e and v850es/jj3-e refer to the chapter 35 electrical specifications . the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx.yyy? is described as is in a program, however, the compiler/assembler cannot recognize it correctly. the mark conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/jh3-e and v850es/jj3-e document name document no. v850es architecture user?s manual u15943e v850es/jh3-e, v850es/jj3-e hardware user?s manual this manual documents related to development tools document name document no. qb-v850esjx3e in-circuit emulator u19170e qb-v850mini on-chip debug emulator u17638e qb-mini2 on-chip debug emulator with programming function u18371e operation u18512e c language u18513e assembly language u18514e ca850 ver. 3.20 c compiler package link directives u18515e pm+ ver. 6.30 project manager u18416e id850qb ver. 3.40 integrated debugger operation u18604e sm850 ver. 2.50 system simulator operation u16218e sm850 ver. 2.00 or later system si mulator external part user open interface specification u14873e operation u18601e sm+ system simulator user open interface u18212e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 real-time os task debugger u17420e basics u18165e installation u17421e rx850 pro ver. 3.21 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp5 flash memory programmer u18865e caution: this product uses superflash ? technology licensed from silicon storage technology, inc. eeprom is a trademark of re nesas electronics corporation. iecube is a registered trademark of renesas electronics corporation in japan and germany. minicube is a registered trademark of renesas electronics corporation in jap an and germany or a trademark in the united states of america. windows and windows nt are either regist ered trademarks or trademarks of mi crosoft corporation in the united states and/or other countries. superflash is a registered trademark of silicon stor age technology, inc. in sever al countries, including the united states and japan. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. tron is an abbreviation of the r eal-time operating system nucleus. itron is an abbreviati on of industrial tron. contents chapter 1 introduction ...................................................................................................... ........... 24 1.1 general ........................................................................................................................ .............. 24 1.2 features ....................................................................................................................... ............. 27 1.3 application fields ............................................................................................................. ....... 29 1.4 ordering information ........................................................................................................... .... 29 1.5 pin configuration (top view).................................................................................................. 3 0 1.6 function block configurat ion................................................................................................. 33 1.6.1 internal bl ock di agram ......................................................................................................... ............33 1.6.2 internal units ................................................................................................................. ..................35 chapter 2 pin functio ns .................................................................................................... ........... 38 2.1 list of pin functions.......................................................................................................... ...... 38 2.2 pin states ..................................................................................................................... ............. 51 2.3 pin i/o circuit types, i/o buffer power supplies and connection of unused pins.......... 52 2.4 cautions ....................................................................................................................... ............. 57 chapter 3 cpu functio n ..................................................................................................... ........... 58 3.1 features ....................................................................................................................... ............. 58 3.2 cpu register set............................................................................................................... ....... 59 3.2.1 program regi ster set ........................................................................................................... ............60 3.2.2 system regi ster set ............................................................................................................ .............61 3.3 operation modes ................................................................................................................ ...... 67 3.3.1 specifying oper ation mode...................................................................................................... ........67 3.4 address space .................................................................................................................. ....... 68 3.4.1 cpu address space .............................................................................................................. ..........68 3.4.2 wraparound of cpu addr ess space ...............................................................................................6 9 3.4.3 memory map ..................................................................................................................... ..............70 3.4.4 areas .......................................................................................................................... ....................73 3.4.5 recommended use of address s pace.............................................................................................78 3.4.6 peripheral i/o regist ers ....................................................................................................... ............81 3.4.7 programmable peripher al i/o regi sters .......................................................................................... .99 3.4.8 special r egister s .............................................................................................................. .............100 3.4.9 cauti ons....................................................................................................................... .................104 chapter 4 port functio ns ................................................................................................... ...... 109 4.1 features ....................................................................................................................... ........... 109 4.2 basic port configuration....................................................................................................... 109 4.3 port configuration ............................................................. ................................................ .... 111 4.3.1 port 0 ......................................................................................................................... ...................117 4.3.2 port 2 ......................................................................................................................... ...................120 4.3.3 port 3 ......................................................................................................................... ...................127 4.3.4 port 4 ......................................................................................................................... ...................132 4.3.5 port 5 ......................................................................................................................... ...................141 4.3.6 port 7 ......................................................................................................................... ...................148 4.3.7 port 9 ......................................................................................................................... ...................151 4.3.8 port cm........................................................................................................................ .................160 4.3.9 port cs ........................................................................................................................ .................163 4.3.10 port ct ........................................................................................................................ .................166 4.3.11 port dh ........................................................................................................................ .................168 4.3.12 port dl........................................................................................................................ ..................175 4.4 port register settings when alternate function is used.................................................. 177 4.5 cautions ....................................................................................................................... ........... 191 4.5.1 cautions on se tting port pins.................................................................................................. .......191 .5.2 cautions on bit manipulation instru ction for port n r egister (pn) ....................................................194 4.5.3 cautions on on-chip debug pi ns (v850es/jh 3-e onl y).................................................................195 4.5.4 cautions on p54/in tp11/drst pin..............................................................................................19 5 4.5.5 cautions on p51 pin when power is tu rned on ..............................................................................195 4.5.6 hysteresis char acterist ics ..................................................................................................... ........195 chapter 5 bus control function ............................ .............................................................. 19 6 5.1 features ....................................................................................................................... ........... 196 5.2 bus control pins ............................................................................................................... ..... 197 5.2.1 pin status when internal rom, internal ra m, or on-chip peripher al i/o is a ccessed ....................198 5.2.2 pin status in eac h operati on m ode.............................................................................................. ..198 5.3 memory block function ........................................................................................................ 19 9 5.4 bus access ..................................................................................................................... ........ 200 5.4.1 number of clo cks for a ccess .................................................................................................... .....200 5.4.2 bus size setti ng func tion ...................................................................................................... .........200 5.4.3 access by bus si ze ............................................................................................................. ..........201 5.5 wait function.................................................................................................................. ........ 208 5.5.1 programmable wa it func tion..................................................................................................... .....208 5.5.2 external wait func tion......................................................................................................... ...........209 5.5.3 relationship between programmabl e wait and exte rnal wa it.........................................................210 5.5.4 programmable address wait func tion ............................................................................................2 11 5.6 idle state insertion func tion................................................................................................. 2 12 5.7 bus hold function .............................................................................................................. ... 213 5.7.1 functional outlin e............................................................................................................. .............213 5.7.2 bus hold pr ocedur e............................................................................................................. ..........214 5.7.3 operation in pow er save mode ................................................................................................... ..214 5.8 bus priority ................................................................................................................... .......... 215 5.9 bus timing..................................................................................................................... ......... 216 chapter 6 clock generation function ................ .............................................................. 219 6.1 overview ....................................................................................................................... .......... 219 6.2 configuration.................................................................................................................. ........ 220 6.3 registers ...................................................................................................................... ........... 222 6.4 operation ...................................................................................................................... .......... 227 6.4.1 operation of each cl ock ........................................................................................................ ........227 6.4.2 clock output functi on .......................................................................................................... ..........227 6.5 pll function ................................................................................................................... ....... 228 6.5.1 overvi ew ....................................................................................................................... ................228 6.5.2 regist ers...................................................................................................................... .................228 6.5.3 usage .......................................................................................................................... .................231 chapter 7 16-bit timer/event counter aa (taa) .............................................................. 232 7.1 overview ....................................................................................................................... .......... 232 7.2 functions ...................................................................................................................... .......... 232 7.3 configuration.................................................................................................................. ........ 233 7.3.1 pin confi guratio n .............................................................................................................. .............235 7.4 registers ...................................................................................................................... ........... 236 7.5 operation ...................................................................................................................... .......... 253 7.5.1 interval timer mode (taanmd2 to taanmd0 bi ts = 000) ............................................................. 259 7.5.2 external event count mode (taan md2 to taanmd0 bits = 001).................................................. 269 7.5.3 external trigger pulse output mode (taanmd2 to taanmd 0 bits = 010) .....................................277 7.5.4 one-shot pulse output mode (taan md2 to taanmd0 bits = 011) ............................................... 289 7.5.5 pwm output mode (taanmd2 to taanmd0 bi ts = 100) .............................................................. 296 7.5.6 free-running timer mode (taanmd2 to taanmd0 bi ts = 101)..................................................... 305 7.5.7 pulse width measurement mode (taan md2 to taanmd0 bits = 110) ......................................... 322 7.5.8 timer output operati ons ........................................................................................................ ........327 7.6 timer-tuned operation function .................................. ....................................................... 328 7.6.1 free-running timer mode (dur ing timer-tuned operati on) .............................................................. 330 7.6.2 pwm output mode (during timer-tuned oper ation) ........................................................................337 7.7 simultaneous-start func tion ................................................................................................ 339 7.7.1 pwm output mode (simult aneous-start oper ation) ........................................................................340 7.8 cascade connection............................................................................................................. . 342 7.9 selector function .............................................................................................................. ..... 347 7.10 cautions ....................................................................................................................... ........... 348 chapter 8 16-bit timer/event counter ab (tab) .............................................................. 349 8.1 overview ....................................................................................................................... .......... 349 8.2 functions ...................................................................................................................... .......... 349 8.3 configuration.................................................................................................................. ........ 350 8.4 registers ...................................................................................................................... ........... 353 8.5 operation ...................................................................................................................... .......... 370 8.5.1 interval timer mode (tabnmd2 to tabnmd0 bi ts = 000) ............................................................. 371 8.5.2 external event count mode (tabn md2 to tabnmd0 bits = 001).................................................. 380 8.5.3 external trigger pulse output mode (tabnmd2 to tabnmd 0 bits = 010) .....................................389 8.5.4 one-shot pulse output mode (tabn md2 to tabnmd0 bits = 011) ............................................... 402 8.5.5 pwm output mode (tabnmd2 to tabnmd0 bi ts = 100) .............................................................. 411 8.5.6 free-running timer mode (tabnmd2 to tabnmd0 bi ts = 101)..................................................... 422 8.5.7 pulse width measurement mode (tabn md2 to tabnmd0 bits = 110) ......................................... 442 8.5.8 triangular wave pwm mode (tabnmd 2 to tabnmd0 bits = 111) ............................................... 448 8.5.9 timer output operati ons ........................................................................................................ ........450 8.6 timer-tuned operation function/simultaneous-start function ...................................... 451 8.7 cautions ....................................................................................................................... ........... 452 chapter 9 16-bit timer/event counter t (tmt) ................................................................. 453 9.1 overview ....................................................................................................................... .......... 453 9.2 functions ...................................................................................................................... .......... 453 9.3 configuration.................................................................................................................. ........ 454 9.3.1 pin confi guratio n .............................................................................................................. .............457 9.4 registers ...................................................................................................................... ........... 458 9.5 timer output operat ions....................................................................................................... 4 79 9.6 operation ...................................................................................................................... .......... 480 9.6.1 interval timer mode (tt0md 3 to tt0md0 bi ts = 0000) .................................................................488 9.6.2 external event count mode (tt0 md3 to tt0md0 bits = 0001) .....................................................498 9.6.3 external trigger pulse output mode (tt0md3 to tt0md 0 bits = 0010) .........................................508 9.6.4 one-shot pulse output mode (tt0 md3 to tt0md0 bits = 0011) ..................................................521 9.6.5 pwm output mode (tt0md3 to tt0md0 bits = 0100) ..................................................................528 9.6.6 free-running timer mode (tt0md 3 to tt0md0 bi ts = 0101) ........................................................537 9.6.7 pulse width measurement mode ( tt0md3 to tt0md0 bits = 0110) ............................................553 9.6.8 triangular-wave pwm output mode ( tt0md3 to tt0md0 bits = 0111) .......................................559 9.6.9 encoder count func tion ......................................................................................................... ........561 9.6.10 encoder compare mode (tt0md 3 to tt0md0 bi ts = 1000) .........................................................577 chapter 10 16-bit interval timer m (tmm) ......... ................................................................. 585 10.1 overview ....................................................................................................................... .......... 585 10.2 configuration.................................................................................................................. ........ 586 10.3 registers ...................................................................................................................... ........... 588 10.4 operation ...................................................................................................................... .......... 590 10.4.1 interval ti mer m ode ............................................................................................................ ...........590 10.4.2 cauti ons....................................................................................................................... .................594 chapter 11 motor control function .................... .............................................................. 595 11.1 functional overview ............................................................................................................ .. 595 11.2 configuration.................................................................................................................. ........ 596 11.3 control registers .............................................................................................................. ..... 600 11.4 operation ...................................................................................................................... .......... 610 11.4.1 system outlin e ................................................................................................................. .............610 11.4.2 dead-time control (generation of negative-phase wa ve signal ).....................................................615 11.4.3 interrupt culli ng func tion ..................................................................................................... ...........622 11.4.4 operation to rewrite regist er with transfe r functi on........................................................................ 629 11.4.5 taa4 tuning operation for a/d conver sion start trigger signal output ............................................647 11.4.6 a/d conversion start tri gger output f unction ..................................................................................6 50 chapter 12 real-time counter............................................................................................... .. 655 12.1 functions ...................................................................................................................... .......... 655 12.2 configuration.................................................................................................................. ........ 656 12.2.1 pin confi guratio n .............................................................................................................. .............658 12.2.2 interrupt functi ons ............................................................................................................ .............658 12.3 registers ...................................................................................................................... ........... 659 12.4 operation ...................................................................................................................... .......... 674 12.4.1 initial setti ngs ............................................................................................................... .................674 12.4.2 rewriting each counter dur ing clock oper ation .............................................................................675 12.4.3 reading each counter duri ng clock oper ation ...............................................................................676 12.4.4 changing intrtc0 interrupt setti ng during clock operatio n .........................................................677 12.4.5 changing intrtc1 interrupt setti ng during clock operatio n .........................................................678 12.4.6 initial intrtc2 in terrupt settings ............................................................................................. .....679 12.4.7 changing intrtc2 interrupt setti ng during clock operatio n .........................................................680 12.4.8 initializing real -time c ounter ................................................................................................. .........681 12.4.9 watch error correction exampl e of real-tim e count er .................................................................... 682 chapter 13 functions of watchdog timer 2 .. ................................................................. 686 13.1 functions ...................................................................................................................... .......... 686 13.2 configuration.................................................................................................................. ........ 687 13.3 registers ...................................................................................................................... ........... 688 13.4 operation ...................................................................................................................... .......... 690 chapter 14 real-time output function (rto).. ................................................................. 691 14.1 function ....................................................................................................................... ........... 691 14.2 configuration.................................................................................................................. ........ 692 14.3 registers ...................................................................................................................... ........... 694 14.4 operation ...................................................................................................................... .......... 696 14.5 usage.......................................................................................................................... ............. 697 14.6 cautions ....................................................................................................................... ........... 697 chapter 15 a/d converter ................................................................................................... ...... 698 15.1 overview ....................................................................................................................... .......... 698 15.2 functions ...................................................................................................................... .......... 698 15.3 configuration.................................................................................................................. ........ 699 15.4 registers ...................................................................................................................... ........... 702 15.5 operation ...................................................................................................................... .......... 713 15.5.1 basic oper ation ................................................................................................................ .............713 15.5.2 conversion operat ion ti ming .................................................................................................... .....714 15.5.3 trigger mode................................................................................................................... ..............715 15.5.4 operati on m ode ................................................................................................................. ...........717 15.5.5 power-fail co mpare mode ........................................................................................................ .....721 15.6 cautions ....................................................................................................................... ........... 726 15.7 how to read a/d converter characteristics table . ........................................................... 730 chapter 16 asynchronous serial interface b with fifo (uartbn) ..................... 734 16.1 features ....................................................................................................................... ........... 734 16.2 configuration.................................................................................................................. ........ 735 16.3 switching between uartb and other serial inte rface modes ......................................... 739 16.3.1 using uartb0 and csif4 at the same time ................................................................................739 16.3.2 switching between uart b1 and csif 3 mode .............................................................................741 16.4 control registers .............................................................................................................. ..... 742 16.5 interrupt request signals .................................................... ................................................. 7 58 16.6 control modes .................................................................................................................. ...... 761 16.7 operation ...................................................................................................................... .......... 765 16.7.1 data fo rmat .................................................................................................................... ...............765 16.7.2 transmit oper ation ............................................................................................................. ...........766 16.7.3 continuous transmi ssion operat ion .............................................................................................. .769 16.7.4 receive oper ation .............................................................................................................. ...........770 16.7.5 reception error ................................................................................................................ .............773 16.7.6 parity types and corre sponding operat ion.....................................................................................77 4 16.7.7 receive data noi se f ilter ...................................................................................................... ..........775 16.8 dedicated baud rate generator (brg) ..................... .......................................................... 776 16.9 control flow ................................................................................................................... ........ 782 16.10 cautions....................................................................................................................... ........ 793 chapter 17 asynchronous serial interface c (uartc) ............................................. 795 17.1 features ....................................................................................................................... ........... 795 17.2 configuration.................................................................................................................. ........ 796 17.3 mode switching between uartc and other serial interfaces ......................................... 798 17.3.1 mode switching between uartc0 and csif2 .............................................................................798 17.3.2 mode switching between uartc1, csif1 and i 2 c00 ...................................................................799 17.3.3 mode switching between uartc2, i 2 c02, and can0 ...................................................................800 17.3.4 mode switching between uartc3, csif0, and i 2 c01 ..................................................................801 17.3.5 mode switching between uartc4 and csie0 .............................................................................802 17.3.6 mode switching between uartc5, csie1 and i 2 c03 ...................................................................803 17.3.7 mode switching between uartc6 and csif5 .............................................................................804 17.3.8 mode switching between uartc7 and csif6 .............................................................................805 17.4 registers ...................................................................................................................... ........... 806 17.5 interrupt request signals .................................................... ................................................. 8 16 17.6 operation ...................................................................................................................... .......... 817 17.6.1 data fo rmat .................................................................................................................... ...............817 17.6.2 sbf transmission/re ception format .............................................................................................. .819 17.6.3 sbf trans missi on............................................................................................................... ...........821 17.6.4 sbf rec eptio n .................................................................................................................. .............822 17.6.5 uart trans missi on .............................................................................................................. .........823 17.6.6 continuous transmi ssion proc edure.............................................................................................. 824 17.6.7 uart rec eptio n ................................................................................................................. ...........826 17.6.8 reception errors ............................................................................................................... ............828 17.6.9 parity types and operat ions.................................................................................................... .......830 17.6.10 receive data noi se f ilter ...................................................................................................... ........831 17.7 dedicated baud rate generator................................ ........................................................... 832 17.8 cautions ....................................................................................................................... ........... 840 chapter 18 clocked serial interface e with fifo (csie) ......................................... 841 18.1 port setting of csie0 and csie1 .......................................................................................... 841 18.1.1 v850es/jh 3-e................................................................................................................... ...........841 18.1.2 v850es/ jj3-e................................................................................................................... ............842 18.2 features ....................................................................................................................... ........... 843 18.3 configuration.................................................................................................................. ........ 844 18.4 control registers .............................................................................................................. ..... 848 18.5 baud rate generator n (brgn) ............................................................................................ 858 18.6 operation ...................................................................................................................... .......... 860 18.7 how to use..................................................................................................................... ......... 881 18.8 cautions ....................................................................................................................... ........... 888 chapter 19 clocked serial interface f (csif) ............................................................... 889 19.1 features ....................................................................................................................... ........... 889 19.2 configuration.................................................................................................................. ........ 890 19.3 mode switching between csif and other serial interfaces.............................................. 891 19.3.1 switching between csif0, uartc3, and i 2 c01 m ode ................................................................. 891 19.3.2 mode switching between csif1, uartc1, and i 2 c00 ..................................................................892 19.3.3 mode switching between csif2 and ua rtc0 .............................................................................893 19.3.4 mode switching between csif3 and ua rtb1 ..............................................................................894 19.3.5 using csif4 and uartb0 at the same time ................................................................................895 19.3.6 mode switching between csif5 and ua rtc6 .............................................................................897 19.3.7 mode switching between csif6 and ua rtc7 .............................................................................898 19.4 registers ...................................................................................................................... ........... 899 19.5 interrupt request signals .................................................... ................................................. 9 08 19.6 operation ...................................................................................................................... .......... 909 19.6.1 single transfer mode (master mode, transmi ssion m ode)............................................................. 909 19.6.2 single transfer mode (master mode, recept ion m ode) .................................................................. 911 19.6.3 single transfer mode (master mode, transmission/rec eption m ode) ............................................. 913 19.6.4 single transfer mode (slave mode, transmi ssion m ode) ............................................................... 915 19.6.5 single transfer mode (slave mode, recept ion m ode) .....................................................................917 19.6.6 single transfer mode (slave mode, transmission/rec eption m ode)................................................ 919 19.6.7 continuous transfer mode (master mode, transmi ssion m ode)..................................................... 921 19.6.8 continuous transfer mode (master mode, recept ion m ode) .......................................................... 923 19.6.9 continuous transfer mode (master m ode, transmission/re ception mode) .....................................926 19.6.10 continuous transfer mode (s lave mode, trans mission m ode)..................................................... 930 19.6.11 continuous transfer mode (s lave mode, rec eption m ode) .......................................................... 932 19.6.12 continuous transfer mode (slave mode, transmission/re ception mode) .....................................935 19.6.13 recept ion e rror........................................................................................................ ...................939 19.6.14 clock timi ng........................................................................................................... .....................940 19.7 output pins .................................................................................................................... ......... 942 19.8 baud rate generator ............................................................................................................ . 943 19.8.1 baud rate generatio n ........................................................................................................... .........944 19.9 cautions ....................................................................................................................... ........... 945 chapter 20 i 2 c bus ......................................................................................................................... . 946 20.1 features ....................................................................................................................... ........... 946 20.2 configuration.................................................................................................................. ........ 947 20.3 mode switching of i 2 c bus and other serial interfaces...... ............................................... 951 20.3.1 mode switching between i 2 c00, csif1, and uart c1 ..................................................................951 20.3.2 mode switching between i 2 c01, csif0, and uart c3 ..................................................................952 20.3.3 mode switching between i 2 c02, uartc2 , and ca n0...................................................................953 20.3.4 mode switching between i 2 c03, csie1, and uart c5..................................................................954 20.4 registers ...................................................................................................................... ........... 955 20.5 i 2 c bus mode functions ........................................................................................................ 970 20.5.1 pin confi guratio n .............................................................................................................. .............970 20.6 i 2 c bus definitions and control methods .................. .......................................................... 971 20.6.1 start c onditi on ................................................................................................................ ...............972 20.6.2 addre sses ...................................................................................................................... ...............973 20.6.3 transfer direction specific ation ............................................................................................... ......974 20.6.4 ack ............................................................................................................................ ..................975 20.6.5 stop condi tion ................................................................................................................. ..............976 20.6.6 wait state..................................................................................................................... .................977 20.6.7 wait state canc ellation method ................................................................................................. ....979 20.7 i 2 c interrupt request signals (intiicn)..................... ........................................................... 980 20.7.1 master devic e operat ion........................................................................................................ ........980 20.7.2 slave device operation (when receiving sl ave address data (addr ess matc h)) .............................983 20.7.3 slave device operation (when re ceiving extens ion c ode).............................................................. 987 20.7.4 operation without communica tion................................................................................................ .990 20.7.5 arbitration loss operation (operation as slave after arbi tration loss) ..............................................991 20.7.6 operation when arbitration loss occurs ( no communication after arbitrati on loss) ........................993 20.8 interrupt request signal (intiicn) generation timing and wait control ...................... 1000 20.9 address match detection method .. .................................................................................... 1002 20.10 error detection.......................................................................................................... ........ 1002 20.11 extension code........................................................................................................... ...... 1002 20.12 arbitration.............................................................................................................. ............ 1003 20.13 wakeup function .......................................................................................................... .... 1004 20.14 communication reservation ................................... ........................................................ 1005 20.14.1 when communication reservation function is enabled (iicfn.iicr svn bit = 0)........................1005 20.14.2 when communication reservation function is disabled (iicfn.ii crsvn bit = 1) .......................1009 20.15 cautions................................................................................................................. ............ 1010 20.16 communication operat ions............................................................................................. 1011 20.16.1 master operation in single mast er system ............................................................................... .1012 20.16.2 master operation in multimas ter syst em................................................................................. ..1013 20.16.3 slave operatio n ........................................................................................................ ................1016 20.17 timing of data communication.............................. ......................................................... 1020 chapter 21 can controller .................................................................................................. . 1027 21.1 overview ....................................................................................................................... ........ 1027 21.1.1 featur es....................................................................................................................... ...............1027 21.1.2 overview of func tions .......................................................................................................... ........1028 21.1.3 configur ation.................................................................................................................. .............1029 21.2 can protocol ................................................................................................................... ..... 1030 21.2.1 frame fo rmat ................................................................................................................... ...........1030 21.2.2 frame types .................................................................................................................... ............1031 21.2.3 data frame and re mote frame .................................................................................................... .1031 21.2.4 error fr ame.................................................................................................................... ..............1039 21.2.5 overload frame ................................................................................................................. ..........1040 21.3 functions ...................................................................................................................... ........ 1041 21.3.1 determining bus prio rity ....................................................................................................... .......1041 21.3.2 bit stu ffing ................................................................................................................... ................1041 21.3.3 multi ma sters.................................................................................................................. .............1041 21.3.4 multi cast..................................................................................................................... ................1041 21.3.5 can sleep mode/can st op mode func tion .................................................................................1042 21.3.6 error contro l func tion......................................................................................................... ..........1042 21.3.7 baud rate cont rol func tion ..................................................................................................... ......1049 21.4 connection with target system .. ....................................................................................... 1053 21.5 internal registers of can contro ller ................................................................................. 1054 21.5.1 can controller c onfigurat ion ................................................................................................... ....1054 21.5.2 register a ccess ty pe........................................................................................................... ........1055 21.5.3 register bit c onfigurat ion ..................................................................................................... .......1072 21.6 registers ...................................................................................................................... ......... 1076 21.7 bit set/clear function......................................................................................................... . 1112 21.8 can controller initializat ion ............................................................................................... 111 4 21.8.1 initialization of can m odule ................................................................................................... .....1114 21.8.2 initialization of message buffer............................................................................................... .....1114 21.8.3 redefinition of message bu ffer ................................................................................................. ..1114 21.8.4 transition from initializati on mode to operat ion m ode ................................................................. 1115 21.8.5 resetting error counter c0 erc of can module .........................................................................1116 21.9 message reception.............................................................................................................. 1117 21.9.1 message rec eptio n.............................................................................................................. ........1117 21.9.2 reading recept ion dat a ......................................................................................................... ......1118 21.9.3 receive history list func tion.................................................................................................. .......1119 21.9.4 mask func tion.................................................................................................................. ............1121 21.9.5 multi buffer receiv e block f uncti on............................................................................................ ...1123 21.9.6 remote frame recept ion......................................................................................................... .....1124 21.10 message transmission .................................................................................................... 1 125 21.10.1 message trans missi on ........................................................................................................... ..1125 21.10.2 transmit history list func tion................................................................................................. ....1127 21.10.3 automatic block tr ansmission ( abt) ........................................................................................1129 21.10.4 transmission abor t proc ess ..................................................................................................... 1131 21.10.5 remote frame transmissi on .....................................................................................................1 132 21.11 power saving modes ....................................................................................................... . 1133 21.11.1 can sleep m ode......................................................................................................... .............1133 21.11.2 can stop m ode.......................................................................................................... ..............1135 21.11.3 example of usi ng power sa ving m odes.................................................................................... 1136 21.12 interrupt function ....................................................................................................... ...... 1137 21.13 diagnosis functions and special operational modes.................................................. 1138 21.13.1 receiv e-only mode ...................................................................................................... ............1138 21.13.2 single- shot mode ....................................................................................................... ..............1139 21.13.3 self-t est m ode......................................................................................................... .................1140 21.13.4 transmission/reception operat ion in each oper ation m ode ...................................................... 1141 21.14 time stamp function ...................................................................................................... . 1142 21.14.1 time st amp func tion.................................................................................................... .............1142 21.15 baud rate settings ....................................................................................................... .... 1144 21.15.1 bit rate setting c onditi ons ............................................................................................ .............1144 21.15.2 representativ e examples of baud rate se ttings .......................................................................114 8 21.16 operation of can controller .................................. ......................................................... 115 2 chapter 22 usb function controller (usbf) . ............................................................... 1178 22.1 overview ....................................................................................................................... ........ 1178 22.2 configuration.................................................................................................................. ...... 1179 22.2.1 block di agram .................................................................................................................. ...........1179 22.2.2 usb memory map................................................................................................................. ......1180 22.3 external circuit configuratio n ............................................................................................ 1181 22.3.1 outline ........................................................................................................................ ................1181 22.3.2 connection conf igurat ion ....................................................................................................... .....1182 22.4 cautions ....................................................................................................................... ......... 1184 22.5 requests ....................................................................................................................... ........ 1185 22.5.1 automatic reques ts ............................................................................................................. ........1185 22.5.2 other r equests ................................................................................................................. ...........1192 22.6 register configuration ...................................................... .................................................. 1 193 22.6.1 usb control regist ers .......................................................................................................... ........1193 22.6.2 usb function controlle r register list .......................................................................................... ...1194 22.6.3 epc control regist ers .......................................................................................................... ........1210 22.6.4 data hold r egister s............................................................................................................ ..........1262 22.6.5 epc request data regist ers ..................................................................................................... ....1285 22.6.6 bridge r egist er................................................................................................................ .............1300 22.6.7 dma regi ster ................................................................................................................... ............1304 22.6.8 peripheral contro l regist ers ................................................................................................... ......1308 22.7 stall handshake or no handshake......................... ........................................................ 1312 22.8 register values in specific status ......................... ............................................................ 1313 22.9 fw processing .................................................................................................................. ... 1315 22.9.1 initialization proce ssing ...................................................................................................... .........1317 22.9.2 interrupt se rvicin g ............................................................................................................ ...........1320 22.9.3 usb main pr ocessi ng ............................................................................................................ .....1321 22.9.4 suspend/resume processi ng .....................................................................................................1 347 22.9.5 processing after pow er applic ation ............................................................................................. 1350 22.9.6 receiving data for bulk trans fer (out) in dma m ode ................................................................. 1353 22.9.7 transmitting data for bulk trans fer (in) in dma m ode................................................................. 1358 chapter 23 ethernet controller............................ ............................................................ 1363 23.1 general ........................................................................................................................ .......... 1363 23.1.1 functi ons ...................................................................................................................... ..............1363 23.2 configuration.................................................................................................................. ...... 1364 23.2.1 system conf igurat ion ........................................................................................................... .......1364 23.2.2 interrupt reques ts............................................................................................................. ...........1365 23.3 initialization................................................................................................................. .......... 1365 23.4 registers for controlling the ethernet controller ............................................................ 1368 23.4.1 mac control regist ers .......................................................................................................... .......1372 23.4.2 statistics counter s............................................................................................................ ...........1402 23.4.3 fifo controller c ontrol regi sters.............................................................................................. ....1441 23.4.4 dmac control registers in ethernet c ontrolle r .............................................................................1468 23.5 mac/fifo/dmac function.................................................................................................. 1478 23.5.1 frame fo rmat ................................................................................................................... ...........1478 23.5.2 transmit f uncti on .............................................................................................................. ..........1481 23.5.3 receive f uncti on ............................................................................................................... ..........1485 23.5.4 mac control functi on........................................................................................................... ........1487 23.5.5 dedicat ed dm ac ................................................................................................................. .......1491 23.5.6 serial management interface .................................................................................................... ..1493 23.5.7 address f ilterin g .............................................................................................................. ............1497 23.5.8 statistics counter s............................................................................................................ ...........1502 23.6 data transmission .............................................................................................................. .. 1503 23.6.1 buffer structure........................................................................................................ ....................1503 23.6.2 descriptor mechani sm ........................................................................................................... .....1505 23.6.3 frame trans missi on ............................................................................................................. .......1514 23.6.4 frame rec eptio n................................................................................................................ ..........1519 23.6.5 error occu rrence ............................................................................................................... ..........1524 23.7 receive checksum .............................................................................................................. 1 525 23.7.1 processing by softw are ......................................................................................................... ......1525 23.8 notes.................................................................................................................... .................. 1527 23.8.1 notes on fifo .................................................................................................................. ..........1527 chapter 24 dma function (dma controller) .. ............................................................... 1528 24.1 features ....................................................................................................................... ......... 1528 24.2 configuration.................................................................................................................. ...... 1529 24.3 registers ...................................................................................................................... ......... 1530 24.4 transfer targets.............................................................. ................................................. .... 1539 24.5 transfer modes ................................................................................................................. ... 1539 24.6 transfer types ................................................................................................................. .... 1540 24.7 dma channel priorities ....................................................................................................... 15 41 24.8 time related to dma transfer ............................................................................................ 1541 24.9 dma transfer start factors ................................................................................................ 1542 24.10 dma abort factors ........................................................................................................ ... 1543 24.11 end of dma transfer ...................................................................................................... .. 1543 24.12 operation timing ......................................................................................................... ..... 1543 24.13 cautions................................................................................................................. ............ 1548 chapter 25 interrupt/exception processing function............................................. 1553 25.1 features ....................................................................................................................... ......... 1553 25.2 non-maskable interrupt s ..................................................................................................... 156 5 25.2.1 operat ion ...................................................................................................................... ..............1567 25.2.2 restore ........................................................................................................................ ...............1568 25.2.3 np fl ag ........................................................................................................................ ................1569 25.3 maskable interrupts ............................................................................................................ . 1570 25.3.1 operat ion ...................................................................................................................... ..............1570 25.3.2 restore ........................................................................................................................ ...............1572 25.3.3 priorities of ma skable inte rrupts.............................................................................................. ....1573 25.3.4 interrupt control r egister ( xxicn) ............................................................................................. ....1577 25.3.5 interrupt mask registers 0 to 7 (imr0 to imr7 ) ...........................................................................1582 25.3.6 in-service priority register (ispr) ............................................................................................ ....1584 25.3.7 id flag ........................................................................................................................ .................1585 25.3.8 watchdog timer mode regi ster 2 (w dtm2) .................................................................................1585 25.4 software exception............................................................................................................. . 1586 25.4.1 operat ion ...................................................................................................................... ..............1586 25.4.2 restore ........................................................................................................................ ...............1587 25.4.3 ep fl ag ........................................................................................................................ ................1588 25.5 exception trap ................................................................................................................. .... 1589 25.5.1 illegal opcode ................................................................................................................. .............1589 25.5.2 debug tr ap ..................................................................................................................... .............1591 25.6 external interrupt request input pins (nmi and intp00 to intp25)............................... 1593 25.6.1 noise elim inatio n.............................................................................................................. ...........1593 25.6.2 edge detec tion ................................................................................................................. ...........1593 25.7 interrupt acknowledge time of cpu.................................................................................. 1601 25.8 periods in which interrupts are not acknowledge d by cpu ......................................... 1602 25.9 cautions ....................................................................................................................... ......... 1602 chapter 26 key interrupt function ....................... ............................................................ 1603 26.1 function ....................................................................................................................... ......... 1603 26.2 register ....................................................................................................................... .......... 1604 26.3 cautions ....................................................................................................................... ......... 1604 chapter 27 standby functi on ................................................................................................ 1605 27.1 overview ....................................................................................................................... ........ 1605 27.2 registers ...................................................................................................................... ......... 1607 27.3 halt mode ...................................................................................................................... ..... 1610 27.3.1 setting and operat ion st atus ................................................................................................... ....1610 27.3.2 releasing ha lt m ode ............................................................................................................ ....1610 27.4 idle1 mode..................................................................................................................... ...... 1612 27.4.1 setting and operat ion st atus ................................................................................................... ....1612 27.4.2 releasing id le1 m ode ........................................................................................................... ....1613 27.5 idle2 mode..................................................................................................................... ...... 1615 27.5.1 setting and operat ion st atus ................................................................................................... ....1615 27.5.2 releasing id le2 m ode ........................................................................................................... ....1616 27.5.3 securing setup time when releasing id le2 m ode....................................................................... 1618 27.6 stop mode ...................................................................................................................... ..... 1619 27.6.1 setting and operat ion st atus ................................................................................................... ....1619 27.6.2 releasing st op m ode ............................................................................................................ ...1619 27.6.3 securing oscillation stabilization ti me when releasi ng stop mode ............................................1622 27.7 subclock operation mode................................................................................................... 1623 27.7.1 setting and operat ion st atus ................................................................................................... ....1623 27.7.2 releasing subclock operation mode ...........................................................................................162 3 27.8 sub-idle mode.................................................................................................................. ... 1625 27.8.1 setting and operat ion st atus ................................................................................................... ....1625 27.8.2 releasing sub- idle mode ........................................................................................................ ..1625 chapter 28 reset functions ................................................................................................. .. 1628 28.1 overview ....................................................................................................................... ........ 1628 28.2 registers to check reset source ............................. ......................................................... 1629 28.3 operation ...................................................................................................................... ........ 1630 28.3.1 reset operation vi a reset pin .................................................................................................. 1630 28.3.2 reset operation by watchdog time r 2..........................................................................................16 32 28.3.3 reset by clo ck moni tor......................................................................................................... .......1634 28.3.4 reset operation by lo w-voltage det ector .....................................................................................163 5 28.3.5 operation after reset re lease .................................................................................................. ....1636 28.3.6 reset function operation flow.................................................................................................. ....1637 chapter 29 clock monito r ................................................................................................... ... 1638 29.1 functions ...................................................................................................................... ........ 1638 29.2 configuration.................................................................................................................. ...... 1638 29.3 register ....................................................................................................................... .......... 1639 29.4 operation ...................................................................................................................... ........ 1640 chapter 30 low-voltage detector (lvi) ............ ............................................................... 1643 30.1 functions ...................................................................................................................... ........ 1643 30.2 configuration.................................................................................................................. ...... 1643 30.3 registers ...................................................................................................................... ......... 1644 30.4 operation ...................................................................................................................... ........ 1646 30.4.1 to use for inter nal rese t signal............................................................................................... .....1646 30.4.2 to use for interr upt........................................................................................................... ...........1647 30.5 ram retention voltage detection operation........... ......................................................... 1648 chapter 31 crc function .................................................................................................... ...... 1649 31.1 functions ...................................................................................................................... ........ 1649 31.2 configuration.................................................................................................................. ...... 1649 31.3 registers ...................................................................................................................... ......... 1650 31.4 operation ...................................................................................................................... ........ 1651 31.5 usage method................................................................................................................... .... 1652 chapter 32 regulator ........................................................................................................ ....... 1654 32.1 overview ....................................................................................................................... ........ 1654 32.2 operation ...................................................................................................................... ........ 1655 chapter 33 flash memory .................................................................................................... .... 1656 33.1 features ....................................................................................................................... ......... 1656 33.2 memory configuratio n......................................................................................................... 16 57 33.3 functional overview ............................................................................................................ 1658 33.4 rewriting by dedicated flash programmer ............. ......................................................... 1661 33.4.1 programming environm ent........................................................................................................ ..1661 33.4.2 communicati on m ode ............................................................................................................. ....1662 33.4.3 flash memory cont rol ........................................................................................................... ......1673 33.4.4 selection of comm unication mode ..............................................................................................16 74 33.4.5 communicati on comm ands ......................................................................................................... 1675 33.4.6 pin connec tion ................................................................................................................. ...........1676 33.5 rewriting by self programming... ....................................................................................... 1680 33.5.1 overvi ew ....................................................................................................................... ..............1680 33.5.2 featur es....................................................................................................................... ...............1681 33.5.3 standard self pr ogramming flow ................................................................................................. 1682 33.5.4 flash f uncti ons................................................................................................................ ............1683 33.5.5 pin proc essi ng ................................................................................................................. ...........1683 33.5.6 internal res ources used........................................................................................................ .......1684 33.6 creating rom code to place order for previously written product ................................ 1685 33.6.1 procedure for using rom c ode to place an order ....................................................................... 1685 chapter 34 on-chip debug function .................... ............................................................... 1686 34.1 debugging with dcu ........................................................................................................... 16 87 34.1.1 connection circui t exam ple ..................................................................................................... ....1687 34.1.2 interface signal s.............................................................................................................. ............1687 34.1.3 maskable f uncti ons ............................................................................................................. ........1689 34.1.4 regist er ....................................................................................................................... ...............1689 34.1.5 operat ion ...................................................................................................................... ..............1691 34.1.6 cauti ons....................................................................................................................... ...............1691 34.2 debugging without using dcu ..................................... ..................................................... 1692 34.2.1 circuit connecti on exam ples .................................................................................................... ...1692 34.2.2 maskable f uncti ons ............................................................................................................. ........1695 34.2.3 securement of us er res ources ................................................................................................... .1696 34.2.4 cauti ons....................................................................................................................... ...............1703 34.3 rom security function ....................................................................................................... 170 4 34.3.1 security id .................................................................................................................... ..............1704 34.3.2 setti ng........................................................................................................................ .................1705 chapter 35 electrical specifications ................... ............................................................ 1707 35.1 absolute maximum ratings ................................................................................................ 1707 35.2 capacitance .................................................................................................................... ...... 1709 35.3 operating conditions .......................................................................................................... 1 709 35.4 oscillator characteris tics.................................................................................................... 1 710 35.4.1 main clock oscillato r characte ristics .......................................................................................... ..1710 35.4.2 subclock oscillato r characte ristics ..................................................................................... .........1711 35.4.3 pll char acterist ics..................................................................................................... .................1712 35.4.4 internal oscillator characteri stics ............................................................................................ .....1712 35.5 dc characteristics ............................................................................................................. .. 1713 35.5.1 i/o level...................................................................................................................... .................1713 35.5.2 supply cu rrent................................................................................................................. ............1715 35.6 data retention characteristics.... ....................................................................................... 1716 35.7 ac characteristics ............................................................................................................. .. 1717 35.7.1 clkout output timi ng........................................................................................................... .....1718 35.7.2 bus ti ming ..................................................................................................................... ..............1719 35.8 basic operation................................................................................................................ .... 1726 35.9 flash memory programming characteristics ........... ........................................................ 1746 chapter 36 package drawings .............................................................................................. 17 47 chapter 37 recommended soldering condition s......................................................... 1749 appendix a development tools............................................................................................. 17 51 a.1 software package ............................................................................................................... . 1753 a.2 language processing software ......................................................................................... 1753 a.3 control software ............................................................................................................... ... 1753 a.4 debugging tools (hardware) .............................................................................................. 1754 a.4.1 when using iecube qb-v850esj x3e ......................................................................................1754 a.4.2 when using minicu be qb-v850m ini .......................................................................................1756 a.4.3 when using minicu be2 qb-mi ni2............................................................................................1757 a.5 debugging tools (software) ............................................................................................... 1758 a.6 embedded software............................................................................................................. 1 759 a.7 flash memory writing tools ............................................................................................... 1759 appendix b major differences between v850es/jx3-e and v850es/jx3-h............ 1760 appendix c register index .................................................................................................. ..... 1761 appendix d instruction set list ........................................................................................... 1804 d.1 conventions.................................................................................................................... ...... 1804 d.2 instruction set (in alphabetical order) .................. ............................................................ 1807 appendix e revision history................................................................................................. .... 1814 e.1 major revisions in this edition.............................. ............................................................ 1814 e.2 revision history of preceding editions.................... ......................................................... 1814 r01uh0290ej0300 rev.3.00 page 24 of 1817 sep 19, 2011 r01uh0290ej0300 rev.3.00 sep 19, 2011 v850es/jh3-e, v850es/jj3-e renesas mcu chapter 1 introduction the v850es/jh3-e and v850es/jj3-e are products in the low- power series of renesas electronics? v850 single-chip microcontrollers designed for real -time control applications. 1.1 general the v850es/jh3-e and v850es/jj3-e are 32-bit single-chi p microcontrollers that use the v850es cpu core and incorporate peripheral functions such as rom/ram, a timer/counter, serial interfaces, an a/d converter, a d/a converter, a dma controller, can, a usb function c ontroller, and an ethernet controller. in addition to high real-time response characteristics and 1-clock-pitch bas ic instructions, the v850es/jh3-e and v850es/jj3-e feature multiply instructions realized by a hardware multiplier, saturated operation instructions, and bit manipulation instructions. table 1-1 lists the products of the v850es/jh3-e, and table 1-2 lists the products of the v850es/jj3-e. v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 25 of 1817 sep 19, 2011 table 1-1. v850es/jh3-e product list generic name v850es/jh3-e part number pd70f3778 pd70f3779 pd70f3780 pd70f3781 pd70f3782 pd70f3783 flash memory 256 kb 384 kb 512 kb 384 kb 512 kb 512 kb internal ram 60 kb 60 kb 60 kb 60 kb 60 kb 60 kb internal memory data-only ram 16 kb 16 kb 16 kb 64 kb 64 kb 64 kb logical space 64 mb memory space external memory area 5 mb external bus interface address bus: 22, address/data bus: 16 separate bus/multiplexed bus general-purpose register 32 bits 32 registers main clock pll mode: f x = 3 to 6.25 mhz, f xx = 24 to 50 mhz (multiplied by 8) clock through mode: f x = 3 to 6.25 mhz (internal: f xx = 3 to 6.25 mhz) subclock f xt = 32.768 khz internal oscillator f r = 220 khz (typ.) clock minimum instruction execution time 20 ns (main clock (f xx ) = 50 mhz) i/o port i/o: 84 (5 v tolerant: 38) 16-bit taa 6 channels 16-bit tab 2 channels 16-bit tmm 4 channels 16-bit tmt 1 channel motor control 1 channel (functions with combination of taa and tab; includes hi-z output control function) watch timer 1 channel (rtc) timer wdt 1 channel real-time output function 6 bits 1 channel 10-bit a/d converter 10 channels csif/uartc 1 channel csif/uartc/i 2 c 2 channels csie/uartc 1 channel csie note 1 /uartc/i 2 c 1 channel csif/uartb 2 channels (including one ch annel that is assigned to two pins) csie note 1 1 channel uartc/i 2 c 1 channel ? uartc/i 2 c/can ? 1 channel usb controller usb function (full speed):1 channel serial interface ethernet controller 1 channel dma controller 4 channels (transfer target: on-chip peripheral i/o, internal ram, external memory) external notes 2, 3 22 (22) 22 (22) 22 (22) 22 (22) 22 (22) 22 (22) interrupt source internal 78 78 78 78 78 82 power save function halt/idle1/idle2/stop/subclock/sub-idle mode reset source reset pin input, watchdog timer 2 (wdt2), clock monitor (clm), low-voltage detector (lvi) on-chip debugging minicube ? , minicube2 supported operating power supply voltage 2.85 to 3.6 v operating ambient temperature ? 40 to +85 c package 128-pin plastic lqfp (fine pitch) (14 20 mm) notes 1. csie of the same channel is assigned to two pins. 2. the figures in parentheses indicate the number of external interrupts that can release stop mode. 3. including nmi. v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 26 of 1817 sep 19, 2011 table 1-2. v850es/jj3-e product list generic name v850es/jj3-e part number pd70f3784 pd70f3785 pd70f3786 flash memory 512 kb 512 kb 512 kb internal ram 60 kb 60 kb 60 kb internal memory data-only ram 16 kb 64 kb 64 kb logical space 64 mb memory space external memory area 13 mb external bus interface address bus: 24, address/data bus: 16 separate bus/multiplexed bus general-purpose register 32 bits 32 registers main clock pll mode: f x = 3 to 6.25 mhz, f xx = 24 to 50 mhz (multiplied by 8) clock through mode: f x = 3 to 6.25 mhz (internal: f xx = 3 to 6.25 mhz) subclock f xt = 32.768 khz internal oscillator f r = 220 khz (typ.) clock minimum instruction execution time 20 ns (main clock (f xx ) = 50 mhz) i/o port i/o: 100 (5 v tolerant: 47) 16-bit taa 6 channels 16-bit tab 2 channels 16-bit tmm 4 channels 16-bit tmt 1 channel motor control 1 channel (functions with combination of taa and tab; includes hi-z output control function) watch timer 1 channel(rtc) timer wdt 1 channel real-time output function 8 bits 1 channel 10-bit a/d converter 12 channels csif/uartc 3 channels csif/uartc/i 2 c 2 channels csie/uartc 1 channel csie note 1 /uartc/i 2 c 1 channel csif/uartb 2 channels (including one ch annel that is assigned to two pins) csie note 1 1 channel i 2 c 1 channel uartc/i 2 c 1 channel ? uartc/i 2 c/can ? 1 channel usb controller usb function (full speed):1 channel serial interface ethernet controller 1 channel dma controller 4 channels (transfer target: on-chip peripheral i/o, internal ram, external memory) external notes 2, 3 27 (27) 27 (27) 27 (27) interrupt source internal 84 84 88 power save function halt/idle1/idle2/stop/subclock/sub-idle mode reset source reset pin input, watchdog timer 2 (wdt2), clock monitor (clm), low-voltage detector (lvi) on-chip debugging minicube, minicube2 supported operating power supply voltage 2.85 to 3.6 v operating ambient temperature ? 40 to +85 c package 144-pin plastic lqfp (fine pitch) (20 20 mm) notes 1. csie of the same channel is assigned to two pins. 2. the figures in parentheses indicate the number of external interrupts that can release stop mode. 3. including nmi. v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 27 of 1817 sep 19, 2011 1.2 features { minimum instruction execution time: 20.0 ns (main clock (f xx ) = 50 mhz: v dd = 2.85 to 3.6 v) 30.5 s (subclock (f xt ) = 32.768 khz) { general-purpose registers: 32 bits 32 registers { cpu features: signed multiplication (16 16 32): 1 or 2 clocks signed multiplication (32 32 64): 1 to 5 clocks saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space (for programs and data) external expansion: up to 14 mb (including 1 mb used as internal rom/ram space) ? internal memory: ram: 76/124 kb (see table 1-1 and table 1-2 ) flash memory: 256/384/512 kb (see table 1-1 and table 1-2 ) ? external bus interface: separate bus/multiplexed bus selectable 8/16-bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function { interrupts and exceptions: internal external non-maskable maskable total non-maskable maskable total pd70f3778 1 78 79 1 21 22 pd70f3779 1 78 79 1 21 22 pd70f3780 1 78 79 1 21 22 pd70f3781 1 78 79 1 21 22 pd70f3782 1 78 79 1 21 22 v850es/jh3-e pd70f3783 1 82 83 1 21 22 pd70f3784 1 83 84 1 26 27 pd70f3785 1 83 84 1 26 27 v850es/jj3-e pd70f3786 1 87 88 1 26 27 software exceptions: 32 sources exception trap: 2 sources { i/o lines: i/o ports: 84 (v850es/jh3-e) 100 (v850es/jj3-e) { timer function: 16-bit interv al timer m (tmm): 4 channels 16-bit timer/event counter aa (taa): 6 channels 16-bit timer/event counter ab (tab): 2 channels 16-bit timer/event counter t (tmt): 1 channel motor control function (timers used: tab1, taa4) 6-phase pwm function with dead-time function of 16-bit accuracy high-impedance output control function a/d trigger generation by timer-tuned operation function arbitrary cycle setting function arbitrary dead-time setting function real-time counter (rtc): 1 channel v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 28 of 1817 sep 19, 2011 watchdog timer: 1 channel { real-time output port: 6 bits 1 channel { serial interface: asynchronous serial interface b with fifo (uartb) asynchronous serial interface c (uartc) 3-wire variable-length serial interface e with fifo (csie) 3-wire variable-length serial interface f (csif) i 2 c bus interface (i 2 c) can interface usb function controller ethernet controller remark for the number of channels incorporated, see tables 1-1 and 1-2 . { a/d converter (10-bit resolution): 10ch (v850es/jh3-e) 12ch (v850es/jj3-e) { dma controller: 4 channels { dcu (debug control unit): jtag interface { clock generator: main clock or subclock operation: 7-level cpu clock (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { internal oscillation clock: 220 khz (typ.) { power-save functions: halt/idle1/idle2/stop/subclock/sub-idle mode { package: 128-pin plastic lqfp (fine pitch) (14 20) (v850es/jh3-e) 144-pin plastic lqfp (fine pitch) (20 20) (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 29 of 1817 sep 19, 2011 1.3 application fields equipment requiring an ethernet cont roller, industrial equipment, fa equipment, network control including building management system. 1.4 ordering information ? v850es/jh3-e part number package internal flash memory pd70f3778gf-gat-ax pd70f3779gf-gat-ax pd70f3780gf-gat-ax pd70f3781gf-gat-ax pd70f3782gf-gat-ax pd70f3783gf-gat-ax 128-pin plastic lqfp (fine pitch) (14 20) 128-pin plastic lqfp (fine pitch) (14 20) 128-pin plastic lqfp (fine pitch) (14 20) 128-pin plastic lqfp (fine pitch) (14 20) 128-pin plastic lqfp (fine pitch) (14 20) 128-pin plastic lqfp (fine pitch) (14 20) 256 kb 384 kb 512 kb 384 kb 512 kb 512 kb ? v850es/jj3-e part number package internal flash memory pd70f3784gj-gae-ax pd70f3785gj-gae-ax pd70f3786gj-gae-ax 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 512 kb 512 kb 512 kb remark the v850es/jh3-e and v850es/jj3-e are lead-free products. v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 30 of 1817 sep 19, 2011 1.5 pin configuration (top view) ? v850es/jh3-e 128-pin plastic lqfp (fine pitch) (14 20) pd70f3778gf-gat-ax pd70f3779gf-gat-ax pd70f3780gf-gat-ax pd70f3781gf-gat-ax pd70f3782gf-gat-ax pd70f3783gf-gat-ax p21/tiab00/toab00/rtcdiv/rtccl p22/tiab01/toab01/rtc1hz/intp02 p1txd0 p1txd1 p1txd2 p1txd3 p1txer p1txen p1txclk p1rxd0 p1rxd1 p1rxd2 p1rxd3 p1rxdv p1rxer p1rxclk p1crs p1col p1mdc p1mdio p23/sif1/txdc1/sda00/intp03 v ss ev dd p24/sof1/rxdc1/scl00/intp04 p25/sckf1/tiaa30/toaa30/udmarq0 p26/tiaa31/toaa31/intp05/udmaak0 av ref0 av ss p40/sif0/txdc3/sda01/rtp00 p41/sof0/rxdc3/scl01/rtp01 p42/sckf0/tiaa40/toaa40/rtp02 p43/sie0/txdc4/rtp03/hldak p44/soe0/rxdc4/rtp04/hldrq p45/scke0/tiaa41/toaa41/rtp05 udmf udpf uv dd flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp00/adtrg/exclk p50/intp07/ddi p51/intp08/ddo p52/intp09/dck p53/intp10/dms p54/intp11/drst p30/txdc0/sif2/tiaa00/toaa00 p31/rxdc0/sof2/tiaa01/toaa01 p32/asckc0/sckf2/tiaa10/toaa10 p33/sif4/txdb0/tiaa11/toaa11 p34/sof4/rxdb0/tiaa20/toaa20 p35/sckf4/tiaa21/toaa21/toaa1off/intp06 v ss ev dd p36/txdc2/sda02(/ctxd0 note 3 ) p37/rxdc2/scl02(/crxd0 note 3 ) p20/tiab02/toab02/intp01 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 e v dd v ss pcs2/cs2 pcs0/cs0 pct6/astb pct4/rd pct1/wr1 pct0/wr0 pdh5/a21/sckf4 pdh4/a20/sof4/rxdb0 pdh3/a19/sif4/txdb0 pdh2/a18/scke1 pdh1/a17/soe1 pdh0/a16/sie1 pdl15/ad15 pdl14/ad14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 e v dd v ss pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 pcm0/wait ev dd v ss regc note 2 v dd pcm1/clkout p915/sckf3/tiaa51/toaa51/a15 p914/sof3/rxdb1/intp20/a14 p913/sif3/txdb1/intp19/a13 p912/toab1off/intp18/a12 p911/scke1/tiaa50/toaa50/a11 p910/soe1/rxdc5/scl03/a10 p99/sie1/txdc5/sda03/a9 p98/tenc01/intp17/a8 p97/tenc00/tit01/kr7/tot01/a7 p96/tecr0/tit00/kr6/tot00/a6 p95/toab1b3/evtb1/kr5/intp16/a5 p94/toab1t3/toab13/tiab13/kr4/intp15/a4 p93/toab1b2/trgab1/kr3/intp14/a3 p92/toab1t2/toab12/tiab12/kr2/intp13/a2 p91/toab1b1/tiab10/kr1/toab10/a1 p90/toab1t1/toab11/tiab11/kr0/intp12/a0 notes 1. connect this pin to v ss in the normal mode. 2. connect the regc pin to v ss via a 4.7 f (recommend value) capacitor. 3. pd70f3783 only v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 31 of 1817 sep 19, 2011 ? v850es/jj3-e 144-pin plastic lqfp (fine pitch) (20 20) pd70f3784gj-gae-ax pd70f3785gj-gae-ax pd70f3786gj-gae-ax ev dd v ss pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 pcm0/wait ev dd v ss regc note 2 v dd pcm1/clkout p915/sckf3/tiaa51/toaa51/a15 p914/sof3/rxdb1/intp20/a14 p913/sif3/txdb1/intp19/a13 p912/toab1off/intp18/a12 p911/scke1/tiaa50/toaa50/a11 p910/soe1/rxdc5/scl03/a10 p99/sie1/txdc5/sda03/a9 p98/tenc01/intp17/a8 p97/tenc00/tit01/kr7/tot01/a7 p96/tecr0/tit00/kr6/tot00/a6 p95/toab1b3/evtb1/kr5/intp16/a5 p94/toab1t3/toab13/tiab13/kr4/intp15/a4 p93/toab1b2/trgab1/kr3/intp14/a3 p92/toab1t2/toab12/tiab12/kr2/intp13/a2 av ref0 av ss p40/sif0/txdc3/sda01/rtp00 p41/sof0/rxdc3/scl01rtp01 p42/sckf0/tiaa40/toaa40/rtp02 p43/sie0/txdc4/rtp03 p44/soe0/rxdc4/rtp04 p45/scke0/tiaa41/toaa41/rtp05 udmf udpf uv dd flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp00/adtrg/exclk p50/intp07/ddi p51/intp08/ddo p52/intp09/dck p53/intp10/dms p54/intp11/drst p30/txdc0/sif2/tiaa00/toaa00 p31/rxdc0/sof2/tiaa01/toaa01 p32/asckc0/sckf2/tiaa10/toaa10 p33/sif4/txdb0/tiaa11/toaa11 p34/sof4/rxdb0/tiaa20/toaa20 p35/sckf4/tiaa21/toaa21/toaa1off/intp06 v ss ev dd p36/txdc2/sda02(/ctxd0 note 3 ) p37/rxdc2/scl02(/ctxd0 note 3 ) p20/tiab02/toab02/intp01 p21/tiab00/toab00/rtcdiv/rtccl p22/tiab01/toab01/rtc1hz/intp02 p27/tiab03/toab03/intp21 p55/sda04/intp23/udmarq1 p56/scl04/intp24/udmaak1 p1txd0 p1txd1 p1txd2 p1txd3 p1txer p1txen p1txclk p1rxd0 p1rxd1 p1rxd2 p1rxd3 p1rxdv p1rxer p1rxclk p1crs p1col p1mdc p1mdio p57/sif6/txdc7 p58/sof6/rxdc7 p59/sckf6/intp25 p23/sif1/txdc1/sda00/intp03 v ss ev dd p24/sof1/rxdc1/scl00/intp04 p25/sckf1/tiaa30/toaa30/udmarq0 p26/tiaa31/toaa31/intp05/udmaak0 p90/toab1t1/toab11/tiab11/kr0/intp12/a0 p91/toab1b1/tiab10/kr1/toab10/a1 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 ev dd v ss p48/sckf5/intp22 p47/sof5/rxdc6/rtp07 p46/sif5/txdc6/rtp06 pcs3/cs3 pcs2/cs2 pcs0/cs0 pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pdh7/a23 pdh6/a22 pdh5/a21/sckf4 pdh4/a20/sof4/rxdb0 pdh3/a19/sif4/txdb0 pdh2/a18/scke1 pdh1/a17/soe1 pdh0/a16/sie1 pdl15/ad15 pdl14/ad14 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 notes 1. connect this pin to v ss in the normal mode. 2. connect the regc pin to v ss via a 4.7 f (recommend value) capacitor. 3. pd70f3786 only v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 32 of 1817 sep 19, 2011 pin names a0 to a23: ad0 to ad15: adtrg: ani0 to ani11: asckc0: astb: av ref0 : av ss : clkout: crxd0: cs0, cs2, cs3: ctxd0: dck: ddi: ddo: dms: drst: ev dd : evtab1: exclk: flmd0, flmd1: hldak: hldrq: intp00 to intp25: kr0 to kr7: nmi: p02, p03: p1col, p1crs, p1mdc, p1mdio, p1rxclk, p1rxd0 to p1rxd3, p1rxdv, p1rxer, p1txclk, p1txd0 to p1txd3, p1txen, p1txer: p20 to p27: p30 to p37: p40 to p48: p50 to p59: p70 to p711: p90 to p915: pcm0 to pcm3: pcs0, pcs2 pcs03: pct0, pct1, pct4, pct6: pdh0 to pdh7: pdl0 to pdl15: rd: regc: reset: rtc1hz, rtccl, rtcdiv: address bus address/data bus a/d trigger input analog input asynchronous serial clock address strobe analog reference voltage grand for analog pin clock output can receive data chip select can transmit data debug clock debug data input debug data output debug mode select debug reset power supply for external pin timer event count input external clock input flash programming mode hold acknowledge hold request external interrupt input key return non-maskable interrupt request port 0 ethernet phy interface port 2 port 3 port 4 port 5 port 7 port 9 port cm port cs port ct port dh port dl read strobe regulator control reset real-time counter clock output rtp00 to rtp07: rxdb0, rxdb1: rxdc0 to rxdc7: scke0, scke1: sckf0 to sckf6 scl00 to scl04: sda00 to sda04: sie0, sie1: sif0 to sif6 soe0, soe1: sof0 to sof6 tecr0: tenc00, tenc01: tiaa00, tiaa01, tiaa10, tiaa11, tiaa20, tiaa21, tiaa30, tiaa31, tiaa40, tiaa41, tiaa50, tiaa51, tiab00 to tiab03, tiab10 to tiab13, tit00, tit01: toaa00, toaa01, toaa10, toaa11, toaa20, toaa21, toaa30, toaa31, toaa40, toaa41, toaa50, toaa51, toab00 to toab03, toab10 to toab13, toab1b1 to toab1b3, toab1t1 to toab1t3, tot00, tot01: toaa1off, toab1off: trgab1: txdb0, txdb1 txdc0 to txdc5: udmaak0, udmaak1: udmarq0, udmarq1: udmf: udpf: uv dd : v dd : v ss : wait: wr0 : wr1: x1, x2 : xt1, xt2: real-time output port receive data serial clock serial clock serial data serial input serial output timer encoder clear input timer encoder input timer input timer output timer output off timer trigger input serial output dma acknowledge for external usb dma request for external usb usb data i/o ( ? ) function usb data i/o (+) function power supply for external usb power supply ground external wait input lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 33 of 1817 sep 19, 2011 1.6 function block configuration 1.6.1 internal block diagram ? v850es/jh3-e nmi intp00 to intp20 rtp00 to rtp05 kr0 to kr7 rto wdt dcu rtc rom ram pc alu cpu hldrq hldak astb rd wait wr0, wr1 cs0, cs2 a0 to a21 ad0 to ad15 port timer/counter function serial interface function pdl0 to pdl15 pdh0 to pdh5 pct0, pct1, pct4, pct6 pcs0, pcs2 pcm0, pcm1 p90 to p915 p70 to p79 p50 to p54 p40 to p45 p30 to p37 p20 to p26 p02, p03 av ref0 av ss ani0 to ani9 v dd regc ev dd uv dd v ss flmd0 flmd1 drst dms ddi dck ddo dma ethernet controller usb function intc exclk cg pll clkout x1 x2 xt1 xt2 reset debug function interrupt function bcu tiaa00 to tiaa50, tiaa01 to tiaa51, toaa1off toab00 to toab02, toab10 to toab13 toab1t1 to toab1t3, toab1b1 to toab1b3 tiab00 to tiab02, tiab10 to tiab13, evtab1, trgab1, toab1off toaa00 to toaa50, toaa01 to toaa51 tot00, tot01 tecr0, tenc00, tenc01, evtt0, tit00, tit01 rtc1hz rtccl rtcdiv rxdc0 to rxdc5 txdc0 to txdc5 asckc0 rxdb0, rxdb1 txdb0, txdb1 uartb: 2 ch iic0: 4 ch uartc: 6 ch csie: 2 ch sie0, sie1 soe0, soe1 scke0, scke1 csif: 5 ch sif0 to sif4 sof0 to sof4 sckf0 to sckf4 sda00 to sda03 scl00 to scl03 can note 3 : 1 ch crxd0 ctxd0 note 1 note 2 16-bit timer/ event counter ab: 2 ch 32-bit barrel shifter 16-bit timer/ event counter aa: 6 ch 16-bit interval timer m: 4 ch 16-bit timer/ counter t: 1 ch flash memory controller system register general-purpose registers 32 bits 32 multiplier 16 16 32 key return function regulator a/d converter notes 1. pd70f3778: 256 kb pd70f3779, 70f3781: 384 kb pd70f3780, 70f3782, 70f3783: 512 kb 2. pd70f3778, 70f3779, 70f3780: 76 kb pd70f3781, 70f3782, 70f3783: 124 kb 3. pd70f3783 only v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 34 of 1817 sep 19, 2011 ? v850es/jj3-e nmi intp00 to intp25 rtp00 to rtp07 kr0 to kr7 rto wdt dcu rtc rom ram pc alu cpu hldrq hldak astb rd wait wr0, wr1 cs0, cs2, cs3 a0 to a23 ad0 to ad15 timer/counter function serial interface function pdl0 to pdl15 pdh0 to pdh7 pct0, pct1, pct4, pct6 pcs0, pcs2, pcs3 pcm0 to pcm3 p90 to p915 p70 to p711 p50 to p59 p40 to p48 p30 to p37 p20 to p27 p02, p03 av ref0 av ss ani0 to ani11 v dd regc ev dd uv dd v ss flmd0 flmd1 drst dms ddi dck ddo dma ethernet controller intc exclk cg pll clkout x1 x2 xt1 xt2 reset debug function interrupt function bcu tiaa00 to tiaa50, tiaa01 to tiaa51, toaa1off toab00 to toab03, toab10 to toab13 toab1t1 to toab1t3, toab1b1 to toab1b3 tiab00 to tiab03, tiab10 to tiab13, evtab1, trgab1, toab1off toaa00 to toaa50, toaa01 to toaa51 tot00, tot01 tecr0, tenc00, tenc01, evtt0, tit00, tit01 rtc1hz rtccl rtcdiv rxdc0 to rxdc7 txdc0 to txdc7 asckc0 rxdb0, rxdb1 txdb0, txdb1 uartb: 2 ch iic0: 5 ch uartc: 8 ch csie: 2 ch sie0, sie1 soe0, soe1 scke0, scke1 csif: 7 ch sif0 to sif6 sof0 to sof6 sckf0 to sckf6 sda00 to sda04 scl00 to scl04 can note 3 : 1 ch crxd0 ctxd0 usb function 16-bit timer/ event counter ab: 2 ch 16-bit timer/ event counter aa: 6 ch 16-bit interval timer m: 4 ch 16-bit timer/ counter t: 1 ch note 1 note 2 flash memory controller 32-bit barrel shifter system register general-purpose registers 32 bits 32 multiplier 16 16 32 ports regulator key return function a/d converter notes 1. pd70f3784: 512 kb pd70f3785: 512 kb pd70f3786: 512 kb 2. pd70f3784: 76 kb pd70f3785, 70f3786: 124 kb 3. pd70f3786 only v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 35 of 1817 sep 19, 2011 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single-cl ock execution of address calc ulations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetc hes the instruction code. the prefetch ed instruction code is stored in an instruction queue. (3) flash memory (rom) this is a 512/384/256 kb flash memory mapped to addresses 0000000h to 007ffffh/0000000h to 005ffffh/0000000h to 003ffffh. it c an be accessed from the cpu in one clock during instruction fetch. (4) ram this is a 60 kb ram mapped to addresses 3ff0000h to 3ffefffh. it can be accessed from the cpu in one clock during data access. an 16/64 kb data-only ram is incorporated at addresses 00280000h to 00283fffh/00280000h to 0028ffffh. (5) interrupt controller (intc) this controller handles hardware interrupt requests (n mi, intp00 to intp25) from on-chip peripheral hardware and external hardware. eight levels of interrupt prio rities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (6) clock generator (cg) a main clock oscillator and subclock oscillator are pr ovided and generate the main clock oscillation frequency (f x ) and subclock frequency (f xt ), respectively. there are two modes: in the clock-through mode, f x is used as the main clock frequency (f xx ) as is. in the pll mode, f x is used multiplied by 8. the cpu clock frequency (f cpu ) can be selected from among f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (7) internal oscillator an internal oscillator is provided on chip. the oscillati on frequency is 220 khz (typ). the internal oscillator supplies the clock for watchdog timer 2 and timer m. (8) timer/counter six-channel 16-bit timer/event counter aa (taa), two-channel 16-bit timer/event counter ab (tab), one-channel 16- bit timer/event counter t (tmt), and fou r-channel 16-bit interval timer m (tmm) are provided on chip. the motor control function can be realized using tab1 and taa4 in combination. v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 36 of 1817 sep 19, 2011 (9) real-time counter (for watch) the real-time counter count s the reference time (one second) for wa tch counting based on the subclock (32.768 khz) or main clock. this can simultaneously be used as the interval timer based on the main clock. hardware counters dedicated to year, month, da y of week, day, hour, minute, and second are provided, and can count up to 99 years. (10) watchdog timer 2 a watchdog timer is provided on chip to detect inadv ertent program loops, system abnormalities, etc. the internal oscillation clock, the main clock, or t he subclock can be selected as the source clock. watchdog timer 2 generates a non-maskable interrupt request signal (intwdt2) or a system reset signal (wdt2res) after an overflow occurs. (11) serial interface the v850es/jh3-e and v850es/jj3-e include eight kinds of serial interfaces (asynchronous serial interface c (uartc), asynchronous serial interface b with fifo (uar tb), 3-wire variable-length serial interface f (csif), 3- wire variable-length serial interface e with fifo (csie), an i 2 c bus interface (i 2 c), a can controller (can) note , a usb function controller (usbf), and a ethernet controller). uartc transfers data via the txdc0 to txdc5 and rxdc0 to rxdc5 pins. uartb transfers data via the txdb0, txdb1, rxdb0, and rxdb1 pins. csif transfers data via the sof0 to sof6 , sif0 to sif6, and sckf0 to sckf6 pins. csie transfers data via the soe0, soe1, sie0, sie1, scke0, and scke1 pins. i 2 c transfers data via the sda00 to sda04 and scl00 to scl04 pins. can note transfers data via the crxd0 note and ctxd0 note pins. usbf transfers data via the udmf and udpf pins. ethernet transfers data via the p1col, p1crs, p1mdc, p1mdio, p1rxclk, p1rxd0, p1rxd1, p1rxd2, p1rxd3, p1rxdv, p1rxer, p1txcl k, p1txd0, p1txd1, p1txd2, p1 txd3, p1txen, and p1txer pins. note pd70f3783, 70f3786 only (12) a/d converter this 10-bit a/d converter includes 10 or 12 analog input pins. conversion is performed using the successive approximation method. (13) dma controller a 4-channel dma controller is provided on chip. this c ontroller transfers data between the internal ram, on-chip peripheral i/o devices, and external memory in response to interrupt requests sent by on-chip peripheral i/o devices. (14) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the key input pins (8 channels). (15) real-time output function the real-time output function transfe rs preset 6/8-bit data to output la tches upon the occurrence of a timer compare register match signal. v850es/jh3-e, v850es/jj3-e chapter 1 introduction r01uh0290ej0300 rev.3.00 page 37 of 1817 sep 19, 2011 (16) crc function a crc operation circuit that generates a 16-bit crc (cycl ic redundancy check) code upon setting of 8-bit data is provided on-chip. (17) dcu (debug control unit) an on-chip debug function that uses the jtag (joint test action group) communication s pecifications is provided. switching between the normal port function and on-chip de bugging function is done with the control pin input level and the ocdm register. (18) ports the following general-purpose port functions and control pin functions are available. ? v850es/jh3-e port i/o alternate function p0 2-bit i/o nmi, external interrupt, a/d converter trigger, external clock input p2 7-bit i/o timer i/o, serial interface, external interrupt, real-time counter p3 8-bit i/o external interrupt, serial interface, timer i/o p4 6-bit i/o external interrupt, serial interface, timer i/o p5 5-bit i/o timer i/o, serial interface, real-time output, key interrupt input, debug i/o p7 10-bit i/o a/d converter analog input p9 16-bit i/o serial interface, key interrupt input, timer i/o, external interrupt, address bus pcm 2-bit i/o external bus control signal pcs 2-bit i/o external bus control signal pct 4-bit i/o external bus control signal pdh 6-bit i/o external address bus, serial interface pdl 16-bit i/o external address/data bus ? v850es/jj3-e port i/o alternate function p0 2-bit i/o nmi, external interrupt, a/d converter trigger, external clock input p2 8-bit i/o timer i/o, serial interface, external interrupt, real-time counter p3 8-bit i/o external interrupt, serial interface, timer i/o p4 9-bit i/o external interrupt, serial interface, timer i/o p5 10-bit i/o timer i/o, serial interface, real-time output, key interrupt input, debug i/o p7 12-bit i/o a/d converter analog input p9 16-bit i/o serial interface, key interrupt input, timer i/o, external interrupt, address bus pcm 4-bit i/o external bus control signal pcs 3-bit i/o external bus control signal pct 4-bit i/o external bus control signal pdh 8-bit i/o external address bus, serial interface pdl 16-bit i/o external address/data bus v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 38 of 1817 sep 19, 2011 chapter 2 pin functions 2.1 list of pin functions the names and functions of the pins of the v 850es/jh3-e and v850es/jj3-e are described below. there are three types of pin i/o buffer power supplies: av ref0 , ev dd , and uv dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies corresponding pins power supply v850es/jh3-e v850es/jj3-e av ref0 port 7 port 7 ev dd reset, ports 0, 2 to 5, 9, cm, cs, ct, dh, dl reset, ports 0, 2 to 5, 9, cm, cs, ct, dh, dl uv dd udpf, udmf udpf, udmf v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 39 of 1817 sep 19, 2011 (1) port pins (1/3) pin no. pin name i/o function alternate function jh3-e jj3-e p02 nmi 21 21 p03 i/o port 0 2-bit i/o port input/output can be specified in 1-bit units. 5 v tolerant. intp00/adtrg/exclk 22 22 p20 tiab02/toab02/intp01 38 38 p21 tiab00/toab00/rtgdiv/rtccl 39 39 p22 tiab01/toab01/rtc1hz/intp02 40 40 p23 sif1/txdc1/sda00/intp03 59 65 p24 sof1/rxdc1/sdl00/intp04 62 68 p25 sckf1/tiaa30/toaa30/udmarq0 63 69 p26 tiaa31/toaa31/intp05/udmaak0 64 70 p27 i/o port 2 7-bit i/o port (v850es/jh3-e) 8-bit i/o port (v850es/jj3-e) input/output can be specified in 1-bit units. 5 v tolerant. tiab03/toab03/intp21 ? 41 p30 txdc0/sif2/tiaa00/toaa00 28 28 p31 rxdc0/sof2/tiaa01/toaa01 29 29 p32 asckc0/sckf2/tiaa10/toaa10 30 30 p33 sif4/txdb0/tiaa11/toaa11 31 31 p34 sof4/rxdb0/tiaa20/toaa20 32 32 p35 sckf4/tiaa21/toaa21/toaa21off/intp06 33 33 p36 txdc2/sda02/ctxd0 note 36 36 p37 i/o port 3 8-bit i/o port input/output can be specified in 1-bit units. 5 v tolerant. rxdc2/scl02/crxd0 note 37 37 p40 sif0/txdc3/sda01/rtp00 3 3 p41 sof0/rxdc3/scl01/rtp01 4 4 p42 sckf0/tiaa40/toaa40/rtp02 5 5 sie0/txdc4/rtp03 ? 6 p43 sie0/txdc4/rtp03/hldak 6 ? soe0/rxdc4/rtp04 ? 7 p44 soe0/rxdc4/rtp04/hldrq 7 ? p45 scke0/tiaa41/toaa41/rtp05 8 8 p46 sif5/txdc6/rtp06 ? 128 p47 sof5/rxdc6/rtp07 ? 129 p48 i/o port 4 6-bit i/o port (v850es/jh3-e) 9-bit i/o port (v850es/jj3-e) input/output can be specified in 1-bit units. 5 v tolerant (p46 to p48). sckf5/intp22 ? 130 note internal can controller only remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 40 of 1817 sep 19, 2011 (2/3) pin no. pin name i/o function alternate function jh3-e jj3-e p50 intp07/ddi 23 23 p51 intp08/ddo 24 24 p52 intp09/dck 25 25 p53 intp10/dms 26 26 p54 intp11/drst 27 27 p55 sda04/intp23/udmarq1 ? 42 p56 scl04/intp24/udmaak1 ? 43 p57 sif6/txdc7 ? 62 p58 sof6/rxdc7 ? 63 p59 i/o port 5 5-bit i/o port (v850es/jh3-e) 10-bit i/o port (v850es/jj3-e) input/output can be specified in 1-bit units. 5 v tolerant. sckf6/intp25 ? 64 p70 ani0 128 144 p71 ani1 127 143 p72 ani2 126 142 p73 ani3 125 141 p74 ani4 124 140 p75 ani5 123 139 p76 ani6 122 138 p77 ani7 121 137 p78 ani8 120 136 p79 ani9 119 135 p710 ani10 ? 134 p711 i/o port 7 10-bit i/o port (v850es/jh3-e) 12-bit i/o port (v850es/jj3-e) input/output can be specified in 1-bit units. ani11 ? 133 p90 toab1t1/toab11/tiab11/kr0/intp12/a0 65 71 p91 toab1b1/tiab10/kr1/toab10/a1 66 72 p92 toab1t2/toab12/tiab12/kr2/intp13/a2 67 73 p93 toab1b2/trgab1/kr3/intp14/a3 68 74 p94 toab1t3/toab13/tiab13/kr4/intp15/a4 69 75 p95 toab1b3/evtb1/kr5/intp16/a5 70 76 p96 tecr0/tit00/kr6/tot00/a6 71 77 p97 tenc00/tit01/kr7/tot01/a7 72 78 p98 tenc01/intp17/a8 73 79 p99 sie1/txdc5/sda03/a9 74 80 p910 soe1/rxdc5/scl03/a10 75 81 p911 scke1/tiaa50/toaa50/a11 76 82 p912 toab1off/intp18/a12 77 83 p913 sif3/txdb1/intp19/a13 78 84 p914 sof3/rxdb1/intp20/a14 79 85 p915 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. 5 v tolerant. sckf3/tiaa51/toaa51/a15 80 86 remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 41 of 1817 sep 19, 2011 (3/3) pin no. pin name i/o function alternate function jh3-e jj3-e pcm0 wait 86 92 pcm1 clkout 81 87 pcm2 hldak ? 119 pcm3 i/o port cm 2-bit i/o port (v850es/jh3-e) 4-bit i/o port (v850es/jj3-e) input/output can be specified in 1-bit units. hldrq ? 120 pcs0 cs0 115 125 pcs2 cs2 116 126 pcs3 i/o port cs 2-bit i/o port (v850es/jh3-e) 3-bit i/o port (v850es/jj3-e) input/output can be specified in 1-bit units. cs3 ? 127 pct0 wr0 111 121 pct1 wr1 112 122 pct4 rd 113 123 pct6 i/o port ct 4-bit i/o port input/output can be specified in 1-bit units. astb 114 124 pdh0 a16/sie1 105 111 pdh1 a17/soe1 106 112 pdh2 a18/scke1 107 113 pdh3 a19/sif4/txdb0 108 114 pdh4 a20/sof4/rxdb0 109 115 pdh5 a21/sckf4 110 116 pdh6 a22 ? 117 pdh7 i/o port dh 6-bit i/o port (v850es/jh3-e) 8-bit i/o port (v850es/jj3-e) input/output can be specified in 1-bit units. a23 ? 118 pdl0 ad0 87 93 pdl1 ad1 88 94 pdl2 ad2 89 95 pdl3 ad3 90 96 pdl4 ad4 91 97 pdl5 ad5/flmd1 92 98 pdl6 ad6 93 99 pdl7 ad7 94 100 pdl8 ad8 95 101 pdl9 ad9 96 102 pdl10 ad10 97 103 pdl11 ad11 98 104 pdl12 ad12 99 105 pdl13 ad13 100 106 pdl14 ad14 103 109 pdl15 i/o port dl 16-bit i/o port input/output can be specified in 1-bit units. ad15 104 110 remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 42 of 1817 sep 19, 2011 (2) non-port pins (1/9) pin no. pin name i/o function alternate function jh3-e jj3-e a0 p90/toab1t1/toab11/tiab11/ kr0/intp12 65 71 a1 p91/toab1b1/tiab10/kr1/ toab10 66 72 a2 p92/toab1t2/toab12/tiab12/ kr2/intp13 67 73 a3 p93/toab1b2/trgab1/kr3/ intp14 68 74 a4 p94/toab1t3/toab13/tiab13/ kr4/intp15 69 75 a5 p95/toab1b3/evtab1/kr5/ intp16 70 76 a6 p96/tecr0/tit00/kr6/tot00 71 77 a7 p97/tenc00/tit01/kr7/tot01 72 78 a8 p98/tenc01/intp17 73 79 a9 p99/sie1/txdc5/sda03 74 80 a10 p910/soe1/rxdc5/scl03 75 81 a11 p911/scke1/tiaa50/toaa50 76 82 a12 p912/toab1off/intp18 77 83 a13 p913/sif3/txdb1/intp19 78 84 a14 p914/sof3/rxdb1/intp20 79 85 a15 p915/sckf3/tiaa51/toaa51 80 86 a16 pdh0/sie1 105 111 a17 pdh1/soe1 106 112 a18 pdh2/scke1 107 113 a19 pdh3/sif4/txdb0 108 114 a20 pdh4/sof4/rxdb0 109 115 a21 pdh5/sckf4 110 116 a22 pdh6 ? 117 a23 output address bus for external memory (when using separate bus) 5 v tolerant (a0 to a15). pdh7 ? 118 remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 43 of 1817 sep 19, 2011 (2/9) pin no. pin name i/o function alternate function jh3-e jj3-e ad0 pdl0 87 93 ad1 pdl1 88 94 ad2 pdl2 89 95 ad3 pdl3 90 96 ad4 pdl4 91 97 ad5 pdl5/flmd1 92 98 ad6 pdl6 93 99 ad7 pdl7 94 100 ad8 pdl8 95 101 ad9 pdl9 96 102 ad10 pdl10 97 103 ad11 pdl11 98 104 ad12 pdl12 99 105 ad13 pdl13 100 106 ad14 pdl14 103 109 ad15 i/o address/data bus for external memory pdl15 104 110 adtrg input external trigger input for a/d converter, 5 v tolerant. p03/intp00/exclk 22 22 ani0 p70 128 144 ani1 p71 127 143 ani2 p72 126 142 ani3 p73 125 141 ani4 p74 124 140 ani5 p75 123 139 ani6 p76 122 138 ani7 p77 121 137 ani8 p78 120 136 ani9 p79 119 135 ani10 p710 ? 134 ani11 input analog voltage input for a/d converter p711 ? 133 asckc0 input uartc0 baud rate clock input, 5 v tolerant. p32/sckf2/tiaa10/toaa10 30 30 astb output address strobe signal output for external memory pct6 114 124 av ref0 ? reference voltage input for a/d converter, port ground potential ? 1 1 av ss ? ground potential for a/d converters ? 2 2 clkout output internal system clock output pcm1 81 87 crxd0 note input can receive data input, 5 v tolerant. p37/rxdc2/scl02 37 37 cs0 pcs0 115 125 cs2 pcs2 116 126 cs3 output chip select output pcs3 ? 127 ctxd0 note output can transmit data output, 5 v tolerant. p36/txdc2/sda02 36 36 note internal can controller only remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 44 of 1817 sep 19, 2011 (3/9) pin no. pin name i/o function alternate function jh3-e jj3-e dck input clock input for on-chip debug, 5 v tolerant. p52/intp09 25 25 ddi input data input for on-chip debug, 5 v tolerant. p50/intp07 23 23 ddo output data output for on-chip debugging, in the on-chip debug mode, high-level output is forcibly set, 5 v tolerant. p51/intp08 24 24 dms input mode select signal input for on-chip debugging, 5 v tolerant. p53/intp10 26 26 drst input reset signal inpu t for on-chip debugging, 5 v tolerant. p54/intp11 27 27 ev dd ? positive power supply for external devices (same potential as v dd ) ? 35, 61, 85, 102, 118 35, 67, 91, 108, 132 evtab1 input tab1 external event count input toab1b3/kr5/intp16/a5 70 76 exclk input external usb clock signal input p03/intp00/adtrg 22 22 flmd0 input ? 12 12 flmd1 input flash memory programming mode setting pin pdl5/ad5 92 98 pcm2 ? 119 hldak output bus hold acknowledge output p43/sie0/txdc4/rtp03 6 ? pcm3 ? 120 hldrq input bus hold request input p44/soe0/rxdc4/rtp04 7 ? intp00 p03/adtrg/exclk 22 22 intp01 p20/tiab02/toab02 38 38 intp02 p22/tiab01/toab01/rtc1hz 40 40 intp03 p23/sif1/txdc1/sda00 59 65 intp04 p24/sof1/rxdc1/sdl00 62 68 intp05 p26/tiaa31/toaa31/udmaak0 64 70 intp06 p35/sckf4/tiaa21/toaa21/ toaa1off 33 33 intp07 p50/ddi 23 23 intp08 p51/ddo 24 24 intp09 p52/dck 25 25 intp10 p53/dms 26 26 intp11 p54/drst 27 27 intp12 p90/toab1t1/toab11/tiab11/ kr0/a0 65 71 intp13 p92/toab1t2/toab12/tiab12/ kr2/a2 67 73 intp14 p93/toab1b2/trgab1/kr3/a3 68 74 intp15 p94/toab1t3/toab13/tiab13/ kr4/a4 69 75 intp16 p95/toab1b3/evtab1/kr5/a5 70 76 intp17 p98/tenc01/a8 73 79 intp18 p912/toab1off/a12 77 83 intp19 input external interrupt request input (maskable, analog noise elimination) analog noise elimination or digital noise elimination selectable for intp02 pin. 5 v tolerant. p913/sif3/txdb1/a13 78 84 remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 45 of 1817 sep 19, 2011 (4/9) pin no. pin name i/o function alternate function jh3-e jj3-e intp20 p914/sof3/rxdb1/a14 79 85 intp21 p27/tiab03/toab03 ? 41 intp22 p48/sckf5 ? 130 intp23 p55/sda04/udmarq1 ? 42 intp24 p56/scl04/udmaak1 ? 43 intp25 input external interrupt request input (maskable, analog noise elimination) 5 v tolerant. p59/sckf6 ? 64 kr0 p90/toab1t1/toab11/tiab11/ intp12/a0 65 71 kr1 p91/toab1b1/tiab10/toab10/ a1 66 72 kr2 p92/toab1t2/toab12/tiab12/ intp13/a2 67 73 kr3 p93/toab1b2/trgab1/intp14/ a3 68 74 kr4 p94/toab1t3/toab13/tiab13/ intp15/a4 69 75 kr5 p95/toab1b3/evtab1/intp16/ a5 70 76 kr6 p96/tecr0/tit00/tot00/a6 71 77 kr7 input key interrupt input (on-chip analog noise eliminator) 5 v tolerant. p97/tenc00/tit01/tot01/a7 72 78 nmi input external interrupt input (non-maskable, analog noise elimination) 5 v tolerant. p02 21 21 p1col input conflict detection input for ethernet ? 56 59 p1crs input carrier detection input for ethernet ? 55 58 p1mdc output serial transfer clock output ? 57 60 p1mdio i/o serial i/o ? 58 61 p1rxclk input receive clock input for ethernet ? 54 57 p1rxd0 input receive data input for ethernet ? 48 51 p1rxd1 input receive data input for ethernet ? 49 52 p1rxd2 input receive data input for ethernet ? 50 53 p1rxd3 input receive data input for ethernet ? 51 54 p1rxdv input receive data valid input for ethernet ? 52 55 p1rxer input receive data error input for ethernet ? 53 56 p1txclk input transmit clock input for ethernet ? 47 50 p1txd0 output transmit data output for ethernet ? 41 44 p1txd1 output transmit data output for ethernet ? 42 45 p1txd2 output transmit data output for ethernet ? 43 46 p1txd3 output transmit data output for ethernet ? 44 47 p1txen output transmit data enable output for ethernet ? 46 49 p1txer output transmit error output for ethernet ? 45 48 remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 46 of 1817 sep 19, 2011 (5/9) pin no. pin name i/o function alternate function jh3-e jj3-e rd output read strobe signal output for external memory pct4 113 123 regc ? connection of regulator output stabilization capacitance (4.7 f: recommend value) ? 14, 83 14, 89 reset input system reset input ? 18 18 rtc1hz output real-time counter correction clock (1 hz) output, 5 v tolerant. p22/tiab01/toab01/intp02 40 40 rtccl output real-time counter clock (32 khz primary oscillation) output, 5 v tolerant. p21/tiab00/toab00/rtcdiv 39 39 rtcdiv output real-time counter clock (32 khz division) output, 5 v tolerant. p21/tiab00/toab00/rtccl 39 39 rtp00 p40/sif0/txdc3/sda01 3 3 rtp01 p41/sof0/rxdc3/scl01 4 4 rtp02 p42/sckf0/tiaa40/toaa40 5 5 p43/sie0/txdc4 ? 6 rtp03 p43/sie0/txdc4/hldak 6 ? p44/soe0/rxdc4 ? 7 rtp04 p44/soe0/rxdc4/hldrq 7 ? rtp05 p45/scke0/tiaa41/toaa41 8 8 rtp06 p46/sif5/txdc6 ? 128 rtp07 output real-time output port rtp00, rtp01, rtp06, and rtp07 are n-ch open-drain output selectable, 5 v tolerant (rtp06, rtp07). p47/sof5/rxdc6 ? 129 serial receive data input (uartb0), 5 v tolerant. p34/sof4/tiaa20/toaa20 32 32 rxdb0 serial receive data input (uartb0) pdh4/a20/sof4 109 115 rxdb1 input serial receive data input (uartb1), 5 v tolerant. p914/sof3/intp20/a14 79 85 rxdc0 p31/sof2/tiaa01/toaa01 29 29 rxdc1 p24/sof1/rxdc1/sdl00/intp04 62 68 rxdc2 p37/scl02/crxd0 note 37 37 rxdc3 p41/sof0/scl01/rtp01 4 4 p44/soe0/rtp04 ? 7 rxdc4 p44/soe0/rtp04/hldrq 7 ? rxdc5 p910/soe1/scl03/a10 75 81 rxdc6 p47/sof5/rtp07 ? 129 rxdc7 input serial receive data input (uartc0 to uartc7) 5 v tolerant (rxdc0 to rxdc2, rxdc5, rxdc6). p58/sof6 ? 63 scke0 serial clock i/o (csie0) p45/tiaa41/toaa41/rtp05 8 8 serial clock i/o (csie1) , 5 v tolerant. p911/tiaa50/toaa50/a11 76 82 scke1 i/o serial clock i/o (csie1) pdh2/a18 107 113 sckf0 p42/tiaa40/toaa40/rtp02 5 5 sckf1 p25/tiaa30/toaa30/umdarq0 63 69 sckf2 p32/asckc0/tiaa10/toaa10 30 30 sckf3 serial clock i/o (csif0 to csif3) 5 v tolerant (sckf1 to sckf3). p915/tiaa51/toaa51/a15 80 86 serial clock i/o (csif4) 5 v tolerant. p35/tiaa21/toaa21/toaa1off/ intp06 33 33 sckf4 serial clock i/o (csif4) pdh5/a21 110 116 sckf5 p48/intp22 ? 130 sckf6 i/o serial clock i/o (csif5, csif6) 5 v tolerant. p59/intp25 ? 64 note internal can controller only remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 47 of 1817 sep 19, 2011 (6/9) pin no. pin name i/o function alternate function jh3-e jj3-e scl00 p24/sof1/rxdc1/intp04 62 68 scl01 p41/sof0/rxdc3/rtp01 4 4 scl02 p37/rxdc2/crxd0 note 37 37 scl03 p910/soe1/rxdc5/a10 75 81 scl04 i/o serial clock i/o (i 2 c00 to i 2 c04) n-ch open-drain output selectable 5 v tolerant (scl00, scl02 to scl04). p56/intp24/udmaak1 ? 43 sda00 p23/sif1/txdc1/intp03 59 65 sda01 p40/sif0/txdc3/rtp00 3 3 sda02 p36/txdc2/ctxd0 note 36 36 sda03 p99/sie1/txdc5/a9 74 80 sda04 i/o serial transmit/receive data i/o (i 2 c00 to i 2 c04) n-ch open-drain output selectable 5 v tolerant (sda00, sda02 to sda04) . p55/intp23/udmarq1 ? 42 p43/txdc4/rtp03 ? 6 sie0 serial receive data input (csie0) p43/txdc4/rtp03/hldak 6 ? serial receive data input (csie1), 5 v tolerant p99/txdc5/sda03/a9 74 80 sie1 input serial receive data input (csie1) pdh0/a16 105 111 sif0 p40/txdc3/sda01/rtp00 3 3 sif1 p23/txdc1/sda00/intp03 59 65 sif2 p30/txdc0/tiaa00/toaa00 28 28 sif3 serial receive data input (csif0 to csif3) 5 v tolerant (sif1 to sif3). p913/txdb1/intp19/a13 78 84 serial receive data input (csif4), 5 v tolerant. p33/txdb0/tiaa11/toaa11 31 31 sif4 serial receive data input (csif4) pdh3/txdb0 108 114 sif5 p46/txdc6/rtp06 ? 128 sif6 input serial receive data input (csif5, csif6) 5 v tolerant. p57/txdc7 ? 62 p44/rxdc4/rtp04 ? 7 soe0 serial transmit data output (csie0) p44/rxdc4/rtp04/hldrq 7 ? serial transmit data output (csie1), 5 v tolerant. p910/rxdc5/scl03/a10 75 81 soe1 output serial transmit data output (csie1) pdh1/a17 106 112 sof0 p41/rxdc3/scl01/rtp01 4 4 sof1 p24/rxdc1/sdl00/intp04 62 68 sof2 p31/rxdc0/tiaa01/toaa01 29 29 sof3 serial transmit data output (csif0 to csif3) n-ch open-drain output selectable 5 v tolerant (sof1 to sof3). p914/rxdb1/intp20/a14 79 85 serial transmit data output (csif4) n-ch open-drain output selectable, 5 v tolerant p34/rxdb0/tiaa20/toaa20 32 32 sof4 serial transmit data output (csif4) pdh4/a20/rxdb0 109 115 sof5 p47/rxdc6/rtp07 ? 129 sof6 output serial transmit data output (csif5, csif6) n-ch open-drain output selectable, 5 v tolerant. p58/rxdc7 ? 63 tecr0 tmt0 encoder clear input n-ch open-drain output selectable, 5 v tolerant. p96/tit00/kr6/tot00/a6 71 77 tenc00 encoder input/external event count input/ external trigger input n-ch open-drain output selectable, 5 v tolerant. p97/tit01/kr7/tot01/a7 72 78 tenc01 input encoder input n-ch open-drain output selectable, 5 v tolerant. p98/intp17/a8 73 79 note internal can controller only remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 48 of 1817 sep 19, 2011 (7/9) pin no. pin name i/o function alternate function jh3-e jj3-e tiaa00 external event count input/capture trigger input/external trigger input (taa0) , 5 v tolerant. p30/txdc0/sif2/toaa00 28 28 tiaa01 capture trigger input (taa0) , 5 v tolerant. p31/rxdc0/sof2/toaa01 29 29 tiaa10 external event count input/capture trigger input/external trigger input (taa1) , 5 v tolerant. p32/asckc0/sckf2/toaa10 30 30 tiaa11 capture trigger input (taa1) , 5 v tolerant. p33/sif4/txdb0/toaa11 31 31 tiaa20 external event count input/capture trigger input/external trigger input (taa2) , 5 v tolerant. p34/sof4/rxdb0/toaa20 32 32 tiaa21 capture trigger input (taa2) , 5 v tolerant. p35/sckf4/toaa21/toaa1off/ intp06 33 33 tiaa30 external event count input/capture trigger input/external trigger input (taa3) , 5 v tolerant. p25/sckf1/toaa30/udmarq0 63 69 tiaa31 capture trigger input (taa3) , 5 v tolerant. p26/toaa31/intp05/udmaak0 64 70 tiaa40 external event count input/capture trigger input/external trigger input (taa4) p42/sckf0/toaa40/rtp02 5 5 tiaa41 capture trigger input (taa4) p45/scke0/toaa41/rtp05 8 8 tiaa50 external event count input/capture trigger input/external trigger input (taa5) , 5 v tolerant. p911/scke1/toaa50/a11 76 82 tiaa51 input capture trigger input (taa5) , 5 v tolerant. p915/sckf3/toaa51/a15 80 86 tiab00 external event count input/capture trigger input /external trigger input (tab0) , 5 v tolerant. p21/toab00/rtcdiv/rtccl 39 39 tiab01 p22/toab01/rtc1hz/intp02 40 40 tiab02 p20/toab02/intp01 38 38 tiab03 input capture trigger input (tab0) , 5 v tolerant. p27/toab03/intp21 ? 41 tiab10 input capture trigger input/external event count input/external trigger input (tab1) n-ch open-drain output selectable, 5 v tolerant. p91/toab1b1/kr1/toab10/a1 66 72 tiab11 p90/toab1t1/toab11/kr0/ intp12/a0 65 71 tiab12 p92/toab1t2/toab12/kr2/ intp13/a2 67 73 tiab13 input capture trigger input (tab1) n-ch open-drain output selectable 5 v tolerant. p94/toab1t3/toab13/kr4/ intp15/a4 69 75 tit00 input p96/tecr0/kr6/tot00/a6 71 77 tit01 input tmt0 capture trigger input n-ch open-drain output selectable, 5 v tolerant. p97/tenc00/kr7/tot01/a7 72 78 toaa00 p30/txdc0/sif2/tiaa00 28 28 toaa01 timer output (taa0) n-ch open-drain output selectable, 5 v tolerant. p31/rxdc0/sof2/tiaa01 29 29 toaa10 p32/asckc0/sckf2/tiaa10 30 30 toaa11 output timer output (taa1) n-ch open-drain output selectable, 5 v tolerant. p33/sif4/txdb0/tiaa11 31 31 toaa1off input taa1 high-impedance output control signal input 5 v tolerant. p35/sckf4/tiaa21/toaa21 /intp06 33 33 remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 49 of 1817 sep 19, 2011 (8/9) pin no. pin name i/o function alternate function jh3-e jj3-e toaa20 p34/sof4/rxdb0/tiaa20 32 32 toaa21 timer output (taa2) n-ch open-drain output selectable, 5 v tolerant. p35/sckf4/tiaa21/toaa1off/ intp06 33 33 toaa30 p25/sckf1/tiaa30/udmarq0 63 69 toaa31 timer output (taa3) n-ch open-drain output selectable, 5 v tolerant. p26/tiaa31/intp05/udmaak0 64 70 toaa40 p42/sckf0/tiaa40/rtp02 5 5 toaa41 timer output (taa4) n-ch open-drain output selectable p45/scke0/tiaa41/rtp05 8 8 toaa50 p911/scke1/tiaa50/a11 76 82 toaa51 output timer output (taa5) n-ch open-drain output selectable, 5 v tolerant. p915/sckf3/tiaa51/a15 80 86 toab00 p21/tiab00/rtcdiv/rtccl 39 39 toab01 p22/tiab01/rtc1hz/intp02 40 40 toab02 p20/tiab02/intp01 38 38 toab03 output timer output (tab0) n-ch open-drain output selectable, 5 v tolerant. p27/tiab03/intp21 ? 41 toab10 p91/toab1b1/tiab10/kr1/a1 66 72 toab11 p90/toab1t1/tiab11/kr0/ intp12/a0 65 71 toab12 p92/toab1t2/tiab12/kr2/ intp13/a2 67 73 toab13 output timer output (tab1) n-ch open-drain output selectable, 5 v tolerant. p94/toab1t3/tiab13/kr4/ intp15/a4 69 75 toab1b1 p91/tiab10/kr1/toab10/a1 66 72 toab1b2 p93/trgab1/kr3/intp14/a3 68 74 toab1b3 output pulse signal output for 6-phase pwm low-arm of tab1 n-ch open-drain output selectable, 5 v tolerant. p95/evtab1/kr5/intp16/a5 70 76 toab1off input tab1 high-impedance output control signal input, 5 v tolerant. p912/intp18/a12 77 83 toab1b1 p90/toab11/tiab11/kr0/ intp12/a0 65 71 toab1b2 p92/toab12/tiab12/kr2/ intp13/a2 67 73 toab1b3 output pulse signal output for 6-phase pwm high-arm of tab1 n-ch open-drain output selectable, 5 v tolerant. p94/toab13/tiab13/kr4/ intp15/a4 69 75 tot00 p96/tecr0/tit00/kr6/a6 71 77 tot01 output timer output (tmt0) n-ch open-drain output selectable, 5 v tolerant. p97/tenc00/tit01/kr7/a7 72 78 trgab1 input external trigger input of tab1 n-ch open-drain output selectable, 5 v tolerant. p93/toab1b2/kr3/intp14/a3 68 74 serial transmit data output (uartb0), 5 v tolerant. p33/sif4/tiaa11/toaa11 31 31 txdb0 serial transmit data output (uartb0) pdh3/a19/sif4 108 114 txdb1 output serial transmit data output (uartb1), 5 v tolerant. p913/sif3/intp19/a13 78 84 remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 50 of 1817 sep 19, 2011 (9/9) pin no. pin name i/o function alternate function jh3-e jj3-e txdc0 p30/sif2/tiaa00/toaa00 28 28 txdc1 p23/sif1/sda00/intp03 59 65 txdc2 serial transmit data output (uartc0 to uartc2) n-ch open-drain output selectable 5 v tolerant. p36/sda02/ctxd0 note 36 36 txdc3 p40/sif0/sda01/rtp00 3 3 p43/sie0/rtp03 ? 6 txdc4 serial transmit data output (uartc3, uartc4) p43/sie0/rtp03/hldak 6 ? txdc5 p99/sie1/sda03/a9 74 80 txdc6 p46/sif5/rtp06 ? 128 txdc7 output serial transmit data output (uartc5 to uartc7) n-ch open-drain output selectable 5 v tolerant. p57/sif6 ? 62 exclk input external usb clock signal i nput, 5 v tolerant. p03/intp00/adtrg 22 22 udmaak0 p26/tiaa31/toaa31/intp05 64 70 udmaak1 output dma acknowledge for usb, 5 v tolerant. p56/scl04/intp24 ? 43 udmarq0 p25/sckf1/tiaa30/toaa30 63 69 udmarq1 input dma request for usb, 5 v tolerant. p55/sdl04/intp23 ? 42 udmf usb data i/o ( ? ) function ? 9 9 udpf i/o usb data i/o (+) function ? 10 10 uv dd ? 3.3 v positive power supply for usb ? 11 11 v dd ? positive power supply pin for internal unit ? 13, 82 13, 88 v ss ? ground potential for internal unit ? 15, 34, 60, 84, 101, 117 15, 34, 66, 90, 107, 131 wait input external wait input pcm0 86 92 wr0 write strobe for external memory (lower 8 bits) pct0 111 121 wr1 output write strobe for external memory (higher 8 bits) pct1 112 122 x1 input ? 16 16 x2 ? connecting resonator for main clock ? 17 17 xt1 input ? 19 19 xt2 ? connecting resonator for subclock ? 20 20 note internal can controller only remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 51 of 1817 sep 19, 2011 2.2 pin states the operation states of pins in the vari ous operation modes are described below. table 2-2. pin operation stat us in each operation mode pin name when power is turned on note 1 during reset (other than when power is turned on) halt mode note 2 idle1, idle2, sub-idle mode note 2 stop mode note 2 idle state note 3 bus hold drst pull down pull down note 4 held held held held held ddo undefined hi-z note 5 held held held held held ad0 to ad15 undefined note 7 a0 to a15 note 8 a16 to a23 undefined note 7 hi-z hi-z held hi-z wait note 7 ? ? ? ? wr0, wr1 rd astb cs0, cs2, cs3 h note 7 hi-z hldak h h h l hldrq ? ? ? operating clkout hi-z note 6 hi-z note 6 operating l l operating operating other port pins hi-z hi-z held held held held held notes 1. duration until 1 ms elapses after the supply voltage reaches the operating supply voltage range (lower limit) when the power is turned on. 2. operates while alternat e functions are operating. 3. the state of the pins in the idle state inserted after the t3 state is shown. 4. pulled down during external reset. during internal reset by the watchdog timer or clock monitor, etc., the state of this pin differs according to the ocdm.ocdm0 bit setting. 5. in the on-chip debug mode, data is output from the ddo pin. 6. the bus control pins function alternately as port pins, so they are initialized to the input mode (port mode). 7. operates even in the halt mode, during dma operation. 8. the a0 to a15 pins are used in the separate bus mode. remark hi-z high impedance held: the state during the immediately preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged) v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 52 of 1817 sep 19, 2011 2.3 pin i/o circuit types, i/o buffer powe r supplies and connection of unused pins table 2-3. pin i/o circuit types a nd connection of unused pins (1/4) pin name alternate function i/o ci rcuit type recommended connection jh3-e jj3-e p02 nmi p03 intp00/adtrg/exclk 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. p20 tiab02/toab02/intp01 p21 tiab00/toab00/rtcdiv/rtccl p22 tiab01/toab01/rtc1hz/intp02 p23 sif1/txdc1/sda00/intp03 p24 sof1/rxdc1/sdl00/intp04 p25 sckf1/tiaa30/toaa30/udmarq0 p26 tiaa31/toaa31/intp05/udmaak0 p27 tiab03/toab03/intp21 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. ? p30 txdc0/sif2/tiaa00/toaa00 p31 rxdc0/sof2/tiaa01/toaa01 p32 asckc0/sckf2/tiaa10/toaa10 p33 sif4/txdb0/tiaa11/toaa11 p34 sof4/rxdb0/tiaa20/toaa20 p35 sckf4/tiaa21/toaa21/ toaa1off/intp06 p36 txdc2/sda02/ctxd0 note p37 rxdc2/scl02/crxd0 note 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. p40 sif0/txdc3/sda01/rtp00 p41 sof0/rxdc3/scl01/rtp01 p42 sckf0/tiaa40/toaa40/rtp02 sie0/txdc4/rtp03 ? p43 sie0/txdc4/rtp03/hldak ? soe0/rxdc4/rtp04 ? p44 soe0/rxdc4/rtp04/hldrq ? p45 scke0/tiaa41/toaa41/rtp05 p46 sif5/txdc6/rtp06 ? p47 sof5/rxdc6/rtp07 ? p48 sckf5/intp22 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. ? note internal can controller only remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 53 of 1817 sep 19, 2011 table 2-3. pin i/o circuit types a nd connection of unused pins (2/4) pin name alternate function i/o ci rcuit type recommended connection jh3-e jj3-e p50 intp07/ddi p51 intp08/ddo p52 intp09/dck p53 intp10/dms 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. p54 intp11/drst 10-n input: independently connect to ev ss via a resistor. fixing to v dd level is prohibited. output: leave open. internally pulled down after reset by reset pin. p55 sda04/intp23/udmarq1 ? p56 scl04/intp24/udmaak1 ? p57 sif6/txdc7 ? p58 sof6/rxdc7 ? p59 sckf6/intp25 10-d ? p70 to p79 ani0 to ani9 p710, p711 ani10, ani11 11-g input: independently connect to av ref0 or av ss via a resistor. output: leave open. ? p90 toab1t1/toab11/tiab11/kr0/ intp12/a0 p91 toab1b1/tiab10/kr1/toab10/a1 p92 toab1t2/toab12/tiab12/kr2/ intp13/a2 p93 toab1b2/trgab1/kr3/intp14/a3 p94 toab1t3/toab13/tiab13/kr4/ intp15/a4 p95 toab1b3/evtb1/kr5/intp16/a5 p96 tecr0/tit00/kr6/tot00/a6 p97 tenc00/tit01/kr7/tot01/a7 p98 tenc01/intp17/a8 p99 sie1/txdc5/sda03/a9 p910 soe1/rxdc5/scl03/a10 p911 scke1/tiaa50/toaa50/a11 p912 toab1off/intp18/a12 p913 sif3/txdb1/intp19/a13 p914 sof3/rxdb1/intp20/a14 p915 sckf3/tiaa51/toaa51/a15 10-d input: independently connect to ev dd or v ss via a resistor. output: leave open. pcm0 wait pcm1 clkout pcm2 hldak ? pcm3 hldrq 5 input: independently connect to ev dd or v ss via a resistor. output: leave open. ? remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 54 of 1817 sep 19, 2011 table 2-3. pin i/o circuit types a nd connection of unused pins (3/4) pin name alternate function i/o ci rcuit type recommended connection jh3-e jj3-e pcs0 cs0 pcs2 cs2 pcs3 cs3 5 input: independently connect to ev dd or v ss via a resistor. output: leave open. ? pct0 wr0 pct1 wr1 pct4 rd pct6 astb 5 input: independently connect to ev dd or v ss via a resistor. output: leave open. pdh0 a16/sie1 10-d pdh1 a17/soe1 5 pdh2 a18/scke1 pdh3 a19/sif4/txdb0 pdh4 a20/sof4/rxdb0 pdh5 a21/sckf4 10-d pdh6, pdh7 a22, a23 5 input: independently connect to ev dd or v ss via a resistor. output: leave open. ? pdl0 to pdl4 ad0 to ad4 pdl5 ad5/flmd1 pdl6 to pdl15 ad6 to ad15 5 input: independently connect to ev dd or v ss via a resistor. output: leave open. av ref0 ? ? directly connect to v dd and always supply power. (the same applies during standby.) av ss ? ? always directly connect to ground. (the same applies during standby.) ev dd ? ? directly connect to v dd and always supply power. flmd0 ? ? directly connect to v ss in other than flash mode. p1col ? 5 p1crs ? 5 p1mdio ? 5 p1rxclk ? 5 p1rxd0 ? 5 p1rxd1 ? 5 p1rxd2 ? 5 p1rxd3 ? 5 p1rxdv ? 5 p1rxer ? 5 p1txclk ? 5 independently connect to ev dd or v ss via a resistor. v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 55 of 1817 sep 19, 2011 table 2-3. pin i/o circuit types a nd connection of unused pins (4/4) pin name alternate function i/o ci rcuit type recommended connection jh3-e jj3-e p1mdc ? 5 p1txd0 ? 5 p1txd1 ? 5 p1txd2 ? 5 p1txd3 ? 5 p1txen ? 5 p1txer ? 5 leave open. regc ? ? connect to regulator output stabilization capacitor (4.7 f (recommend value)). reset ? 2 ? udmf ? ? leave open. udpf ? ? always directly connect to ground via a resistor. uv dd ? ? always directly connect to ground. (the same applies during standby.) v dd ? ? always directly connect to ground. (the same applies during standby.) v ss ? ? always directly connect to ground. (the same applies during standby.) x1 ? ? ? x2 ? ? ? xt1 ? 16-c connect to v ss via a resistor. xt2 ? 16-c leave open. remark jh3-e: v850es/jh3-e, jj3-e: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 56 of 1817 sep 19, 2011 figure 2-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics type 5 in data output disable p-ch in/out ev dd v ss n-ch input enable type 11-g type 10-d data output disable ev dd v ss note p-ch in/out n-ch open drain input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch v ref0 (threshold voltage) comparator input enable + _ av ss av ss data output disable ev dd v ss p-ch in/out n-ch open drain input enable ocdm0 bit note n-ch type 16-c p-ch feedback cut-off xt1 xt2 type 10-n note hysteresis characteristics are not available in port mode. v850es/jh3-e, v850es/jj3-e chapter 2 pin functions r01uh0290ej0300 rev.3.00 page 57 of 1817 sep 19, 2011 2.4 cautions when the power is turned on, the following pins may ou tput an undefined level temporarily even during reset. ? p51/intp08/ddo pin v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 58 of 1817 sep 19, 2011 chapter 3 cpu function the cpu of the v850es/jh3-e and v850es/jj3-e is based on risc architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time: 20 ns (operating with main clock (f xx ) of 50 mhz: v dd = 2.85 to 3.6 v) 30.5 s (operating with subclock (f xt ) of 32.768 khz) memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 59 of 1817 sep 19, 2011 3.2 cpu register set the registers of the v850es/jh3-e and v850es/jj3-e can be classified into two types: general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 60 of 1817 sep 19, 2011 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are ava ilable. any of these register s can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is some times used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that indicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function pc program counter holds the instruction address during program execution remark for further details on the r1, r3 to r5, and r31 that are used in the assembler and c compiler, refer to the ca850 (c compiler package) assembly language user?s manual . (2) program counter (pc) the program counter holds the instructio n address during program execution. the lower 32 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 61 of 1817 sep 19, 2011 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/store inst ructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification system register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) note 1 3 nmi status saving register (fepsw) note 1 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of these registers is availabl e, the contents of these registers must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only during the inte rval between the execution of the dbtrap instruction or illegal opcode and dbret instruction execution. caution even if eipc or fepc, or bi t 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti in struction after interr upt servicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 62 of 1817 sep 19, 2011 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, the contents of the program counter (pc) are saved to eipc, and the contents of the program stat us word (psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and fepsw) if a non-maskable interrupt occurs). the address of the instruction next to the instruction under execution, except some instructions (see 25.8 periods in which interrupts are not acknowledged by cpu ), is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the cont ents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved for future function expansion (these bits are always fixed to 0). the value of eipc is restored to the pc and the val ue of eipsw to the psw by the reti instruction. 31 0 eipc (contents of saved pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (contents of saved psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 63 of 1817 sep 19, 2011 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the pr ogram counter (pc) are saved to f epc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to t he one of the instruction under execution, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. because only one set of nmi status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). the value of fepc is restored to the pc and the value of fepsw to the psw by the reti instruction. 31 0 fepc (contents of saved pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (contents of saved psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) holds the source of an e xception or interrupt if an exception or interrupt occurs. this register holds the exception code of each interrupt s ource. because this register is a read-only register, data cannot be written to this regist er using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 64 of 1817 sep 19, 2011 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the status of the program (result of instruction execution) and the st atus of the cpu. if the contents of a bit of this regist er are changed by using the ldsr instru ction, the new contents are validated immediately after completion of ldsr instruction execution. however if the id flag is set to 1, interrupt requests will not be acknowledged while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being processed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a carry or a borrow o ccurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 65 of 1817 sep 19, 2011 (2/2) note the result of the operation that has performed satu ration processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execut ion status saving registers. when the callt instruction is executed, the contents of the program counter (pc) are saved to ctpc, and those of the program status word (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 66 of 1817 sep 19, 2011 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. this register can be read or written only during the inte rval between the execution of the dbtrap instruction or illegal opcode and the dbret instruction. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). the value of dbpc is restored to the pc and the value of dbpsw to the psw by the dbret instruction. 31 0 dbpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a table address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 67 of 1817 sep 19, 2011 3.3 operation modes the v850es/jh3-e and v850es/jj3-e ha ve the following operation modes. (1) normal operation mode in this mode, each pin related to the bus interface is se t to the port mode after system reset has been released. execution branches to the reset entry address of the intern al rom, and then instruction processing is started. (2) flash memory programming mode in this mode, the internal flash memory can be programmed by using a flash programmer. (3) on-chip debug mode the v850es/jh3-e and v850es/jj3-e are provided with an on-chip debug function that employs the jtag (joint test action group) communication specifications. for details, see chapter 34 on-chip debug function . 3.3.1 specifying operation mode specify the operation mode by using the flmd0 and flmd1 pins. in the normal mode, make sure that a low level is input to the flmd0 pin when reset is released. in the flash memory programming mode, a high level is input to the flmd0 pin from the flash programmer if a flash programmer is connected, but it must be input from an external circuit in the self-programming mode. operation when reset is released flmd0 flmd1 operation mode after reset l normal operation mode h l flash memory programming mode h h setting prohibited remark l: low-level input h: high-level input : don?t care v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 68 of 1817 sep 19, 2011 3.4 address space 3.4.1 cpu address space for instruction addressing, up to a combined total of 16 mb of external memory area and internal rom area, plus an internal ram area, are supported in a linear address space (program space) of up to 64 mb. for operand addressing (data access), up to 4 gb of a linear addr ess space (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical address space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. image on address space program space internal ram area use-prohibited area use-prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 peripheral i/o area internal ram area use-prohibited area external memory area internal rom area (external memory area) 16 mb 4 gb 64 mb 64 mb v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 69 of 1817 sep 19, 2011 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counte r), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the highest address of the program space, 03ffffffh, and t he lowest address, 00000000h, are contiguous addresses. that the highest address and the lo west address of the progra m space are contiguous in this way is called wraparound. caution because the 4 kb area of ad dresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetched fr om this area. therefore, do no t execute an operation in which the result of a branch addre ss calculation affects this area. program space program space (+) direction ( ? ) direction 00000001h 00000000h 03ffffffh 03fffffeh (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the highest address of the data space, ffffffffh, and t he lowest address, 00000000h, are contiguous, and wraparound occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction 00000001h 00000000h ffffffffh fffffffeh v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 70 of 1817 sep 19, 2011 3.4.3 memory map the areas shown below are reserved in the v850es/jh3-e and v850es/jj3-e. figure 3-2. data memory map (physical addresses) cs3 cs2 cs0 cs1 note 2 (80 kb) use prohibited external memory area note 1 (8 mb) internal rom area note 6 (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) external memory area (4 mb) usb function/ ethernet used area (refer to figure3-3. ) (2 mb) use prohibited note 3 programmable peripheral i/o area note 4 use prohibited note 5 00000000h 001fffffh 00200000h 003fffffh 00400000h 007fffffh 00800000h 00ffffffh 03ffffffh 03ffffffh 03fff000h 03ffefffh 03ff0000h 03fef000h 03feefffh 03feffffh 00000000h 00100000h 001fffffh 000fffffh 03fec000h 01000000h 03febfffh 03fec000h notes 1. use of this area is allowed only for the v850es/jj3-e . this area cannot be used in the v850es/jh3-e. 2. cs1 is not provided as an external signal of the v850 es/jx3-e; it is used internally as a chip select signal for the usb and ethernet. 3. use of addresses 03fef000h to 03feffffh is prohibited becaus e they overlap an on-chip peripheral i/o area. 4. the programmable peripheral i/o area is seen as 256 mb areas in the 4 gb address space. 5. in on-chip can controller products, addre sses 03fec000h to 03fee fffh are assigned to addresses 03fec000h to 03fecbffh as a program mable peripheral i/o area. in other products, use of this area is prohibited. 6. this area is used as an external memory area when data write access to this area is executed. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 71 of 1817 sep 19, 2011 figure 3-3. memory map of cs1 macad register mff register ethermac register usb function area (512 kb) 02ffffffh 002f0004h 002f0003h 002f0000h 002fffffh 002e0400h 002e03ffh 002e0300h 002e02ffh 002e0200h 002e01ffh 002e0000h 002effffh 002880000h 00287ffffh 002900000h 0028fffffh 00280000h 0027ffffh 00000000h 32 bits access space 16 bits access space 002c00000h 002bffffh access-prohibited area bridge-rerated register access-prohibited area access-prohibited area access-prohibited area data-only ram (32 kb) data-only ram (32 kb) v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 72 of 1817 sep 19, 2011 figure 3-4. program memory map internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area note (8 mb) external memory area (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h use prohibited (program fetch prohibited area) external memory area (4 mb) 01000000h 00ffffffh 01000000h 00ffffffh note use of this area is allowed only when using t he v850es/jj3-e. when using the v850es/jh3-e, this area cannot be used. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 73 of 1817 sep 19, 2011 3.4.4 areas (1) internal rom area up to 1 mb is reserved as an internal rom area. (a) internal rom (256 kb) in the pd70f3778, 256 kb are allocated to addresses 00000000h to 0003ffffh in the following products. accessing addresses 00040000h to 000fffffh is prohibited. figure 3-5. internal rom area (256 kb) access-prohibited area internal rom (256 kb) 00040000h 0003ffffh 00000000h 000fffffh (b) internal rom (384 kb) 384 kb are allocated to addre sses 00000000h to 0005ffffh in the following products. accessing addresses 00060000h to 000fffffh is prohibited. ? pd70f3779, 70f3781 figure 3-6. internal rom area (384 kb) access-prohibited area internal rom (384 kb) 00060000h 0005ffffh 00000000h 000fffffh v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 74 of 1817 sep 19, 2011 (c) internal rom (512 kb) 512 kb are allocated to addre sses 00000000h to 0007ffffh in the following products. accessing addresses 00080000h to 000fffffh is prohibited. ? pd70f3780, 70f3782, 70f3783, 70f3784, 70f3785, 70f3786 figure 3-7. internal rom area (512 kb) access-prohibited area internal rom (512 kb) 00080000h 0007ffffh 00000000h 000fffffh (2) internal ram area up to 60 kb are reserved as the internal ram area. the v850es/jh3-e and v850es/jj3-e include a data- only ram in addition to the internal ram. the ram capacity of v850es/jh3-e and v850es/jj3-e is as follows. table 3-3 ram area generic name product name internal ram data-only ram total ram pd70f3778, 70f3779, 70f3780 60 kb 16 kb 76 kb v850es/jh3-e pd70f3781, 70f3782, 70f3783 60 kb 64 kb 124 kb pd70f3784 60 kb 16 kb 76 kb v850es/jj3-e pd70f3785, 70f3786 60 kb 64 kb 124 kb v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 75 of 1817 sep 19, 2011 (a) internal ram (60 kb) an internal ram area of 60 kb is allocated to addresses 03ff0000h to 03ffefffh in the v850es/jh3-e and v850es/jj3-e. figure 3-8. internal ram area (60 kb) physical address space internal ram (60 kb) logical address space 03ffefffh ffffefffh 03ff0000h ffff0000h (b) data-only ram (16 kb) a data-only ram area of 16 kb is allocated to addresse s 00280000h to 00283fffh in the following products. accessing addresses 03ff0000h to 03ff2fffh is prohibited. ? pd70f3778, 70f3779, 70 f3780, 70f3784 figure 3-9. data-only ram area (16 kb) logical address space access-prohibited area access-prohibited area 00282000h 00281fffh 00280000h 0027ffffh data-only ram (16 kb) v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 76 of 1817 sep 19, 2011 (c) data-only ram (64 kb) a data-only ram of 64 kb is allocated to addresse s 00280000h to 0028ffffh in the following products. ? pd70f3781, 70f3782, 70f 3783, 70f3785, 70f3786 figure 3-10. data-only ram area (64 kb) logical address space access-prohibited area access-prohibited area 00290000h 0028ffffh 00280000h 0027ffffh data-only ram (64 kb) v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 77 of 1817 sep 19, 2011 (3) on-chip peripheral i/o area 4 kb of addresses 03fff000h to 03ffffffh are re served as the on-chip peripheral i/o area. figure 3-11. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 03ffffffh 03fff000h ffffffffh fffff000h physical address space logical address space peripheral i/o registers that have functions to specify the operation mode for and monitor the status of the on-chip peripheral i/o are mapped to the on-ch ip peripheral i/o area. program ca nnot be fetched from this area. cautions 1. when a register is accessed in word unit s, a word area is accessed twice in halfword units in the order of lower area and higher area, wit h the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte uni ts is accessed in halfword units, the higher 8 bits are undefined when the register is read, a nd data is written to the lower 8 bits. 3. addresses not defined as registers are reser ved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. 4. the internal rom/ram area and on-chip peripheral i/o area are assigned to successive addresses. when accessing the internal rom/ram area by incrementing or decrementing addresses using a pointer opera tion or such, be careful not to acces s the on-chip peripheral i/o area by mistakenly extending over the internal rom/ram area boundary. (4) external memory area an area of 5 mb (00100000h to 001fffffh and 004 00000h to 007fffffh) in v850es/jh3-e and 13 mb (00100000h to 001fffffh and 004000 00h to 00ffffffh) in v850es/jj3-e is allocated as the external memory area. for details, see chapter 5 bus control function . v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 78 of 1817 sep 19, 2011 3.4.5 recommended use of address space the architecture of the v850es/jh3-e an d v850es/jj3-e requires that a register that serves as a pointer be secured for address generation when operand data in the data spac e is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. be cause the number of general- purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possi ble can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program count er), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb s pace of contiguous addresse s starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the program spac e, access the 03ff0000h to 03ffefffh addresses. caution if a branch instruction is at the upper limit of the internal ram area, a prefetch operation (invalid fetch) straddling the on-chip peripheral i/o area does not occur. (2) data space with the v850es/jh3-e and v850es/jj3-e, it seems that there are sixty-four 64 mb address spaces on the 4 gb cpu address space. therefore, the least significant bit (b it 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 79 of 1817 sep 19, 2011 (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st di sp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the re sources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by ha rdware, and practically eliminates the need for registers dedicated to pointers. example : pd70f3786 internal rom area on-chip peripheral i/o area internal ram area 32 kb 4 kb 28 kb 0007ffffh 00007fffh 00000000h fffff000h ffffefffh ffff8000h ffff3000h (r = ) v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 80 of 1817 sep 19, 2011 figure 3-12. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ff0000h 03feffffh 01000000h 00ffffffh 00080000h 0007ffffh 00100000h 000fffffh 00000000h ffffffffh fffff000h ffffefffh ffff3000h ffff2fffh ffff0000h fffeffffh 00100000h 000fffffh 00000000h use prohibited remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd70f3786. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 81 of 1817 sep 19, 2011 3.4.6 peripheral i/o registers (1/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl register pdl 0000h note 1 fffff004h port dl register l pdll 00h note 1 fffff005h port dl register h pdlh 00h note 1 fffff006h port dh register note 2 pdh note 2 00h note 1 fffff008h port cs register pcs 00h note 1 fffff00ah port ct register pct 00h note 1 fffff00ch port cm register pcm 00h note 1 fffff024h port dl mode register pmdl ffffh fffff024h port dl mode register l pmdll ffh fffff025h port dl mode register h pmdlh ffh fffff026h port dh mode register note 2 pmdh note 2 ffh fffff028h port cs mode register pmcs ffh fffff02ah port ct mode register pmct ffh fffff02ch port cm mode register pmcm ffh fffff044h port dl mode control register pmcdl 0000h fffff044h port dl mode control register l pmcdll 00h fffff045h port dl mode control register h pmcdlh 00h fffff046h port dh mode control register note 2 pmcdh note 2 00h fffff048h port cs mode control register pmccs 00h fffff04ah port ct mode control register pmcct 00h fffff04ch port cm mode control register pmccm 00h fffff056h port dh function control register pfcdh 00h fffff064h peripheral i/o area select control register note 3 bpc note 3 0000h fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h r/w undefined notes 1 the output latch is 00h or 0000h. when these regist ers are in the input mode, the pin statuses are read. 2. v850es/jj3-e only 3. pd70f3783, 70f3786 only v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 82 of 1817 sep 19, 2011 (2/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff108h interrupt mask register 4 imr4 ffffh fffff108h interrupt mask register 4l imr4l ffh fffff109h interrupt mask register 4h imr4h ffh fffff10ah interrupt mask register 5 imr5 ffffh fffff10ah interrupt mask register 5l imr5l ffh fffff10bh interrupt mask register 5h imr5h ffh fffff10ch interrupt mask register 6 imr6 ffffh fffff10ch interrupt mask register 6l imr6l ffh fffff10dh interrupt mask register 6h imr6h ffh fffff10eh interrupt mask register 7 imr7 001fh fffff10eh interrupt mask register 7l imr7l 1fh fffff110h interrupt control register lviic 47h fffff112h interrupt control register pic00 r/w 47h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 83 of 1817 sep 19, 2011 (3/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff114h interrupt control register pic01 47h fffff116h interrupt control register pic02 47h fffff118h interrupt control register pic03 47h fffff11ah interrupt control register pic04 47h fffff11ch interrupt control register pic05 47h fffff11eh interrupt control register pic06 47h fffff120h interrupt control register pic07 47h fffff122h interrupt control register pic08 47h fffff124h interrupt control register pic09 47h fffff126h interrupt control register pic10 47h fffff128h interrupt control register pic11 47h fffff12ah interrupt control register pic12 47h fffff12ch interrupt control register pic13 47h fffff12eh interrupt control register pic14 47h fffff130h interrupt control register pic15 47h fffff132h interrupt control register pic16 47h fffff134h interrupt control register pic17 47h fffff136h interrupt control register pic18 47h fffff138h interrupt control register pic19 47h fffff13ah interrupt control register pic20 47h fffff13ch interrupt control register pic21 note 47h fffff13eh interrupt control register pic22 note 47h fffff140h interrupt control register pic23 note 47h fffff142h interrupt control register pic24 note 47h fffff144h interrupt control register pic25 note 47h fffff146h interrupt control register tab0ovic 47h fffff148h interrupt control register tab0ccic0 47h fffff14ah interrupt control register tab0ccic1 47h fffff14ch interrupt control register tab0ccic2 47h fffff14eh interrupt control register tab0ccic3 47h fffff150h interrupt control register tab1ovic 47h fffff1 52 h interrupt control register tab1ccic0 47h fffff1 54 h interrupt control register tab1ccic1 47h fffff156h interrupt control register tab1ccic2 47h fffff158h interrupt control register tab1ccic3 47h fffff15ah interrupt control register tt0ovic 47h fffff15ch interrupt control register tt0ccic0 47h fffff15eh interrupt control register tt0ccic1 47h fffff160h interrupt control register tt0iecic 47h fffff162h interrupt control register taa0ovic r/w 47h note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 84 of 1817 sep 19, 2011 (4/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff164h interrupt control register taa0ccic0 47h fffff166h interrupt control register taa0ccic1 47h fffff168h interrupt control register taa1ovic 47h fffff16ah interrupt control register taa1ccic0 47h fffff16ch interrupt control register taa1ccic1 47h fffff16eh interrupt control register taa2ovic 47h fffff170h interrupt control register taa2ccic0 47h fffff172h interrupt control register taa2ccic1 47h fffff174h interrupt control register taa3ovic 47h fffff176h interrupt control register taa3ccic0 47h fffff178h interrupt control register taa3ccic1 47h fffff17ah interrupt control register taa4ovic 47h fffff17ch interrupt control register taa4ccic0 47h fffff17eh interrupt control register taa4ccic1 47h fffff180h interrupt control register taa5ovic 47h fffff182h interrupt control register taa5ccic0 47h fffff184h interrupt control register taa5ccic1 47h fffff186h interrupt control register tm0eqic0 47h fffff188h interrupt control register tm1eqic0 47h fffff18ah interrupt control register tm2eqic0 47h fffff18ch interrupt control register tm3eqic0 47h fffff18eh interrupt control register ce0tic/uc4ric 47h fffff190h interrupt control register ce0tiofic/ uc4tic 47h fffff192h interrupt control register ce1tic/iicic3/ uc5ric 47h fffff194h interrupt control register ce1tiofic/ uc5tic 47h fffff196h interrupt control register cf0ric/iicic1 /uc3ric 47h fffff198h interrupt control register cf0tic/uc3tic 47h fffff19ah interrupt control register cf1ric/iicic0 /uc1ric 47h fffff19ch interrupt control register cf1tic/uc1ric 47h fffff19eh interrupt control register cf2ric/uc0ric 47h fffff1a0h interrupt control register cf2tic/uc0ric 47h fffff1a2h interrupt control register cf3ric/ ub1tiric 47h fffff1a4h interrupt control register cf3tic/ ub1titic 47h fffff1a6h interrupt control register ub1tific r/w 47h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 85 of 1817 sep 19, 2011 (5/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff1a8h interrupt control register ub1tireic 47h fffff1aah interrupt control register ub1titoic 47h fffff1ach interrupt control register cf4ric/ ub0tiric 47h fffff1aeh interrupt control register cf4tic/ ub0titic 47h fffff1b0h interrupt control register ub0tific 47h fffff1b2h interrupt control register ub0tireic 47h fffff1b4h interrupt control register ub0titoic 47h fffff1b6h interrupt control register cf5ric/uc6ric note 1 47h fffff1b8h interrupt control register cf5tic/uc6tic note 1 47h fffff1bah interrupt control register cf6ric/uc7ric note 1 47h fffff1bch interrupt control register cf6tic/uc7tic note 1 47h fffff1beh interrupt control register iicic2/uc2ric 47h fffff1c0h interrupt control register uc2tic 47h fffff1c2h interrupt control register iicic4 note 1 47h fffff1c4h interrupt control register adic 47h fffff1c6h interrupt control register dmaic0 47h fffff1c8h interrupt control register dmaic1 47h fffff1cah interrupt control register dmaic2 47h fffff1cch interrupt control register dmaic3 47h fffff1ceh interrupt control register kric 47h fffff1d0h interrupt control register rtc0ic 47h fffff1d2h interrupt control register rtc1ic 47h fffff1d4h interrupt control register rtc2ic 47h fffff1d6h interrupt control register ufic0 47h fffff1d8h interrupt control register ufic1 47h fffff1ech interrupt control register erric0 note 2 47h fffff1eeh interrupt control register wupic0 note 2 47h fffff1f0h interrupt control register recic0 note 2 47h fffff1f2h interrupt control register trxic0 note 2 r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail compare mode register ada0pfm 00h fffff205h power-fail compare threshold value register ada0pft r/w 00h notes 1 v850es/jj3-e only 2. pd70f3783, 70f3786 only v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 86 of 1817 sep 19, 2011 (6/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0cr0h undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0cr1h undefined fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0cr2h undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0cr3h undefined fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0cr4h undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0cr5h undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0cr6h undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0cr7h undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0cr8h undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0cr9h undefined fffff224h a/d conversion result register 10 ada0cr10 note 1 undefined fffff225h a/d conversion result register 10h ada0cr10h note 1 undefined fffff226h a/d conversion result register 11 ada0cr11 note 1 undefined fffff227h a/d conversion result register 11h ada0cr11h note 1 undefined fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff310h crc input register crcin 00h fffff312h crc data register crcd 0000h fffff320h prescaler mode register 1 prsm1 00h fffff321h prescaler compare register 1 prscm1 00h fffff324h prescaler mode register 2 prsm2 00h fffff325h prescaler compare register 2 prscm2 00h fffff328h prescaler mode register 3 prsm3 00h fffff329h prescaler compare register 3 prscm3 00h fffff32ch prescaler mode register 4 prsm4 00h fffff32dh prescaler compare register 4 prscm4 00h fffff340h iic division clock select register 0 ocks0 00h fffff344h iic division clock select register 1 ocks1 00h fffff348h iic division clock select register 2 ocks2 r 00h fffff400h port 0 register p0 00h note 2 fffff404h port 2 register p2 00h note 2 fffff406h port 3 register p3 r/w 00h note 2 notes 1 v850es/jj3-e only 2. the output latch is 00h or 0000h. when these registers are in the input mode, the pin statuses are read. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 87 of 1817 sep 19, 2011 (7/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff408h port 4 register p4 0000h note fffff408h port 4 register l p4l 00h note fffff409h port 4 register h p4h 00h note fffff40ah port 5 register p5 0000h note fffff40ah port 5 register l p5l 00h note fffff40bh port 5 register h p5h 00h note fffff40eh port 7 register p7 0000h note fffff40eh port 7 register l p7l 00h note fffff40fh port 7 register h p7h 00h note fffff412h port 9 register p9 0000h note fffff412h port 9 register l p9l 00h note fffff413h port 9 register h p9h 00h note fffff420h port 0 mode register pm0 ffh fffff424h port 2 mode register pm2 ffh fffff426h port 3 mode register pm3 ffh fffff428h port 4 mode register pm4 ffffh fffff428h port 4 mode register l pm4l ffh fffff429h port 4 mode register h pm4h ffh fffff42ah port 5 mode register pm5 ffffh fffff42ah port 5 mode register l pm5l ffh fffff42bh port 5 mode register h pm5h ffh fffff42eh port 7 mode register l pm7l ffh fffff42fh port 7 mode register h pm7h ffh fffff432h port 9 mode register pm9 ffffh fffff432h port 9 mode register l pm9l ffh fffff433h port 9 mode register h pm9h ffh fffff440h port 0 mode control register pmc0 00h fffff444h port 2 mode control register pmc2 00h fffff446h port 3 mode control register pmc3 00h fffff448h port 4 mode control register pmc4 0000h fffff448h port 4 mode control register l pmc4l 00h fffff449h port 4 mode control register h pmc4h 00h fffff44ah port 5 mode control register pmc5 0000h fffff44ah port 5 mode control register l pmc5l 00h fffff44bh port 5 mode control register h pmc5h 00h fffff452h port 9 mode control register pmc9 0000h fffff452h port 9 mode control register l pmc9l 00h fffff453h port 9 mode control register h pmc9h 00h fffff460h port 0 function control register pfc0 00h fffff464h port 2 function control register pfc2 00h fffff466h port 3 function control register pfc3 r/w 00h note the output latch is 00h or 0000h. when these registers are input, the pin statuses are read. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 88 of 1817 sep 19, 2011 (8/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff468h port 4 function control register pfc4 0000h fffff468h port 4 function control register l pfc4l 00h fffff469h port 4 function control register h pfc4h 00h fffff46ah port 5 function control register pfc5 0000h fffff46ah port 5 function control register l pfc5l 00h fffff46bh port 5 function control register h pfc5h 00h fffff472h port 9 function control register pfc9 0000h fffff472h port 9 function control register l pfc9l 00h fffff473h port 9 function control register h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff540h tab0 control register 0 tab0ctl0 00h fffff541h tab0 control register 1 tab0ctl1 00h fffff542h tab0 i/o control register 0 tab0ioc0 00h fffff543h tab0 i/o control register 1 tab0ioc1 00h fffff544h tab0 i/o control register 2 tab0ioc2 00h fffff545h tab0 option register 0 tab0opt0 00h fffff546h tab0 capture/compare register 0 tab0ccr0 0000h fffff548h tab0 capture/compare register 1 tab0ccr1 0000h fffff54ah tab0 capture/compare register 2 tab0ccr2 0000h fffff54ch tab0 capture/compare register 3 tab0ccr3 r/w 0000h fffff54eh tab0 counter read buffer register tab0cnt r 0000h fffff550h tab0 i/o control register 4 tab0ioc4 00h fffff560h tab1 control register 0 tab1ctl0 00h fffff561h tab1 control register 1 tab1ctl1 00h fffff562h tab1 i/o control register 0 tab1ioc0 00h fffff563h tab1 i/o control register 1 tab1ioc1 00h fffff564h tab1 i/o control register 2 tab1ioc2 00h fffff565h tab1 option register 0 tab1opt0 00h fffff566h tab1 capture/compare register 0 tab1ccr0 0000h fffff568h tab1 capture/compare register 1 tab1ccr1 0000h fffff56ah tab1 capture/compare register 2 tab1ccr2 0000h fffff56ch tab1 capture/compare register 3 tab1ccr3 r/w 0000h fffff56eh tab1 counter read buffer register tab1cnt r 0000h fffff570h tab1 i/o control register 4 tab1ioc4 00h fffff580h tab1 option register 1 tab1opt1 00h fffff581h tab1 option register 2 tab1opt2 00h fffff582h tab1 i/o control register 3 tab1ioc3 a8h fffff584h tab1 dead time compare register 1 tab1dtc 0000h fffff590h high impedance output control register 0 hza0ctl0 r/w 00h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 89 of 1817 sep 19, 2011 (9/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff591h high impedance output control register 1 hzactl1 00h fffff5a0h taa0 noise elimination control register tanfc0 00h fffff5a2h taa1 noise elimination control register tanfc1 00h fffff5a4h taa2 noise elimination control register tanfc2 00h fffff5a6h taa3 noise elimination control register tanfc3 00h fffff5a8h taa4 noise elimination control register tanfc4 00h fffff5aah taa5 noise elimination control register tanfc5 00h fffff5ach tmt noise elimination control register ttnfc 00h fffff5b0h noise elimination control register intnfc 00h fffff600h tmt0 control register 0 tt0ctl0 00h fffff601h tmt0 control register 1 tt0ctl1 00h fffff602h tmt0 control register 2 tt0ctl2 00h fffff603h tmt0 i/o control register 0 tt0ioc0 00h fffff604h tmt0 i/o control register 1 tt0ioc1 00h fffff605h tmt0 i/o control register 2 tt0ioc2 00h fffff606h tmt0 i/o control register 3 tt0ioc3 00h fffff607h tmt0 option register 0 tt0opt0 00h fffff608h tmt0 option register 1 tt0opt1 00h fffff60ah tmt0 capture/compare register 0 tt0ccr0 0000h fffff60ch tmt0 capture/compare register 1 tt0ccr1 r/w 0000h fffff60eh tmt0 counter read buffer register tt0cnt r 0000h fffff610h tmt0 counter write register tt0tcw 0000h fffff630h taa0 control register 0 taa0ctl0 00h fffff631h taa0 control register 1 taa0ctl1 00h fffff632h taa0 i/o control register 0 taa0ioc0 00h fffff633h taa0 i/o control register 1 taa0ioc1 00h fffff634h taa0 i/o control register 2 taa0ioc2 00h fffff635h taa0 option register 0 taa0opt0 00h fffff636h taa0 capture/compare register 0 taa0ccr0 0000h fffff638h taa0 capture/compare register 1 taa0ccr1 r/w 0000h fffff63ah taa0 counter read buffer register taa0cnt r 0000h fffff63ch taa0 i/o control register 4 taa0ioc4 00h fffff63dh taa0 option register 1 taa0opt1 00h fffff640h taa1 control register 0 taa1ctl0 00h fffff641h taa1 control register 1 taa1ctl1 00h fffff642h taa1 i/o control register 0 taa1ioc0 00h fffff643h taa1 i/o control register 1 taa1ioc1 00h fffff644h taa1 i/o control register 2 taa1ioc2 00h fffff645h taa1 option register 0 taa1opt0 00h fffff646h taa1 capture/compare register 0 taa1ccr0 0000h fffff648h taa1 capture/compare register 1 taa1ccr1 r/w 0000h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 90 of 1817 sep 19, 2011 (10/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff64ah taa1 counter read buffer register taa1cnt r 0000h fffff64ch taa1 i/o control register 4 taa1ioc4 00h fffff650h taa2 control register 0 taa2ctl0 00h fffff651h taa2 control register 1 taa2ctl1 00h fffff652h taa2 i/o control register 0 taa2ioc0 00h fffff653h taa2 i/o control register 1 taa2ioc1 00h fffff654h taa2 i/o control register 2 taa2ioc2 00h fffff655h taa2 option register 0 taa2opt0 00h fffff656h taa2 capture/compare register 0 taa2ccr0 0000h fffff658h taa2 capture/compare register 1 taa2ccr1 r/w 0000h fffff65ah taa2 counter read buffer register taa2cnt r 0000h fffff65ch taa2 i/o control register 4 taa2ioc4 00h fffff65dh taa2 option register 1 taa2opt1 00h fffff660h taa3 control register 0 taa3ctl0 00h fffff661h taa3 control register 1 taa3ctl1 00h fffff662h taa3 i/o control register 0 taa3ioc0 00h fffff663h taa3 i/o control register 1 taa3ioc1 00h fffff664h taa3 i/o control register 2 taa3ioc2 00h fffff665h taa3 option register 0 taa3opt0 00h fffff666h taa3 capture/compare register 0 taa3ccr0 0000h fffff668h taa3 capture/compare register 1 taa3ccr1 r/w 0000h fffff66ah taa3 counter read buffer register taa3cnt r 0000h fffff66ch taa3 i/o control register4 taa3ioc4 00h fffff670h taa4 control register 0 taa4ctl0 00h fffff671h taa4 control register 1 taa4ctl1 00h fffff672h taa4 i/o control register 0 taa4ioc0 00h fffff673h taa4 i/o control register 1 taa4ioc1 00h fffff674h taa4 i/o control register 2 taa4ioc2 00h fffff675h taa4 option register 0 taa4opt0 00h fffff676h taa4 capture compare register 0 taa4ccr0 0000h fffff678h taa4 capture compare register 1 taa4ccr1 r/w 0000h fffff67ah taa4 counter read buffer register taa4cnt r 0000h fffff67ch taa4 i/o control register 4 taa4ioc4 00h fffff680h taa5 control register 0 taa5ctl0 00h fffff681h taa5 control register 1 taa5ctl1 00h fffff682h taa5 i/o control register 0 taa5ioc0 00h fffff683h taa5 i/o control register 1 taa5ioc1 00h fffff684h taa5 i/o control register 2 taa5ioc2 00h fffff685h taa5 option register 0 taa5opt0 00h fffff686h taa5 capture/compare register 0 taa5ccr0 0000h fffff688h taa5 capture/compare register 1 taa5ccr1 r/w 0000h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 91 of 1817 sep 19, 2011 (11/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff68ah taa5 counter read buffer register taa5cnt r 0000h fffff68ch taa5 i/o control register 4 taa5ioc4 00h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff6e0h real-time output buffer register 0l rtbl0 00h fffff6e2h real-time output buffer register 0h rtbh0 00h fffff6e4h real-time output port mode register 0 rtpm0 00h fffff6e5h real-time output port control register 0 rtpc0 00h fffff700h port 0 function control expansion register pfce0 00h fffff704h port 2 function control expansion register pfce2 00h fffff706h port 3 function control expansion register pfce3 00h fffff708h port 4 function control expansion register l pfce4l 00h fffff70ah port 5 function control expansion register l pfce5l 00h fffff712h port 9 function control expansion register pfce9 0000h fffff712h port 9 function control expansion register l pfce9l 00h fffff713h port 9 function control expansion register h pfce9h 00h fffff726h port dh function control expansion register pfcedh 00h fffff802h system status register sys 00h fffff80ch internal oscillation mode register rcm 00h fffff810h dma trigger factor register 0 dtfr0 00h fffff812h dma trigger factor register 1 dtfr1 00h fffff814h dma trigger factor register 2 dtfr2 00h fffff816h dma trigger factor register 3 dtfr3 00h fffff820h power save mode register psmr 00h fffff822h clock control register ckc r/w 0ah fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operation clock status register ccls r 00h fffff870h clock monitor mode register clm 00h fffff888h reset source flag register resf 00h fffff890h low-voltage detection register lvim 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffffa00h uartc0 control register 0 uc0ctl0 10h fffffa01h uartc0 control register 1 uc0ctl1 00h fffffa02h uartc0 control register 2 uc0ctl2 r/w ffh v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 92 of 1817 sep 19, 2011 (12/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffa03h uartc0 option control register 0 uc0opt0 14h fffffa04h uartc0 status register uc0str r/w 00h fffffa06h uartc0 receive data register uc0rx r 01ffh fffffa06h uartc0 receive data register l uc0rxl ffh fffffa08h uartc0 transmit data register uc0tx 01ffh fffffa08h uartc0 transmit data register l uc0txl ffh fffffa0ah uartc0 option control register 1 uc0opt1 00h fffffa10h uartc1 control register 0 uc1ctl0 10h fffffa11h uartc1 control register 1 uc1ctl1 00h fffffa12h uartc1 control register 2 uc1ctl2 ffh fffffa13h uartc1 option control register 0 uc1opt0 14h fffffa14h uartc1 status register uc1str r/w 00h fffffa16h uartc1 receive data register uc1rx r 01ffh fffffa16h uartc1 receive data register l uc1rxl ffh fffffa18h uartc1 transmit data register uc1tx 01ffh fffffa18h uartc1 transmit data register l uc1txl ffh fffffa1ah uartc1 option control register 1 uc1opt1 00h fffffa20h uartc2 control register 0 uc2ctl0 10h fffffa21h uartc2 control register 1 uc2ctl1 00h fffffa22h uartc2 control register 2 uc2ctl2 ffh fffffa23h uartc2 option control register 0 uc2opt0 14h fffffa24h uartc2 status register uc2str r/w 00h fffffa26h uartc2 receive data register uc2rx 01ffh fffffa26h uartc2 receive data register l uc2rxl r ffh fffffa28h uartc2 transmit data register uc2tx 01ffh fffffa28h uartc2 transmit data register l uc2txl ffh fffffa2ah uartc2 option control register 1 uc2opt1 00h fffffa30h uartc3 control register 0 uc3ctl0 10h fffffa31h uartc3 control register 1 uc3ctl1 00h fffffa32h uartc3 control register 2 uc3ctl2 ffh fffffa33h uartc3 option control register 0 uc3opt0 14h fffffa34h uartc3 status register uc3str r/w 00h fffffa36h uartc3 receive data register uc3rx 01ffh fffffa36h uartc3 receive data register l uc3rxl r ffh fffffa38h uartc3 transmit data register uc3tx 01ffh fffffa38h uartc3 transmit data register l uc3txl ffh fffffa3ah uartc3 option control register 1 uc3opt1 00h fffffa40h uartc4 control register 0 uc4ctl0 10h fffffa41h uartc4 control register 1 uc4ctl1 00h fffffa42h uartc4 control register 2 uc4ctl2 ffh fffffa43h uartc4 option control register 0 uc4opt0 r/w 14h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 93 of 1817 sep 19, 2011 (13/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffa44h uartc4 status register uc4str r/w 00h fffffa46h uartc4 receive data register uc4rx 01ffh fffffa46h uartc4 receive data register l uc4rxl r ffh fffffa48h uartc4 transmit data register uc4tx 01ffh fffffa48h uartc4 transmit data register l uc4txl ffh fffffa4ah uartc4 option control register 1 uc4opt1 00h fffffa50h uartc5 control register 0 uc5ctl0 10h fffffa51h uartc5 control register 1 uc5ctl1 00h fffffa52h uartc5 control register 2 uc5ctl2 ffh fffffa53h uartc5 option control register 0 uc5opt0 14h fffffa54h uartc5 status register uc5str r/w 00h fffffa56h uartc5 receive data register uc5rx 01ffh fffffa56h uartc5 receive data register l uc5rxl r ffh fffffa58h uartc5 transmit data register uc5tx 01ffh fffffa58h uartc5 transmit data register l uc5txl ffh fffffa5ah uartc6 option control register 1 uc6opt1 note 00h fffffa60h uartc6 control register 0 uc6ctl0 note 10h fffffa61h uartc6 control register 1 uc6ctl1 note 00h fffffa62h uartc6 control register 2 uc6ctl2 note ffh fffffa63h uartc6 option control register 0 uc6opt0 note 14h fffffa64h uartc6 status register uc6str note r/w 00h fffffa66h uartc6 receive data register uc6rx note 01ffh fffffa66h uartc6 receive data register l uc6rxl note r ffh fffffa68h uartc6 transmit data register uc6tx note 01ffh fffffa68h uartc6 transmit data register l uc6txl note ffh fffffa6ah uartc6 option control register 1 uc6opt1 note 00h fffffa70h uartc7 control register 0 uc7ctl0 note 10h fffffa71h uartc7 control register 1 uc7ctl1 note 00h fffffa72h uartc7 control register 2 uc7ctl2 note ffh fffffa73h uartc7 option register uc7opt0 note 14h fffffa74h uartc7 status register uc7str note r/w 00h fffffa76h uartc7 receive data register uc7rx note 01ffh fffffa76h uartc7 receive data register l uc7rxl note r ffh fffffa78h uartc7 transmit data register uc7tx note 01ffh fffffa78h uartc7 transmit data register l uc7txl note ffh fffffa7ah uartc7 option control register 1 uc7opt1 00h fffffa80h tmm0 control register 0 tm0ctl0 00h fffffa84h tmm0 compare register 0 tm0cmp0 0000h fffffa90h tmm1 control register 0 tm1ctl0 00h fffffa94h tmm1 compare register 0 tm1cmp0 0000h fffffaa0h tmm2 control register 0 tm2ctl0 r/w 00h note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 94 of 1817 sep 19, 2011 (14/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffaa4h tmm2 compare register 0 tm2cmp0 0000h fffffab0h tmm3 control register 0 tm3ctl0 00h fffffab4h tmm3 compare register 0 tm3cmp0 r/w 0000h fffffad0h sub-count register rc1subc r 0000h fffffad2h second count register rc1sec 00h fffffad3h minute count register rc1min 00h fffffad4h hour count register rc1hour 12h fffffad5h week count register rc1week 00h fffffad6h day count register rc1day 01h fffffad7h month count register rc1month 01h fffffad8h year count register rc1year 00h fffffad9h time error correction register rc1subu 00h fffffadah alarm minute set register rc1alm 00h fffffadbh alarm time set register rc1alh 12h fffffadch alarm week set register rc1alw 00h fffffaddh rtc control register 0 rc1cc0 00h fffffadeh rtc control register 1 rc1cc1 00h fffffadfh rtc control register 2 rc1cc2 00h fffffae0h rtc control register 3 rc1cc3 00h fffffb00h csie0 control register 0 ce0ctl0 00h fffffb01h csie0 control register 1 ce0ctl1 r/w 07h fffffb02h csie0 receive data register 0 ce0rx0 0000h fffffb02h csie0 receive data register 0l ce0rxl0 00h fffffb03h csie0 receive data register 0h ce0rxh0 r 00h fffffb06h csie0 transmit data register ce0tx0 0000h fffffb06h csie0 transmit data register l ce0txl0 00h fffffb07h csie0 transmit data register h ce0txh0 00h fffffb08h csie0 status register ce0str 20h fffffb09h csie0 control register 2 ce0ctl2 00h fffffb0ch csie0 control register 3 ce0ctl3 00h fffffb40h csie1 control register 0 ce1ctl0 00h fffffb41h csie1 control register 1 ce1ctl1 r/w 07h fffffb42h csie1 receive data register ce1rx0 0000h fffffb42h csie1 receive data register l ce1rxl0 00h fffffb43h csie1 receive data register h ce1rxh0 r 00h fffffb46h csie1 transmit data register ce1tx0 0000h fffffb46h csie1 transmit data register l ce1txl0 00h fffffb47h csie1 transmit data register h ce1txh0 00h fffffb48h csie1 status register ce1str 20h fffffb49h csie1 control register 2 ce1ctl2 00h fffffb4ch csie1 control register 3 ce1ctl3 r/w 00h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 95 of 1817 sep 19, 2011 (15/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffb80h uartb0 control register 0 ub0ctl0 10h fffffb82h uartb0 control register 2 ub0ctl2 ffffh fffffb84h uartb0 status register ub0str r/w 00h fffffb86h uartb0 receive data register ap ub0rxap 00ffh fffffb86h uartb0 receive data register ub0rx r ffh fffffb88h uartb0 transmit data register ub0tx ffh fffffb8ah uartb0 fifo control register 0 ub0fic0 00h fffffb8bh uartb0 fifo control register 1 ub0fic1 00h fffffb8ch uartb0 fifo control register 2 ub0fic2 0000h fffffb8ch uartb0 fifo control register 2l ub0fic2l 00h fffffb8dh uartb0 fifo control register 2h ub0fic2h r/w 00h fffffb8eh uartb0 status register 0 ub0fis0 00h fffffb8fh uartb0 status register 1 ub0fis1 r 10h fffffba0h uartb1 control register 0 ub1ctl0 10h fffffba2h uartb1 control register 2 ub1ctl2 ffffh fffffba4h uartb1 status register ub1str r/w 00h fffffba6h uartb1 receive data register ap ub1rxap 00ffh fffffba6h uartb1 receive data register ub1rx r ffh fffffba8h uartb1 transmit data register ub1tx ffh fffffbaah uartb1 fifo control register 0 ub1fic0 00h fffffbabh uartb1 fifo control register 1 ub1fic1 00h fffffbach uartb1 fifo control register 2 ub1fic2 0000h fffffbach uartb1 fifo control register 2l ub1fic2l 00h fffffbadh uartb1 fifo control register 2h ub1fic2h r/w 00h fffffbaeh uartb1 status register 0 ub1fis0 00h fffffbafh uartb1 status register 1 ub1fis1 r 10h fffffbc0h iic shift register 4 iic4 00h fffffbc2h iic control register 4 iicc4 00h fffffbc3h slave address register 4 sva4 00h fffffbc4h iic clock selection register 4 iiccl4 00h fffffbc5h iic function expansion register 4 iicx4 r/w 00h fffffbc6h iic status register 4 iics4 r 00h fffffbcah iic flag register 4 iicf4 00h fffffbe0h ethernet control register miictl 00h fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc04h external interrupt falling edge specification register 2 intf2 00h fffffc06h external interrupt falling edge specification register 3 intf3 00h fffffc09h external interrupt falling edge specification register 4 intf4h note 00h fffffc0ah external interrupt falling edge specification register 5 intf5 0000h fffffc0ah external interrupt falling edge specification register 5l intf5l 00h fffffc0bh external interrupt falling edge specification register 5h intf5h r/w 00h note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 96 of 1817 sep 19, 2011 (16/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc12h external interrupt falling edge specification register 9 intf9 0000h fffffc12h external interrupt falling edge specification register 9h intf9h 00h fffffc13h external interrupt falling edge specification register 9l intf9l 00h fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc24h external interrupt rising edge specification register 2 intr2 00h fffffc26h external interrupt rising edge specification register 3 intr3 00h fffffc29h external interrupt rising edge specification register 4 note intr4h note 00h fffffc2ah external interrupt rising edge specification register 5 intr5 0000h fffffc2ah external interrupt rising edge specification register 5l intr5l 00h fffffc2bh external interrupt rising edge specification register 5h intr5h 00h fffffc32h external interrupt rising edge specification register 9 intr9 0000h fffffc32h external interrupt rising edge specification register 9h intr9h 00h fffffc33h external interrupt rising edge specification register 9l intr9l 00h fffffc60h port 0 function register pf0 00h fffffc64h port 2 function register pf2 00h fffffc66h port 3 function register pf3 00h fffffc68h port 4 function register pf4 0000h fffffc68h port 4 function register l pf4l 00h fffffc69h port 4 function register h pf4h 00h fffffc6ah port 5 function register pf5 0000h fffffc6ah port 5 function register l pf5l 00h fffffc6bh port 5 function register h pf5h 00h fffffc72h port 9 function register pf9 0000h fffffc72h port 9 function register l pf9l 00h fffffc73h port 9 function register h pf9h 00h fffffd00h csif0 control register 0 cf0ctl0 01h fffffd01h csif0 control register 1 cf0ctl1 00h fffffd02h csif0 control register 2 cf0ctl2 00h fffffd03h csif0 status register cf0str r/w 00h fffffd04h csif0 receive data register cf0rx 0000h fffffd04h csif0 receive data register l cf0rxl r 00h fffffd06h csif0 transmit data register cf0tx 0000h fffffd06h csif0 transmit data register l cf0txl 00h fffffd10h csif1 control register 0 cf1ctl0 01h fffffd11h csif1 control register 1 cf1ctl1 00h fffffd12h csif1 control register 2 cf1ctl2 00h fffffd13h csif1 status register cf1str r/w 00h fffffd14h csif1 receive data register cf1rx 0000h fffffd14h csif1 receive data register l cf1rxl r 00h fffffd16h csif1 transmit data register cf1tx 0000h fffffd16h csif1 transmit data register l cf1txl r/w 00h note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 97 of 1817 sep 19, 2011 (17/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffd20h csif2 control register 0 cf2ctl0 01h fffffd21h csif2 control register 1 cf2ctl1 00h fffffd22h csif2 control register 2 cf2ctl2 00h fffffd23h csif2 status register cf2str r/w 00h fffffd24h csif2 receive data register cf2rx 0000h fffffd24h csif2 receive data register l cf2rxl r 00h fffffd26h csif2 transmit data register cf2tx 0000h fffffd26h csif2 transmit data register l cf2txl 00h fffffd30h csif3 control register 0 cf3ctl0 01h fffffd31h csif3 control register 1 cf3ctl1 00h fffffd32h csif3 control register 2 cf3ctl2 00h fffffd33h csif3 status register cf3str r/w 00h fffffd34h csif3 receive data register cf3rx 0000h fffffd34h csif3 receive data register l cf3rxl r 00h fffffd36h csif3 transmit data register cf3tx 0000h fffffd36h csif3 transmit data register l cf3txl 00h fffffd40h csif4 control register 0 cf4ctl0 01h fffffd41h csif4 control register 1 cf4ctl1 00h fffffd42h csif4 control register 2 cf4ctl2 00h fffffd43h csif4 status register cf4str r/w 00h fffffd44h csif4 receive data register cf4rx 0000h fffffd44h csif4 receive data register l cf4rxl r 00h fffffd46h csif4 transmit data register cf4tx 0000h fffffd46h csif4 transmit data register l cf4txl 00h fffffd50h csif5 control register 0 cf5ctl0 note 01h fffffd51h csif5 control register 1 cf5ctl1 note 00h fffffd52h csif5 control register 2 cf5ctl2 note 00h fffffd53h csif5 status register cf5str note r/w 00h fffffd54h csif5 receive data register cf5rx note 0000h fffffd54h csif5 receive data register l cf5rxl note r 00h fffffd56h csif5 transmit data register cf5tx note 0000h fffffd56h csif5 transmit data register l cf5txl note 00h fffffd60h csif6 control register 0 cf6ctl0 note 01h fffffd61h csif6 control register 1 cf6ctl1 note 00h fffffd62h csif6 control register 2 cf6ctl2 note 00h fffffd63h csif6 status register cf6str note r/w 00h fffffd64h csif6 receive data register cf6rx note 0000h fffffd64h csif6 receive data register l cf6rxl note r 00h fffffd66h csif6 transmit data register cf6tx note 0000h fffffd66h csif6 transmit data register l cf6txl note r/w 00h note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 98 of 1817 sep 19, 2011 (18/18) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffd80h iic shift register 0 iic0 00h fffffd82h iic control register 0 iicc0 00h fffffd83h slave address register 0 sva0 00h fffffd84h iic clock select register 0 iiccl0 00h fffffd85h iic function expansion register 0 iicx0 r/w 00h fffffd86h iic status register 0 iics0 r 00h fffffd8ah iic flag register 0 iicf0 00h fffffd90h iic shift register 1 iic1 00h fffffd92h iic control register 1 iicc1 00h fffffd93h slave address register 1 sva1 00h fffffd94h iic clock select register 1 iiccl1 00h fffffd95h iic function expansion register 1 iicx1 r/w 00h fffffd96h iic status register 1 iics1 r 00h fffffd9ah iic flag register 1 iicf1 00h fffffda0h iic shift register 2 iic2 r/w 00h fffffda2h iic control register 2 iicc2 00h fffffda3h slave address register 2 sva2 00h fffffda4h iic clock select register 2 iiccl2 00h fffffda5h iic function expansion register 2 iicx2 r/w 00h fffffda6h iic status register 2 iics2 r 00h fffffdaah iic flag register 2 iicf2 00h fffffdb0h iic shift register 3 iic3 00h fffffdb2h iic control register 3 iicc3 00h fffffdb3h slave address register 3 sva3 00h fffffdb4h iic clock selection register 3 iiccl3 00h fffffdb5h iic function expansion register 3 iicx3 r/w 00h fffffdb6h iic status register 3 iics3 r 00h fffffdbah iic flag register 3 iicf3 00h ffffff40h usb clock selection register ucksel 00h ffffff41h usb function control register ufckmsk 03h ffffff60h external dma request enable register exdrqen r/w 00h v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 99 of 1817 sep 19, 2011 3.4.7 programmable peripheral i/o registers the bpc register is used to select the programmable peripheral i/o register area. the bpc register is valid only in the pd70f3783 and 70f3786. (1) peripheral i/o area selec t control register (bpc) this register can be read or written in 16-bit units. reset sets this register to 0000h. bpc 12 1 08 6 42 14 0 1 3 11 9 7 53 1 5 pa1 5 0 pa13 pa1 2 pa1 1 pa1 0 pa09 pa08 pa07 pa06 pa05 pa04 pa03 pa02 pa01 pa00 1 pa15 0 1 pa13 to pa00 after reset: 0000h r/w address: fffff064h do not allow use of programmable peripheral i/o area. allow use of programmable peripheral i/o area. allows/does not allow use of programmable peripheral i/o area. set address of programmable peripheral i/o area. (correspond to a27 to a14) caution if the pa15 bit is set to 1, be su re to set the bpc register to 8ffbh. if the pa15 bit is set to 0, be su re to set the bpc register to 0000h. for the list of programmable peri pheral i/o registers, refer to table 21-16 register access type . v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 100 of 1817 sep 19, 2011 3.4.8 special registers special registers are registers that ar e protected from being written with ille gal data due to a program loop. the v850es/jh3-e and v850es/jj3-e have the following eight special registers. ? power save control register (psc) ? clock control register (ckc) ? processor clock control register (pcc) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) ? internal ram data status register (rams) ? on-chip debug mode register (ocdm) in addition, the prcdm register is provided to protect agai nst a write access to the special registers so that the application system does not inadvertently stop due to a program loop. a write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the sys register. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 101 of 1817 sep 19, 2011 (1) setting data to special registers set data to the special registers in the following sequence. <1> disable dma operation. <2> prepare data to be set to the special register in a general-purpose register. <3> write the data prepared in <2> to the prcmd register. <4> write the setting data to the special regi ster (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) (<5> to <9> insert nop instructions (5 instructions).) note <10> enable dma operation if necessary. [example] with psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle1, idle2, and stop modes). <1>clr1 0, dchcn[r0] ; disable dma operation. n = 0 to 3 <2>mov0x02, r10 <3>st.b r10, prcmd[r0] ; write prcmd register. <4>st.b r10, psc[r0] ; set psc register. <5>nop note ; dummy instruction <6>nop note ; dummy instruction <7>nop note ; dummy instruction <8>nop note ; dummy instruction <9>nop note ; dummy instruction <10>set1 0, dchcn[r0] ; enable dma operation. n = 0 to 3 (next instruction) there is no special sequence to read a special register. note five nop instructions or more must be inserted i mmediately after setting the idle1 mode, idle2 mode, or stop mode (by setting the psc.stp bit to 1). cautions 1. when a store instruction is executed to store data in the command register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instru ction is placed between <3> and <4>, and if an interrupt is acknowledged by that instructi on, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e prcmd register, use the same general-purpose register used to set the special register (<4> in example) to write data to the prcmd register (<3> in example). the same a pplies when a general-purpose regi ster is used for addressing. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 102 of 1817 sep 19, 2011 (2) command register (prcmd) the prcmd register is an 8-bit register that protects the regist ers that may seriously af fect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. the first write access to a special register is valid after data has been written in adv ance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to pr otect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 103 of 1817 sep 19, 2011 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 protection error did not occur protection error occurred prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <4> is executed without executing <3> in 3.4.8 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o regi ster other than a sp ecial register (including execution of a bit manipulation instruction) after writ ing data to the prcmd register (if <4> in 3.4.8 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is read (except by a bit manipulation instruction) between an operation to write the prcmd register and an ope ration to write a special register, the prerr flag is not set, and the set data can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcmd register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd register, which is not a special regi ster, immediately after a write access to the prcmd register , the prerr bit is set to 1. v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 104 of 1817 sep 19, 2011 3.4.9 cautions (1) registers to be set first be sure to set the following registers first when using the v850es/jh3-e and v850es/jj3-e. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register 2 (wdtm2) after setting the vswc, ocdm, and wdtm2 registers, set the other registers as necessary. when using the external bus, set each pin to the alternat e-function bus control pin mode by using the port-related registers after setting the above registers. (a) system wait control register (vswc) the vswc register controls wait of bus a ccess to the on-chip peripheral i/o registers. three clocks are required to access an on-chip peripheral i/o register (without a wa it cycle). the v850es/jh3- e and v850es/jj3-e require wait cycles according to t he operating frequency. set the following value to the vswc register in accordance with the frequency used. the vswc register can be read or written in 8-bit units. reset sets this register to 77h. vswc operating frequency (f cpu ) f cpu < 16.6 mhz 16.6 mhz f cpu < 25 mhz 25 mhz f cpu < 33.3 mhz 33.3 mhz f cpu 50 mhz set value of vswc 00h 01h 11h 12h number of waits 0 (no waits) 1 2 3 after reset: 77h r/w address: fffff06eh (b) on-chip debug mode register (ocdm) for details, see chapter 34 on-chip debug function . (c) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time a nd the operation clock of watchdog timer 2. watchdog timer 2 automatically starts in the reset mode af ter reset is released. write the wdtm2 register to activate this operation. for details, see chapter 13 functions of watchdog timer 2 . v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 105 of 1817 sep 19, 2011 (2) accessing specific on-chip peripheral i/o registers this product has two types of internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with low-speed peripheral hardware. the clock of the cpu bus and the clock of the periphera l bus are asynchronous. if an access to the cpu and an access to the peripheral hardware conflict, therefore, unex pected illegal data may be transferred. if there is a possibility of a conflict, the number of cycles for accessing the cpu changes when the peripheral hardware is accessed, so that correct data is transferred. as a resul t, the cpu does not start proce ssing of the next instruction but enters the wait status. if this wait status occurs, the number of cl ocks required to execute an instruction increases by the number of wait clocks shown below. this must be taken into consideration if real-time processing is required. when specific on-chip peripheral i/o registers are accessed, more wait states may be required in addition to the wait states set by the vswc register. the access conditions and how to calculate the number of wait states to be inserted (number of cpu clocks) at this time are shown below. (1/2) peripheral function register name access k taancnt read 1 or 2 write ? 1st access: no wait ? continuous write: 0 to 3 taanccr0, taanccr1 read 1 or 2 write ? 1st access: no wait ? continuous write: 0 to 3 16-bit timer/event counter aa (taa) (n = 0 to 5) taamioc4 read 1 or 2 tabncnt read 1 or 2 write ? 1st access: no wait ? continuous write: 0 to 3 tabnccr0 to tabnccr3 read 1 or 2 write ? 1st access: no wait ? continuous write: 0 to 3 16-bit timer/event counter ab (tab) (n = 0, 1) tabnioc4 read 1 or 2 tab0opt1 write ? 1st access: no wait ? continuous write: 0 to 3 motor control tab0dtc write ? 1st access: no wait ? continuous write: 0 to 3 tt0cnt read 1 or 2 write ? 1st access: no wait ? continuous write: 0 to 3 tmt tt0tcr0, tt0tcr1 read 1 or 2 watchdog timer 2 (wdt2) wdtm2 write (when wdt2 operating) 3 real-time output function (rto) rtbl0, rtbh0 write (rtpc0.rtpoe0 bit = 0) 1 ada0m0 read 1 or 2 ada0cr0 to ada0cr11 read 1 or 2 a/d converter ada0cr0h to ada0cr11h read 1 or 2 v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 106 of 1817 sep 19, 2011 (2/2) peripheral function register name access k cenctl0 write 1 centx0 (centx0h, centx0l) write 1 cencs (cencsl) write 1 csie (n = 0, 1) censtr read 1 ubntx write 1 ubnrx read 1 ubnrxap read 1 ubnfis0 read 1 uartb (n = 0, 1) ubnfis1 read 1 i 2 c00 to i 2 c04 iics0 to iics4 read 1 crc crcd write 1 c0gmabt, c0gmabtd, c0maskal, c0maskah, c0lec, c0info, c0erc, c0ie, c0ints, c0brp, c0btr, c0ts read/write f xx /f canmod + 1) / (2 + j) (min.) note (2 f xx /f canmod + 1) / (2 + j) (max.) note c0gmctrl, c0gmcs, c0ctrl read/write (f xx /f can + 1) / (2 + j) (min.) note (2 f xx /f can + 1) / (2 + j) (max.) note write (f xx /f canmod + 1) / (2 + j) (min.) note (2 f xx /f canmod + 1) / (2 + j) (max.) note c0rgpt, c0tgpt read (3 f xx /f canmod + 1) / (2 + j) (min.) note (4 f xx /f canmod + 1) / (2 + j) (max.) note c0lipt, c0lopt read (3 f xx /f canmod + 1) / (2 + j) (min.) note (4 f xx /f canmod + 1) / (2 + j) (max.) note write (4 f xx /f can + 1) / (2 + j) (min.) note (5 f xx /f can + 1) / (2 + j) (max.) note c0mctrlm read (3 f xx /f can + 1) / (2 + j) (min.) note (4 f xx /f can + 1) / (2 + j) (max.) note write (8 bits) (4 f xx /f canmod + 1) / (2 + j) (min.) note (5 f xx /f canmod + 1) / (2 + j) (max.) note write (16 bits) (2 f xx /f canmod + 1) / (2 + j) (min.) note (3 f xx /f canmod + 1) / (2 + j) (max.) note can controller (m = 0 to 31, a = 1 to 4) c0mdata01m, c0mdata0m, c0mdata1m, c0mdata23m, c0mdata2m, c0mdata3m, c0mdata45m, c0mdata4m, c0mdata5m, c0mdata67m, c0mdata6m, c0mdata7m, c0mdlcm, c0mconfm, c0midlm, c0midhm read (8/16 bits) (3 f xx /f canmod + 1) / (2 + j) (min.) note (4 f xx /f canmod + 1) / (2 + j) (max.) note v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 107 of 1817 sep 19, 2011 number of clocks necessary for access = 3 + i + j + (2 + j) k note digits below the decimal point are rounded up. caution accessing the above registers is prohibited in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock remark i: values (0) of higher 4 bits of vswc register j: values (0 or 1) of lower 4 bits of vswc register v850es/jh3-e, v850es/jj3-e chapter 3 cpu function r01uh0290ej0300 rev.3.00 page 108 of 1817 sep 19, 2011 (3) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an inst ruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request be fore the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 109 of 1817 sep 19, 2011 chapter 4 port functions 4.1 features { i/o ports ? v850es/jh3-e: 84 5 v tolerant/n-ch open-drain output selectable: 48 ? v850es/jj3-e: 100 5 v tolerant/n-ch open-drain output selectable: 59 { input/output specifiable in 1-bit units 4.2 basic port configuration the v850es/jh3-e features a total of 84 i/o ports consisting of ports 0, 2 to 5, 7, 9, cm, cs, ct, dh, and dl. the v850es/jj3-e features a total of 100 i/o ports consisting of ports 0, 2 to 5, 7, 9, cm, cs, ct, dh, and dl. the port configuration is shown below. table 4-1. i/o buffer power supplies for pins (v850es/jh3-e) power supply corresponding pins av ref0 port 7 ev dd reset, ports 0, 2 to 5, 9, cm, cs, ct, dh, dl table 4-2. i/o buffer power supplies for pins (v850es/jj3-e) power supply corresponding pins av ref0 port 7 ev dd reset, ports 0, 2 to 5, 9, cm, cs, ct, dh, dl v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 110 of 1817 sep 19, 2011 figure 4-1. port configuration diagram (v850es/jh3-e) pcm0 pcm1 port cm pcs0 pcs2 port cs p90 p915 port 9 pdl0 pdl15 port dl p30 p37 port 3 p20 p26 port 2 port 0 p40 p45 port 4 p50 p54 port 5 p70 p79 port 7 p02 p03 pct0 pct1 pct4 pct6 port ct pdh0 pdh5 port dh figure 4-2. port configuration diagram (v850es/jj3-e) pcm0 pcm3 port cm pcs0 pcs2 pcs3 pct0 pct1 pct4 pct6 port cs port ct pdh0 pdh7 port dh pdl0 pdl15 port dl p30 p37 port 3 p20 p27 port 2 p40 p48 port 4 p02 p03 port 0 p70 p711 p90 p915 port 7 p50 p59 port 5 port 9 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 111 of 1817 sep 19, 2011 4.3 port configuration table 4-3. port configuration (v850es/jh3-e) item configuration control register port n mode register (pmn: n = 0, 2 to 5, 7, 9, cm, cs, ct, dh, dl) port n mode control register (pmcn: n = 0, 2 to 5, 9, cm, cs, ct, dh, dl) port n function control register (pfcn: n = 0, 2 to 4, 9, dh) port n function control expansion register (pfcen: n = 2 to 4, 9, dh) port n function register (pfn: n = 0, 2 to 5, 9) ports i/o: 84 table 4-4. port configuration (v850es/jj3-e) item configuration control register port n mode register (pmn: n = 0, 2 to 5, 7, 9, cm, cs, ct, dh, dl) port n mode control register (pmcn: n = 0, 2 to 5, 9, cm, cs, ct, dh, dl) port n function control register (pfcn: n = 0, 2 to 5, 9, dh) port n function control expansion register (pfcen: n = 2 to 5, 9, dh) port n function register (pfn: n = 0, 2 to 5, 9) ports i/o: 100 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 112 of 1817 sep 19, 2011 (1) port n register (pn) data is input from or output to an external device by writing or reading the pn register. the pn register consists of a port latch that holds output data, and a circ uit that reads the status of pins. each bit of the pn register corresponds to one pin of port n, and can be read or written in 1-bit units. pn7 outputs 0. outputs 1. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h (output latch) r/w data is written to or read from the pn register as follows, regardless of the setting of the pmcn register. table 4-5. writing/reading pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm = 0) data is written to the output latch note . in the port mode (pmcn = 0), the contents of the output latch are output from the pins. the value of the output latch is read. input mode (pmnm = 1) data is written to the output latch. the pin status is not affected note . the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 113 of 1817 sep 19, 2011 (2) port n mode register (pmn) the pmn register specifies the input or output mode of the corresponding port pin. each bit of this register corresponds to one pin of por t n, and the input or output mode can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of input/output mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the pmcn register specifies the port mode or alternate function. each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. port mode alternate-function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 114 of 1817 sep 19, 2011 (4) port n function control register (pfcn) the pfcn register specifies the alternat e function of a port pin to be used if the pin has two alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function (5) port n function control expansion register (pfcen) the pfcen register specifies the alternate function of a port pin to be us ed if the pin has three or more alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 115 of 1817 sep 19, 2011 (6) port n function register (pfn) the pfn register specifies normal output or n-ch open-drain output. each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1- bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit of the pfn register is valid only when the pmnm bit of the pmn register is 0 (when the output mode is specified) in port mode (pmcnm bit = 0). when the pmnm bit is 1 (when the input mode is specified), the set value of the pfn register is invalid. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 116 of 1817 sep 19, 2011 (7) port setting set a port as illustrated below. figure 4-3. setting of each register and pin function pfcenm 0 1 0 1 pfcnm pmcn register output mode input mode pmn register ?0? ?1? ?0? ?1? ?0? ?1? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register 0 0 1 1 (a) (b) (c) (d) remark set the alternate functions in the following sequence. <1> set the pfcn and pfcen registers. <2> set the pmcn register. <3> set the intrn or intfn register (to specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 117 of 1817 sep 19, 2011 4.3.1 port 0 port 0 is 2-bit port for which i/o setti ngs can be controlled in 1-bit units. port 0 includes the following alternate-function pins. table 4-6. port 0 alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark p02 21 21 nmi input p03 22 22 intp00/adtrg/exclk input can be specified as an n-ch open-drain output caution the p02 and p03 pins have hysteresis characteri stics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (1) port 0 register (p0) outputs 0. outputs 1. p0n 0 1 output data control (in output mode) (n = 2, 3) p0 after reset: 00h (output latch) r/w address: fffff400h 0 0 0 0 p03 p02 0 0 76543210 (2) port 0 mode register (pm0) output mode input mode pm0n 0 1 i/o mode control (n = 2, 3) pm0 after reset: ffh r/w address: fffff420h 1 1 1 1 pm03 pm02 1 1 76543210 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 118 of 1817 sep 19, 2011 (3) port 0 mode control register (pmc0) pmc0 i/o port intp00 input/adtrg input/exclk input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode after reset: 00h r/w address: fffff440h 0 0 0 0 pmc03 pmc02 0 0 76543210 (4) port 0 function control register (pfc0) pfc0 after reset: 00h r/w address: fffff460h 0 0 0 0 pfc03 0 0 0 76543210 remark for details of alternate function specification, see 4.3.1 (6) port 0 alternate function specifications . (5) port 0 function control expansion register (pfce0) pfce0 after reset: 00h r/w address: fffff700h 0 0 0 0 pfce03 0 0 0 76543210 remark for details of alternate function specification, see 4.3.1 (6) port 0 alternate function specifications . (6) port 0 alternate function specifications pfce03 pfc03 specification of p03 pin alternate function 0 0 intp00 input 0 1 adtrg input 1 0 exclk input 1 1 setting prohibited (7) port 0 function register (pf0) v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 119 of 1817 sep 19, 2011 normal output n-ch open-drain output pf0n 0 1 control of normal output or n-ch open-drain output (n = 2, 3) pf0 after reset: 00h r/w address: fffffc60h 0 0 0 0 pf03 pf02 0 0 76543210 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 120 of 1817 sep 19, 2011 4.3.2 port 2 port 2 is a 7-bit (v850es/jh3-e)/8-bit (v850es/jj3-e) port for which i/o settings can be controlled in 1-bit units. port 2 includes the following alternate-function pins. table 4-7. port 2 alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark p20 38 38 tiab02/toab02/intp01 i/o p21 39 39 tiab00/toab00/rtcdiv/rtccl i/o p22 40 40 tiab01/toab01/rtc1hz/intp02 i/o p23 59 65 sif1/txdc1/sda00/intp03 i/o p24 62 68 sof1/rxdc1/scl00/intp04 input p25 63 69 sckf1/tiaa30/toaa30/udmarq0 i/o p26 64 70 tiaa31/toaa31/intp05/udmaak0 i/o p27 ? 41 tiab03/toab03/intp21 i/o can be specified as an n-ch open- drain output caution the p20 to p27 pins have hysteresis characteristi cs in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) port 2 register (p2) (a) v850es/jh3-e outputs 0. outputs 1. p2n 0 1 output data control (in output mode) (n = 0 to 6) p2 after reset: 00h (output latch) r/w address: fffff404h 0 p26 p25 p24 p23 p22 p21 p20 76543210 (b) v850es/jj3-e outputs 0. outputs 1. p2n 0 1 output data control (in output mode) (n = 0 to 7) p2 after reset: 00h (output latch) r/w address: fffff404h p27 p26 p25 p24 p23 p22 p21 p20 76543210 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 121 of 1817 sep 19, 2011 (2) port 2 mode register (pm2) (a) v850es/jh3-e output mode input mode pm2n 0 1 output data control (n = 0 to 6) pm2 after reset: ffh r/w address: fffff424h 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 76543210 (b) v850es/jj3-e output mode input mode pm2n 0 1 output data control (n = 0 to 7) pm2 after reset: ffh r/w address: fffff424h pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 76543210 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 122 of 1817 sep 19, 2011 (3) port 2 mode control register (pmc2) (1/2) (a) v850es/jh3-e pmc2 i/o port sckf1 i/o/tiaa30 input/toaa30 output/udmarq0 input pmc25 0 1 specification of p25 pin operation mode i/o port tiaa31 input/toaa31 output/intp05 input/udmaak0 output pmc26 0 1 specification of p26 pin operation mode i/o port sof1 output/rxdc1 input/scl00 i/o/intp04 input pmc24 0 1 specification of p24 pin operation mode i/o port sif1 input/txdc1 output/sda00 i/o/intp03 input pmc23 0 1 specification of p23 pin operation mode i/o port tiab01 input/toab01 output/rtc1hz output/intp02 input pmc22 0 1 specification of p22 pin operation mode i/o port tiab00 input/toab00 output/rtcdiv output/rtccl output pmc21 0 1 specification of p21 pin operation mode i/o port tiab02 input/toab02 output/intp01 input pmc20 0 1 specification of p20 pin operation mode after reset: 00h r/w address: fffff444h 0 pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 pmc20 76543210 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 123 of 1817 sep 19, 2011 (2/2) (b) v850es/jj3-e pmc2 i/o port sckf1 i/o/tiaa30 input/toaa30 output/udmarq0 input pmc25 0 1 specification of p25 pin operation mode i/o port tiaa31 input/toaa31 output/intp05 input/udmaak0 output pmc26 0 1 specification of p26 pin operation mode i/o port sof1 output/rxdc1 input/scl00 i/o/intp04 input pmc24 0 1 specification of p24 pin operation mode i/o port sif1 input/txdc1 output/sda00 i/o/intp03 input pmc23 0 1 specification of p23 pin operation mode i/o port tiab01 input/toab01 output/rtc1hz output/intp02 input pmc22 0 1 specification of p22 pin operation mode i/o port tiab00 input/toab00 output/rtcdiv output/rtccl output pmc21 0 1 specification of p21 pin operation mode i/o port tiab02 input/toab02 output/intp01 input pmc20 0 1 specification of p20 pin operation mode after reset: 00h r/w address: fffff444h pmc27 pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 pmc20 76543210 i/o port tiab03 input/toab03 output/intp21 input pmc27 0 1 specification of p27 pin operation mode v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 124 of 1817 sep 19, 2011 (4) port 2 function control register (pfc2) (a) v850es/jh3-e pfc2 after reset: 00h r/w address: fffff464h 0 pfc26 pfc25 pfc24 pfc23 pfc22 pfc21 pfc20 76543210 (b) v850es/jj3-e pfc2 after reset: 00h r/w address: fffff464h pfc27 pfc26 pfc25 pfc24 pfc23 pfc22 pfc21 pfc20 76543210 remark for details of alternate function specification, see 4.3.2 (6) port 2 alternate function specifications . (5) port 2 function control expansion register (pfce2) (a) v850es/jh3-e pfce2 after reset: 00h r/w address: fffff704h 0 pfce26 pfce25 pfce24 pfce23 pfce22 pfce21 pfce20 76543210 (b) v850es/jj3-e pfce2 after reset: 00h r/w address: fffff704h pfce27 pfce26 pfce25 pfce24 pfce23 pfce22 pfce21 pfce20 76543210 remark for details of alternate function specification, see 4.3.2 (6) port 2 alternate function specifications . v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 125 of 1817 sep 19, 2011 (6) port 2 alternate function specifications pfce27 pfc27 specification of p27 pin alternate function (v850es/jj3-e only) 0 0 tiab03 input 0 1 toab03 output 1 0 intp21 input 1 1 setting prohibited pfce26 pfc26 specification of p26 pin alternate function 0 0 tiab31 input 0 1 toab31 output 1 0 intp05 input 1 1 udmaak0 output pfce25 pfc25 specification of p25 pin alternate function 0 0 sckf1 i/o 0 1 tiaa30 input 1 0 toaa30 output 1 1 udmarq0 input pfce24 pfc24 specification of p24 pin alternate function 0 0 sof1 output 0 1 rxdc1 input 1 0 scl00 i/o 1 1 intp04 input pfce23 pfc23 specification of p23 pin alternate function 0 0 sif1 input 0 1 txdc1 output 1 0 sda00 i/o 1 1 intp03 input pfce22 pfc22 specification of p22 pin alternate function 0 0 tiab01 input 0 1 toab00 output 1 0 rtc1hz output 1 1 intp02 input pfce21 pfc21 specification of p21 pin alternate function 0 0 tiab00 input 0 1 toab00 output 1 0 rtcdiv output 1 1 rtccl output v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 126 of 1817 sep 19, 2011 pfce20 pfc20 specification of p20 pin alternate function 0 0 tiab02 input 0 1 toab02 output 1 0 intp01 input 1 1 setting prohibited (7) port 2 function register (pf2) (a) v850es/jh3-e normal output n-ch open-drain output pf2n 0 1 control of normal output or n-ch open-drain output (n = 0 to 6) pf2 after reset: 00h r/w address: fffffc64h 0 pf26 pf25 pf24 pf23 pf22 pf21 pf20 76543210 (b) v850es/jj3-e normal output n-ch open-drain output pf2n 0 1 control of normal output or n-ch open-drain output (n = 0 to 7) pf2 after reset: 00h r/w address: fffffc64h pf27 pf26 pf25 pf24 pf23 pf22 pf21 pf20 76543210 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 127 of 1817 sep 19, 2011 4.3.3 port 3 port 3 is a 8-bit port that controls i/o in 1-bit units. port 3 includes the following alternate-function pins. table 4-8. port 3 alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark p30 28 28 txdc0/sif2/tiaa00/toaa00 i/o p31 29 29 rxdc0/sof2/tiaa01/toaa01 i/o p32 30 30 asckc0/sckf2/tiaa10/toaa10 i/o p33 31 31 sif4/txdb0/tiaa11/toaa11 i/o p34 32 32 sof4/rxdb0/tiaa20/toaa20 i/o p35 33 33 sckf4/tiaa21/toaa21/toaa1off /intp06 i/o p36 36 36 txdc2/sda02/ctxd0 note i/o p37 37 37 rxdc2/scl02/crxd0 note i/o can be specified as an n-ch open- drain output note pd70f3783, 70f3786 only caution the p30 to p37 pins have hysteresis characteristi cs in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) port 3 register (p3) outputs 0. outputs 1. p3n 0 1 output data control (in output mode) (n = 0 to 7) p3 after reset: 00h (output latch) r/w address: fffff406h p37 p36 p35 p34 p33 p32 p31 p30 76543210 (2) port 3 mode register (pm3) output mode input mode pm3n 0 1 i/o mode control (n = 0 to 7) pm3 after reset: ffh r/w address: fffff426h pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 76543210 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 128 of 1817 sep 19, 2011 (3) port 3 mode control register (pmc3) i/o port rxdc2 input/scl02 i/o/crxd0 input note pmc37 0 1 specification of p37 pin operation mode i/o port txdc2 output/sda02 i/o/ctxd0 output note pmc36 0 1 specification of p36 pin operation mode pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pmc3 after reset: 00h r/w address: fffff446h i/o port sckf4 i/o/tiaa21 input/toaa21 output/toaa1off input/intp06 input pmc35 0 1 specification of p35 pin operation mode i/o port sof4 output/rxdb0 input/tiaa20 input/toaa20 output pmc34 0 1 specification of p34 pin operation mode i/o port sif4 input/txdb0 output/tiaa11 input/toaa11 output pmc33 0 1 specification of p33 pin operation mode i/o port ascka0 input/sckf2 i/o/tiaa10 input/toaa10 output pmc32 0 1 specification of p32 pin operation mode i/o port rxdc0 input/sof2 output/tiaa01 input/toaa01 output pmc31 0 1 specification of p31 pin operation mode i/o port txdc0 output/sif2 input/tiaa00 input/toaa00 output pmc30 0 1 specification of p30 pin operation mode note pd70f3783, 70f3786 only v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 129 of 1817 sep 19, 2011 (4) port 3 function control register (pfc3) pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 pfc3 after reset: 00h r/w address: fffff466h remark for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications . (5) port 3 function control expansion register (pfce3) pfce3 after reset: 00h r/w address: fffff706h pfce37 note pfce36 note pfce35 pfce34 pfce33 pfce32 pfce31 pfce30 note pd70f3783, 70f3786 only remark for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications . (6) port 3 alternate function specifications pfce37 note pfc37 specification of p37 pin alternate function 0 0 rxdc2 input 0 1 scl02 i/o 1 0 crxd0 input note 1 1 setting prohibited note note pd70f3783, 70f3786 only pfce36 note pfc36 specification of p36 pin alternate function 0 0 txdc2 output 0 1 sda02 i/o 1 0 ctxd0 output note 1 1 setting prohibited note note pd70f3783, 70f3786 only v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 130 of 1817 sep 19, 2011 pfce35 pfc35 specification of p35 pin alternate function 0 0 sckf4 i/o note 1 0 1 tiaa21 input 1 0 toaa21 output 1 1 toaa1off input/intp06 input note 2 notes 1. the sckf4 function is assigned to the pdh5 pin as well as the p35 pin. when using the p35 pin for the sckf4 function, do not specify the p dh5 pin to be used for this function. 2. toaa1off and intp09 are alternate functions. w hen using the pin as the toaa1off pin, disable intp09 pin edge detection, which is the alternate functi on. also, when using the pin as the intp09 pin, stop the high-impedance output controller. pfce34 pfc34 specification of p34 pin alternate function 0 0 sof4 output note 0 1 rxdb0 input 1 0 tiaa20 input 1 1 toaa20 output note the sof4 function is assigned to the pdh4 pin as we ll as the p34 pin. when using the p34 pin for the sof4 function, do not specify the pdh4 pin to be used for this function. pfce33 pfc33 specification of p33 pin alternate function 0 0 sif4 input note 0 1 txdb0 output 1 0 tiaa11 input 1 1 toaa11 output note the sif4 function is assigned to the pdh3 pin as well as the p33 pin. when using the p33 pin for the sif4 function, do not specify the pdh3 pin to be used for this function. pfce32 pfc32 specification of p32 pin alternate function 0 0 asckc0 input 0 1 sckf2 i/o 1 0 tiaa10 input 1 1 toaa10 output pfce31 pfc31 specification of p31 pin alternate function 0 0 rxdc0 input 0 1 sof2 input 1 0 tiaa01 input 1 1 toaa01 output pfce30 pfc30 specification of p30 pin alternate function 0 0 txdc0 output 0 1 sif2 input 1 0 tiaa00 input 1 1 toaa00 output v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 131 of 1817 sep 19, 2011 (7) port 3 function register (pf3) pf37 pf36 pf35 pf34 pf33 pf32 pf31 pf30 normal output (cmos output) n-ch open-drain output pf3n 0 1 control of normal output or n-ch open-drain output (n = 0 to 7) pf3 after reset: 00h r/w address: fffffc66h v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 132 of 1817 sep 19, 2011 4.3.4 port 4 port 4 is a 6-bit (v850es/jh3-e) and 9-bit (v850es/ jj3-e) port that controls i/o in 1-bit units. port 4 includes the following alternate-function pins. table 4-9. port 4 alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark p40 3 3 sif0/txdc3/sda01/rtp00 i/o p41 4 4 sof0/rxdc3/scl01/rtp01 i/o can be specified as an n-ch open-drain output p42 5 5 sckf0/tiaa40/toaa40/rtp02 i/o 6 ? sie0/txdc4/rtp03/hldak i/o p43 ? 6 sie0/txdc4/rtp03 i/o 7 ? soe0/rxdc4/rtp04/hldrq i/o p44 ? 7 soe0/rxdc4/rtp04 i/o p45 8 8 scke0/tiaa41/toaa41/rtp05 i/o ? p46 ? 128 sif5/txdc6/rtp06 i/o p47 ? 129 sof5/rxdc6/rtp07 i/o p48 ? 130 sckf5/intp22 i/o can be specified as an n-ch open-drain output caution the p40 to p48 pins have hysteresis characteristi cs in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 133 of 1817 sep 19, 2011 (1) port 4 register (p4) (a) v850es/jh3-e 0 outputs 0. outputs 1. p4n 0 1 output data control (in output mode) (n = 0 to 5) p4 0 p45 p44 p43 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (b) v850es/jj3-e 0 outputs 0. outputs 1. p4n 0 1 output data control (in output mode) (n = 0 to 8) 0 0 0 0 0 0 p48 p47 p46 p45 p44 p43 p42 p41 p40 8 9 10 11 12 13 14 15 p4 (p4h) (p4l) after reset: 0000h (output latch) r/w address: p4 fffff408h, p4l fffff408h, p4h fffff409h v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 134 of 1817 sep 19, 2011 (2) port 4 mode register (pm4) (a) v850es/jh3-e 1 output mode input mode pm4n 0 1 i/o mode control (n = 0 to 5) pm4 1 pm45 pm44 pm43 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h (b) v850es/jj3-e 1 output mode input mode pm4n 0 1 i/o mode control (n = 0 to 8) 1 1 1 1 1 1 pm48 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 8 9 10 11 12 13 14 15 pm4 (pm4h) (pm4l) after reset: ffffh r/w address: pm4 fffff428h, pm4l fffff428h, pm4h fffff429h v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 135 of 1817 sep 19, 2011 (3) port 4 mode control register (pmc4) (1/2) (a) v850es/jh3-e 0 pmc4 0 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 i/o port scke0 i/o/tiaa41 input/toaa41 output/rtp05 output pmc45 0 1 specification of p45 pin operation mode i/o port soe0 output/rxdc4 input/rtp04 output/hldrq input pmc44 0 1 specification of p44 pin operation mode i/o port sie0 input/txdc4 output/rtp03 output/hldak output pmc43 0 1 specification of p43 pin operation mode after reset: 00h r/w address: fffff448h i/o port sckf0 i/o/tiaa40 input/toaa40 output/rtp02 output pmc42 0 1 specification of p42 pin operation mode i/o port sof0 output/rxdc3 input/scl01 i/o/rtp01 output pmc41 0 1 specification of p41 pin operation mode i/o port sif0 input/txdc3 output/sda01 i/o/rtp00 output pmc40 0 1 specification of p40 pin operation mode v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 136 of 1817 sep 19, 2011 (2/2) (b) v850es/jj3-e 0 i/o port sckf5 i/o/intp22 input pmc48 0 1 specification of p48 pin operation mode 0 0 0 0 0 0 pmc48 pmc47 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 8 9 10 11 12 13 14 15 pmc4 (pmc4h) (pmc4l) after reset: 0000h (output latch) r/w address: pmc4 fffff448h, pmc4l fffff448h, pmc4h fffff449h i/o port scke0 i/o/tiaa41 input/toaa41 output/rtp05 output pmc45 0 1 specification of p45 pin operation mode i/o port soe0 output/rxdc4 input/rtp04 pmc44 0 1 specification of p44 pin operation mode i/o port sie0 input/txdc4 output/rtp03 output pmc43 0 1 specification of p43 pin operation mode i/o port sof5 output/rxdc6 input/rtp07 output pmc47 0 1 specification of p47 pin operation mode i/o port sif5 input/txdc6 output/rtp06 output pmc46 0 1 specification of p46 pin operation mode i/o port sckf0 i/o/tiaa40 input/toaa40 output/rtp02 output pmc42 0 1 specification of p42 pin operation mode i/o port sof0 output/rxdc3 input/scl01 i/o/rtp01 output pmc41 0 1 specification of p41 pin operation mode i/o port sif0 input/txdc3 output/sda01 i/o/rtp00 output pmc40 0 1 specification of p40 pin operation mode v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 137 of 1817 sep 19, 2011 (4) port 4 function control register (pfc4) (a) v850es/jh3-e pfc4 after reset: 00h r/w address: fffff468h 0 0 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 (b) v850es/jj3-e 0 0 0 0 0 0 0 pfc48 pfc47 pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 8 9 10 11 12 13 14 15 pfc4 (pfc4h) (pfc4l) after reset: 0000h r/w address: pfc4 fffff468h, pfc4l fffff468h, pfc4h fffff469h remarks 1. for details of alternate- function specification, see 4.3.4 (6) port 4 alternate function specifications . 2. the pfc4 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc4 register as the pfc4h register and the lower 8 bits as the pfc4l register, t he register can be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfc4 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc4h register. (5) port 4 function control ex pansion register l (pfce4l) (a) v850es/jh3-e pfce4l after reset: 00h r/w address: fffff708h 0 0 pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 (b) v850es/jj3-e pfce4l after reset: 00h r/w address: fffff708h pfce47 pfce46 pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 remark for details of alternate function specification, see 4.3.4 (6) port 4 alternate function specifications . v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 138 of 1817 sep 19, 2011 (6) port 4 alternate function specifications pfc48 note specification of p48 pin note alternate function 0 sckf5 i/o 1 intp22 input note v850es/jj3-e only pfce47 note pfc47 note specification of p47 pin note alternate function 0 0 sof5 output 0 1 rxdc6 input 1 0 rtp07 output 1 1 setting prohibited note v850es/jj3-e only pfce46 note pfc46 note specification of p46 pin note alternate function 0 0 sif5 input 0 1 txdc6 output 1 0 rtp06 output 1 1 setting prohibited note v850es/jj3-e only pfce45 pfc45 specification of p45 pin alternate function 0 0 scke0 i/o 0 1 tiaa41 input 1 0 toaa41 output 1 1 rtp05 output pfce44 pfc44 specification of p44 pin alternate function 0 0 soe0 output 0 1 rxdc4 input 1 0 rtp04 output 1 1 hldrq input note note v850es/jh3-e only, setting prohibited in v850es/jj3-e pfce43 pfc43 specification of p44 pin alternate function 0 0 sie0 input 0 1 txdc4 output 1 0 rtp03 output 1 1 hldak output note note v850es/jh3-e only, setting prohibited in v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 139 of 1817 sep 19, 2011 pfce42 pfc42 specification of p42 pin alternate function 0 0 sckf0 i/o 0 1 tiaa40 input 1 0 toaa40 output 1 1 rtp02 output pfce41 pfc41 specification of p41 pin alternate function 0 0 sof0 output 0 1 rxdc3 input 1 0 scl01 i/o 1 1 rtp01 output pfce40 pfc40 specification of p40 pin alternate function 0 0 sif0 input 0 1 txdc3 output 1 0 sda01 i/o 1 1 rtp00 output v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 140 of 1817 sep 19, 2011 (7) port 4 function register (pf4) (a) v850es/jh3-e 0 normal output (cmos output) n-ch open-drain output pf4n 0 1 control of normal output or n-ch open-drain output (n = 0 to 2) pf4 0 0 0 0 pf42 pf41 pf40 after reset: 00h r/w address: fffffc68h (b) v850es/jj3-e 0 normal output (cmos output) n-ch open-drain output pf4n 0 1 control of normal output or n-ch open-drain output (n = 0 to 2, 6 to 8) 0 0 0 0 0 0 pf48 pf47 pf46 0 0 0 pf42 pf41 pf40 8 9 10 11 12 13 14 15 pf4 (pf4h) (pf4l) after reset: 0000h r/w address: pf4 fffffc68h, pf4l fffffc68h, pf4h fffffc69h remarks 1. the pf4 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf4 register as the pf4h register and the lower 8 bits as the pf4l register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pf4 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pf4h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 141 of 1817 sep 19, 2011 4.3.5 port 5 port 5 is a 5-bit (v850es/jh3-e) /10-bit (v850es/jj3-e) port that controls i/o in 1-bit units. port 5 includes the following alternate-function pins. table 4-10. port 5 alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark p50 23 23 intp07/ddi note input p51 24 24 intp08/ddo note i/o p52 25 25 intp09/dck note input p53 26 26 iintp10/dms note input p54 27 27 intp11/drst note input p55 ? 42 sda04/intp23/udmarq1 i/o p56 ? 43 scl04/intp24/udmaak1 i/o p57 ? 62 sif6/txdc7 i/o p58 ? 63 sof6/rxdc7 i/o p59 ? 64 sckf6/intp25 input can be specified as an n-ch open-drain output note the ddi, ddo, dck, dms, and drst pins are used for on-chip debugging. if on-chip debugging is not used, fix the p54/intp11/d rst pin to low level between when the reset by the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). for details, see 4.5.3 cautions on on-chip debug pins . cautions 1. when the power is turn ed on, the p51 pin may output an undefined level temporarily even during reset. 2. the p50 to p59 pins have hysteresis characteri stics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 142 of 1817 sep 19, 2011 (1) port 5 register (p5) (a) v850es/jh3-e 0 outputs 0. outputs 1. p5n 0 1 output data control (in output mode) (n = 0 to 4) p5 0 0 p54 p53 p52 p51 p50 after reset: 00h (output latch) r/w address: fffff40ah (b) v850es/jj3-e 0 outputs 0. outputs 1. p5n 0 1 output data control (in output mode) (n = 0 to 9) 0 0 0 0 0 p59 p58 p57 p56 p55 p54 p53 p52 p51 p50 8 9 10 11 12 13 14 15 p5 (p5h) (p5l) after reset: 0000h (output latch) r/w address: p5 fffff40ah, p5l fffff40ah, p5h fffff40bh remarks 1. the p5 register can be read or written in 16-bit units. however, when using the higher 8 bits of the p5 register as the p5h register and the lower 8 bits as the p5l register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p5 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p5h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 143 of 1817 sep 19, 2011 (2) port 5 mode register (pm5) (a) v850es/jh3-e 1 output mode input mode pm5n 0 1 i/o mode control (n = 0 to 4) pm5 1 1 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah (b) v850es/jj3-e 1 output mode input mode pm5n 0 1 i/o mode control (n = 0 to 9) 1 1 1 1 1 pm59 pm58 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 8 9 10 11 12 13 14 15 pm5 (pm5h) (pm5l) after reset: ffffh r/w address: pm5 fffff42ah, pm5l fffff42ah, pm5h fffff42bh remarks 1. the pm5 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pm5 register as the pm5h register and the lower 8 bits as the pm5l register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pm5 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm5h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 144 of 1817 sep 19, 2011 (3) port 5 mode control register (pmc5) (1/2) (a) v850es/jh3-e 0 pmc5 0 0 pmc54 pmc53 pmc52 pmc51 pmc50 i/o port intp11 input pmc54 0 1 specification of p54 pin operation mode i/o port intp10 input pmc53 0 1 specification of p53 pin operation mode i/o port intp09 input pmc52 0 1 specification of p52 pin operation mode i/o port intp08 input pmc51 0 1 specification of p51 pin operation mode i/o port intp07 input pmc50 0 1 specification of p50 pin operation mode after reset: 00h r/w address: fffff44ah v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 145 of 1817 sep 19, 2011 (2/2) (b) v850es/jj3-e 0 i/o port sckf6 i/o/intp25 input pmc59 0 1 specification of p59 pin operation mode 0 0 0 0 0 pmc59 pmc58 pmc57 pmc56 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 8 9 10 11 12 13 14 15 pmc5 (pmc5h) (pmc5l) after reset: 0000h r/w address: pmc5 fffff44ah, pmc5l fffff44ah, pmc5h fffff44bh i/o port sda04 i/o/intp23 input/udmarq1 input pmc56 0 1 specification of p56 pin operation mode i/o port scl04 i/o/intp24 input/udmaak1 output pmc55 0 1 specification of p55 pin operation mode i/o port sof6 output/rxdc7 input pmc58 0 1 specification of p58 pin operation mode i/o port sif6 input/txdc7 output pmc57 0 1 specification of p57 pin operation mode i/o port intp11 input pmc54 0 1 specification of p54 pin operation mode i/o port intp10 input pmc53 0 1 specification of p53 pin operation mode i/o port intp09 input pmc52 0 1 specification of p52 pin operation mode i/o port intp08 input pmc51 0 1 specification of p51 pin operation mode i/o port intp07 input pmc50 0 1 specification of p50 pin operation mode remarks 1. the pmc5 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc5 register as the pmc5h register and the lower 8 bits as the pmc5l register, they can be read or written in 8-bit or 1- bit units. 2. to read/write bits 8 to 15 of the pmc5 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc5h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 146 of 1817 sep 19, 2011 (4) port 5 function control register (pfc5) (v850es/jj3-e only) 0 0 0 0 0 0 pfc59 pfc58 pfc57 pfc56 pfc55 0 0 0 0 0 8 9 10 11 12 13 14 15 pfc5 (pfc5h) (pfc5l) after reset: 0000h r/w address: pfc5 fffff46ah, pfc5l fffff46ah, pfc5h fffff46bh remarks 1. for details of alternate f unction specification, see 4.3.5 (6) port 5 alternate function specifications . 2. the pfc5 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc5 register as the pfc5h register and the lower 8 bits as the pfc5l register, they can be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfc5 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc5h register. (5) port 5 function control expansion register l (pfce5l) (v850es/jj3-e only) 0 pfce5l pfce56 pfce55 0 0 0 0 0 after reset: 00h r/w address: fffff70ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (6) port 5 alternate function specifications (v850es/jj3-e only) pfc59 specification of p59 pin alternate function 0 sckf6 i/o 1 intp25 input pfc58 specification of p58 pin alternate function 0 sof6 output 1 rxdc7 input pfc57 specification of p57 pin alternate function 0 sif6 input 1 txdc7 output v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 147 of 1817 sep 19, 2011 pfce56 pfc56 specification of p56 pin alternate function 0 0 scl04 i/o 0 1 intp24 input 1 0 udmaak1 output 1 1 setting prohibited pfce55 pfc55 specification of p55 pin alternate function 0 0 sda04 i/o 0 1 intp23 input 1 0 udmarq1 input 1 1 setting prohibited (7) port 5 function register (pf5) (a) v850es/jh3-e 0 normal output (cmos output) n-ch open-drain output pf5n 0 1 control of normal output or n-ch open-drain output (n = 0 to 4) pf5 0 0 pf54 pf53 pf52 pf51 pf50 after reset: 00h r/w address: fffffc6ah (b) v850es/jj3-e 0 normal output (cmos output) n-ch open-drain output pf5n 0 1 control of normal output or n-ch open-drain output (n = 0 to 9) 0 0 0 0 0 pf59 pf58 pf57 pf56 pf55 pf54 pf53 pf52 pf51 pf50 8 9 10 11 12 13 14 15 pf5 (pf5h) (pf5l) after reset: 0000h r/w address: pf5 fffffc6ah, pf5l fffffc6ah, pf5h fffffc6bh remarks 1. the pf5 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf5 register as the pf5h register and the lower 8 bits as the pf5l register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pf5 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pf5h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 148 of 1817 sep 19, 2011 4.3.6 port 7 port 7 is a 10-bit (v850es/jh3-e) and 12-bit (v850es/jj3-e) port for which i/o settings can be controlled in 1-bit units. port 7 includes the following alternate-function pins. table 4-11. port 7 alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark p70 128 144 ani0 input p71 127 143 ani1 input p72 126 142 ani2 input p73 125 141 ani3 input p74 124 140 ani4 input p77 123 139 ani5 input p76 122 138 ani6 input p77 121 137 ani7 input p78 120 136 ani8 input p79 119 135 ani9 input p710 ? 134 ani10 input p711 ? 133 ani11 input ? v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 149 of 1817 sep 19, 2011 (1) port 7 register h, port 7 register l (p7h, p7l) (a) v850es/jh3-e outputs 0. outputs 1. p7n 0 1 output data control (in output mode) (n = 0 to 9) p7h p7l after reset: 00h (output latch) r/w address: p7l fffff40eh, p7h fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 0 0 0 0 0 0 p79 p78 (b) v850es/jj3-e outputs 0. outputs 1. p7n 0 1 output data control (in output mode) (n = 0 to 11) p7h p7l after reset: 00h (output latch) r/w address: p7l fffff40eh, p7h fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 0 0 0 0 p711 p710 p79 p78 caution do not read or write the p7h and p7 l registers during a/d co nversion (see 15.6 (4) alternate i/o). remark these registers cannot be accessed in 16-bit uni ts as the p7 register. they can be read or written in 8-bit or 1-bit units as the p7h and p7l registers. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 150 of 1817 sep 19, 2011 (2) port 7 mode register h, port 7 mode register l (pm7h, pm7l) (a) v850es/jh3-e 1 output mode input mode pm7n 0 1 i/o mode control (n = 0 to 9) pm7h pm7l 1 1 1 1 1 pm79 pm78 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 after reset: ffh r/w address: pm7l fffff42eh, pm7h fffff42fh (b) v850es/jj3-e 1 output mode input mode pm7n 0 1 i/o mode control (n = 0 to 11) pm7h pm7l 1 1 1 pm711 pm710 pm79 pm78 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 after reset: ffh r/w address: pm7l fffff42eh, pm7h fffff42fh caution when using the p7n pin as its alternate function (anin pin), set the pm7n bit to 1. remark these registers cannot be accessed in 16-bit units as the pm7 register. they can be read or written in 8-bit or 1-bit uni ts as the pm7h and pm7l registers. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 151 of 1817 sep 19, 2011 4.3.7 port 9 port 9 is a 16-bit port for which i/o settings can be controlled in 1-bit units. port 9 includes the following alternate-function pins. table 4-12. port 9 alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark p90 65 71 toab1t1/toab11/tiab11/kr0 /intp12/a0 i/o p91 66 72 toab1b1/tiab10/kr1/toab10/a1 i/o p92 67 73 toab1t2/toab12/tiab12/kr2 /intp13/a2 i/o p93 68 74 toab1b2/trgab1/kr3/intp14/a3 i/o p94 69 75 toab1t3/toab13/tiab13/kr4 /intp15/a4 i/o p95 70 76 toab1b3/evtab1/kr5/intp16/a5 i/o p96 71 77 tecr0/tit00/kr6/tot00/a6 i/o p97 72 78 tenc00/tit01/kr7/tot01/a7 i/o p98 73 79 tenc01/intp17/a8 i/o p99 74 80 sie1/txdc5/sda03/a9 i/o p910 75 81 soe1/rxdc5/scl03/a10 i/o p911 76 82 scke1/tiaa50/toaa50/a11 i/o p912 77 83 toab1off/intp18/a12 i/o p913 78 84 sif3/txdb1/intp19/a13 i/o p914 79 85 sof3/rxdb1/intp20/a14 i/o p915 80 86 sckf3/tiaa51/toaa51/a15 i/o can be specified as an n-ch open- drain output caution the p90 to p915 pins have hyst eresis characteristics in the input m ode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 152 of 1817 sep 19, 2011 (1) port 9 register (p9) p915 outputs 0. outputs 1. p9n 0 1 output data control (in output mode) (n = 0 to 15) p914 p913 p912 p911 p910 p99 p98 p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 p9 (p9h) (p9l) after reset: 0000h (output latch) r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h remarks 1. the p9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the p9 register as the p9h register and the lower 8 bits as the p9l register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p9h register. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 i/o mode control (in output mode) (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 pm9 (pm9h) (pm9l) after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h remarks 1. the pm9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pm9 register as the pm9h register and the lower 8 bits as the pm9l register, th ey can be read or written in 8-bit and 1-bit units. 2. to read/write bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm9h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 153 of 1817 sep 19, 2011 (3) port 9 mode control register (pmc9) (1/2) i/o port sckf3 i/o/tiaa51 input/toaa51 output/a15 output pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port sof3 output/rxdb1 input/intp20 input/a14 output pmc914 0 1 specification of p914 pin operation mode i/o port scke1 i/o/tiaa50 input/toaa50 output/a11 output pmc911 0 1 specification of p911 pin operation mode i/o port soe1 output/rxdc5 input/scl03 i/o/a10 output pmc910 0 1 specification of p910 pin operation mode i/o port sie1 input/txdc5 output/sda03 i/o/a9 output pmc99 0 1 specification of p99 pin operation mode i/o port sif3 input/txdb1 output/intp19 input/a13 output pmc913 0 1 specification of p913 pin operation mode i/o port toab1off input/intp18 input/a12 output pmc912 0 1 specification of p912 pin operation mode pmc9 (pmc9h) (pmc9l) after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h i/o port tenc01 input/intp17 input/a8 output pmc98 0 1 specification of p98 pin operation mode remarks 1. the pmc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc9 register as the pmc9h register and the lower 8 bits as the pmc9l register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc9 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc9h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 154 of 1817 sep 19, 2011 (2/2) i/o port tenc00 input/tit01 input/kr7 input/tot01 output/a7 output pmc97 0 1 specification of p97 pin operation mode i/o port tecr0 input/tit00 input/kr06 input/tot00 output/a6 output pmc96 0 1 specification of p96 pin operation mode i/o port toab1b3 output/evtab1 input/kr5 input/intp16 input/a5 output pmc95 0 1 specification of p95 pin operation mode i/o port toab1t3 output/toab13 output/tiab13 input/kr4 input/intp15 input/a4 output pmc94 0 1 specification of p94 pin operation mode i/o port toab1b2 output/trgab1 input/kr3 input/intp14 input/a3 output pmc93 0 1 specification of p93 pin operation mode i/o port toab1t2 output/toab12 output/tiab12 input/kr2 input/intp13 input/a2 output pmc92 0 1 specification of p92 pin operation mode i/o port toab1b1 output/tiab10 input/kr1 input/toab10 output/a1 output pmc91 0 1 specification of p91 pin operation mode i/o port toab1t1 output/toab11 output/tiab11 input/kr0 input/intp12 input/a0 output pmc90 0 1 specification of p90 pin operation mode caution when using the a0 to a15 pins as the alternate functions of the p90 to p915 pins, be sure to set all 16 bits of the pmc9 register to ffffh at once. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 155 of 1817 sep 19, 2011 (4) port 9 function control register (pfc9) caution when performing separate ad dress bus output (a0 to a15), set the pmc9 register to ffffh for all 16 bits at once after clearing the pfc9 regist er to feffh and the pfce 9 registers to efffh. pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc9 (pfc9h) (pfc9l) remarks 1. for details of alternate f unction specification, see 4.3.7 (6) port 9 alternate function specifications . 2. the pfc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc9 register as the pfc9h register and the lower 8 bits as the pfc9l register, th ey can be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfc9 regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc9h register. (5) port 9 function control expansion register (pfce9) caution when performing separate ad dress bus output (a0 to a15), set the pmc9 register to ffffh for all 16 bits at once after clearing the pfc9 regist er to feffh and the pfce9 registers to 0000h. pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 pfce915 pfce914 pfce913 0 pfce911 pfce910 pfce99 pfce98 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h pfce9 (pfce9h) (pfce9l) remarks 1. for details of alternate f unction specification, see 4.3.7 (6) port 9 alternate function specifications . 2. the pfce9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfce9 register as the pfce9h register and the lower 8 bits as the pfce9l register, they can be read or written in 8-bit or 1- bit units. 3. to read/write bits 8 to 15 of the pfce9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfce9h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 156 of 1817 sep 19, 2011 (6) port 9 alternate function specifications pfce915 pfc915 specification of p915 pin alternate function 0 0 sckf3 i/o 0 1 tiaa51 input 1 0 toaa51 output 1 1 a15 output pfce914 pfc914 specification of p914 pin alternate function 0 0 sof3 output 0 1 rxdb1 input 1 0 intp20 input 1 1 a14 output pfce913 pfc913 specification of p913 pin alternate function 0 0 sif3 input 0 1 txdb1 output 1 0 intp19 input 1 1 a13 output pfc912 specification of p912 pin alternate function 0 toab1off input/intp18 input 1 a12 output caution toab1off and intp18 are alternate functions of the p912 pin. when using the pin for the toab1off function, disable interrupt detection of intp18, which is an alternate function (set the intr9.intr912 and intf9.intf912 bits to 0) . also, when using the pin for the intp18 function, disable edge detection of toab1off, which is an alternate function (set the hza0ctl0. hza0dcn0 and nza0dcp0 bits to 00). pfce911 pfc911 specification of p911 pin alternate function 0 0 scke1 i/o 0 1 tiaa50 input 1 0 toaa50 output 1 1 a11 output caution the scke1 function is assigned to the pdh2 pi n as well as the p911 pin. when using the p911 pin for the scke1 function, do not specify the pdh2 pin to be used for this function. pfce910 pfc910 specification of p910 pin alternate function 0 0 soe1 output 0 1 rxdc5 input 1 0 scl03 i/o 1 1 a10 output v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 157 of 1817 sep 19, 2011 pfce99 pfc99 specification of p99 pin alternate function 0 0 sie1 input 0 1 txdc5 output 1 0 sda03 i/o 1 1 a9 output caution the sie1 function is assigned to the pdh0 pin as well as the p 99 pin. when using the p99 pin for the sie1 function, do not set the pdh0 pin to be used for this function. pfce98 pfc98 specification of p98 pin alternate function 0 0 tenc01 input 0 1 intp17 input 1 0 a8 output 1 1 setting prohibited pfce97 pfc97 specification of p97 pin alternate function 0 0 tenc00 input 0 1 tit01 input/kr7 input 1 0 tot01 output 1 1 a7 output caution kr7 and tit01 are alternate functions. when using the pin fo r the tit01 function, disable key return detection of kr7, which is the alternate f unction (set the krm.krm7 bit to 0). also, when using the pin for the kr7 function, disable edge detection of tit01, which is the alternate function (set the tti0ioc1.tt0is3 and tt0is2 bits to 00). pfce96 pfc96 specification of p96 pin alternate function 0 0 tecr0 input 0 1 tit00 input/kr6 input 1 0 tot00 output 1 1 a6 output caution kr6 and tit00 are alternate functions. when using the pin fo r the tit00 function, disable key return detection of kr6, which is the alternate f unction (set the krm.krm6 bit to 0). also, when using the pin for the kr6 function, disable edge detection of tit00, which is the alternate function (set the tti0ioc1.tt0is1 and tt0is0 bits to 00). pfce95 pfc95 specification of p95 pin alternate function 0 0 toab1b3 output 0 1 evtab1 input/kr5 input 1 0 intp16 input 1 1 a5 output caution kr5 and evtab1 are alternate functions. wh en using the pin for the evtab1 function, disable key return detection of kr5, which is the altern ate function (set the krm.krm5 bit to 0). also, when using the pin for the kr5 function, disab le edge detection of evtab1, which is the alternate function (set the tab1ioc2. tab1ees1 and tab1ees0 bits to 00). v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 158 of 1817 sep 19, 2011 pfce94 pfc94 specification of p94 pin alternate function 0 0 toab1t3 output/toab13 output 0 1 tiab13 input/kr4 input 1 0 intp15 input 1 1 a4 output caution kr4 and tiab13 are alternate functions. wh en using the pin for the tiab13 function, disable key return detection of kr4, which is the altern ate function (set the krm.krm4 bit to 0). also, when using the pin for the kr4 function, disable edge detection of tiab13, which is the alternate function (set the tab1ioc1.tab1is7 and tab1is6 bits to 00). pfce93 pfc93 specification of p93 pin alternate function 0 0 toab1b2 output 0 1 trgab1 input/kr3 input 1 0 intp14 input 1 1 a3 output caution kr3 and trgab1 are alternate functions. wh en using the pin for the trgab1 function, disable key return detection of kr3, which is the altern ate function (set the krm.krm3 bit to 0). also, when using the pin for the kr3 function, disab le edge detection of trgab1, which is the alternate function (set the tab1ioc2.ta b1ets1 and tab1ets0 bits to 00). pfce92 pfc92 specification of p92 pin alternate function 0 0 toab1t2 output/toab12 output 0 1 tiab12 input/kr2 input 1 0 intp13 input 1 1 a2 output caution kr2 and tiab12 are alternate functions. wh en using the pin for the tiab12 function, disable key return detection of kr2, which is the altern ate function (set the krm.krm2 bit to 0). also, when using the pin for the kr2 function, disable edge detection of tiab12, which is the alternate function (set the tab1ioc1.tab1is5 and tab1is4 bits to 00). pfce91 pfc91 specification of p91 pin alternate function 0 0 toab1b1 output 0 1 tiab10 input/kr1 input 1 0 toab10 output 1 1 a1 output caution kr1 and tiab10 are alternate functions. wh en using the pin for the tiab10 function, disable key return detection of kr1, which is the altern ate function (set the krm.krm1 bit to 0). also, when using the pin for the kr1 function, disable edge detection of tiab10, which is the alternate function (set the tab1ioc1.tab1is1 and tab1is0 bits to 00). pfce90 pfc90 specification of p90 pin alternate function 0 0 toab1t1 output/toab11 output 0 1 tiab11 input/kr0 input 1 0 intp12 input 1 1 a0 output caution kr0 and tiab11 are alternate functions. wh en using the pin for the tiab11 function, disable key return detection of kr0, which is the altern ate function (set the krm.krm0 bit to 0). also, when using the pin for the kr0 function, disable edge detection of tiab11, which is the alternate function (set the tab1ioc1.tab1is3 and tab1is2 bits to 00). v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 159 of 1817 sep 19, 2011 (7) port 9 function register (pf9) pf97 pf96 pf95 pf94 pf93 pf92 pf91 pf90 pf915 pf914 pf913 pf912 pf911 pf910 pf99 pf98 8 9 10 11 12 13 14 15 normal output (cmos output) n-ch open-drain output pf9n 0 1 control of normal output or n-ch open-drain output (n = 0 to 15) pf9 (pf9l) after reset: 0000h r/w address: pf9 fffffc72h, pf9l fffffc72h caution when output pins are pulled up to ev dd or higher, be sure to set the pf9n bit to 1. remarks 1. the pf9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf9 register as the pf9h register and the lower 8 bits as the pf9l register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pf9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pf9h register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 160 of 1817 sep 19, 2011 4.3.8 port cm port cm is a 2-bit (v850es/jh3-e)/4-bit (v850es/jj3-e) port for which i/o settings can be controlled in 1-bit units. port cm includes the following alternate-function pins. table 4-13. port cm alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark pcm0 86 92 wait input pcm1 81 87 clkout output pcm2 ? 119 hldak output pcm3 ? 120 hldrq input ? (1) port cm register (pcm) (a) v850es/jh3-e 0 outputs 0. outputs 1. pcmn 0 1 output data control (in output mode) (n = 0, 1) pcm 0 0 0 0 0 pcm1 pcm0 after reset: 00h (output latch) r/w address: fffff00ch (b) v850es/jj3-e 0 outputs 0. outputs 1. pcmn 0 1 output data control (in output mode) (n = 0 to 3) pcm 0 0 0 pcm3 pcm2 pcm1 pcm0 after reset: 00h (output latch) r/w address: fffff00ch v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 161 of 1817 sep 19, 2011 (2) port cm mode register (pmcm) (a) v850es/jh3-e 1 output mode input mode pmcmn 0 1 i/o mode control (n = 0, 1) pmcm 1 1 1 1 1 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch (b) v850es/jj3-e 1 output mode input mode pmcmn 0 1 i/o mode control (n = 0 to 3) pmcm 1 1 1 pmcm3 pmcm2 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 162 of 1817 sep 19, 2011 (3) port cm mode control register (pmccm) (a) v850es/jh3-e 0 pmccm 0 0 0 0 0 pmccm1 pmccm0 i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch (b) v850es/jj3-e 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldrq input pmccm3 0 1 specification of pcm3 pin operation mode i/o port hldak output pmccm2 0 1 specification of pcm2 pin operation mode i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 163 of 1817 sep 19, 2011 4.3.9 port cs port cs is a 2-bit (v850es/jh3-e)/3-bit (v850es/jj3-e) port for which i/o settings can be controlled in 1-bit units. port cs includes the following alternate-function pins. table 4-14. port cm alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark pcs0 115 125 cs0 output pcs2 116 126 cs2 output pcs3 ? 127 cs3 output ? (1) port cs register (pcs) (a) v850es/jh3-e 0 outputs 0. outputs 1. pcsn 0 1 output data control (in output mode) (n = 0, 2) pcs 0 0 0 0 pcs2 0 pcs0 after reset: 00h (output latch) r/w address: fffff008h (b) v850es/jj3-e 0 outputs 0. outputs 1. pcsn 0 1 output data control (in output mode) (n = 0, 2, 3) pcs 0 0 0 pcs3 pcs2 0 pcs0 after reset: 00h (output latch) r/w address: fffff008h v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 164 of 1817 sep 19, 2011 (2) port cs mode register (pmcs) (a) v850es/jh3-e 1 output mode input mode pmcsn 0 1 i/o mode control (n = 0, 2) pmcs 1 1 1 1 pmcs2 1 pmcs0 after reset: ffh r/w address: fffff028h (b) v850es/jj3-e 1 output mode input mode pmcsn 0 1 i/o mode control (n = 0, 2, 3) pmcs 1 1 1 pmcs3 pmcs2 1 pmcs0 after reset: ffh r/w address: fffff028h v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 165 of 1817 sep 19, 2011 (3) port cs mode control register (pmccs) (a) v850es/jh3-e 0 pmccs 0 0 0 0 pmccs2 0 pmccs0 i/o port cs2 output pmccs2 0 1 specification of pcs2 pin operation mode i/o port cs0 output pmccs0 0 1 specification of pcs0 pin operation mode after reset: 00h r/w address: fffff048h (b) v850es/jj3-e 0 pmccs 0 0 0 pmccs3 pmccs2 0 pmccs0 i/o port cs3 output pmccs3 0 1 specification of pcs3 pin operation mode i/o port cs2 output pmccs2 0 1 specification of pcs2 pin operation mode i/o port cs0 output pmccs0 0 1 specification of pcs0 pin operation mode after reset: 00h r/w address: fffff048h v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 166 of 1817 sep 19, 2011 4.3.10 port ct port ct is a 4-bit port for which i/o setti ngs can be controlled in 1-bit units. port ct includes the following alternate-function pins. table 4-15. port ct alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark pct0 111 121 wr0 output pct1 112 122 wr1 output pct4 113 123 rd output pct6 114 124 astb output ? (1) port ct register (pct) 0 outputs 0. outputs 1. pcmn 0 1 output data control (in output mode) (n = 0, 1, 4, 6) pct pct6 0 pct4 0 0 pct1 pct0 after reset: 00h (output latch) r/w address: fffff00ah (2) port ct mode register (pmct) 1 output mode input mode pmctn 0 1 i/o mode control (n = 0, 1, 4, 6) pmct pmct6 1 pmct4 1 1 pmct1 pmct0 after reset: ffh r/w address: fffff02ah v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 167 of 1817 sep 19, 2011 (3) port ct mode control register (pmcct) 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specification of pct6 pin operation mode i/o port rd output pmcct4 0 1 specification of pct4 pin operation mode i/o port wr1 output pmcct1 0 1 specification of pct1 pin operation mode i/o port wr0 output pmcct0 0 1 specification of pct0 pin operation mode after reset: 00h r/w address: fffff04ah v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 168 of 1817 sep 19, 2011 4.3.11 port dh port dh is an 6-bit (v850es/jh3-e)/8-bit (v850es/jj3-e) port for which i/o settings can be controlled in 1-bit units. port dh includes the following alternate-function pins. table 4-16. port dh alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark pdh0 105 111 a16/sie1 i/o pdh1 106 112 a17/soe1 output pdh2 107 113 a18/scke1 i/o pdh3 108 114 a19/sif4/txdb0 i/o pdh4 109 115 a20/sof4/rxdb0 i/o pdh5 110 116 a21/sckf4 i/o pdh6 ? 117 a22 output pdh7 ? 118 a23 output ? v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 169 of 1817 sep 19, 2011 (1) port dh register (pdh) (a) v850es/jh3-e outputs 0. outputs 1. pdhn 0 1 output data control (in output mode) (n = 0 to 5) pdh after reset: 00h (output latch) r/w address: fffff006h 0 0 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 (b) v850es/jj3-e outputs 0. outputs 1. pdhn 0 1 output data control (in output mode) (n = 0 to 7) pdh after reset: 00h (output latch) r/w address: fffff006h pdh7 pdh6 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 170 of 1817 sep 19, 2011 (2) port dh mode register (pmdh) (a) v850es/jh3-e 1 output mode input mode pmdhn 0 1 i/o mode control (n = 0 to 5) 1 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh (b) v850es/jj3-e pmdh7 output mode input mode pmdhn 0 1 i/o mode control (n = 0 to 7) pmdh6 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 171 of 1817 sep 19, 2011 (3) port dh mode control register (pmcdh) (1/2) (a) v850es/jh3-e 0 0 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h i/o port a21 output/sckf4 i/o pmcdh5 0 1 specification of pdh5 pin operation mode i/o port a20 output/sof4 output/rxdb0 input pmcdh4 0 1 specification of pdh4 pin operation mode i/o port a19 output/sif4 input/txdb0 output pmcdh3 0 1 specification of pdh3 pin operation mode i/o port a18 output/scke1 i/o pmcdh2 0 1 specification of pdh2 pin operation mode i/o port a17 output/soe1 output pmcdh1 0 1 specification of pdh1 pin operation mode i/o port a16 output/sie1 input pmcdh0 0 1 specification of pdh0 pin operation mode pmcdh v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 172 of 1817 sep 19, 2011 (2/2) (b) v850es/jj3-e i/o port a23 output pmcdh7 0 1 specification of pdh7 pin operation mode pmcdh7 pmcdh6 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h i/o port a22 output pmcdh6 0 1 specification of pdh6 pin operation mode i/o port a21 output/sckf4 i/o pmcdh5 0 1 specification of pdh5 pin operation mode i/o port a20 output/sof4 output/rxdb0 input pmcdh4 0 1 specification of pdh4 pin operation mode i/o port a19 output/sif4 input/txdb0 output pmcdh3 0 1 specification of pdh3 pin operation mode i/o port a18 output/scke1 i/o pmcdh2 0 1 specification of pdh2 pin operation mode i/o port a17 output/soe1 output pmcdh1 0 1 specification of pdh1 pin operation mode i/o port a16 output/sie1 input pmcdh0 0 1 specification of pdh0 pin operation mode pmcdh v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 173 of 1817 sep 19, 2011 (4) port dh function control register (pfcdh) pfcdh after reset: 00h r/w address: fffff056h 0 0 pfcdh5 pfcdh4 pfcdh3 pfcdh2 pfcdh1 pfcdh0 76543210 remark for details of alternate-f unction specification, see 4.3.11 (6) port dh alternate function specifications . (5) port dh function control ex pansion register (pfcedh) pfcedh after reset: 00h r/w address: fffff726h 0 0 0 pfcedh4 pfcedh3 0 0 0 76543210 remark for details of alternate f unction specification, see 4.3.11 (6) port dh alternate function specifications . (6) port dh alternate function specifications pfcdh5 specification of pdh5 pin alternate function 0 a21 output 1 sckf4 i/o caution the sckf4 function is assi gned to the pdh5 pin as well as the p35 pin. when using the pdh5 pin for the sckf4 function, do not set the p35 pin to be used for this function. pfcedh4 pfcdh4 specification of pdh4 pin alternate function 0 0 a20 output 0 1 sof4 output 1 0 rxdb0 input 1 1 setting prohibited caution the sof4/rxdb0 function is assigned to the pdh4 pin as well as the p34 pin. when using the pdh4 pin for the sof4/rxdb0 function, do not set the p34 pin to be used for this function. pfcedh3 pfcdh3 specification of pdh3 pin alternate function 0 0 a19 output 0 1 sif4 input 1 0 txdb0 output 1 1 setting prohibited caution the sif4/txdb0 function is assigned to the p dh3 pin as well as the p33 pin. when using the pdh3 pin for the sif4/txdb0 function, do not set the p33 pin to be used for this function. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 174 of 1817 sep 19, 2011 pfcdh2 specification of pdh2 pin alternate function 0 a18 output 1 scke1 i/o caution the scke1 function is assi gned to the pdh2 pin as well as the p911 pin. when using the pdh2 pin for the scke1 function, do not set the p911 pin to be used for this function. pfcdh1 specification of pdh1 pin alternate function 0 a17 output 1 soe1 output caution the soe1 function is assigned to the pdh1 pin as well as the p910 pin. when using the pdh1 pin for the soe1 function, do not set the p910 pin to be used for this function. pfcdh0 specification of pdh0 pin alternate function 0 a16 output 1 sie1 input caution the sie1 function is assigned to the pdh0 pi n as well as the p99 pin. when using the pdh0 pin for the sie1 function, do not set the p99 pin to be used for this function. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 175 of 1817 sep 19, 2011 4.3.12 port dl port dl is a 16-bit port for which i/o se ttings can be controll ed in 1-bit units. port dl includes the following alternate-function pins. table 4-17. port dl alternate-function pins pin no. pin name v850es/ jh3-e v850es/ jj3-e alternate-function pin name i/o remark pdl0 87 93 ad0 i/o pdl1 88 94 ad1 i/o pdl2 89 95 ad2 i/o pdl3 90 96 ad3 i/o pdl4 91 97 ad4 i/o pdl5 92 98 ad5/flmd1 note i/o pdl6 93 99 ad6 i/o pdl7 94 100 ad7 i/o pdl8 95 101 ad8 i/o pdl9 96 102 ad9 i/o pdl10 97 103 ad10 i/o pdl11 98 104 ad11 i/o pdl12 99 105 ad12 i/o pdl13 100 106 ad13 i/o pdl14 103 109 ad14 i/o pdl15 104 110 ad15 i/o ? note since this pin is set in the flash memory progra mming mode, it does not need to be manipulated with the port control register. for details, see chapter 33 flash memory . v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 176 of 1817 sep 19, 2011 (1) port dl register (pdl) pdl15 outputs 0. outputs 1. pdln 0 1 output data control (in output mode) (n = 0 to 15) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 pdl (pdlh) (pdll) after reset: 0000h (output latch) r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h remarks 1. the pdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pdl register as the pdlh register and the lower 8 bits as the pdll register, they ca n be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pdl regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pdlh register. (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 i/o mode control (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 pmdl (pmdlh) (pmdll) after reset: ffffh r/w address: pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h remarks 1. the pmdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmdl register as the pmdlh register and the lower 8 bits as the pmdll register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmdl regist er in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 177 of 1817 sep 19, 2011 (3) port dl mode control register (pmcdl) i/o port adn i/o (address/data bus i/o) pmcdln 0 1 specification of pdln pin operation mode (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 pmcdl15 pmcdl14pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 pmcdl (pmcdlh) (pmcdll) after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h remarks 1. the pmcdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmcdl register as the pmcdlh register and the lower 8 bits as the pmcd ll register, they can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmcdl regi ster in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register. 4.4 port register settings when alternate function is used table 4-18 shows the port register settings when each port is used for an alternate function. when using a port pin as an alternate-function pin, refer to the description of each pin. r01uh0290ej0300 rev.3.00 page 178 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (1/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) p02 nmi input p02 = setting not required pm02 = setting not required pmc02 = 1 ? ? intp00 input p03 = setting not required pm03 = setting not required pmc03 = 1 pfce03 = 0 pfc03 = 0 adtrg input p03 = setting not required pm03 = setting not required pmc03 = 1 pfce03 = 0 pfc03 = 1 p03 exclk input p03 = setting not required pm03 = setting not required pmc03 = 1 pfce03 = 1 pfc03 = 0 tiab02 input p20 = setting not required pm20 = setting not required pmc20 = 1 pfce20 = 0 pfc20 = 0 toab03 output p20 = setting not required pm20 = setting not required pmc20 = 1 pfce20 = 0 pfc20 = 1 p20 intp01 input p20 = setting not required pm20 = setting not required pmc20 = 1 pfce20 = 1 pfc20 = 0 tiab00 input p21 = setting not required pm21 = setting not required pmc21= 1 pfce21 = 0 pfc21 = 0 toab00 output p21 = setting not required pm21 = setting not required pmc21= 1 pfce21 = 0 pfc21 = 1 rtcdiv output p21 = setting not required pm21 = setting not required pmc21= 1 pfce21 = 1 pfc21 = 0 p21 rtccl output p21 = setting not required pm21 = setting not required pmc21= 1 pfce21 = 1 pfc21 = 1 tiab01 input p22 = setting not required pm22 = setting not required pmc22= 1 pfce22 = 0 pfc22 = 0 toab00 output p22 = setting not required pm22 = setting not required pmc22= 1 pfce22 = 0 pfc22 = 1 rtc1hz output p22 = setting not required pm22 = setting not required pmc22= 1 pfce22 = 1 pfc22 = 0 p22 intp02 input p22 = setting not required pm22 = setting not required pmc22= 1 pfce22 = 1 pfc22 = 1 sif1 input p23 = setting not required pm23 = setting not required pmc23= 1 pfce23 = 0 pfc23 = 0 txdc1 output p23 = setting not required pm23 = setting not required pmc23= 1 pfce23 = 0 pfc23 = 1 sda00 i/o p23 = setting not required pm23 = setting not required pmc23= 1 pfce23 = 1 pfc23 = 0 pf23 (pf2) = 1 p23 intp03 input p23 = setting not required pm23 = setting not required pmc23= 1 pfce23 = 1 pfc23 = 1 sof1 output p24 = setting not required pm24 = setting not required pmc24= 1 pfce24 = 0 pfc24 = 0 rxdc1 input p24 = setting not required pm24 = setting not required pmc24= 1 pfce24 = 0 pfc24 = 1 scl00 i/o p24 = setting not required pm24 = setting not required pmc24= 1 pfce24 = 1 pfc24 = 0 pf24 (pf2)= 1 p24 intp04 input p24 = setting not required pm24 = setting not required pmc24= 1 pfce24 = 1 pfc24 = 1 r01uh0290ej0300 rev.3.00 page 179 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (2/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) sckf1 i/o p25 = setting not required pm25 = setting not required pmc25= 1 pfce25 = 0 pfc25 = 0 tiab30 input p25 = setting not required pm25 = setting not required pmc25= 1 pfce25 = 0 pfc25 = 1 toab30 output p25 = setting not required pm25 = setting not required pmc25= 1 pfce25 = 1 pfc25 = 0 p25 udmarq0 input p25 = setting not required pm25 = setting not required pmc25= 1 pfce25 = 1 pfc25 = 1 tiab31 input p26 = setting not required pm26 = setting not required pmc26= 1 pfce26 = 0 pfc26 = 0 toab31 output p26 = setting not required pm26 = setting not required pmc26= 1 pfce26 = 0 pfc26 = 1 intp05 input p26 = setting not required pm26 = setting not required pmc26= 1 pfce26 = 1 pfc26 = 0 p26 udmaak0 output p26 = setting not required pm26 = setting not required pmc26= 1 pfce26 = 1 pfc26 = 1 tiab03 input p27 = setting not required pm27 = setting not required pmc27= 1 pfce27 = 0 pfc27 = 0 toab03 output p27 = setting not required pm27 = setting not required pmc27= 1 pfce27 = 0 pfc27 = 1 p27 note intp21 input p27 = setting not required pm27 = setting not required pmc27= 1 pfce27 = 1 pfc27 = 0 txdc0 output p30 = setting not required pm30 = setting not required pmc30= 1 pfce30 = 0 pfc30 = 0 sif2 input p30 = setting not required pm30 = setting not required pmc30= 1 pfce30 = 0 pfc30 = 1 intp05 input p30 = setting not required pm30 = setting not required pmc30= 1 pfce30 = 1 pfc30 = 0 p30 udmaak0 output p30 = setting not required pm30 = setting not required pmc30= 1 pfce30 = 1 pfc30 = 1 rxdc0 input p31 = setting not required pm31 = setting not required pmc31= 1 pfce31 = 0 pfc31 = 0 sof2 output p31 = setting not required pm31 = setting not required pmc31= 1 pfce31 = 0 pfc31 = 1 tiaa01 input p31 = setting not required pm31 = setting not required pmc31= 1 pfce31 = 1 pfc31 = 0 p31 toaa01 output p31 = setting not required pm31 = setting not required pmc31= 1 pfce31 = 1 pfc31 = 1 asckc0 i/o p32 = setting not required pm32 = setting not required pmc32= 1 pfce32 = 0 pfc32 = 0 sckf2 i/o p32 = setting not required pm32 = setting not required pmc32= 1 pfce32 = 0 pfc32 = 1 tiaa10 input p32 = setting not required pm32 = setting not required pmc32= 1 pfce32 = 1 pfc32 = 0 p32 toaa10 output p32 = setting not required pm32 = setting not required pmc32= 1 pfce32 = 1 pfc32 = 1 r01uh0290ej0300 rev.3.00 page 180 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (3/13) pin name alternate function pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) sif4 note 1 input p33 = setting not required pm33 = setting not required pmc33= 1 pfce33 = 0 pfc33 = 0 txdb0 output p33 = setting not required pm33 = setting not required pmc33= 1 pfce33 = 0 pfc33 = 1 tiaa11 input p33 = setting not required pm33 = setting not required pmc33= 1 pfce33 = 1 pfc33 = 0 p33 toaa11 output p33 = setting not required pm33 = setting not required pmc33= 1 pfce33 = 1 pfc33 = 1 sof4 note 2 output p34 = setting not required pm34 = setting not required pmc34 = 1 pfce34 = 0 pfc34 = 0 rxdb0 input p34 = setting not required pm34 = setting not required pmc34 = 1 pfce34 = 0 pfc34 = 1 tiaa20 input p34 = setting not required pm34 = setting not required pmc34 = 1 pfce34 = 1 pfc34 = 0 p34 toaa20 output p34 = setting not required pm34 = setting not required pmc34 = 1 pfce34 = 1 pfc34 = 1 sckf4 note 3 i/o p35 = setting not required pm35 = setting not required pmc35 = 1 pfce35 = 0 pfc35 = 0 tiaa21 input p35 = setting not required pm35 = setting not required pmc35 = 1 pfce35 = 0 pfc35 = 1 toaa21 output p35 = setting not required pm35 = setting not required pmc35 = 1 pfce35 = 1 pfc35 = 0 toaa1off note 4 input p35 = setting not required pm35 = setting not required pmc35 = 1 pfce35 = 1 pfc35 = 1 p35 intp06 note 4 input p35 = setting not required pm35 = setting not required pmc35 = 1 pfce35 = 1 pfc35 = 1 txdc2 output p36 = setting not required pm36 = setting not required pmc36 = 1 pfce36 = 0 pfc36 = 0 sda02 i/o p36 = setting not required pm36 = setting not required pmc36 = 1 pfce36 = 0 pfc36 = 1 pf36 (pf3) = 1 p36 ctxd0 note 5 input p36 = setting not required pm36 = setting not required pmc36 = 1 pfce36 = 1 pfc36 = 0 rxdc2 input p37 = setting not required pm37 = setting not required pmc37 = 1 pfce37 = 0 pfc37 = 0 scl02 i/o p37 = setting not required pm37 = setting not required pmc37 = 1 pfce37 = 0 pfc37 = 1 pf37 (pf3) = 1 p37 crxd0 note 5 input p37 = setting not required pm37 = setting not required pmc37 = 1 pfce37 = 1 pfc37 = 0 notes 1. the sif4 function is assigned to the pdh3 pin as well as the p33 pin. when using t he p33 pin for the sif4 function, do not set the pdh3 pin to be used for this function. 2. the sof4 function is assigned to the pdh4 pin as well as the p 34 pin. when using the p34 pin for the sof4 function, do not set the pdh4 pin to be used for this function. 3. the sckf4 function is assigned to the pdh5 pin as well as the p35 pin. when using t he p35 pin for the sckf 4 function, do not s et the pdh5 pin to be used for this function. 4. toaa1off and intp09 are alternate functions. when using the pi n for the toaa1off function, disa ble edge detection of intp09, which is the alternate function. also, when using the pin for the intp09 functi on, stop the high-impeda nce output controller. 5. pd70f3783 and 70f3786 only r01uh0290ej0300 rev.3.00 page 181 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (4/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) sif0 input p40 = setting not required pm40 = setting not required pmc40 = 1 pfce40 = 0 pfc40 = 0 txdc3 output p40 = setting not required pm40 = setting not required pmc40 = 1 pfce40 = 0 pfc40 = 1 sda01 i/o p40 = setting not required pm40 = setting not required pmc40 = 1 pfce40 = 1 pfc40 = 0 pf40 (pf4) = 1 p40 rtp00 output p40 = setting not required pm40 = setting not required pmc40 = 1 pfce40 = 1 pfc40 = 1 sof0 output p41 = setting not required pm41 = setting not required pmc41 = 1 pfce41 = 0 pfc41 = 0 rxdc3 input p41 = setting not required pm41 = setting not required pmc41 = 1 pfce41 = 0 pfc41 = 1 scl01 i/o p41 = setting not required pm41 = setting not required pmc41 = 1 pfce41 = 1 pfc41 = 0 pf41 (pf4) = 1 p41 rtp01 output p41 = setting not required pm41 = setting not required pmc41 = 1 pfce41 = 1 pfc41 = 1 sckf0 i/o p42 = setting not required pm42 = setting not required pmc42 = 1 pfce42 = 0 pfc42 = 0 tiaa40 input p42 = setting not required pm42 = setting not required pmc42 = 1 pfce42 = 0 pfc42 = 1 toaa40 output p42 = setting not required pm42 = setting not required pmc42 = 1 pfce42 = 1 pfc42 = 0 p42 rtp02 output p42 = setting not required pm42 = setting not required pmc42 = 1 pfce42 = 1 pfc42 = 1 sie0 input p43 = setting not required pm43 = setting not required pmc43 = 1 pfce43 = 0 pfc43 = 0 txdc4 output p43 = setting not required pm43 = setting not required pmc43 = 1 pfce43 = 0 pfc43 = 1 rtp03 output p43 = setting not required pm43 = setting not required pmc43 = 1 pfce43 = 1 pfc43 = 0 p43 hldak note output p43 = setting not required pm43 = setting not required pmc43 = 1 pfce43 = 1 pfc43 = 1 soe0 output p44 = setting not required pm44 = setting not required pmc44 = 1 pfce44 = 0 pfc44 = 0 rxdc4 input p44 = setting not required pm44 = setting not required pmc44 = 1 pfce44 = 0 pfc44 = 1 rtp04 output p44 = setting not required pm44 = setting not required pmc44 = 1 pfce44 = 1 pfc44 = 0 p44 hldrq note output p44 = setting not required pm44 = setting not required pmc44 = 1 pfce44 = 1 pfc44 = 1 scke0 output p45 = setting not required pm45 = setting not required pmc45 = 1 pfce45 = 0 pfc45 = 0 tiaa41 input p45 = setting not required pm45 = setting not required pmc45 = 1 pfce45 = 0 pfc45 = 1 toaa41 output p45 = setting not required pm45 = setting not required pmc45 = 1 pfce45 = 1 pfc45 = 0 p45 rtp05 output p45 = setting not required pm45 = setting not required pmc45 = 1 pfce45 = 1 pfc45 = 1 note v850es/jh3-e only r01uh0290ej0300 rev.3.00 page 182 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (5/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) sif5 input p46 = setting not required pm46 = setting not required pmc46 = 1 pfce46 = 0 pfc46 = 0 txdc6 output p46 = setting not required pm46 = setting not required pmc46 = 1 pfce46 = 0 pfc46 = 1 p46 note rtp06 output p46 = setting not required pm46 = setting not required pmc46 = 1 pfce46 = 1 pfc46 = 0 sof5 output p47 = setting not required pm47 = setting not required pmc47 = 1 pfce47 = 0 pfc47 = 0 rxdc6 input p47 = setting not required pm47 = setting not required pmc47 = 1 pfce47 = 0 pfc47 = 1 p47 note rtp07 output p47 = setting not required pm47 = setting not required pmc47 = 1 pfce47 = 1 pfc47 = 0 sckf5 i/o p48 = setting not required pm48 = setting not required pmc48 = 1 ? pfc48 = 0 p48 note intp22 input p48 = setting not required pm48 = setting not required pmc48 = 1 ? pfc48 = 1 intp07 input p50 = setting not required pm50 = setting not required pmc50 = 1 ? ? p50 ddi input p50 = setting not required pm50 = setting not required pmc50 = setting not required ? ? ocdm0 (ocdm) = 1 intp08 input p51 = setting not required pm51 = setting not required pmc51 = 1 ? ? p51 ddo output p51 = setting not required pm51 = setting not required pmc51 = setting not required ? ? ocdm0 (ocdm) = 1 intp09 input p52 = setting not required pm52 = setting not required pmc52 = 1 ? ? p52 dck input p52 = setting not required pm52 = setting not required pmc52 = setting not required ? ? ocdm0 (ocdm) = 1 intp10 input p53 = setting not required pm53 = setting not required pmc53 = 1 ? ? p53 dms input p53 = setting not required pm53 = setting not required pmc53 = setting not required ? ? ocdm0 (ocdm) = 1 intp11 input p54 = setting not required pm54 = setting not required pmc54 = 1 ? ? p54 drst input p54 = setting not required pm54 = setting not required pmc54 = setting not required ? ? ocdm0 (ocdm) = 1 sda04 i/o p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 0 pf55 (pf5) = 1 intp23 input p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 0 p55 note udmarq1 input p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 1 note v850es/jj3-e only r01uh0290ej0300 rev.3.00 page 183 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (6/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) scl04 i/o p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 0 pf55 (pf5) = 1 intp24 input p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 1 p56 note udmaak1 output p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 1 pfc55 = 1 sif6 input p57 = setting not required pm57 = setting not required pmc57 = 1 ? pfc57 = 0 p57 note txdc7 output p57 = setting not required pm57 = setting not required pmc57 = 1 ? pfc57 = 1 sof6 output p58 = setting not required pm58 = setting not required pmc58 = 1 ? pfc58 = 0 p58 note rxdc7 input p58 = setting not required pm58 = setting not required pmc58 = 1 ? pfc58 = 1 sckf6 i/o p59 = setting not required pm59 = setting not required pmc59 = 1 ? pfc59 = 0 p59 note intp25 input p59 = setting not required pm59 = setting not required pmc59 = 1 ? pfc59 = 1 p70 ani0 input p70 = setting not required pm70 = 1 ? ? ? p71 ani1 input p71 = setting not required pm71 = 1 ? ? ? p72 ani2 input p72 = setting not required pm72 = 1 ? ? ? p73 ani3 input p73 = setting not required pm73 = 1 ? ? ? p74 ani4 input p74 = setting not required pm74 = 1 ? ? ? p75 ani5 input p75 = setting not required pm75 = 1 ? ? ? p76 ani6 input p76 = setting not required pm76 = 1 ? ? ? p77 ani7 input p77 = setting not required pm77 = 1 ? ? ? p78 ani8 input p78 = setting not required pm78 = 1 ? ? ? p79 ani9 input p79 = setting not required pm79 = 1 ? ? ? p710 note ani10 input p710 = setting not require d pm710 = 1 ? ? ? p711 note ani11 input p711 = setting not require d pm711 = 1 ? ? ? note v850es/jj3-e only r01uh0290ej0300 rev.3.00 page 184 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (7/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) toab1t1 output p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 0 pfc90 = 0 toab11 output p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 0 pfc90 = 0 tiab11 note 1 input p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 0 pfc90 = 1 krm0 (krm) = 0 kr0 note 1 input p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 0 pfc90 = 1 tab1tis3, tab1tis2 (tab1i0c1) = 0 intp12 input p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 1 pfc90 = 0 p90 a0 note 2 output p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 1 pfc90 = 1 toab1b1 output p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 0 pfc91 = 0 tiab10 note 3 input p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 0 pfc91 = 1 krm1 (krm) = 0 kr1 note 3 input p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 0 pfc91 = 1 tab1tis1, tab1tis0 (tab1i0c1) = 0 toab10 output p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 1 pfc91 = 0 pf91 (pf9) = 1 p91 a1 note 2 output p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 1 pfc91 = 1 toab1t2 output p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 0 pfc92 = 0 toab12 output p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 0 pfc92 = 0 tiab12 note 4 input p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 0 pfc92 = 1 krm2 (krm) = 0 kr2 note 4 input p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 0 pfc92 = 1 tab1tis5, tab1tis4 (tab1i0c1) = 0 intp13 input p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 1 pfc92 = 0 p92 a2 note 1 output p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 1 pfc92 = 1 notes 1. kr0 and tiab11 are alternate functions. w hen using the pin for the tiab11 function, di sable key return detection of kr0, whic h is the alternate function (set the krm.krm0 bit to 0). also, when using the pin for the kr0 func tion, disable edge detection of ti ab11, which is the alternate fu nction (set the tab1ioc1.tab1is3 and tab1is2 bits to 00). 2. when using as the a0 to a15 pins, be sure to set all 16 bits of the pmc9 register to ffffh at once. 3. kr1 and tiab10 are alternate functions. w hen using the pin for the tiab10 function, di sable key return detection of kr1, whic h is the alternate function (set the krm.krm1 bit to 0). also, when using the pin for the kr1 func tion, disable edge detection of ti ab10, which is the alternate fu nction (set the tab1ioc1.tab1is1 and tab1is0 bits to 00). 4. kr2 and tiab12 are alternate functions. w hen using the pin for the tiab12 function, di sable key return detection of kr2, whic h is the alternate function (set the krm.krm2 bit to 0). also, when using the pin for the kr2 func tion, disable edge detection of ti ab12, which is the alternate fu nction (set the tab1ioc1.tab1is5 and tab1is4 bits to 00). r01uh0290ej0300 rev.3.00 page 185 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (8/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) toab1b2 output p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 0 pfc93 = 0 trgab1 note 1 input p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 0 pfc93 = 1 krm3 (krm) = 0 kr3 note 1 input p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 0 pfc93 = 1 tab1ets1, tab1ets0 (tab1i0c1) = 0 intp14 input p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 1 pfc93 = 0 p93 a3 note 2 output p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 1 pfc93 = 1 toab1t3 output p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 0 pfc94 = 0 toab13 output p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 0 pfc94 = 0 tiab13 note 3 input p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 0 pfc94 = 1 krm2 (krm) = 0 kr 4note 3 input p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 0 pfc94 = 1 tab1tis7, tab1tis6 (tab1i0c1) = 0 intp15 input p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 1 pfc94 = 0 p94 a4 note 2 output p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 1 pfc94 = 1 toab1b3 output p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 0 pfc95 = 0 evtab1 note 4 input p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 0 pfc95 = 1 krm5 (krm) = 0 kr5 note 4 input p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 0 pfc95 = 1 tab1ees1, tab1ees0 (tab1i0c1) = 0 intp16 input p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 1 pfc95 = 0 p95 a5 note 2 output p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 1 pfc95 = 1 notes 1. kr3 and trgab1 are alternate functions. when using the pin for the trgab1 function, disable key return detection of kr3, whic h is the alternate function (set the krm.krm3 bit to 0). also, when using the pin for the kr3 functi on, disable edge detection of trgab1, which is the alternate fu nction (set the tab1ioc2.tab1ets1 and tab1ets0 bits to 00). 2. when using as the a0 to a15 pins, be sure to set all 16 bits of the pmc9 register to ffffh at once. 3. kr4 and tiab13 are alternate functions. w hen using the pin for the tiab13 function, di sable key return detection of kr4, whic h is the alternate function (set the krm.krm4 bit to 0). also, when using the pin for the kr4 func tion, disable edge detection of ti ab13, which is the alternate fu nction (set the tab1ioc1.tab1is7 and tab1is6 bits to 00). 4. kr5 and evtab1 are alternate functions. when using the pin for t he evtab1 function, disable key return detection of kr5, whic h is the alternate function (set the krm.krm5 bit to 0). also, when using the pin for the kr5 functi on, disable edge detection of ev tab1, which is the alternate fu nction (set the tab1ioc2.tab1ees1 and tab1ees0 bits to 00). r01uh0290ej0300 rev.3.00 page 186 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (9/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) tecr0 input p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 0 pfc96 = 0 tit00 note 1 input p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 1 pfc96 = 0 krm6 (krm) = 0 kr6 note 1 input p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 1 pfc96 = 0 tt0is1, tt0is0 (tti0ioc1) = 0 tot00 output p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 1 pfc96 = 0 p96 a6 note 2 output p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 1 pfc96 = 1 note 2 tenc00 input p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 0 pfc97 = 0 tit01 note 3 input p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 0 pfc97 = 1 krm7 (krm) = 0 kr7 note 3 input p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 0 pfc97 = 1 tt0is3, tt0is2 (tti0ioc1) = 0 tot01 output p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 1 pfc97 = 0 p97 a7 note 2 output p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 1 pfc97 = 1 tenc01 input p98 = setting not required pm98 = setting not required pmc98 = 1 pfce98 = 0 pfc98 = 0 intp17 input p98 = setting not required pm98 = setting not required pmc98 = 1 pfce98 = 0 pfc98 = 1 p98 a8 note 2 output p98 = setting not required pm98 = setting not required pmc98 = 1 pfce98 = 1 pfc98 = 0 sie1 note 4 input p99 = setting not required pm99 = setting not required pmc99 = 1 pfce99 = 0 pfc99 = 0 txdc5 output p99 = setting not required pm99 = setting not required pmc99 = 1 pfce99 = 0 pfc99 = 1 sda03 i/o p99 = setting not required pm99 = setting not required pmc99 = 1 pfce99 = 1 pfc99 = 0 p99 a9 note 2 output p99 = setting not required pm99 = setting not required pmc99 = 1 pfce99 = 1 pfc99 = 1 notes 1. kr6 and tit00 are alternate functions. w hen using the pin for the tit 00 function, disable key return detection of kr6, which is the alternate function (set the krm.krm6 bit to 0). also, when using the pin for the kr6 functi on, disable edge detection of tit 00, which is the alternate fun ction (set the tti 0ioc1.tt0is1 and tt0is0 bits to 00). 2. when using as the a0 to a15 pins, be sure to set all 16 bits of the pmc9 register to ffffh at once. 3. kr7 and tit01 are alternate functions. w hen using the pin for the tit 01 function, disable key return detection of kr7, which is the alternate function (set the krm.krm7 bit to 0). also, when using the pin for the kr7 functi on, disable edge detection of tit 01, which is the alternate fun ction (set the tti 0ioc1.tt0is3 and tt0is2 bits to 00). 4. the sie1 function is assigned to the pdh0 pin as well as the p99 pin. when using t he p99 pin for the sie1 function, do not sp ecify the pdh0 pin to be used for this function. r01uh0290ej0300 rev.3.00 page 187 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (10/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) soe1 output p910 = setting not required pm910 = setting not required pmc910 = 1 pfce910 = 0 pfc910 = 0 rxdc5 output p910 = setting not required pm910 = setting not required pmc910 = 1 pfce910 = 0 pfc910 = 1 scl03 i/o p910 = setting not required pm910 = setting not required pmc910 = 1 pfce910 = 1 pfc910 = 0 pf910 (pf9) = 1 p910 a10 note 1 output p910 = setting not required pm910 = setting not required pmc910 = 1 pfce910 = 1 pfc910 = 1 scke1 note 2 i/o p911 = setting not required pm911 = setting not required pmc911 = 1 pfce911 = 0 pfc911 = 0 tiaa50 input p911 = setting not required pm911 = setting not required pmc911 = 1 pfce911 = 0 pfc911 = 1 toaa50 output p911 = setting not required pm911 = setting not required pmc911 = 1 pfce911 = 1 pfc911 = 0 p911 a11 note 1 output p911 = setting not required pm911 = setting not required pmc911 = 1 pfce911 = 1 pfc911 = 1 toab1off note 3 input p912 = setting not required pm912 = setting not required pmc912 = 1 ? pfc912 = 0 intr912 (intr9) = 0, intf912 (intf9) = 0 intp18 note 3 input p912 = setting not required pm912 = setting not required pmc912 = 1 ? pfc912 = 0 hza0dcn0, nza0dcp0 (hza0ctl0) = 00 p912 a12 note 1 output p912 = setting not required pm912 = setting not required pmc912 = 1 ? pfc912 = 1 sif3 input p913 = setting not required pm913 = setting not required pmc913 = 1 pfce913 = 0 pfc913 = 0 txdb1 output p913 = setting not required pm913 = setting not required pmc913 = 1 pfce913 = 0 pfc913 = 1 intp19 input p913 = setting not required pm913 = setting not required pmc913 = 1 pfce913 = 1 pfc913 = 0 p913 a13 note 1 output p913 = setting not required pm913 = setting not required pmc913 = 1 pfce913 = 1 pfc913 = 1 sof3 output p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 0 pfc914 = 0 rxdb1 input p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 0 pfc914 = 1 intp20 input p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 1 pfc914 = 0 p914 a14 note 1 output p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 1 pfc914 = 1 notes 1. when using as the a0 to a15 pins, be sure to set all 16 bits of the pmc9 register to ffffh at once. 2. the scke1 function is assigned to the pdh2 pin as well as the p911 pin. when using the p911 pin for the scke1 function, do no t set the pdh2 pin to be used for this function. 3. toab1off and intp18 are alternate functions. when using the pin for the toab1off function, disable interrupt detection of int p18 , which is the alternate function (set the intr9.intr912 and intf9.intf912 bits to 0). also , when using the pin for the intp18 function, disable edge d etection of toab1off, which is the alternate function (set the hza0ct l0. hza0dcn0 and nza0dcp0 bits to 00). r01uh0290ej0300 rev.3.00 page 188 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (11/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) sckf3 i/o p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 0 pfc915 = 0 tiaa50 input p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 0 pfc915 = 1 toaa0 output p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 1 pfc915 = 0 p915 a15 note 1 output p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 1 pfc915 = 1 pcm0 wait input pcm0 = setting not required pmcm0 = setting not required pmccm0 = 1 ? ? pcm1 clkout output pcm1 = setting not required pmcm1 = setting not required pmccm1 = 1 ? ? pcm2 hldak note 2 output pcm2 = setting not required pmcm2 = setting not required pmccm2 = 1 ? ? pcm3 hldrq note 2 input pcm3 = setting not required pmcm3 = setting not required pmccm3 = 1 ? ? pcs0 cs0 output pcs0 = setting not required pmcs0 = setting not required pmccs0 = 1 ? ? pcs2 cs2 output pcs2 = setting not required pmcs2 = setting not required pmccs2 = 1 ? ? pcs3 cs3 note 2 output pcs3 = setting not required pmcs3 = setting not required pmccs3 = 1 ? ? pct0 wr0 output pct0 = setting not required pmct0 = setting not required pmcct0 = 1 ? ? pct1 wr1 output pct1 = setting not required pmct1 = setting not required pmcct1 = 1 ? ? pct4 rd output pct4 = setting not required pmct4 = setting not required pmcct4 = 1 ? ? pct6 astb output pct6 = setting not required pmct6 = setting not required pmcct6 = 1 ? ? a16 output pdh0 = setting not required pmdh0 = setting not required pmcdh0 = 1 ? fecdh0 = 0 pdh0 sie1 note 3 input pdh0 = setting not required pmdh0 = setting not required pmcdh0 = 1 ? fecdh0 = 1 a17 output pdh1 = setting not required pmdh1 = setting not required pmcdh1 = 1 ? fecdh1 = 0 pdh1 soe1 note 4 output pdh1 = setting not required pmdh1 = setting not required pmcdh1 = 1 ? fecdh1 = 1 a18 output pdh2 = setting not required pmdh2 = setting not required pmcdh2 = 1 ? fecdh2 = 0 pdh2 scke1 i/o pdh2 = setting not required pmdh2 = setting not required pmcdh2 = 1 ? fecdh2 = 1 notes 1. when using as the a0 to a15 pins, be sure to set all 16 bits of the pmc9 register to ffffh at once. 2. v850es/jj3-e only 3. the sie1 function is assigned to the pdh0 pin as well as the p99 pin. when using the pdh0 pin for the sie1 function, do not s et the p99 pin to be used for this function. 4. the soe1 function is assigned to the pdh1 pin as well as the p910 pin. when using the pdh1 pi n for the soe1 function, do not set the p910 pin to be used for this function. 5. the scke1 function is assigned to the pdh2 pin as well as the p911 pin. when using the pdh2 pin for the scke1 function, do no t set the p911 pin to be used for this function. r01uh0290ej0300 rev.3.00 page 189 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (12/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) a19 output pdh3 = setting not required pmdh3 = setting not required pmcdh3 = 1 fecedh3 = 0 fecdh3 = 0 sif4 note 1 input pdh3 = setting not required pmdh3 = setting not required pmcdh3 = 1 fecedh3 = 0 fecdh3 = 1 pdh3 txdb0 note 1 output pdh3 = setting not required pmdh3 = setting not required pmcdh3 = 1 fecedh3 = 1 fecdh3 = 0 a20 output pdh4 = setting not required pmdh4 = setting not required pmcdh4 = 1 fecedh4 = 0 fecdh4 = 0 sof4 note 2 output pdh4 = setting not required pmdh4 = setting not required pmcdh4 = 1 fecedh4 = 0 fecdh4 = 1 pdh4 rxdb0 note 2 input pdh4 = setting not required pmdh4 = setting not required pmcdh4 = 1 fecedh4 = 1 fecdh4 = 0 a21 output pdh5 = setting not required pmdh5 = setting not required pmcdh5 = 1 ? fecdh5 = 0 pdh5 sckf4 note 3 i/o pdh5 = setting not required pmdh5 = setting not required pmcdh5 = 1 ? fecdh5 = 1 pdh6 a22 note 4 output pdh6 = setting not required pmdh6 = setting not required pmcdh6 = 1 ? ? pdh7 a23 note 4 output pdh7 = setting not required pmdh7 = setting not required pmcdh7 = 1 ? ? pdl0 ad0 i/o pdl0 = setting not required pmdl0 = setting not required pmcdl0 = 1 ? ? pdl1 ad1 i/o pdl1 = setting not required pmdl1 = setting not required pmcdl1 = 1 ? ? pdl2 ad2 i/o pdl2 = setting not required pmdl2 = setting not required pmcdl2 = 1 ? ? pdl3 ad3 i/o pdl3 = setting not required pmdl3 = setting not required pmcdl3 = 1 ? ? pdl4 ad4 i/o pdl4 = setting not required pmdl4 = setting not required pmcdl4 = 1 ? ? notes 1. the sif4/txdb0 function is assigned to the p dh3 pin as well as the p33 pin. when usi ng the pdh3 pin for t he sif4/txdb0 functio n, do not set the p33 pin to be used for this function. 2. the sof4/rxdb0 function is assigned to the pdh4 pin as well as the p34 pin. when using the pdh4 pin for the sof4/rxdb0 functi on, do not set the p34 pin to be used for this function. 3. the sckf4 function is assigned to the pdh5 pin as well as the p35 pin. when using the pdh5 pin for the sckf4 function, do not set the p35 pin to be used for this function. 4. v850es/jj3-e only r01uh0290ej0300 rev.3.00 page 190 of 1817 sep 19, 2011 v850es/jj3-e, v850es/jh3-e chapter 4 port functions table 4-18. using port pin as alternate-function pin (13/13) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ad5 i/o pdl5 = setting not required pmdl5 = setting not required pmcdl5 = 1 ? ? pdl5 flmd1 note input pdl5 = setting not required pmdl5 = setting not required pmcdl5 = setting not required ? ? pdl6 ad6 i/o pdl6 = setting not required pmdl6 = setting not required pmcdl6 = 1 ? ? pdl7 ad7 i/o pdl7 = setting not required pmdl7 = setting not required pmcdl7 = 1 ? ? pdl8 ad8 i/o pdl8 = setting not required pmdl8 = setting not required pmcdl8 = 1 ? ? pdl9 ad9 i/o pdl9 = setting not required pmdl9 = setting not required pmcdl9 = 1 ? ? pdl10 ad10 i/o pdl10 = setting not required pmdl10 = setting not required pmcdl10 = 1 ? ? pdl11 ad11 i/o pdl11 = setting not required pmdl11 = setting not required pmcdl11 = 1 ? ? pdl12 ad12 i/o pdl12 = setting not required pmdl12 = setting not required pmcdl12 = 1 ? ? pdl13 ad13 i/o pdl13 = setting not required pmdl13 = setting not required pmcdl13 = 1 ? ? pdl14 ad14 i/o pdl14 = setting not required pmdl14 = setting not required pmcdl14 = 1 ? ? pdl15 ad15 i/o pdl15 = setting not required pmdl15 = setting not required pmcdl15 = 1 ? ? note since this pin is set in the flash memory programming mode, it does not need to be manipulated using the port control register . for details, see chapter 33 flash memory . v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 191 of 1817 sep 19, 2011 4.5 cautions 4.5.1 cautions on setting port pins (1) in the v850es/jh3-e and v850es/jj3-e, the general-purpose port functions share pins with several peripheral function i/o pins. switch between the general-purpose port ( port mode) and the peripheral function i/o pin (alternate-function mode) by setting the pmcn register. note the following cautions with regards to this register setting sequence. (a) cautions on switching from por t mode to alternate-function mode switch from the port mode to alternate-function mode in the following order. <1> set the pfn register note 1 : n-ch open-drain setting <2> set the pfcn and pfcen regist ers: alternate-function selection <3> set the corresponding bit of the pmcn regist er to 1: switch to alternate-function mode <4> set the intrn and intfn registers note 2 : external interrupt setting if the pmcn register is set first, note that unexpected operations may occur at t hat moment or depending on the change of the pin states in accordance with t he setting of the pfn, pfcn, and pfcen registers. a concrete example is shown in [example] below. notes 1. n-ch open-drain output pin only 2. only when the external in terrupt function is selected caution regardless of the port mode /alternate-function mode, the pn re gister is read and written as follows. ? pn register read: read the port output latch value (when pmn.pmnm bit = 0), or read the pin states (pmn.pmnm bit = 1). ? pn register write: write to the port output latch [example] scl01 pin setting example the scl01 pin is used alternately as the p41/sof0 pin. select the valid pin function using the pmc4, pfc4, and pf4 registers. pmc41 bit pfc41 bit pf41 bit valid pin function 0 don?t care 1 p41 (in output port mode, n-ch open-drain output) 0 1 sof0 output (n-ch open-drain output) 1 1 1 scl01 i/o (n-ch open-drain output) v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 192 of 1817 sep 19, 2011 the setting procedure that may caus e malfunction on switching from the p41 pin to the scl01 pin is shown below. setting procedure setting contents pin state pin level <1> initial value (pmc41 bit = 0, pfc41 bit = 0, pf41 bit = 0) port mode (input) hi-z <2> pmc41 bit 1 sof0 output low level (high level depending on the csif0 setting) <3> pfc41 bit 1 scl01 i/o high level (cmos output) <4> pf41 bit 1 scl01 i/o hi-z (n-ch open-drain output) in <2>, i 2 c communication may be affected since the altern ate-function sof0 out put is output to the pin. in the cmos output period of <2> or <3>, unnecessary current may be generated. (b) cautions on alternate-function mode (input) the signal input to the alternate-function block is low level when the pmcn.pmcnm bit is 0 due to the and output of the pmcn register set va lue and the pin level. thus, depending on the port setting and alternate- function operation enable timing, unexpected operations ma y occur. therefore, switch between the port mode and alternate-function mode in the following sequence. ? to switch from port mode to alternate-function mode (input) set the pins to the alternate-function mode using the pmcn register and then enab le the alternate-function operation. ? to switch from alternate-function mode (input) to port mode stop the alternate-function operation and then switch the pins to the port mode. concrete examples are shown in [example 1] and [example 2]. [example 1] switching from general-purpose port (p02) to external interrupt pin (nmi) when the p02/nmi pin is pulled up as shown in fi gure 4-4 and the rising edg e is specified by the nmi pin edge detection setting, even though a high level is input continuously to the nmi pin when switching from the p02 pin to the an nmi pin (pmc02 bit = 0 1), this is detected as a rising edge as if a low level changed to a high level, and an nmi interrupt occurs. to avoid this, set the nmi pin?s valid edge after switching from the p02 pin to the nmi pin. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 193 of 1817 sep 19, 2011 figure 4-4. example of switching from p02 to nmi (incorrect) pmc0 nmi interrupt occurrence pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode 7 pmc02 bit = 0: low level pmc02 bit = 1: high level 6 rising edge detector 543 2 p02/nmi 3 v 10 0 1 remark m = 2, 3 [example 2] switching from external pin (nmi) to general-purpose port (p02) when the p02/nmi pin is pulled up as shown in figure 4-5 and the falling edge is specified by the nmi pin edge detection setting, even though a hi gh level is input continuously to the nmi pin when switching from the nmi pin to the p02 pin (pmc02 bit = 1 0), this is detected as a falling edge as if a high level changed to a low level, and an nmi interrupt occurs. to avoid this, set the nmi pin edge detection as ?no edge detected? before switching to the p02 pin. figure 4-5. example of switching from nmi to p02 (incorrect) pmc0 76543 2 p02/nmi 3 v 10 nmi interrupt occurrence 1 0 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode falling edge detector pmc02 bit = 1: high level pmc02 bit = 0: low level remark m = 2, 3 (2) in port mode, the pfn.pfnm bit is valid only in the output mode (pmn.pmnm bit = 0). in the input mode (pmnm bit = 1), the value of the pfnm bit is not reflected in the buffer. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 194 of 1817 sep 19, 2011 4.5.2 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port t hat provides both input and out put functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. v850es/jh3-e, v850es/jj3-e chapter 4 port functions r01uh0290ej0300 rev.3.00 page 195 of 1817 sep 19, 2011 4.5.3 cautions on on-chip debug pins (v850es/jh3-e only) the drst, dck, dms, ddi, and ddo pins are on-chip debug pins. after reset by the reset pin, the p54 /intp11/drst pin is initializ ed to function as an on-chip debug pin (drst). if a high level is input to the drst pin at this time, the on-ch ip debug mode is set, and the dck, dms, ddi, and ddo pins can be used. the following action must be taken if on-chip debugging is not used. ? clear the ocdm0 bit of the ocdm register (special register) (0) at this time, fix the p54/intp11/drst pin to low level from when reset by the reset pin is released until the above action is taken. if a high level is input to the drst pin before the above acti on is taken, it may cause a malfunction (cpu deadlock). handle the p54 pin with the utmost care. caution after reset by the wdt2res signal, clock m onitor (clm), or low-voltage detector (lvi), the p54/intp11/drst pin is not initialized to functi on as an on-chip debug pin (drst). the ocdm register holds the current value. 4.5.4 cautions on p54/intp11/drst pin the p54/intp11/drst pin has an internal pull-down resistor (30 k typ.). after a reset by the reset pin, a pull- down resistor is connected. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0). 4.5.5 cautions on p51 pin when power is turned on when the power is turned on, the following pins may ou tput an undefined level temporarily even during reset. ? p51/intp08/ddo pin 4.5.6 hysteresis characteristics in port mode, the following port pins do not have hysteresis characteristics. p02, p03 p20 to p27 p30 to p37 p40 to p48 p50 to p59 p60 to p65 p90 to p915 v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 196 of 1817 sep 19, 2011 chapter 5 bus control function the v850es/jh3-e and v850es/jj3-e are provided with an extern al bus interface function by which external memories such as rom and ram, and i/o can be connected. 5.1 features output is selectable from multiplexed bus output with a minimum of 3 bus cycles and separate bus output 8-bit/16-bit data bus selectable wait function ? programmable wait function of up to 7 states ? external wait function using wait pin idle state function bus hold function v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 197 of 1817 sep 19, 2011 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (multiplexed bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a23 note 1 pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq p44 note 2 pcm3 note 3 input hldak p43 note 2 pcm2 note 3 output bus hold control cs0, cs2, cs3 note 2 pcs0, pcs2, pcs3 output chip select notes 1. v850es/jj3-e only. a16 to a21 pins are used for the v850es/jh3-e. 2. v850es/jh3-e only 3. v850es/jj3-e only table 5-2. bus control pins (separate bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a23 note 1 pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq p44 note 2 pcm3 note 3 input hldak p43 note 2 pcm2 note 3 output bus hold control cs0, cs2, cs3 note 3 pcs0, pcs2, pcs3 output chip select notes 1. v850es/jj3-e only. the a16 to a21 pins are used in the v850es/jh3-e. 2. v850es/jh3-e only 3. v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 198 of 1817 sep 19, 2011 5.2.1 pin status when internal rom, intern al ram, or on-chip peripheral i/o is accessed when the internal rom, internal ram, or on-chip peripheral i/o are accessed, the status of each pin is as follows. table 5-3. pin statuses when internal rom, in ternal ram, or on-chip peripheral i/o is accessed separate bus mode multiplexed bus mode bus control pin internal rom/ram peripheral i/o internal rom/ram peripheral i/o address/data bus (ad15 to ad0) undefined undefined undefined undefined address bus (a23 to a16) undefined undefined (address output during access) undefined undefined (address output during access) address bus (a15 to a0) undefined undefined (address output during access) undefined undefined (address output during access) control signal inactive inac tive inactive inactive caution when a write access is perfo rmed to the internal rom area, addr ess, data, and control signals are activated in the same way as access to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850es/jh3-e and v850es/jj3-e in each operation mode, see 2.2 pin states . v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 199 of 1817 sep 19, 2011 5.3 memory block function the 16 mb external memory space is divided into memory blocks of 2 mb, 4 mb, and 8 mb from the lowest of the memory space. the programmable wait function and bus cycle operation mode for eac h of these blocks can be independently controlled in one-block units. figure 5-1. data memory map: physical address cs3 cs2 cs0 (cs1 note 2 ) (80 kb) use prohibited use prohibited note 3 programmable peripheral i/o area note 4 or use prohibited note 5 external memory area note 1 (8 mb) external memory area (4 mb) usb function/ ethernet/ used area (2 mb) internal rom area note 6 (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) 03ffffffh 03fec000h 03febfffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00200000h 001fffffh 00000000h 03ffffffh 001fffffh 00100000h 000fffffh 00000000h 03fff000h 03ffefffh 03ff0000h 03feffffh 03fef000h 03feefffh 03fec000h notes 1. use of this area is allowed only when using t he v850es/jj3-e. when using the v850es/jh3-e, this area cannot be used. 2. cs1 is not provided as an external signal of the v8 50es/jx3-e; it is used internally as a chip select signal for the usb and ethernet. 3. use of addresses 03fef000h to 03feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 4. only the programmable peripheral i/o area is s een as images of 256 mb each in the 4 gb address space. 5. in the can controller vers ion, addresses 03fec000h to 03feefffh are assigned as a programmable peripheral i/o area in addresses 03fec000h to 03fecbffh. use of these addresses in a version without a can controller is prohibited. 6. this area is used as an external memory area when data write access to this area is executed. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 200 of 1817 sep 19, 2011 5.4 bus access 5.4.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. external memory (16 bits) area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) multiplexed separate instruction fetch (normal access) 1 1 note 3 + n instruction fetch (branch) 3 2 note 3 + n operand data access 5 1 3 + n note increases by 1 if a conflict with a data access occurs. remark unit: clocks/access 5.4.2 bus size setting function each external memory area selected by memory block csn can be set by using the bsc register. however, the bus size can be set to 8 bits and 16 bits only. the external memory area of the v850es/jh3-e is selected by using cs0 and cs2, and the external memory area of the v850es/jj3-e is selected by using cs0, cs2 and cs3. (1) bus size configuration register (bsc) the bsc register can be read or written in 16-bit units. reset sets this register to 5555h. caution write to the bsc register after reset, and then do not change the set values. also, do not access an external memory area until the initial se ttings of the bsc register are complete. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 note 0 0 1 bs20 0 0 1 1 0 0 1 bs00 8 9 10 11 12 13 data bus width of m emory block csn space (n = 0, 2, 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 note v850es/jj3-e only. be sure to set this bit to 1 in the v850es/jh3-e. caution be sure to set bits 14, 12, 10, 8, and 2 to ?1?, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 201 of 1817 sep 19, 2011 5.4.3 access by bus size the v850es/jh3-e and v850es/jj3-e acce ss the on-chip peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/jh3-e and v850es/jj3-e support only the little-endian format. figure 5-2. little-endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/jh3-e and v850es/jj3-e have an address misalign function. with this function, data can be placed at all addresses, re gardless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (b) word-length data access (i) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 202 of 1817 sep 19, 2011 (2) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 203 of 1817 sep 19, 2011 (3) halfword access (16 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 204 of 1817 sep 19, 2011 (4) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 205 of 1817 sep 19, 2011 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 206 of 1817 sep 19, 2011 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 207 of 1817 sep 19, 2011 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 208 of 1817 sep 19, 2011 5.5 wait function 5.5.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each cs space. the number of wait states can be programmed by using the dwc0 register. immediat ely after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. reset sets this register to 7777h. cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-ch ip peripheral i/o area is also not subject to programmable wait, and only wa it control from each periphe ral function is performed. 2. write to the dwc0 register after reset, an d then do not change the set values. also, do not access an external memory area until the initial se ttings of the dwc0 register are complete. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 dw32 note1 dw12 note2 dw31 note1 dw11 note2 dw30 note1 dw10 note2 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 notes 1. v850es/jj3-e only. be sure to set 1 in the v850es/jh3-e. 2. the dw12 to dw10 bits set wait of access to the usb function area. it is recommended to set the dw12 to dw10 bits to 001b (1 wait). caution be sure to set bits 15, 11, 7, and 3 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 209 of 1817 sep 19, 2011 5.5.2 external wait function to synchronize an extremely slow external memory, i/o, or asynchronous system, any num ber of wait states can be inserted in the bus cycle by using the external wait pin (wait). when the pcm0 pin is set to its alternate func tion, the external wait function is enabled. access to each area of the internal rom, internal ram, and on-chip peripheral i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in the multiple xed bus mode. in the separate bus mode, it is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 210 of 1817 sep 19, 2011 5.5.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. inserting wait example clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 211 of 1817 sep 19, 2011 5.5.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be se t by using the awc register. address wait insertion is set for each chip select area (cs0, cs2, cs3). if an address setup wait is inserted, it s eems that the high-clock period of the t1 state is extended by 1 clock. if an address-hold wait is inserted, it seems that the low- clock period of the t1 state is extended by 1 clock. (1) address wait control register (awc) the awc register can be read or written in 16-bit units. reset sets this register to ffffh. cautions 1. address-setup wait and address-hold wait cycles are not inserted when the internal rom area, internal ram area, and on-chip peripheral i/o areas are accessed. 2. write to the awc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the awc register are complete. after reset: ffffh r/w address: fffff488h 1 ahw3 note1 ahwn 0 1 not inserted inserted awc 1 asw3 note1 1 ahw2 1 asw2 1 ahw1 note2 1 asw1 note2 1 ahw0 1 asw0 8 9 10 11 12 13 specifies insertion of address-hold wait (n = 0, 2, 3) 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address-setup wait (n = 0, 2, 3) cs0 cs3 cs2 notes 1. v850es/jj3-e only. be sure to set 1 in the v850es/jh3-e. 2. it is recommended to clear the ahw1 bit and the asw1 bit to 0. caution be sure to set bits 15 to 8 to ?1?. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 212 of 1817 sep 19, 2011 5.6 idle state insertion function to facilitate interfacing with low-speed me mories, one idle state (ti) can be insert ed after the t3 state in the bus cycle that is executed for each space selected by the chip select. by inserting an idle state, the data output float delay time of the memory can be secured during read access (an id le state cannot be inserted during write access). whether the idle state is to be inserted c an be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) the bcc register can be read or written in 16-bit units. reset sets this register to aaaah. cautions 1. the internal rom, internal ram, and on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and th en do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. after reset: aaaah r/w address: fffff48ah 1 bc31 note1 bcn1 0 1 not inserted i nserted bcc 0 0 1 bc21 0 0 1 bc11 note2 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs3 cs2 cs0 notes1. v850es/jj3-e only. be sure to set 1 in the v850es/jh3-e. 2. it is recommended to clear the bc11 bit to 0. caution be sure to set bits 15, 13, 11 and 9 to ?1?, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 213 of 1817 sep 19, 2011 5.7 bus hold function 5.7.1 functional outline the hldrq and hldak functions are valid if the p43 note 1 , p44 note 1 , pcm2 note 2 , and pcm3 note 2 pins are set to their alternate function. when the hldrq pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus goes into a hi gh-impedance state and is released (bus hold status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in th e internal rom and internal ram is continued until an on- chip peripheral i/o register or the external memory is accessed. the bus hold status is indicated by assertion of the hldak pin (low leve l). the bus hold function enables the configuration of mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not ac knowledged during a multiple -access cycle initiated by the bus sizing function or a bit manipulation instruction. notes 1. v850es/jh3-e 2. v850es/jj3-e status data bus width access type timing at which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 214 of 1817 sep 19, 2011 5.7.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.7.3 operation in power save mode because the internal system clock is stopped in the stop, id le1, and idle2 modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asse rted, and the bus hold status is entered. when the hldrq pin is la ter deasserted, the hldak pin is also deasserted, and the bus hold status is cleared. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 215 of 1817 sep 19, 2011 5.8 bus priority bus hold, dma transfer, operand data accesses, instructi on fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. bus hold has the highest priority, followed by dma transfe r, operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-4. bus priority priority external bus cycle bus master bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu high low instruction fetch (successive) cpu v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 216 of 1817 sep 19, 2011 5.9 bus timing figure 5-4. multiplexed/sep arate bus read timing (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 clkout a23 to a0 note 1 astb cs3, cs2, cs0 notes 2, 3 wait ad15 to ad0 rd ad15 to ad8 ad7 to ad0 hi-z hi-z active active odd address even address 8-bit access programmable wait external wait idle state notes 1. v850es/jj3-e only. the a21 to a0 pins are used in the v850es/jh3-e. 2. v850es/jj3-e only. the cs2 and cs0 pi ns are used in the v850es/jh3-e. 3. only the cs space subject to access is active. remark the broken lines indicate high impedance. figure 5-5. multiplexed/separate bu s read timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 clkout a23 to a0 note 1 , ad15 to ad8 astb wait ad7 to ad0 rd cs3, cs2, cs0 notes 2, 3 programmable wait external wait idle state notes 1. v850es/jj3-e only. the a21 to a0 pins are used in the v850es/jh3-e. 2. v850es/jj3-e only. the cs2 and cs0 pi ns are used in the v850es/jh3-e. 3. only the cs space subject to access is active. remark the broken lines indicate high impedance. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 217 of 1817 sep 19, 2011 figure 5-6. multiplexed/separ ate bus write timing (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 clkout a23 to a0 note 1 astb wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 cs3, cs2, cs0 notes 2, 3 ad15 to ad8 ad7 to ad0 undefined hi-z active active odd address even address 8-bit access programmable wait external wait notes 1. v850es/jj3-e only. the a21 to a0 pins are used in the v850es/jh3-e. 2. v850es/jj3-e only. the cs2 and cs0 pi ns are used in the v850es/jh3-e. 3. only the cs space subject to access is active. figure 5-7. multiplexed/separate bu s write timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 clkout a23 to a0 note 1 , ad15 to ad8 astb wait ad7 to ad0 wr1, wr0 cs3, cs2, cs0 notes 2, 3 programmable wait external wait notes 1. v850es/jj3-e only. the a21 to a0 pins are used in the v850es/jh3-e. 2. v850es/jj3-e only. the cs2 and cs0 pi ns are used in the v850es/jh3-e. 3. only the cs space subject to access is active. v850es/jh3-e, v850es/jj3-e chapter 5 bus control function r01uh0290ej0300 rev.3.00 page 218 of 1817 sep 19, 2011 figure 5-8. multiplexed/sep arate bus hold timing (bus size: 16 bits, 16-bit access) t1 a1 a1 a2 undefined undefined undefined t2 t3 ti note 1 th th th th ti note 1 t1 t2 t3 d1 clkout hldrq hldak a23 to a0 note 2 astb ad15 to ad0 rd a2 d2 1111 1111 cs3, cs2, cs0 notes 3, 4 undefined notes 1. this idle state (ti) does not de pend on the bcc register settings. 2. v850es/jj3-e only. the a21 to a0 pins are used in the v850es/jh3-e. 3. v850es/jj3-e only. the cs2 and cs0 pi ns are used in the v850es/jh3-e. 4. only the cs space subject to access is active. remarks 1. see table 2-2 for the pin statuses in the bus hold mode. 2. the broken lines indicate the high-impedance state. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 219 of 1817 sep 19, 2011 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. main clock oscillator ? in clock-through mode f x = 3.0 to 6.25 mhz (f xx = 3.0 to 6.25 mhz) ? in pll mode f x = 3.0 to 6.25 mhz ( 8: f xx = 24 to 50 mhz) subclock oscillator ? f xt = 32.768 khz multiply ( 8) function by pll (phase locked loop) ? clock-through mode/pll mode selectable internal oscillator ? f r = 220 khz (typ.) internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) peripheral clock generation clock output function remark f x : main clock oscillation frequency f xx : main clock frequency f xt : subclock frequency f r : internal oscillation clock frequency v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 220 of 1817 sep 19, 2011 6.2 configuration figure 6-1. clock generator clkout exclk f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xt f xt f r selector selector selector frc bit mfrc bit selpll bit pllon bit cls, ck3 bits ck2 to ck0 bits ucksel bit stop mode subclock oscillator rtc clock, wdt clock rtc clock port cm prescaler 1 prescaler 2 idle control halt mode cpu clock peripheral clock (including clock for ethernet) usb clock wdt clock, tmm clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control rstop bit internal oscillator 1/8 divider xt1 xt2 x1 x2 idle mode pll f xx f x idle control selector selector halt control remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f r : internal oscillation clock frequency v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 221 of 1817 sep 19, 2011 (1) main clock oscillator the main clock oscillator oscillates the following frequencies (f x ). ? in clock-through mode f x = 3.0 to 6.25 mhz ? in pll mode f x = 3.0 to 6.25 mhz ( 8) (2) subclock oscillator the sub-resonator oscillates a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscillat or is stopped in the stop mode or w hen the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) internal oscillator oscillates a frequency (f r ) of 220 khz (typ.). (5) prescaler 1 this prescaler generates the clock (f xx to f xx /1,024) to be supplied to the follo wing on-chip peripheral functions: taa, tab, tmm, tmt, csie, csif, uartb, uartc, i 2 c, can, adc, wdt2, ethernet controller (6) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom, and ram blocks, and can be output from the clkout pin. (7) prescaler 3 this circuit divides the clock generated by the main clock oscillator (f x ) to a specific frequency (32.768 khz) and supplies that clock to the real-time counter (rtc) block. (8) pll this circuit multiplies the clock generated by the main clock oscillator (f x ) by 8. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be selected by using the pllctl.selpll bit. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 222 of 1817 sep 19, 2011 6.3 registers (1) processor clock control register (pcc) the pcc register is a special register. data can be wri tten to this register only in combination of specific sequences (see 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 03h. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 223 of 1817 sep 19, 2011 frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 main clock oscillator control used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) even if the mck bit is set (1) while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. before setting the mck bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. when the main clock is stopped and the device is operating with the subclock, clear (0) the mck bit and secure the oscillation stabilization time by software before switching the cpu clock to the main clock or operating the on-chip peripheral functions. ? ? ? < > < > < > f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 note the cls bit is a read-only bit. cautions 1. do not change the cpu clock (by us ing the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. remark : don't care v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 224 of 1817 sep 19, 2011 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instruction is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if s ubclock operation has started. it takes the following time after the ck3 bit is set unt il subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping the main clock, stop th e pll. also stop the op erations of the on-chip peripheral functions operati ng with the main clock. 2. if the following conditions are not satisf ied, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting the ck2 to ck0 bits [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped. _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. note that in <2> above, the cls bit is read in a closed loop. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 225 of 1817 sep 19, 2011 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock starts oscillating <2> insert waits by the program and wait until the oscillation stabilizat ion time of the main clock elapses. <3> ck3 bit 0: use of a bit manipulation instructi on is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time af ter the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one no p instruction immediately after setting the ck3 bit to 0 or read the cls bit to check if main clock operation has started. caution enable operation of the on -chip peripheral functions operati ng with the main clock only after the oscillation of the main clock stabilizes. if their operations are enabled before the lapse of the oscillation stabilization time, a malfunction may occur. [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating. <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time. _wait_ost : nop nop nop addi -1, r11, r11 cmp r0, r11 bne _wait_ost <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts. bnz _check_cls _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. note that in <4> above, the cls bit is read in a closed loop. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 226 of 1817 sep 19, 2011 (2) internal oscillation mode register (rcm) the rcm register is an 8-bit register that sets the operation mode of the internal oscillator. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 rcm 0 0 0 00 0 rstop internal oscillator oscillation internal oscillator stopped rstop 0 1 oscillation/stop of internal oscillator after reset: 00h r/w address: fffff80ch < > cautions 1. the internal oscilla tor cannot be stopped while the cpu is operating on the internal oscillation clock (ccls.cclsf bit = 1). do not set the rstop bit to 1. 2. the internal oscillator oscillates if the ccls.cclsf bit is set to 1 (when wdt overflow occurs during oscillation stabilization) even when the rstop bit is set to 1. at this time, the rstop bit remains being set to 1. (3) cpu operation clock status register (ccls) the ccls register indicates the stat us of the cpu operation clock. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 ccls 0 0 0 0 0 0 cclsf after reset: 00h note r address: fffff82eh operating on main clock (f x ) or subclock (f xt ). operating on internal oscillation clock (f r ). cclsf 0 1 cpu operation clock status note if wdt overflow occurs during oscillation stabilization after a reset is released, the cclsf bit is set to 1 and the reset value is 01h. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 227 of 1817 sep 19, 2011 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register clk bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle1, idle2 mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) subclock oscillator (f xt ) cpu clock (f cpu ) internal system clock (f clk ) main clock (in pll mode, f xx ) note peripheral clock (f xx to f xx /1,024) wt clock (main) wt clock (sub) wdt2 clock (internal oscillation) wdt2 clock (main) wdt2 clock (sub) note lockup time remark : operable : stopped 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alternately as the pcm1 pin and functions as a clock out put pin if so specif ied by the control register of port cm. the status of the clkout pin is the same as the internal system clo ck in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped status. however, t he clkout pin is in the port mode (pcm1 pin: input mode) after reset and until it is set in the output mode. therefore, t he status of the pin is hi-z. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 228 of 1817 sep 19, 2011 6.5 pll function 6.5.1 overview in the v850es/jh3-e and v850es/jj3-e, an operating clock that is 8 times higher than the oscillation frequency output by the pll function or the clock-through mode can be select ed as the operating clock of the cpu and on-chip peripheral functions. when pll function is used ( 8): input clock = 3.0 to 6.25 mhz (output: 24 to 50 mhz) clock-through mode: input clock = 3.0 to 6.25 mhz (output: 3.0 to 6.25 mhz) 6.5.2 registers (1) pll control register (pllctl) the pllctl register is an 8-bit regi ster that controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. 0 pllctl 0 0 0 00 selpll pllon pll stopped pll operating (after pll operation starts, a lockup time is required for frequency stabilization) pllon 0 1 pll operation stop register clock-through mode pll mode selpll 0 1 cpu operation clock selection register after reset: 01h r/w address: fffff82ch < > < > cautions 1. when the pllon bit is cleared to 0, the selpll bit is automatical ly cleared to 0 (clock- through mode). 2. the selpll bit can be set to 1 only when the pll clock frequency is stabilized. if not (unlocked), "0" is written to the sel pll bit if data is written to it. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 229 of 1817 sep 19, 2011 (2) clock control register (ckc) the ckc register is a special register. data can be wri tten to this register only in a combination of specific sequence (see 3.4.8 special registers ). the ckc register controls the inte rnal system clock in the pll mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 0ah. 0 ckc 0 0 0 1 0 1 ckdiv0 after reset: 0ah r/w address: fffff822h setting prohibited f xx = 8 f x (f x = 3.0 to 6.25 mhz) ckdiv0 0 1 internal system clock (f xx ) in pll mode caution 1. be sure to set the ckc re gister to 0bh. when setting this register to a value other than 0bh or leaving it set to its initial value without setting it to 0bh, enabling pll operation (pllctl.selpll = 1) is prohibited. 2. be sure to set bits 3 and 1 to ?? 1?? and clear bits 7 to 4 and 2 to ??0??. remark both the cpu clock and peripheral clock are divided by the ckc register, but only the cpu clock is divided by the pcc register. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 230 of 1817 sep 19, 2011 (3) lock register (lockr) phase lock occurs at a given frequency following power application or immediately after the stop mode is released, and the time required for stabilization is the lo ckup time (frequency stabilization time). this state until stabilization is called the lockup status, and the stabilized state is called the locked status. the lockr register includes a lock bit that re flects the pll frequency stabilization status. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 lockr 0 0 0 00 0 lock locked status unlocked status lock 0 1 pll lock status check after reset: 00h r address: fffff824h < > caution the lock register does not re flect the lock status of the pl l in real time. the set/clear conditions are as follows. [set conditions] ? upon system reset note ? in idle2 or stop mode ? upon setting of pll stop (clearing of pllctl.pllon bit to 0) ? upon stopping main clock and using cpu with subc lock (setting of pcc.ck3 bit to 1 and setting of pcc.mck bit to 1) note this register is set to 01h by reset and cleared to 00h after the reset has been released and the oscillation stabilization time has elapsed. [clear conditions] ? upon overflow of oscillation stabilization time fo llowing reset release (osts register default time (see 27.2 (3) oscillation stabilization time select register (osts) )) ? upon oscillation stabilization timer overflow (tim e set by osts register) following stop mode release, when the stop mode was set in the pll operating status ? upon pll lockup time timer overflow (time set by plls register) when the pllctl.pllon bit is changed from 0 to 1 ? after the setup time inserted upon release of the id le2 mode is released (time set by the osts register) when the idle2 mode is set during pll operation. v850es/jh3-e, v850es/jj3-e chapter 6 clock generation function r01uh0290ej0300 rev.3.00 page 231 of 1817 sep 19, 2011 (4) pll lockup time specification register (plls) the plls register is an 8-bit register used to select the pll lockup time when the pllctl.pllon bit is changed from 0 to 1. this register can be read or written in 8-bit units. reset sets this register to 03h. 0 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x (default value) plls1 0 0 1 1 plls0 0 1 0 1 selection of pll lockup time plls 0 0 0 0 0 plls1 plls0 after reset: 03h r/w address: fffff6c1h cautions 1. set so that the lockup time is 800 s or longer. 2. do not change the plls register setting during the lockup period. 6.5.3 usage (1) when pll is used ? after the reset signal has been released, the pll o perates (pllctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bi t = 0), select the pll mode (selpll bit = 1). ? to enable pll operation, first set the pllon bit to 1, and then set the selpll bit to 1 after the lockr.lock bit = 0. to stop the pll, first select the clock-throug h mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). ? the pll stops during transition to the idle2 or stop mode regardless of the setting and is restored from the idle2 or stop mode to the status before transition. the time requir ed for restoration is as follows. (a) when transiting to the idle2 or st op mode from the clock through mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or longer. ? idle2 mode: set the osts register so that the setup time is 350 s (min.) or longer. (b) when transiting to the idle 2 or stop m ode while remaining in the pll operation mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or longer. ? idle2 mode: set the osts register so that the setup time is 800 s (min.) or longer. when transiting to the idle1 mode, the pll does not stop. stop the pll if necessary. (2) when pll is not used ? the clock-through mode (selpll bit = 0) is selected a fter the reset signal has been released, but the pll is operating (pllon bit = 1) and must t herefore be stopped (pllon bit = 0). v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 232 of 1817 sep 19, 2011 chapter 7 16-bit timer/ event counter aa (taa) timer aa (taa) is 16-bit timer/event counter. the v850es/jh3-e and v850es/jj3 -e have taa0 to taa5. 7.1 overview an overview of taan is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 2 ? external event count input pins note : 1 ? external trigger input pin note : 1 ? timer/counter: 1 ? capture/compare registers: 2 (32-bit capture timer function available by using a cascade connection of taa0 and taa1, taa2 and taa3.) ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 note external event count input pins and external trigger input pins are alternately used as capture/trigger input pins (tiaan0). remark n = 0 to 5 7.2 functions taan has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? timer-tuned function ? simultaneous-start function v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 233 of 1817 sep 19, 2011 7.3 configuration taan includes the following hardware. table 7-1. configuration of taan item configuration registers 16-bit counter taan capture/compare registers 0, 1 (taanccr0, taanccr1) taan counter read buffer register (taancnt) ccr0, ccr1 buffer registers taan control registers 0, 1 (taanctl0, taanctl1) taan i/o control registers 0 to 2, 4 (taanioc0 to taanioc2, taanioc4) taan option registers 0, 1 (taanopt0, taanopt1) taa noise elimination control register (tanfc) timer inputs note 1 2 (tiaan0 note 2 , tiaan1 pins) timer outputs note 1 2 (toaan0, toaan1 pins) notes 1. when using the functions of the tiaa n0, tiaan1, toaan0, and toaan1 pins, see table 4-18 using port pin as alternate-function pin . 2. the tiaan0 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. remark n = 0 to 5 figure 7-1. block diagram of taan selector internal bus internal bus selector edge detector ccr0 buffer register ccr1 buffer register taanccr0 taanccr1 16-bit counter taancnt inttaanov inttaancc0 inttaancc1 output controller clear toaan0 toaan1 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tiaan0 tiaan1 note note taa2, taa3, taa5: f xx /2, f xx /4, f xx /8, f xx /16, f xx /64, f xx /256, f xx /512, f xx /1024. remark f xx : main clock frequency n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 234 of 1817 sep 19, 2011 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the taancnt register. when the taanctl0.taance bit = 0, the va lue of the 16-bit counter is ffffh. if the taancnt register is read at this time, 0000h is read. reset sets the taance bit to 0. theref ore, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the taanccr0 register is used as a compare regist er, the value written to the taanccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter ma tches the value of the ccr0 buffer register, a compare match interrupt request signal (inttaancc0) is generated. the ccr0 buffer register cannot be read or written directly. reset clears the taanccr0 register to 0000h. ther efore, the ccr0 buffer register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the taanccr1 register is used as a compare regist er, the value written to the taanccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter ma tches the value of the ccr1 buffer register, a compare match interrupt request signal (inttaancc1) is generated. the ccr1 buffer register cannot be read or written directly. reset clears the taanccr1 register to 0000h. ther efore, the ccr1 buffer register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tiaan0 an d tiaan1 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the vali d edge by using the taanioc1 and taanioc2 registers. (5) output controller this circuit controls the output of the toaan0 and toaan 1 pins. the outputs of t he toaan0 and toaan1 pins are controlled by the taanioc0 register. (6) selector this selector selects the count clock for the 16-bit counter. eight types of internal clocks or an external event can be selected as the count clock. remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 235 of 1817 sep 19, 2011 7.3.1 pin configuration the timer inputs and outputs that configur e taan are shared with the following ports. the port functions must be set when using each pin (see table 4-18 using port pin as alternate-function pin ). table 7-2 pin configuration channel port timer aa input timer aa output other alternate function p30 tiaa00 note toaa00 txdc0/sif2 taa0 p31 tiaa01 toaa01 rxdc0/sof2 p32 tiaa10 note toaa10 asckc0/sckf2 taa1 p33 tiaa11 toaa11 sif4/txdb0 p34 tiaa20 note toaa20 sof4/rxdb0 taa2 p35 tiaa21 toaa21 sckf4/toaa1off/intp06 p25 tiaa30 note toaa30 sckf1/udmarq0 taa3 p26 tiaa31 toaa31 intp05/udmaak0 p42 tiaa40 note toaa40 sckf0/rtp02 taa4 p45 tiaa41 toaa41 scke0/rtp05 p911 tiaa50 note toaa50 scke1/a11 taa5 p915 tiaa51 toaa51 sckf3/a15 note the taan0 pin functions alternately as a capture trigger input function, external event input function, and external trigger input function. remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 236 of 1817 sep 19, 2011 7.4 registers the registers that control taan are as follows. ? taan control register 0 (taanctl0) ? taan control register 1 (taanctl1) ? taan i/o control register 0 (taanioc0) ? taan i/o control register 1 (taanioc1) ? taan i/o control register 2 (taanioc2) ? taan i/o control register 4 (taanioc4) ? taan option register 0 (taanopt0) ? taan option register 1 (taanopt1) ? taan capture/compare register 0 (taanccr0) ? taan capture/compare register 1 (taanccr1) ? taan counter read buffer register (taancnt) ? taa noise elimination control register (tanfc) remarks 1. when using the functions of the tiaa n0, tiaan1, toaan0, and toaan1 pins, see table 4-18 using port pin as alternate-function pin . 2. n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 237 of 1817 sep 19, 2011 (1) taan control register 0 (taanctl0) the taanctl0 register is an 8-bit register that controls the operation of taan. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the taanctl0 register by software. taance taan operation disabled (taan reset asynchronously note ). taan operation enabled. taan operation started. taance 0 1 taan operation control taanctl0 (n = 0 to 5) 0000 taancks2 taancks1 taancks0 654321 after reset: 00h r/w address: taa0ctl0 fffff630h, taa1ctl0 fffff640h, taa2ctl0 fffff650h, taa3ctl0 fffff660h, taa4ctl0 fffff670h, taa5ctl0 fffff680h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 (20.0 ns) (40.0 ns) (80.0 ns) (160.0 ns) (320.0 ns) (640.0 ns) (1.28 s) (2.56 s) f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /512 f xx /1024 (40.0 ns) (80.0 ns) (160.0 ns) (320.0 ns) (1.28 s) (5.12 s) (10.24 s) (20.48 s) taancks2 0 0 0 0 1 1 1 1 internal count clock selection n = 0, 1, 4 n = 2, 3, 5 taancks1 0 0 1 1 0 0 1 1 taancks0 0 1 0 1 0 1 0 1 ? ? note taanopt0.taanovf bit, 16-bit counter, timer output (toaan0, toaan1 pins) cautions 1. set the taancks2 to taancks 0 bits when the taance bit = 0. when the value of the taance bit is changed from 0 to 1, the taancks2 to taancks0 bits can be set simultaneously. 2. be sure to set bits 3 to 6 to ?0?. remark f xx : main clock frequency the values in parentheses indicate the cycles when f xx = 50 mhz. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 238 of 1817 sep 19, 2011 (2) taan control register 1 (taanctl1) the taanctl1 register is an 8-bit register that controls the operation of taan. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) taanest 0 1 software trigger control (n = 0 to 5) after reset: 00h r/w address: generates a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the taanest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the taanest bit as the trigger. ? tuned operation mode enable control (n = 0, 2, 4, 5) tuned-operation function (specification of slave operation) simultaneous-start function (specification of slave timer) independent operation mode (asynchronous operation mode) setting prohibited for the tuned-operation function, see 7.6 timer-tuned operation function . for the simultaneous-start function, see 7.7 simultaneous-start function . taa0sye taa0ctl1 taa0est taa0eeetaa0sym 0 taa0md2 taa0md1 taa0md0 taa2sye taa2ctl1 taa2est taa2eeetaa2sym 0 taa2md2 taa2md1 taa2md0 taa5sye taa5ctl1 taa5est taa5eeetaa5sym 0 taa5md2 taa5md1 taa5md0 0 taa1ctl1 taa1est taa1eee 0 0 taa1md2 taa1md1 taa1md0 taa4sye taa4ctl1 taa4est taa4eee taa4sym 0 taa4md2 taa4md1 taa4md0 0 taa3ctl1 taa3est taa3eee 0 0 taa3md2 taa3md1 taa3md0 <6> 4 3 1 taa0ctl1 fffff631h, taa1ctl1 fffff641h, taa2ctl1 fffff651h, taa3ctl1 fffff661h, taa4ctl1 fffff671h, taa5ctl1 fffff681h 7 0 2 taansye 0 0 1 1 taa1 master timer slave timer taa3 tab0 tab1 taa0 taa2 taa5 taa4 taansym 0 1 0 1 these bits can be set only for the slave timer (setting them for the master timer is prohibited). the relationship between the master timer and slave timer is as follows. <5> cautions 1. the taanest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode . in any other mode, writing 1 to this bit is ignored. 2. be sure to clear the sections of the taanctl1 register of each channel, where 0 is specified, to 0. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 239 of 1817 sep 19, 2011 (2/2) disables operation with external event count input. (performs counting with the count clock selected by the taanctl0.taanck0 to taanck2 bits.) taaneee 0 1 count clock selection the taaneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited taanmd2 0 0 0 0 1 1 1 1 timer mode selection taanmd1 0 0 1 1 0 0 1 1 taanmd0 0 1 0 1 0 1 0 1 enables operation with external event count input. (performs counting at every valid edge of the external event count input signal.) cautions 1. external event count input is selected in the external event count mode regardless of the value of the taaneee bit. 2. set the taaneee and taanmd 2 to taanmd0 bits when the taanctl0.taance bit = 0. (the sam e value can be written when the taance bit = 1.) the operation is not guaranteed when rewriting is performed with the taance bit = 1. if rewriting was mistakenly performed, clear the taance bit to 0 an d then set the bits again (n = 0 to 5). v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 240 of 1817 sep 19, 2011 (3) taan i/o control register 0 (taanioc0) the taanioc0 register is an 8-bit register that controls the timer output (toaan0, toaan1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 taanol1 0 1 toaan1 pin output level setting note toaan1 pin output starts at high level toaan1 pin output starts at low level taanioc0 (n = 0 to 5) 0 0 0 taanol1 taanoe1 taanol0 taanoe0 6543<2>1 after reset: 00h r/w address: taa0ioc0 fffff632h, taa1ioc0 fffff642h, taa2ioc0 fffff652h, taa3ioc0 fffff662h, taa4ioc0 fffff672h, taa5ioc0 fffff682h taanoe1 0 1 toaan1 pin output setting timer output disabled ? when taanol1 bit = 0: low level is output from the toaan1 pin ? when taanol1 bit = 1: high level is output from the toaan1 pin taanol0 0 1 toaan0 pin output level setting note toaan0 pin output starts at high level toaan0 pin output starts at low level taanoe0 0 1 toaan0 pin output setting timer output disabled ? when taanol0 bit = 0: low level is output from the toaan0 pin ? when taanol0 bit = 1: high level is output from the toaan0 pin 7 <0> timer output enabled (a square wave is output from the toaan1 pin). timer output enabled (a square wave is output from the toaan0 pin). note the output level of t he timer output pin (toaanm) specified by the taanolm bit is shown below. taance bit toaanm pin output 16-bit counter ? when taanolm bit = 0 taance bit toaanm pin output 16-bit counter ? when taanolm bit = 1 cautions 1. rewrite the taanol1, taanoe1, taanol0, and taanoe0 bits when the taanctl0.taance bit = 0. (the same value can be written when the taance bit = 1.) if rewriting was mistakenly performed, clear th e taance bit to 0 and then set the bits again. 2. even if the taanolm bit is manipulated when the taance and taanoem bits are 0, the toaanm pin output level varies. remark m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 241 of 1817 sep 19, 2011 (4) taan i/o control register 1 (taanioc1) the taanioc1 register is an 8-bit register that controls th e valid edge of the capture tr igger input signals (tiaan0, tiaan1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 taanis3 0 0 1 1 taanis2 0 1 0 1 capture trigger input signal (tiaan1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges taanioc1 (n = 0 to 5) 0 0 0 taanis3 taanis2 taanis1 taanis0 654321 after reset: 00h r/w address: taa0ioc1 fffff633h, taa1ioc1 fffff643h, taa2ioc1 fffff653h, taa3ioc1 fffff663h, taa4ioc1 fffff673h, taa5ioc1 fffff683h taanis1 0 0 1 1 taanis0 0 1 0 1 capture trigger input signal (tiaan0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the taanis 3 to taanis0 bits when the taanctl0.taance bit = 0. (the same value can be written when the taance bit = 1.) if rewriting was mistakenly performed, clear th e taance bit to 0 and then set the bits again. 2. the taanis3 to taanis0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not performed. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 242 of 1817 sep 19, 2011 (5) taan i/o control register 2 (taanioc2) the taanioc2 register is an 8-bit regi ster that controls the va lid edge of the external event count input signal (tiaan0 pin) and external trigger input signal (tiaan0 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 taanees1 0 0 1 1 taanees0 0 1 0 1 external event count input signal (tiaan0 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges taanioc2 (n = 0 to 5) 000 taanees1 taanees0 taanets1 taanets0 654321 after reset: 00h r/w address: taa0ioc2 fffff634h, taa1ioc2 fffff644h, taa2ioc2 fffff654h, taa3ioc2 fffff664h. taa4ioc2 fffff674h, taa5ioc2 fffff684h taanets1 0 0 1 1 taanets0 0 1 0 1 external trigger input signal (tiaan0 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the t aanees1, taanees0, taanets1, and taanets0 bits when the taan ctl0.taance bit = 0. (the same value can be written when the taance bit = 1.) if rewriting was mistakenly perf ormed, clear the taance bit to 0 and then set the bits again. 2. the taanees1 and taanees0 bits are valid only when the taanctl1.taaneee bit = 1 or when the external event count mode (taanctl1.taanmd2 to taanctl1.taanmd0 bits = 001) has been set. 3. the taanets1 and taanets0 bits are valid only when the external trigger pulse output mode (taanctl1.taanmd2 to taanctl1.taanmd0 bits = 010) or the one-shot pulse output mode (taanctl1.taanmd2 to taanctl1.taanmd0 = 011) is set. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 243 of 1817 sep 19, 2011 (6) taan i/o control register 4 (taanioc4) the taanioc4 register is an 8-bit regi ster that controls the timer output. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. this register is not reset by stopping the timer operation (taanctl0.taance = 0). cautions 1. accessing the taanioc4 register is prohibi ted in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock 2. the taanioc4 register can be set only in the interval timer mode and free-running timer mode. be sure to set the taanioc4 register to 00h in all other modes (for details of the mode setting, see 7.4 (2) taan control register 1 (taanctl1)). the taanioc4 register setting is invalid if the taanccr0 and taanccr1 registers are set to the capture functi on, even if the free-running timer mode is set. 0 taanos1 0 0 1 1 taanor1 0 1 0 1 taanioc4 (n = 0 to 5) 0 0 0 taanos1 taanor1 taanos0 taanor0 65 4 3 21 taa0ioc4 fffff63ch, taa1ioc4 fffff64ch, taa2ioc4 fffff65ch, taa3ioc4 fffff66ch, taa4ioc4 fffff67ch, taa5ioc4 fffff68ch taanos0 0 0 1 1 taanor0 0 1 0 1 7 0 after reset: 00h r/w address: toggle control of tiaan1 pin no request. normal toggle operation. reset request fix to inactive level upon next match between value of 16-bit counter and value of taanccr1 register. set request fix to active level upon next match between value of 16-bit counter and value of taanccr1 register. keep request keep current output level. toggle control of tiaan0 no request. normal toggle operation. reset request fix to inactive level upon next match between value of 16-bit counter and value of taanccr0 register. set request fix to active level upon next match between value of 16-bit counter and value of taanccr0 register. keep request keep current output level. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 244 of 1817 sep 19, 2011 (7) taan option register 0 (taanopt0) the taanopt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 taanccs1 0 1 taanccr1 register capture/compare selection the taanccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected taanopt0 (n = 0 to 5) 0 taanccs1taanccs0 0 0 0 taanovf 654321 after reset: 00h r/w address: taa0opt0 fffff635h, taa1opt0 fffff645h, taa2opt0 fffff655h, taa3opt0 fffff665h, taa4opt0 fffff675h, taa5opt0 fffff685h taanccs0 0 1 taanccr0 register capture/compare selection the taanccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected taanovf set (1) reset (0) taan overflow detection flag ? the taanovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an interrupt request signal (inttaanov) is generated at the same time that the taanovf bit is set to 1. the inttaanov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the taanovf bit is not cleared even when the taanovf bit or the taanopt0 register are read when the taanovf bit = 1. ? the taanovf bit can be both read and written, but the taanovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of taan. overflow occurred 0 written to taanovf bit or taanctl0.taance bit = 0 7 <0> cautions 1. rewrite the taanccs 1 and taanccs0 bits when the taance bit = 0. (the same va lue can be written when the taance bit = 1.) if rewriting was mistakenly performed, clear the taance bit to 0 and then set the bits again. 2. be sure to set bits 1 to 3, 6, and 7 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 245 of 1817 sep 19, 2011 (8) taan option register 1 (taanopt1) the taanopt1 register is an 8-bit r egister that controls the 32-bit capt ure function realized by a cascade connection. rewriting this register is prohibited while the timer is operating (taanctl0.taance = 1). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. taancse taancse 0 1 cascade control individual operation or operation as lower side of cascade function operation as higher side of cascade function taanopt1 (n = 0, 2) 0000000 654321 taa0opt1 fffff63dh, taa2opt1 fffff65dh 7 0 after reset: 00h r/w address: cautions 1. cascade connection a nd timer-tuned operation cannot be used together. be sure to set taanctl1.taansye to 0 for a cascade connection. 2. for a cascade connecti on, set the free-running timer mode and use the taanccr0 and taanccr1 registers as capture registers. for details of cascade c onnection, see 7.8 cascade connection. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 246 of 1817 sep 19, 2011 (9) taan capture/compare register 0 (taanccr0) the taanccr0 register can be used as a capture regi ster or a compare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the taanopt0.taanccs0 bit. in the pulse width measurement mode, the taanccr0 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the taanccr0 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the taanccr0 register is prohibite d in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock taanccr0 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: taa0ccr0 fffff636h, taa1ccr0 fffff646h, taa2ccr0 fffff656h, taa3ccr0 fffff666h, taa4ccr0 fffff676h, taa5ccr0 fffff686h 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 247 of 1817 sep 19, 2011 (a) function as compare register the taanccr0 register can be rewritten even when the taanctl0.taance bit = 1. the set value of the taanccr0 register is transferred to the ccr0 buffer register. when the value of the 16- bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttaancc0) is generated. if toaan0 pin output is enabled at this time , the output of the toaan0 pin is inverted. when the taanccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse out put mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count value ma tches the value of the ccr0 buffer register. (b) function as capture register when the taanccr0 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the taanccr0 register if the valid edge of the captur e trigger input pin (tiaan0 pin) is detected. in the pulse width measurement mode, the count value of the 16-bit counter is stored in the taanccr0 register and the 16-bit counter is cleared (000 0h) if the valid edge of the capture trigger input pin (tiaan0) is detected. even if the capture operation and reading the taanccr0 register conflict, the correct value of the taanccr0 register can be read. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 248 of 1817 sep 19, 2011 (10) taan capture/compare register 1 (taanccr1) the taanccr1 register can be used as a capture regi ster or a compare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the taanopt0.taanccs1 bi t. in the pulse width measurement mode, the taanccr1 register can be used only as a capture register. in any other mode, this register can be used only as a compare register. the taanccr1 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the taanccr1 register is prohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock taanccr1 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: taa0ccr1 fffff638h, taa1ccr1 fffff648h, taa2ccr1 fffff658h, taa3ccr1 fffff668h, taa4ccr1 fffff678h, taa5ccr1 fffff688h 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 249 of 1817 sep 19, 2011 (a) function as compare register the taanccr1 register can be rewritten even when the taanctl0.taance bit = 1. the set value of the taanccr1 register is transferred to the ccr1 buffer register. when the value of the 16- bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttaancc1) is generated. if toaan1 pin output is enabled at this time , the output of the toaan1 pin is inverted. (b) function as capture register when the taanccr1 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the taanccr1 register if the valid edge of the captur e trigger input pin (tiaan1 pin) is detected. in the pulse width measurement mode, the count value of the 16-bit counter is stored in the taanccr1 register and the 16-bit counter is cleared (000 0h) if the valid edge of the capture trigger input pin (tiaan1) is detected. even if the capture operation and reading the taanccr1 register conflict, the correct value of the taanccr1 register can be read. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 7-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 250 of 1817 sep 19, 2011 (11) taan counter read bu ffer register (taancnt) the taancnt register is a read buffer register t hat can read the count va lue of the 16-bit counter. if this register is read when the taanctl0.taance bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the taancnt register is cleared to 0000h when the taance bit = 0. if the taancnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. reset clears the taance bit to 0. therefore, the va lue of the taancnt register is cleared to 0000h. caution accessing the taancnt register is prohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock taancnt (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r address: taa0cnt fffff63ah, taa1cnt fffff64ah, taa2cnt fffff65ah, taa3cnt fffff66ah, taa4cnt fffff67ah, taa5cnt fffff68ah 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 251 of 1817 sep 19, 2011 (12) noise elimination control register (tanfcn) digital noise elimination can be selected for the tiaan0 and tiaan1 pins. the noise elimination setting is selected using the tanfcn register. when digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f xx and f xx /4. sampling is performed 3 times. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution time equal to the sampling clock 3 clocks is required until th e digital noise eliminator is initialized after the sampling cloc k has been changed. if the va lid edge of tiaan0 and tiaan1 is input after the sampling clock has been change d and before the time of the sampling clock 3 clocks passes, therefore, an interrupt request si gnal may be generated. therefore, when using the external trigger function, th e external event function, and the capture trigger function of taan, enable taan operation after the time of the sampling clock 3 clocks has elapsed. remark n = 0 to 5 tanfenn tanfcn (n = 0 to 5) 0 0 0 0 0 0 tanfcn0 f xx f xx /4 tanfcn0 0 1 digital sampling clock after reset: 00h r/w address: tanfc0 fffff5a0h, tanfc1 fffff5a2h, tanfc2 fffff5a4h, tanfc3 fffff5a6h, tanfc4 fffff5a8h, tanfc5 fffff5aah does not perform digital noise elimination performs digital noise elimination tanfenn 0 1 setting of digital noise elimination < > remarks 1. since sampling is performed 3 times, the noise width for reliably eliminating noise is 2 sampling clocks. 2. in the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 252 of 1817 sep 19, 2011 a timing example of noise elimination performed by the ti mer aa input pin digital filter is shown figure 7-2. figure 7-2. example of digital noise elimination timing noise elimination clock input signal internal signal 3 clocks sampling 3 times 3 clocks 1 clock 1 clock 2 clocks 2 clocks sampling 3 times remark if there are two or fewer noise elimination cloc ks while the tiaan0 or tiaan1 input signal is high level (or low level), that input signal is eliminated as noise. if it is sampled three times or more, the edge is detected as a valid input (n = 0 to 5). v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 253 of 1817 sep 19, 2011 7.5 operation taan can perform the following operations. operation taanctl1.taanest bit (software trigger bit) tiaan0 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode , specify that the valid edge of the ti aan0 pin capture trigger input is not detected (by clearing the taanioc1.taanis 1 and taanioc1.taanis0 bits to ?00?). 2. when using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the taanctl1.taaneee bit to 0). remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 254 of 1817 sep 19, 2011 (1) anytime write and batch write with taan, the taanccr0 and taanccr1 registers can be rewritten during timer operation (taanctl0.taance bit = 1), but the write method (anytime write, batch wr ite) of the ccr0 and ccr1 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the taanccr0 and taanccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. remark n = 0 to 5 figure 7-3. example of basic anytime write oper ation flowchart (interval timer mode of taa0) start initial settings ? set values to taaccrm register ? timer operation enable (taa0ce bit = 1) transfer values of taa0ccrm register to ccrm buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start inttaa0cc1 signal output taa0ccrm register rewrite transfer to ccrm buffer register inttaa0cc0 signal output note the 16-bit counter is not cleared upon a match between the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between the 16-bit counter value and the ccr0 buffer register value. remark m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 255 of 1817 sep 19, 2011 figure 7-4. example of anytime write timing (interval timer mode of taa0) d 01 d 01 d 01 d 01 0000h taa0ce bit = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter taa0ccr0 register taa0ccr1 register inttaa0c0 signal inttaa0cc1 signal ccr0 buffer register ccr1 buffer register 0000h ffffh remark d 01 , d 02 : set values of taa0ccr0 register d 11 , d 12 : set values of taa0ccr1 register v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 256 of 1817 sep 19, 2011 (b) batch write in this mode, data is transferred all at once from the taanccr0 and taanccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. this da ta is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counte r. transfer is enabled by writing to the taanccr1 register. whether to enable or disable the next transfe r timing is controlled by writ ing or not writing to the taanccr1 register. in order for the set value when the taanccr0 and taanccr1 registers are rewritten to become the 16-bit counter comparison value (in other words, in order fo r this value to be transferred to the ccr0 and ccr1 buffer registers), it is necessary to rewrite the taan ccr0 register and then write to the taanccr1 register before the 16-bit counter value and the ccr0 buffer re gister value match. ther efore, the values of the taanccr0 and taanccr1 registers are transferred to the ccr0 and ccr1 buffer registers upon a match between the count value of the 16-bit counter and the va lue of the ccr0 buffer register. thus even when wishing only to rewrite the value of the taanccr0 register, also write the same value (same as preset value of the taanccr1 register) to the taanccr1 register. remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 257 of 1817 sep 19, 2011 figure 7-5. example of basic batch write oper ation flowchart (pwm output mode of taa0) start initial settings set values to taa0ccrm register enable timer operation (taa0ce bit = 1) transfer values of taa0ccrm register to ccrm buffer register timer operation match between 16-bit counter and ccr1 buffer register note match between 16-bit counter and ccr0 buffer register 16-bit counter clear & start transfer of values of taa0ccrm register to ccrm buffer register inttaa0cc1 signal output taa0ccr0 register rewrite taa0ccr1 register rewrite inttaa0cc0 signal output batch write enable ? ? ? ? ? ? note the 16-bit counter is not cleared upon a matc h between the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a ma tch between the 16-bit count er value and the ccr0 buffer register value. caution writing to the taa0ccr1 register includ es enabling of batch write. thus, rewrite the taa0ccr1 register after rewriting the taa0ccr0 register. remark m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 258 of 1817 sep 19, 2011 figure 7-6. timing of batch write (interval timer mode of taa0) d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 0000h d 11 taa0ce bit = 1 note 1 d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter taa0ccr0 register taa0ccr1 register inttaa0cc0 signal inttaa0cc1 signal toaa01 pin output toaa00 pin output ccr0 buffer register ccr1 buffer register note 1 note 1 note 1 same value write d 02 d 12 0000h d 03 d 12 note 2 note 3 ffffh notes 1. because the taa0ccr1 register was not rewritten, d 03 is not transferred. 2. because the taa0ccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit counter and the value of the taa0ccr0 register (d 01 ). 3. because the taa0ccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit counter and the value of the taa0ccr0 register (d 02 ). remark d 01 , d 02 , d 03 : set values of taa0ccr0 register d 11 , d 12 : set values of taa0ccr1 register v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 259 of 1817 sep 19, 2011 7.5.1 interval timer mode (t aanmd2 to taanmd0 bits = 000) in the interval timer mode, an interrupt request signal (inttaancc0) is generated at any interval if the taanctl0.taance bit is set to 1. a square wave whose half cycle is equal to the interval can be output from the toaan0 pin. usually, the taanccr1 register is not used in the interval timer mode. figure 7-7. configuration of interval timer 16-bit counter output controller ccr0 buffer register taance bit taanccr0 register count clock selection clear match signal toaan0 pin inttaancc0 signal remark n = 0 to 5 figure 7-8. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h taance bit taanccr0 register toaan0 pin output inttaancc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 260 of 1817 sep 19, 2011 when the taance bit is set to 1, the value of the 16-bi t counter is cleared from ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the toaan0 pin is inverted. additionally, the set value of the taanccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the toaan0 pin is inverted, and a compare match interrupt request signal (inttaancc0) is generated. the interval can be calculated by the following expression. interval = (set value of taanccr0 register + 1) count clock cycle remark n = 0 to 5 figure 7-9. register settings for in terval timer mode operation (1/2) (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 select count clock 0: stops counting 1: enables counting 0/1 0/1 0/1 taancks2 taancks1 taancks0 taance (b) taan control register 1 (taanctl1) 0 0 0/1 note 00 taanctl1 0, 0, 0: interval timer mode 0: operates on count clock selected by taancks0 to taancks2 bits 1: counts with external event count input signal 000 taanmd2 taanmd1 taanmd0 taaneee taanest note this bit can be set to 1 only when the interrupt request signals (inttaancc0 and inttaancc1) are masked by the interrupt mask flags (taanccmk0 and taanccmk1) and timer output (toaan1) is performed. however, set the taanccr0 and taanccr1 registers to the same value (see 7.5.1 (2) (d) operation of taanccr1 register ). remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 261 of 1817 sep 19, 2011 figure 7-9. register settings for in terval timer mode operation (2/2) (c) taan i/o control register 0 (taanioc0) 0 0 0 0 0/1 taanioc0 0: disables toaan0 pin output 1: enables toaan0 pin output setting of output level with operation of toaan0 pin disabled 0: low level 1: high level 0: disables toaan1 pin output 1: enables toaan1 pin output setting of output level with operation of toaan1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 taanoe1 taanol0 taanoe0 taanol1 (d) taan counter read buffer register (taancnt) by reading the taancnt regist er, the count value of the 16-bit counter can be read. (e) taan capture/compare register 0 (taanccr0) if the taanccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) taan capture/compare register 1 (taanccr1) usually, the taanccr1 register is not used in the in terval timer mode. however, the set value of the taanccr1 register is transferred to the ccr1 buffer register. a compare match interrupt request signal (inttaancc1) is generated when the count value of t he 16-bit counter matches the value of the ccr1 buffer register. therefore, mask the interrupt request by using the corresponding interrupt mask flag (taanccmk1). remarks 1. taan i/o control register 1 (taanioc1), taan i/o control register 2 (taanioc2), and taan option register 0 (taanopt0) are not used in the interval timer mode. 2. n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 262 of 1817 sep 19, 2011 (1) interval timer mode operation flow figure 7-10. software processing flow in interval timer mode ffffh 16-bit counter 0000h taance bit taanccr0 register toaan0 pin output inttaancc0 signal d 0 d 0 d 0 d 0 <1> <2> taance bit = 1 taance bit = 0 register initial setting taanctl0 register (taancks0 to taancks2 bits), taanctl1 register, taanioc0 register, taanccr0 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting has been started (taance bit = 1). the counter is initialized and counting is stopped by clearing the taance bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 263 of 1817 sep 19, 2011 (2) interval timer mode operation timing (a) operation if taanccr0 register is set to 0000h if the taanccr0 register is set to 0000h, the in ttaancc0 signal is generated at each count clock subsequent to the first count clock, and t he output of the toaan0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter taance bit taanccr0 register toaan0 pin output inttaancc0 signal 0000h interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 264 of 1817 sep 19, 2011 (b) operation if taanccr0 register is set to ffffh if the taanccr0 register is set to ffffh, the 16-bit counter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing . the inttaancc0 signal is generated and the output of the toaan0 pin is inverted. at this time, an overfl ow interrupt request signal (inttaanov) is not generated, nor is the overflow flag (taanopt0.taanovf bit) set to 1. ffffh 16-bit counter 0000h taance bit taanccr0 register toaan0 pin output inttaancc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 265 of 1817 sep 19, 2011 (c) notes on rewriting taanccr0 register to change the value of the taanccr0 register to a sm aller value, stop counting once and then change the set value. if the value of the taanccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h taance bit taanccr0 register taanol0 bit toaan0 pin output inttaancc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0 to 5 if the value of the taanccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the taanccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttaancc0 signal is generated and the output of the toaan0 pin is inverted. therefore, the inttaancc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? as originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 266 of 1817 sep 19, 2011 (d) operation of taanccr1 register figure 7-11. configuration of taanccr1 register ccr0 buffer register taanccr0 register taanccr1 register ccr1 buffer register toaan0 pin inttaancc0 signal toaan1 pin inttaancc1 signal 16-bit counter output controller taance bit count clock selection clear match signal output controller match signal remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 267 of 1817 sep 19, 2011 if the set value of the taanccr1 register is less than the set value of the taanccr0 register, the inttaancc1 signal is generated once per cycle. at the same time, the output of the toaan1 pin is inverted. the toaan1 pin outputs a square wave with the same cycle as that output by the toaan0 pin. figure 7-12. timing chart when d 01 d 11 ffffh 16-bit counter 0000h taance bit taanccr0 register toaan0 pin output inttaancc0 signal taanccr1 register toaan1 pin output inttaancc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 268 of 1817 sep 19, 2011 if the set value of the taanccr1 register is greater than the set value of the t aanccr0 register, the count value of the 16-bit counter does not match the value of the taan ccr1 register. consequently, the inttaancc1 signal is not generated, nor is the output of the toaan1 pin changed. figure 7-13. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h taance bit taanccr0 register toaan0 pin output inttaancc0 signal taanccr1 register toaan1 pin output inttaancc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 269 of 1817 sep 19, 2011 7.5.2 external event count mode (taanmd2 to taanmd0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the taanctl0.taance bit is set to 1, and an interrupt request signal (inttaancc0) is generated each time the specified number of edges have been counted. the toaan0 pin cannot be used. usually, the taanccr1 register is not used in the external event count mode. figure 7-14. configuration in external event count mode 16-bit counter ccr0 buffer register taance bit taanccr0 register edge detector clear match signal inttaancc0 signal tiaan0 pin (external event count input) remark n = 0 to 5 figure 7-15. basic timing in external event count mode ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal d 0 d 0 d 0 d 0 16-bit counter taanccr0 register inttaancc0 signal external event count input (tiaan0 pin input) d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) remarks 1. this figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. 2. n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 270 of 1817 sep 19, 2011 when the taance bit is set to 1, the value of the 16-bit c ounter is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is dete cted. additionally, the set value of the taanccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttaancc0) is generated. the inttaancc0 signal is generated each time the valid edge of the external event count input has been detected (set value of taanccr0 register + 1) times. figure 7-16. register setting for operati on in external event count mode (1/2) (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 0: stops counting 1: enables counting 000 taancks2 taancks1 taancks0 taance (b) taan control register 1 (taanctl1) 00000 taanctl1 0, 0, 1: external event count mode 001 taanmd2 taanmd1 taanmd0 taaneee taanest (c) taan i/o control register 0 (taanioc0) 00000 taanioc0 0: disables toaan0 pin output 0: disables toaan1 pin output 000 taanoe1 taanol0 taanoe0 taanol1 (d) taan i/o control register 2 (taanioc2) 0 0 0 0 0/1 taanioc2 select valid edge of external event count input 0/1 0 0 taanees0 taanets1 taanets0 taanees1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 271 of 1817 sep 19, 2011 figure 7-16. register setting for operati on in external event count mode (2/2) (e) taan counter read buffer register (taancnt) the count value of the 16-bit counter can be read by reading the taancnt register. (f) taan capture/compare register 0 (taanccr0) if d 0 is set to the taanccr0 register, the counter is cleared and a compare match interrupt request signal (inttaancc0) is generated when the num ber of external event counts reaches (d 0 + 1). (g) taan capture/compare register 1 (taanccr1) usually, the taanccr1 register is not used in the exte rnal event count mode. however, the set value of the taanccr1 register is transferred to the ccr1 buff er register. when the count value of the 16-bit counter matches the value of the ccr1 buffer re gister, a compare match interrupt request signal (inttaancc1) is generated. therefore, mask the interrupt signal by using the interrupt mask flag (taanccmk1). caution when an external clock is used as the count clock, the external clock can be input only from the tiaan0 pin. at this time, set the taanioc1.taanis1 and taanioc1.taanis0 bits to 00 (capture trigger input (tiaan0 pin): no edge detection). remarks 1. taan i/o control register 1 (taanioc1) and taan option register 0 (taanopt0) are not used in the external event count mode. 2. n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 272 of 1817 sep 19, 2011 (1) external event count mode operation flow figure 7-17. flow of software processing in external event count mode ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal d 0 d 0 d 0 d 0 <1> <2> taance bit = 1 taance bit = 0 register initial setting taanctl0 register (taancks0 to taancks2 bits), taanctl1 register, taanioc0 register, taanioc2 register, taanccr0 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting has been started (taance bit = 1). the counter is initialized and counting is stopped by clearing the taance bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 273 of 1817 sep 19, 2011 (2) operation timing in external event count mode cautions 1. in the external event count mode , do not set the taanc cr0 register to 0000h. 2. in the external event count mode, use of th e timer output is disabled. if performing timer output using external event count input, set th e interval timer mode, and select the operation of the count clock to be enabled by the ex ternal event count inpu t (taanctl1.taanmd2 to taanctl1.taanmd0 bits = 000, taanctl1.taaneee bit = 1). (a) operation if taanccr0 register is set to ffffh if the taanccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-b it counter is cleared to 0000h in synchronization with the next count-up timing, and the inttaancc0 signal is generated. at this time, the taanopt0.taanovf bit is not set. ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 274 of 1817 sep 19, 2011 (b) notes on rewriting the taanccr0 register to change the value of the taanccr0 register to a sm aller value, stop counting once and then change the set value. if the value of the taanccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) remark n = 0 to 5 if the value of the taanccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the taanccr0 register has been rewritten. consequently, the value that is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttaancc0 signal is generated. therefore, the inttaancc0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? as originally expected, but may be ge nerated at the valid edge count of ?(10000h + d 2 + 1) times?. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 275 of 1817 sep 19, 2011 (c) operation of taanccr1 register figure 7-18. configuration of taanccr1 register ccr0 buffer register taance bit taanccr0 register 16-bit counter taanccr1 register ccr1 buffer register clear match signal match signal inttaancc0 signal inttaancc1 signal edge detector tiaan0 pin remark n = 0 to 5 if the set value of the taanccr1 register is smalle r than the set value of the taanccr0 register, the inttaancc1 signal is generated once per cycle. figure 7-19. timing chart when d 01 d 11 ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal taanccr1 register inttaancc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 276 of 1817 sep 19, 2011 if the set value of the taanccr1 register is greate r than the set value of the taanccr0 register, the inttaancc1 signal is not generated because the count value of the 16-bit counter and the value of the taanccr1 register do not match. figure 7-20. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal taanccr1 register inttaancc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 277 of 1817 sep 19, 2011 7.5.3 external trigger pulse output m ode (taanmd2 to taanmd0 bits = 010) in the external trigger pulse output mode, 16-bit timer/ev ent counter aa waits for a tri gger when the taanctl0.taance bit is set to 1. when the valid edge of an external trigger input signal is detected, 16-bit timer/event counter aa starts counting, and outputs a pwm wave form from the toaan1 pin. pulses can also be output by generating a software trigger inst ead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the toaan0 pin. figure 7-21. configuration in external trigger pulse output mode ccr0 buffer register taance bit taanccr0 register 16-bit counter taanccr1 register ccr1 buffer register clear match signal match signal inttaancc0 signal output controller (rs-ff) output controller toaan1 pin inttaancc1 signal toaan0 pin count clock selection count start control edge detector software trigger generation tiaan0 pin transfer transfer s r remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 278 of 1817 sep 19, 2011 figure 7-22. basic timing in exte rnal trigger pulse output mode ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal taanccr1 register inttaancc1 signal toaan1 pin output external trigger input (tiaan0 pin input) toaan0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) 16-bit timer/event counter aa waits for a trigger when the taance bit is set to 1. when the trigger is generated, the 16- bit counter is cleared from ffffh to 0000h, starts countin g at the same time, and outputs a pwm waveform from the toaan1 pin. if the trigger is generated again while the counter is operating, the counter is cleared to 0000h and restarted. (the output of the toaan0 pin is inverted. the toaan1 pin outputs a high level regard less of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of taanccr1 register) count clock cycle cycle = (set value of taanccr0 register + 1) count clock cycle duty factor = (set value of taanccr1 regist er)/(set value of taanccr0 register + 1) the compare match request signal inttaancc0 is generated t he next time the 16-bit counter counts after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h at the same time. the compare match interrupt request signal inttaancc1 is generat ed when the count value of t he 16-bit counter matches the value of the ccr1 buffer register. the value set to the taanccrm register is transferred to t he ccrm buffer register when the count value of the 16-bit counter matches the value of the ccrm buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal, or setting the software trigger (taanctl1.taanest bit) to 1 is used as the trigger. remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 279 of 1817 sep 19, 2011 figure 7-23. setting of registers in exte rnal trigger pulse output mode (1/2) (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 select count clock 0: stops counting 1: enables counting 0/1 0/1 0/1 taancks2 taancks1 taancks0 taance (b) taan control register 1 (taanctl1) 0 0/1 0 0 0 taanctl1 generates software trigger when 1 is written 010 taanmd2 taanmd1 taanmd0 taanest taaneee 0, 1, 0: external trigger pulse output mode (c) taan i/o control register 0 (taanioc0) 0 0 0 0 0/1 taanioc0 0: disables toaan0 pin output 1: enables toaan0 pin output sets output level while operation of toaan0 pin is disabled 0: low level 1: high level 0: disables toaan1 pin output 1: enables toaan1 pin output specifies active level of toaan1 pin output 0: active-high 1: active-low 0/1 0/1 note 0/1 note taanoe1 taanol0 taanoe0 taanol1 toaan1 pin output 16-bit counter ? when taanol1 bit = 0 toaan1 pin output 16-bit counter ? when taanol1 bit = 1 note clear this bit to 0 when the toaan0 pin is not used in the external trigger pulse output mode. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 280 of 1817 sep 19, 2011 figure 7-23. setting of registers in exte rnal trigger pulse output mode (2/2) (d) taan i/o control register 2 (taanioc2) 00000 taanioc2 select valid edge of external trigger input 0 0/1 0/1 taanets1 taanets0 taanees1 taanees0 (e) taan counter read buffer register (taancnt) the value of the 16-bit counter can be read by reading the taancnt register. (f) taan capture/compare registers 0 and 1 (taanccr0 and taanccr1) if d 0 is set to the taanccr0 register and d 1 to the taanccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. taan i/o control register 1 (taanioc1) and taan option register 0 (taanopt0) are not used in the external trigger pulse output mode. 2. n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 281 of 1817 sep 19, 2011 (1) operation flow in extern al trigger pulse output mode figure 7-24. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h taance bit taanccr0 register ccr0 buffer register inttaancc0 signal taanccr1 register ccr1 buffer register inttaancc1 signal toaan1 pin output external trigger input (tiaan0 pin input) toaan0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 282 of 1817 sep 19, 2011 figure 7-24. software processing flow in ex ternal trigger pulse output mode (2/2) taance bit = 1 setting of taanccr0 register register initial setting taanctl0 register (taancks0 to taancks2 bits), taanctl1 register, taanioc0 register, taanioc2 register, taanccr0 register, taanccr1 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting is enabled (taance bit = 1). trigger wait status taanccr1 register write processing is necessary only when the set cycle is changed. when the counter is cleared after setting, the values of the taanccrm register are transferred to the ccrm buffer register in a batch. start setting of taanccr1 register <1> count operation start flow <2> taanccr0 and taanccr1 register setting change flow setting of taanccr0 register when the counter is cleared after setting, the values of the taanccrm register are transferred to the ccrm buffer register in a batch. setting of taanccr1 register <4> taanccr0, taanccr1 register setting change flow only writing of the taanccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the taanccrm register is transferred to the ccrm buffer register. setting of taanccr1 register <3> taanccr0, taanccr1 register setting change flow taance bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 283 of 1817 sep 19, 2011 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the taanccr1 register last. rewrite the taanccrm register after writing the taanccr 1 register after the inttaancc0 signal is detected. remark n = 0 to 5 m = 0, 1 ffffh 16-bit counter 0000h taance bit taanccr0 register ccr0 buffer register inttaancc0 signal taanccr1 register ccr1 buffer register inttaancc1 signal toaan1 pin output external trigger input (tiaan0 pin input) toaan0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 284 of 1817 sep 19, 2011 in order to transfer data from the taanccrm register to the ccrm buffer register, the taanccr1 register must be written. to change both the cycle and active level width of the pw m waveform at this time, first set the cycle to the taanccr0 register and then set the active level width to the taanccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the taanccr0 register, and then write the same value to the taanccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the taanccr1 register has to be set. after data is written to the taanccr1 register, the value written to the taanccrm register is transferred to the ccrm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the taanccr0 or taanccr1 register again after writing the taanccr1 register once, do so after the inttaancc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the taanccrm register to the ccrm buff er register conflicts with writing the taanccrm register. remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 285 of 1817 sep 19, 2011 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the taanccr1 register to 0000h. if the set value of the taanccr0 register is ffffh, the inttaancc1 signal is generated periodically. count clock 16-bit counter taance bit taanccr0 register taanccr1 register inttaancc0 signal inttaancc1 signal toaan1 pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 5 to output a 100% waveform, set a value of (set value of taanccr0 register + 1) to the taanccr1 register. if the set value of the taan ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter taance bit taanccr0 register taanccr1 register inttaancc0 signal inttaancc1 signal toaan1 pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 286 of 1817 sep 19, 2011 (c) conflict between trigger detecti on and match with taanccr1 register if the trigger is detected immediately after the inttaancc1 signal is generated, the 16-bit counter is cleared to 0000h at the same time, the output signal of the toaa n1 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter taanccr1 register inttaancc1 signal toaan1 pin output external trigger input (tiaan0 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened remark n = 0 to 5 if the trigger is detected immediately before the intt aancc1 signal is generated, the inttaancc1 signal is not generated, and the 16-bit counter is cleared to 00 00h and continues counting. the output signal of the toaan1 pin remains active. consequently, the acti ve period of the pwm waveform is extended. 16-bit counter taanccr1 register inttaancc1 signal toaan1 pin output external trigger input (tiaan0 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 287 of 1817 sep 19, 2011 (d) conflict between trigger detecti on and match with taanccr0 register if the trigger is detected immediately after the inttaancc0 signal is generated, the 16-bit counter is cleared to 0000h again and continues counting up. therefore, t he active period of the toaan1 pin is extended by the time from generation of the inttaancc0 signal to trigger detection. 16-bit counter taanccr0 register inttaancc0 signal toaan1 pin output external trigger input (tiaan0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark n = 0 to 5 if the trigger is detected immediately before the intt aancc0 signal is generated, the inttaancc0 signal is not generated. the 16-bit counter is cleared to 0000h, the toaan1 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter taanccr0 register inttaancc0 signal toaan1 pin output external trigger input (tiaan0 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 288 of 1817 sep 19, 2011 (e) generation timing of compare match interrupt request signal (inttaancc1) the timing of generation of the inttaancc1 signal in th e external trigger pulse output mode differs from the timing of other inttaancc1 signals; the inttaancc1 signal in the external trigger pulse output mode is generated when the count value of the 16-bit counter matches the va lue of the taanccr1 register. count clock 16-bit counter taanccr1 register toaan1 pin output inttaancc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttaancc1 signal is generated in synchroniz ation with the next count-up, after the count value of the 16-bit counter matches the va lue of the taanccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of changin g the output signal of the toaan1 pin. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 289 of 1817 sep 19, 2011 7.5.4 one-shot pulse output mode (taanmd2 to taanmd0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter aa waits for a trigger when the taanctl0.taance bit is set to 1. when the valid edge of an external trigger input is detected, 16-bit timer/event counter aa starts counting, and outputs a one-shot pulse from the toaan1 pin. instead of the external trigger, a software trigger can al so be generated to output the pulse. when the software trigger is used, the toaan0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 7-25. configuration in one-shot pulse output mode ccr0 buffer register taance bit taanccr0 register taanccr1 register ccr1 buffer register clear match signal match signal inttaancc0 signal output controller (rs-ff) toaan1 pin inttaancc1 signal toaan0 pin count clock selection count start control edge detector software trigger generation tiaan0 pin transfer transfer s r output controller (rs-ff) s r 16-bit counter remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 290 of 1817 sep 19, 2011 figure 7-26. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal taanccr1 register inttaancc1 signal toaan1 pin output external trigger input (tiaan0 pin input) toaan0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) delay (d 1 ) delay (d 1 ) active level width (d 0 ? d 1 + 1) active level width (d 0 ? d 1 + 1) active level width (d 0 ? d 1 + 1) when the taance bit is set to 1, 16-bit timer/event counter aa waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting, and outputs a one-shot pulse from the toaan1 pin. after the one-shot pulse is output, t he 16-bit counter is set to ffffh, stops counting, and waits for a trigger. if a trigger is generated again while the one-shot pul se is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of taanccr1 register) count clock cycle active level width = (set value of taanccr0 register ? set value of taanccr1 register + 1) count clock cycle the compare match interrupt request signal inttaancc0 is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal inttaancc1 is generated when the count value of the 16-bit counter matches the val ue of the ccr1 buffer register. the valid edge of an external trigger input or setting the so ftware trigger (taanctl1.taanest bit) to 1 is used as the trigger. remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 291 of 1817 sep 19, 2011 figure 7-27. register setting for operati on in one-shot pulse output mode (1/2) (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 select count clock 0: stops counting 1: enables counting 0/1 0/1 0/1 taancks2 taancks1 taancks0 taance (b) taan control register 1 (taanctl1) 0 0/1 0 0 0 taanctl1 generates software trigger when 1 is written 011 taanmd2 taanmd1 taanmd0 taanest taaneee 0, 1, 1: one-shot pulse output mode (c) taan i/o control register 0 (taanioc0) 0 0 0 0 0/1 taanioc0 0: disables toaan0 pin output 1: enables toaan0 pin output sets output level while operation of toaan0 pin is disabled 0: low level 1: high level 0: disables toaan1 pin output 1: enables toaan1 pin output specifies active level of toaan1 pin output 0: active-high 1: active-low 0/1 0/1 note 0/1 note taanoe1 taanol0 taanoe0 taanol1 toaan1 pin output 16-bit counter ? when taanol1 bit = 0 toaan1 pin output 16-bit counter ? when taanol1 bit = 1 note clear this bit to 0 when the toaan0 pin is not used in the one-shot pulse output mode. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 292 of 1817 sep 19, 2011 figure 7-27. register setting for operati on in one-shot pulse output mode (2/2) (d) taan i/o control register 2 (taanioc2) 00000 taanioc2 select valid edge of external trigger input 0 0/1 0/1 taanets1 taanets0 taanees1 taanees0 (e) taan counter read buffer register (taancnt) the value of the 16-bit counter can be read by reading the taancnt register. (f) taan capture/compare registers 0 and 1 (taanccr0 and taanccr1) if d 0 is set to the taanccr0 register and d 1 to the taanccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d 1 + 1) count clock cycle output delay period = (d 1 ) count clock cycle caution one-shot pulses are not output even in the one-shot pulse out put mode, if the set value of the taanccr1 register is greater th an the set value of the taanccr0 register. remarks 1. taan i/o control register 1 (taanioc1) and taan option register 0 (taanopt0) are not used in the one-shot pulse output mode. 2. n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 293 of 1817 sep 19, 2011 (1) operation flow in one-shot pulse output mode figure 7-28. software processing flow in one-shot pulse output mode ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal taanccr1 register inttaancc1 signal toaan1 pin output external trigger input (tiaan0 pin input) <1> <3> taance bit = 1 register initial setting taanctl0 register (taancks0 to taancks2 bits), taanctl1 register, taanioc0 register, taanioc2 register, taanccr0 register, taanccr1 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting has been started (taance bit = 1). trigger wait status start <1> count operation start flow taance bit = 0 count operation is stopped stop <3> count operation stop flow d 10 d 00 d 11 d 01 d 00 d 10 d 11 <2> d 01 setting of taanccr0, taanccr1 registers as rewriting the taanccrm register immediately forwards to the ccrm buffer register, rewriting immediately after the generation of the inttaanccr0 signal is recommended. <2> taanccr0, taanccr1 register setting change flow remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 294 of 1817 sep 19, 2011 (2) operation timing in one-shot pulse output mode (a) note on rewriting taanccrm register to change the set value of the taanccrm register to a smaller value, stop counting once, and then change the set value. if the value of the taanccrm register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal taanccr1 register inttaancc1 signal toaan1 pin output external trigger input (tiaan0 pin input) toaan0 pin output (only when software trigger is used) d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 delay (d 10 ) delay (d 10 ) active level width (d 00 ? d 10 + 1) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) when the taanccr0 register is rewritten from d 00 to d 01 and the taanccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the taanccr1 register is rewritten wh en the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the taanccr0 register is rewr itten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter c ounts up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the inttaancc1 signal and asserts the toaan1 pin. when the count value matches d 01 , the counter generates the inttaancc0 signal, deasserts the toaan1 pin, and stops counting. therefore, the counter may output a pu lse with a delay period or active per iod different from that of the one- shot pulse that is originally expected. remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 295 of 1817 sep 19, 2011 (b) generation timing of compare match interrupt request signal (inttaancc1) the generation timing of the inttaancc1 signal in the one-shot pulse output mode is different from other inttaancc1 signals; the inttaancc1 signal in the one- shot pulse output mode is generated when the count value of the 16-bit counter matches the value of the taanccr1 register. count clock 16-bit counter taanccr1 register toaan1 pin output inttaancc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttaancc1 signal is generated the next ti me the 16-bit counter counts after its count value matches the value of the taanccr1 register. in the one-shot pulse output mode, however, it is gene rated one clock earlier. this is because the timing is changed to match the change timing of the toaan1 pin. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 296 of 1817 sep 19, 2011 7.5.5 pwm output mode (taanmd 2 to taanmd0 bits = 100) in the pwm output mode, a pwm waveform is output from t he toaan1 pin when the taanctl0.taance bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the toaan0 pin. figure 7-29. configuration in pwm output mode ccr0 buffer register taanccr0 register 16-bit counter taanccr1 register ccr1 buffer register clear match signal match signal inttaancc0 signal output controller (rs-ff) output controller toaan1 pin inttaancc1 signal toaan0 pin taance bit count clock selection transfer transfer s r remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 297 of 1817 sep 19, 2011 figure 7-30. basic timing in pwm output mode ffffh 16-bit counter 0000h taance bit taanccr0 register ccr0 buffer register inttaancc0 signal toaan0 pin output taanccr1 register ccr1 buffer register inttaancc1 signal toaan1 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 ? d 10 + 1) when the taance bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, st arts counting, and outputs a pwm waveform from the toaan1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of taanccr1 register) count clock cycle cycle = (set value of taanccr0 register + 1) count clock cycle duty factor = (set value of taanccr1 regist er)/(set value of taanccr0 register + 1) the pwm waveform can be changed by rewriting the taanccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the va lue of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal inttaancc0 is gene rated the next time the 16-bit counter counts after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is clear ed to 0000h. the compare match interrupt request signal inttaancc1 is generated when the count value of the 16-bit c ounter matches the value of the ccr1 buffer register. the value set to the taanccrm register is transferred to t he ccrm buffer register when the count value of the 16-bit counter matches the value of the ccrm buffer regi ster and the 16-bit counter is cleared to 0000h. remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 298 of 1817 sep 19, 2011 figure 7-31. setting of registers in pwm output mode (1/2) (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 select count clock note 1 0: stops counting 1: enables counting 0/1 0/1 0/1 taancks2 taancks1 taancks0 taance (b) taan control register 1 (taanctl1) 0 0 0/1 0 0 taanctl1 100 taanmd2 taanmd1 taanmd0 taaneee taanest 1, 0, 0: pwm output mode 0: operates on count clock selected by taancks0 to taancks2 bits 1: counts external event input signal (c) taan i/o control register 0 (taanioc0) 0 0 0 0 0/1 taanioc0 0: disables toaan0 pin output 1: enables toaan0 pin output sets output level while operation of toaan0 pin is disabled 0: low level 1: high level 0: disables toaan1 pin output 1: enables toaan1 pin output specifies active level of toaan1 pin output 0: active-high 1: active-low 0/1 0/1 note 2 0/1 note 2 taanoe1 taanol0 taanoe0 taanol1 toaan1 pin output 16-bit counter ? when taanol1 bit = 0 toaan1 pin output 16-bit counter ? when taanol1 bit = 1 notes 1. the setting is invalid when the taanctl1.taaneee bit = 1. 2. clear this bit to 0 when the toaan0 pin is not used in the pwm output mode. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 299 of 1817 sep 19, 2011 figure 7-31. setting of registers in pwm output mode (2/2) (d) taan i/o control register 2 (taanioc2) 0 0 0 0 0/1 taanioc2 select valid edge of external event count input. 0/1 0 0 taanees0 taanets1 taanets0 taanees1 (e) taan counter read buffer register (taancnt) the value of the 16-bit counter can be read by reading the taancnt register. (f) taan capture/compare registers 0 and 1 (taanccr0 and taanccr1) if d 0 is set to the taanccr0 register and d 1 to the taanccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. taan i/o control register 1 (taanioc1) and taan option register 0 (taanopt0) are not used in the pwm output mode. 2. n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 300 of 1817 sep 19, 2011 (1) operation flow in pwm output mode figure 7-32. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h taance bit taanccr0 register ccr0 buffer register inttaancc0 signal toaan0 pin output taanccr1 register ccr1 buffer register inttaancc1 signal toaan1 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <2> <3> <4> <5> <1> remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 301 of 1817 sep 19, 2011 figure 7-32. software processing flow in pwm output mode (2/2) taance bit = 1 setting of taanccr0 register register initial setting taanctl0 register (taancks0 to taancks2 bits), taanctl1 register, taanioc0 register, taanioc2 register, taanccr0 register, taanccr1 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting is enabled (taance bit = 1). taanccr1 write processing is necessary even if only the set cycle is changed. when the counter is cleared after setting, the values of the taanccrm register are transferred to the ccrm buffer register in a batch. start setting of taanccr1 register <1> count operation start flow <2> taanccr0, taanccr1 register setting change flow setting of taanccr0 register when the counter is cleared after setting, the values of compare register m are transferred to the ccrm buffer register in a batch. setting of taanccr1 register <4> taanccr0, taanccr1 register setting change flow only writing of the taanccr1 register must be performed when only the set duty factor is changed. when the counter is cleared after setting, the value of compare register m is transferred to the ccrm buffer register. setting of taanccr1 register <3> taanccr0, taanccr1 register setting change flow taance bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 302 of 1817 sep 19, 2011 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the taanccr1 register last. rewrite the taanccrm register after writing the taanccr 1 register after the inttaancc1 signal is detected. ffffh 16-bit counter 0000h taance bit taanccr0 register ccr0 buffer register taanccr1 register ccr1 buffer register toaan1 pin output inttaancc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the taanccrm register to the ccrm buffer register, the taanccr1 register must be written. to change both the cycle and active leve l of the pwm waveform at this time, first set the cycle to the taanccr0 register and then set the active level to the taanccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the taanccr0 register, and then write the same value to the taanccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the taanccr1 register has to be set. after data is written to the taanccr1 register, the value written to the taanccrm register is transferred to the ccrm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the taanccr0 or taanccr1 register again after writing the taanccr1 register once, do so after the inttaancc0 signal is generated. otherwise, the value of the ccrm buffer register may become undefined because the timing of transferring data from the taanccrm register to the ccrm buff er register conflicts with writing the taanccrm register. remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 303 of 1817 sep 19, 2011 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the taanccr1 register to 0000h. if the set value of the taanccr0 register is ffffh, the inttaancc1 signal is generated periodically. count clock 16-bit counter taance bit taanccr0 register taanccr1 register inttaancc0 signal inttaancc1 signal toaan1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 5 to output a 100% waveform, set a value of (set value of taanccr0 register + 1) to the taanccr1 register. if the set value of the taan ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter taance bit taanccr0 register taanccr1 register inttaancc0 signal inttaancc1 signal toaan1 pin output d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 304 of 1817 sep 19, 2011 (c) generation timing of compare match interrupt request signal (inttaancc1) the timing of generation of the inttaancc1 signal in the pwm output mode differs from the timing of other inttaancc1 signals; the inttaancc1 signal in the pw m output mode is generated when the count value of the 16-bit counter matches the va lue of the taanccr1 register. count clock 16-bit counter taanccr1 register toaan1 pin output inttaancc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 5 usually, the inttaancc1 signal is generated in synchroni zation with the next count-up after the count value of the 16-bit counter matches the va lue of the taanccr1 register. in the pwm output mode, however, it is generated one cl ock earlier. this is because the timing is changed to match the change timing of the out put signal of the toaan1 pin. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 305 of 1817 sep 19, 2011 7.5.6 free-running timer mode (taanmd2 to taanmd0 bits = 101) in the free-running timer mode, 16-bit timer/event counter aa starts counting when the taanctl0.taance bit is set to 1. at this time, the taanccrm register can be used as a co mpare register or a capture register, depending on the setting of the taanopt0.taanccs0 and taanopt0.taanccs1 bits. figure 7-33. configuration in free-running timer mode taanccr0 register (capture) taance bit taanccr1 register (capture) 16-bit counter taanccr1 register (compare) taanccr0 register (compare) output controller taanccs0, taanccs1 bits (capture/compare selection) toaan0 pin output output controller toaan1 pin output edge detector count clock selection edge detector edge detector tiaan0 pin (external event count input/ capture trigger input) tiaan1 pin (capture trigger input) internal count clock 0 1 0 1 inttaanov signal inttaancc1 signal inttaancc0 signal remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 306 of 1817 sep 19, 2011 when the taance bit is set to 1, 16-bit timer/event counter aa starts counting, and the output signals of the toaan0 and toaan1 pins are inverted. when the count value of the 16- bit counter later matches the set value of the taanccrm register, a compare match interrupt request signal (inttaan ccm) is generated, and the output signal of the toaanm pin is inverted. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttaanov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (taanopt0.taanovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the taanccrm register can be rewritten while the counter is operating. if it is re written, the new value is reflected at that time, and compared with the count value. figure 7-34. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal toaan0 pin output taanccr1 register inttaancc1 signal toaan1 pin output inttaanov signal taanovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 307 of 1817 sep 19, 2011 when the taance bit is set to 1, the 16 -bit counter starts counting. when t he valid edge input to the tiaanm pin is detected, the count val ue of the 16-bit counter is stor ed in the taanccrm register, and a capture interrupt request signal (inttaanccm) is generated. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttaanov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (taanopt0.taanovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. figure 7-35. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h taance bit tiaan0 pin input taanccr0 register inttaancc0 signal tiaan1 pin input taanccr1 register inttaancc1 signal inttaanov signal taanovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 308 of 1817 sep 19, 2011 figure 7-36. register setting in free-running timer mode (1/2) (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 select count clock note 0: stops counting 1: enables counting 0/1 0/1 0/1 taancks2 taancks1 taancks0 taance note the setting is invalid when the taanctl1.taaneee bit = 1 (b) taan control register 1 (taanctl1) 0 0 0/1 0 0 taanctl1 101 taanmd2 taanmd1 taanmd0 taaneee taanest 1, 0, 1: free-running mode 0: operates with count clock selected by taancks0 to taancks2 bits 1: counts on external event count input signal (c) taan i/o control register 0 (taanioc0) 0 0 0 0 0/1 taanioc0 0: disables toaan0 pin output 1: enables toaan0 pin output sets output level with operation of toaan0 pin disabled 0: low level 1: high level 0: disables toaan1 pin output 1: enables toaan1 pin output sets output level with operation of toaan1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 taanoe1 taanol0 taanoe0 taanol1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 309 of 1817 sep 19, 2011 figure 7-36. register setting in free-running timer mode (2/2) (d) taan i/o control register 1 (taanioc1) 0 0 0 0 0/1 taanioc1 select valid edge of tiaan0 pin input select valid edge of tiaan1 pin input 0/1 0/1 0/1 taanis2 taanis1 taanis0 taanis3 (e) taan i/o control register 2 (taanioc2) 0 0 0 0 0/1 taanioc2 select valid edge of external event count input 0/1 0 0 taanees0 taanets1 taanets0 taanees1 (f) taan option register 0 (taanopt0) 0 0 0/1 0/1 0 taanopt0 overflow flag specifies if taanccr0 register functions as capture or compare register specifies if taanccr1 register functions as capture or compare register 0 0 0/1 taanccs0 taanovf taanccs1 (g) taan counter read buffer register (taancnt) the value of the 16-bit counter can be read by reading the taancnt register. (h) taan capture/compare regist ers 0 and 1 (taanccr0 and taanccr1) these registers function as capture registers or compare regi sters depending on the setting of the taanopt0.taanccsm bit. when the registers function as capture registers, they store the c ount value of the 16-bit counter when the valid edge input to the tiaanm pin is detected. when the registers function as compare registers and when d m is set to the taanccrm register, the inttaanccm signal is generated when the counter reaches (d m + 1), and the output signal of the toaanm pin is inverted. remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 310 of 1817 sep 19, 2011 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 7-37. software processing flow in fr ee-running timer mode (c ompare function) (1/2) ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal toaan0 pin output taanccr1 register inttaancc1 signal toaan1 pin output inttaanov signal taanovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction set value changed cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> set value changed remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 311 of 1817 sep 19, 2011 figure 7-37. software processing flow in fr ee-running timer mode (c ompare function) (2/2) taance bit = 1 read taanopt0 register (check overflow flag). register initial setting taanctl0 register (taancks0 to taancks2 bits), taanctl1 register, taanioc0 register, taanioc2 register, taanopt0 register, taanccr0 register, taanccr1 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting has been started (taance bit = 1). start execute instruction to clear taanovf bit (clr taanovf). <1> count operation start flow <2> overflow flag clear flow taance bit = 0 counter is initialized and counting is stopped by clearing taance bit to 0. stop <3> count operation stop flow taanovf bit = 1 no yes remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 312 of 1817 sep 19, 2011 (b) when using capture/compare register as capture register figure 7-38. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h taance bit tiaan0 pin input taanccr0 register inttaancc0 signal tiaan1 pin input taanccr1 register inttaancc1 signal inttaanov signal taanovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 313 of 1817 sep 19, 2011 figure 7-38. software processing flow in fr ee-running timer mode (c apture function) (2/2) taance bit = 1 read taanopt0 register (check overflow flag). register initial setting taanctl0 register (taancks0 to taancks2 bits), taanctl1 register, taanioc1 register, taanopt0 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting has been started (taance bit = 1). start execute instruction to clear taanovf bit (clr taanovf). <1> count operation start flow <2> overflow flag clear flow taance bit = 0 counter is initialized and counting is stopped by clearing taance bit to 0. stop <3> count operation stop flow taanovf bit = 1 no yes remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 314 of 1817 sep 19, 2011 (2) operation timing in free-running timer mode (a) interval operation with taanccrm re gister used as compare register when 16-bit timer/event counter aa is used as an inte rval timer with the taanccrm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttaanccm signal has been detected. ffffh 16-bit counter 0000h taance bit taanccr0 register inttaancc0 signal toaan0 pin output taanccr1 register inttaancc1 signal toaan1 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the corresponding taanccrm register must be re-set in the interrupt servicing that is executed when the inttaanccm signal is detected. the set value for re-setting the taanccrm register c an be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent times: previous set value + d m (if the calculation resu lt is greater than ffffh, subtract 10000h fr om the result and set this value to the register.) remark m = 0, 1 n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 315 of 1817 sep 19, 2011 (b) pulse width measurement with t aanccrm used as capture register when pulse width measurement is performed with the taanccrm register used as a capture register, software processing is necessary for reading the captur e register each time the inttaanccm signal has been detected and for calculating the interval. ffffh 16-bit counter 0000h taance bit tiaan0 pin input taanccr0 register inttaancc0 signal tiaan1 pin input taanccr1 register inttaancc1 signal inttaanov signal taanovf bit 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 pulse interval (d 00 ) pulse interval (10000h + d 01 ? d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calculat ed by reading the value of the taanccrm register in synchronization with the inttaanccm signal, and calc ulating the difference between the read value and the previously read value. remark m = 0, 1 n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 316 of 1817 sep 19, 2011 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h taance bit tiaan0 pin input taanccr0 register tiaan1 pin input taanccr1 register inttaanov signal taanovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the taanccr0 register (setting of t he default value of the tiaan0 pin input). <2> read the taanccr1 register (setting of t he default value of the tiaan1 pin input). <3> read the taanccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the taanccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtai n the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 317 of 1817 sep 19, 2011 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h taance bit inttaanov signal taanovf bit taanovf0 flag note tiaan0 pin input taanccr0 register taanovf1 flag note tiaan1 pin input taanccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the taanovf0 and taanovf1 flags are set on the internal ram by software. <1> read the taanccr0 register (setting of t he default value of the tiaan0 pin input). <2> read the taanccr1 register (setting of t he default value of the tiaan1 pin input). <3> an overflow occurs. set the taanovf0 and taanov f1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the taanccr0 register. read the taanovf0 flag. if the taanovf0 flag is 1, clear it to 0. because the taanovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the taanccr1 register. read the taanovf1 flag. if the taanovf1 flag is 1, clear it to 0 (the taanovf0 flag is cleared in <4>, and the taanovf1 flag remains 1). because the taanovf1 flag is 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 318 of 1817 sep 19, 2011 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h taance bit inttaanov signal taanovf bit taanovf0 flag note tiaan0 pin input taanccr0 register taanovf1 flag note tiaan1 pin input taanccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the taanovf0 and taanovf1 flags are set on the internal ram by software. <1> read the taanccr0 register (setting of t he default value of the tiaan0 pin input). <2> read the taanccr1 register (setting of t he default value of the tiaan1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the taanccr0 register. read the overflow flag. if the overflow flag is 1, set only the taanovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the taanccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the taanovf1 flag. if the taanovf1 flag is 1, clear it to 0. because the taanovf1 flag is 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 319 of 1817 sep 19, 2011 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h taance bit tiaanm pin input taanccrm register inttaanov signal taanovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when a long pulse width is measured in the free-running timer mode. <1> read the taanccrm register (setting of t he default value of the tiaanm pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the taanccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 ? d m0 ) because an overflow occurs twice. if an overflow occurs twice or more when the capture trigge r interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. remark m = 0, 1 n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 320 of 1817 sep 19, 2011 example when capture trigger interval is long ffffh 16-bit counter 0000h taance bit tiaanm pin input taanccrm register inttaanov signal taanovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the taanccrm register (setting of t he default value of the tiaanm pin input). <2> an overflow occurs. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the taanccrm register. read the overflow counter. when the overflow counter is ?n?, the pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h). remark m = 0, 1 n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 321 of 1817 sep 19, 2011 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the t aanovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the taanopt0 register. to a ccurately detect an overflow, read the taanovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (taanovf bit) read write 0 write signal overflow set signal register access signal overflow flag (taanovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (taanovf bit) overflow flag (taanovf bit) l h l remark n = 0 to 5 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without chec king if the flag is 1, the se t information of the overflow may be erased by writing 0 ((ii) in the above chart) . therefore, software may judge that no overflow has occurred even when an overflow has actually occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains se t (1) even after execution of the clear instruction. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 322 of 1817 sep 19, 2011 7.5.7 pulse width measurement mode (taanmd2 to taanmd0 bits = 110) in the pulse width measurement mode, 16-bit timer/event counter aa starts counting when the taanctl0.taance bit is set to 1. each time the valid edge input to the tiaanm pin has been detected, the count value of the 16-bit counter is stored in the taanccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be m easured by reading the taanccrm regist er after a capture interrupt request signal (inttaanccm) occurs. select either the tiaan0 or tiaan1 pin as the capture trigger input pin. specify ?no edge detection? for the unused pins by using the taanioc1 register. when an external clock is used as the count clock, measur e the pulse width of the tiaa n1 pin because the external clock is fixed to the tiaan0 pin. at this time, clear t he taanioc1.taanis1 and taanioc1.taanis0 bits to 00 (capture trigger input (tiaan0 pin): no edge detection). figure 7-39. configuration in pulse width measurement mode taanccr0 register (capture) taance bit taanccr1 register (capture) count clock selection edge detector edge detector tiaan1 pin (capture trigger input) tiaan0 pin (capture trigger input) clear inttaanov signal inttaancc0 signal inttaancc1 signal 16-bit counter remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 323 of 1817 sep 19, 2011 figure 7-40. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h taance bit tiaanm pin input taanccrm register inttaanccm signal inttaanov signal taanovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark n = 0 to 5 m = 0, 1 when the taance bit is set to 1, the 16 -bit counter starts counting. when t he valid edge input to the tiaanm pin is later detected, the count value of the 16 -bit counter is stored in the taanccrm re gister, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttaanccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tiaanm pin even when th e 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttaanov) is generated at the next count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (taanopt0.taanovf bi t) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h taanovf bit set (1) count + captured value) count clock cycle remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 324 of 1817 sep 19, 2011 figure 7-41. register setting in pulse width measurement mode (a) taan control register 0 (taanctl0) 0/1 0 0 0 0 taanctl0 select count clock 0: stops counting 1: enables counting 0/1 0/1 0/1 taancks2 taancks1 taancks0 taance (b) taan control register 1 (taanctl1) 00000 taanctl1 110 taanmd2 taanest taaneee taanmd1 taanmd0 1, 1, 0: pulse width measurement mode (c) taan i/o control register 1 (taanioc1) 0 0 0 0 0/1 taanioc1 select valid edge of tiaan0 pin input select valid edge of tiaan1 pin input 0/1 0/1 0/1 taanis2 taanis1 taanis0 taanis3 (d) taan option register 0 (taanopt0) 00000 taanopt0 overflow flag 0 0 0/1 taanovf taanccs1 taanccs0 (e) taan counter read buffer register (taancnt) the value of the 16-bit counter can be read by reading the taancnt register. (f) taan capture/compare registers 0 and 1 (taanccr0 and taanccr1) these registers store the count valu e of the 16-bit counter when the vali d edge input to the tiaanm pin is detected. remarks 1. taan i/o control register 0 (taanioc0), and taan i/o control register 2 (taanioc2) are not used in the pulse width measurement mode. 2. m = 0, 1 n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 325 of 1817 sep 19, 2011 (1) operation flow in pul se width measurement mode figure 7-42. software processing flow in pulse width measurement mode <1> <2> set taanctl0 register (taance bit = 1) taance bit = 0 register initial setting taanctl0 register (taancks0 to taancks2 bits), taanctl1 register, taanioc1 register, taanopt0 register initial setting of these registers is performed before setting the taance bit to 1. the taancks0 to taancks2 bits can be set at the same time when counting has been started (taance bit = 1). the counter is initialized and counting is stopped by clearing the taance bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h taance bit tiaan0 pin input taanccr0 register inttaancc0 signal d 0 0000h 0000h d 1 d 2 remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 326 of 1817 sep 19, 2011 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the t aanovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the taanopt0 register. to a ccurately detect an overflow, read the taanovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (taanovf bit) read write 0 write signal overflow set signal register access signal overflow flag (taanovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (taanovf bit) overflow flag (taanovf bit) l h l remark n = 0 to 5 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without chec king if the flag is 1, the se t information of the overflow may be erased by writing 0 ((ii) in the above chart) . therefore, software may judge that no overflow has occurred even when an overflow has actually occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains se t (1) even after execution of the clear instruction. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 327 of 1817 sep 19, 2011 7.5.8 timer output operations the following table shows the operations and output levels of the toaan0 and toaan1 pins. table 7-5. timer output control in each mode operation mode toaan1 pin toaan0 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? remark n = 0 to 5 table 7-6. truth table of toaan0 and toaan1 pins under control of timer output control bits taanioc0.taanolm bit taanioc0.taanoem bit taanctl0.taance bit level of toaanm pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark n = 0 to 5 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 328 of 1817 sep 19, 2011 7.6 timer-tuned operation function timer aa and timer ab have a timer-tuned operation function. the timer-tuned operation function is us ed to tune the internal timers of the v850es/jh3-e and v850es/jj3-e, so that the number of capture or compare regist ers of the slave timer (the number of timer outputs and the number of compare match interrupts of the slave timer) can be added to the master ti mer. the timers that can be tuned are listed in table 7-7. table 7-7. tuned-operation mode of timers master timer slave timer taa1 taa0 taa3 taa2 tab1 taa4 the tuned-operation function has the following modes. ? pwm output mode ? free-running timer mode figure 7-43 shows an example where individual operation a nd tuned operation of taa0 (as the master timer) and taa1 (as the slave timer) are performed in pwm output mode. figure 7-43. differences between individual operation and tuned op eration using taa0 and taa1 taa1 toaa11 (pwm output) 16-bit timer/counter individual operation two pwm outputs are available when pwm is operated separately with each timer. 16-bit capture/compare 16-bit capture/compare toaa10 (square waveform output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare taa0 toaa01 (pwm output) toaa00 (square- waveform output) taa1 (master) + taa0 (slave) toaa11 (pwm output) 16-bit timer/counter tuned operation 16-bit capture/compare 16-bit capture/compare 16-bit capture/compare toaa10 (square waveform output) toaa01 (pwm output) 16-bit capture/compare toaa01 (pwm output) three pwm outputs are available when pwm is operated in tuned-operation mode. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 329 of 1817 sep 19, 2011 table 7-8 show the timer modes that can be used in the t uned-operation mode and table 7-9 shows the differences of the timer output functions between individual operation and tuned operation ( : settable, : not settable). table 7-8. timer modes usable in tuned-operation mode master timer slave timer fr ee-running timer mode pwm mode taa1 taa0 taa3 taa2 tab0 taa5 tab1 taa4 table 7-9. timer output functions free-running timer mode pwm mode tuned channel timer pin individual operation tuned operation i ndividual operation tuned operation toaa10 ppg toggle taa1 (master) toaa11 ppg pwm toaa00 pgp toggle pwm ch0 taa0 (slave) toaa01 ppg pwm toaa30 ppg toggle taa3 (master) toaa31 ppg pwm toaa20 ppg toggle pwm ch1 taa2 (slave) toaa21 ppg pwm toab00 ppg toggle tab0 (master) toab01 to toab03 ppg pwm toaa50 ppg toggle pwm ch2 taa5 (slave) toaa51 ppg pwm toab10 ppg toggle tab1 (master) toab11 to toab13 ppg pwm toaa40 ppg toggle pwm ch3 taa4 (slave) toaa41 ppg pwm remark the timing of transmitting data from the compare r egister of the buffer register is as follows. ? ppg: cpu write timing ? toggle, pwm, triangular wave pwm: timing at which timer counter and compare register match toaan0 and toabm0 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 330 of 1817 sep 19, 2011 7.6.1 free-running timer mode ( during timer-tuned operation) this section explains the free-runnin g timer mode of the timer-tuned operation. for the combination of timer-tuned operations, see table 7-7 . in this section, an example of timer-tuned operation using taa1 and taa0 is shown. (i) selecting capture/compare registers when the free-running timer mode of the timer-tuned opera tion is used with taa1 and taa0 connected to each other, the two capture/compare regist ers of taa1 and two capture/compare registers of taa0 can be used in combination. how the capture and compare registers are combined is not restricted and can be selected by using the taanccsn bit of the master or slave timer. when the compare register is selected, the set value of the compare register can be rewritten during operation and the rewriting method is anytime write (n = 0, 1). (ii) overflow if the counter overflows, an overflow interrupt (inttaa1ov ) of the master timer is generated and the overflow flag (taa1ovf) is set to ?1?. the overflow interrupt (inttaa0ov) and overflow fl ag (taa0ovf) of the slave timer do not operate and are always at the low level. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 331 of 1817 sep 19, 2011 (1) settings in free-running ti mer mode (compare function) [initial settings] master timer: taa1ctl0.taa1ce = 0 (operation disabled) slave timer: taa0ctl0.taa0ce = 0 (operation disabled) [initial settings of master timer (taa1)] ? taa1ctl1.taa1md2 to taa1ctl1.taa1md0 = 101 (setting of free-running timer mode) ? taa1opt0.taa1ccs1 and taa1opt0.taa1ccs0 = 00 (setting of capture/compare select bit to ?compare?.) ? taa1ctl1.taa1cks2 to taa1ctl1.taa1cks0 (setting of count clock (any)) ? taa1ccr1 and taa1ccr0 registers are set. [initial settings of slave timer (taa0)] ? taa0ctl1.taa0sye = 1 (setting of timer-tuned operation) ? taa0ctl1.taa0md2 to taa0ctl1.taa0md0 = 101 (setting of free-running timer mode) ? taa0opt0.taa0ccs1 and taa0opt0.taa0ccs0 = 00 (setting of capture/compare select bit to ?compare?.) ? taa0ccr0 and taa0ccr1 registers are set. remark the initial settings of the master timer and slave timer may be performed in any order. [starting counting] <1> set taa1ctl0.taa1ce of the master timer to 1. <2> start counting. <3> changing the setting of the register during operation ? the compare register can be rewritten (anytime write). [end condition] ? set taa1ctl0.taa1ce of the master timer to 0. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 332 of 1817 sep 19, 2011 figure 7-44. example of timing in free-running mode (compare function) d 10 d 11 d 00 d 01 toaa10 toaa11 toaa01 inttaa0ov taa0ovf toaa00 taa1ce inttaa1cc0 inttaa1cc1 inttaa0cc0 inttaa0cc1 inttaa1ov taa1ovf ffffh 0000h taa1 16-bit counter taa1ccr0 taa1ccr1 taa0ccr0 taa0ccr1 d 10 d 11 d 00 d 01 d 10 d 11 d 00 d 01 taa1ovf write clear (0) l l v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 333 of 1817 sep 19, 2011 (2) settings in free-running ti mer mode (capture function) [initial settings] master timer: taa1ctl0.taa1ce = 0 (operation disabled) slave timer: taa0ctl0.taa0ce = 0 (operation disabled) [initial settings of master timer (taa1)] ? taa1ctl1.taa1md2 to taa1ctl1.taa1md0 = 101 (setting of free-running timer mode) ? taa1opt0.taa1ccs1 and taa1opt0.taa1ccs0 = 11 (setti ng of capture/compare select bit to ?capture?.) ? taa1ctl1.taa1cks2 to taa1ctl1.taa1cks0 (setting of count clock (any)) ? taa1ioc1.taa1is3 to taa1ioc1.taa1is0 (specif ication of valid edge of capture trigger) [initial settings of slave timer (taa0)] ? taa0ctl1.taa0sye = 1 (setting of timer-tuned operation) ? taa0ctl1.taa0md2 to taa0ctl1.taa0md0 = 101 (setting of free-running timer mode) ? taa0opt0.taa0ccs1 and taa0opt0.taa0ccs0 = 11 (setti ng of capture/compare select bit to ?capture?.) ? taa0ioc1.taa0is3 to taa0ioc1.taa0is0 (specif ication of valid edge of capture trigger) remark the initial settings of the master timer and slave timer may be performed in any order. [starting counting] <1> set taa1ctl0.taa1ce of the master timer to 1. <2> start counting. [end condition] ? set taa1ctl0.taa1ce of the master timer to 0. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 334 of 1817 sep 19, 2011 figure 7-45. example of timing in free-running mode (capture function) d 111 d 101 d 001 d 011 inttaa0ov taa0ovf taa1ce inttaa1cc0 inttaa1cc1 inttaa0cc0 inttaa0cc1 inttaa1ov taa1ovf ffffh 0000h taa1 16-bit counter taa1ccr0 taa1ccr1 taa0ccr0 taa0ccr1 tiaa10 tiaa11 tiaa00 tiaa01 d 100 d 110 d 000 d 110 d 101 d 110 taa1ovf write clear (0) l l 0000 d 110 d 111 0000 d 000 d 001 0000 d 010 d 011 0000 d 100 d 101 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 335 of 1817 sep 19, 2011 (3) settings in free-running timer mode (capture/compare used together) an example of using taa0 as a capture register and taa1 as a compare register is shown below. [initial settings] master timer: taa1ctl0.taa1ce = 0 (operation disabled) slave timer: taa0ctl0.taa0ce = 0 (operation disabled) [initial settings of master timer (taa1)] ? taa1ctl1.taa1md2 to taa1ctl1.taa1md0 = 101 (setting of free-running timer mode) ? taa1opt0.taa1ccs1 and taa1opt0.taa1ccs0 = 11 (setti ng of capture/compare select bit to ?capture?.) ? taa1ctl1.taa1cks2 to taa1ctl1.taa1cks0 (setting of count clock (any)) ? taa1.taa0is3 to taa1.taa1is0 (specification of valid edge of capture trigger) [initial settings of slave timer (taa0)] ? taa0ctl1.taa0sye = 1 (setting of timer-tuned operation) ? taa0ctl1.taa0md2 to taa0ctl1.taa0md0 = 101 (setting of free-running timer mode) ? taa0opt0.taa0ccs1 and taa0opt0.taa0ccs0 = 00 (setting of capture/compare select bit to ?compare?.) ? taa0ccr0 and taa0ccr1 registers are set. remark the initial settings of the master timer and slave timer may be performed in any order. [starting counting] <1> set taa1ctl0.taa1ce of the master timer to 1. <2> start counting. [end condition] ? set taa1ctl0.taa1ce of the master timer to 0. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 336 of 1817 sep 19, 2011 figure 7-46. example of timing in free-runni ng mode (capture/compare used together) d 111 d 000 d 010 taa1ce inttaa1cc1 toaa00 toaa01 inttaa0cc0 inttaa0cc1 inttaa1cc0 ffffh 0000h taa1 16-bit counter taa0ccr0 taa0ccr1 d 110 d 000 d 010 d 100 d 000 d 010 taa1ovf inttaa1ov taa1ovf write clear (0) inttaa0ov l taa0ovf l tiaa10 tiaa11 taa1ccr0 0000 d 000 taa1ccr1 0000 0000 0000 d 110 d 111 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 337 of 1817 sep 19, 2011 7.6.2 pwm output mode (durin g timer-tuned operation) this section explains the pwm output mode of timer-tuned operation. for comb inations of timer-tuned operations, see table 7-7 . this section presents an example of a timer-tuned operation with tab0 and taa5. the tab0ccr0 register of the master timer (tab0) is used as a compare register for cycle, and the tab0ccr1, tab0ccr2, and tab0ccr3 registers of the master timer (t ab0) and the taa5ccr0 and taa5ccr1 registers of the slave timer (taa5) are used as compare registers for duty. the compare registers can be rewritten during opera tion and the rewriting method is batch writing. batch writing is enabled when the tab0ccr1 register of the master timer (tab0) is written, and all the compare registers of the master and slave timers are rewritten or the same value is written to them when an interrupt, which is generated if the value of the tab0ccr0 re gister of the master timer (tab0) matc hes the value of the timer counter, is generated. (1) settings in pwm output mode [initials setting] master timer: tab0ctl0.tab0ce = 0 (operation disabled) slave timer: taa5ctl0.taa5ce = 0 (operation disabled) [initial settings of master timer (tab0)] ? tab0ctl1.tab0md2 to tab0ctl1.tab0md 0 = 100 (setting of pwm output mode) ? tab0opt0.tab0ccs3 to tab0opt0.tab0ccs0 = 0000 (setting of capture/compare select bit to ?compare?.) ? tab0ccr0, tab0ccr1, tab0ccr2, and tab0ccr3 registers are set. [initial settings of slave timer (taa5)] ? taa5ctl1.taa5sye = 1 (setting of timer-tuned operation) ? taa5ctl1.taa5md2 to taa5ctl1.taa5md0 = 101 (setting of free-running timer mode) ? taa5opt0.taa5ccs1 and taa5opt0.taa5ccs0 = 00 (setting of capture/compare select bit to ?compare?.) ? taa5ccr0 and taa5ccr1 registers are set. remark the initial settings of the master timer and slave timer may be performed in any order. [starting counting] <1> set tab0ctl0.tab0ce of the master timer to 1. <2> start counting. <3> changing the setting of the register during operation ? the compare register can be rewritten (batch rewrite). [end condition] ? set tab0ctl0.tab0ce of the master timer to 0. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 338 of 1817 sep 19, 2011 [batch write] in the pwm output mode, the next batch write is enabl ed by writing the tab0ccr1 register of the master timer (tab0). after all the compare registers that must be re written have been rewritten, therefore, the tab0ccr1 register of the master timer (tab0) must be written. batch writing is executed when the value of the timer c ounter matches the value of the compare register for cycle (tab0ccr0). if the tab0ccr1 register of the master timer (tab0) is not written, batch writing is no t enabled even if any other compare register is rewritten. consequently, the valu e of the compare registers is not rewritten even when the value of the timer counter matches the value of the compare register for cycle (tab0ccr0). figure 7-47. timing example of tuned pwm function (tab0, taa5) toab00 pin output toab01 pin output toab02 pin output toaa50 pin output toab03 pin output tab0ccr0 register tab0ce bit inttab0cc0 match interrupt toaa51 pin output inttab0cc1 match interrupt inttab0cc2 match interrupt inttab0cc3 match interrupt inttaa5cc0 match interrupt inttaa5cc1 match interrupt ffffh 0000h tab0 16-bit counter d 00 d 50 d 40 d 30 d 20 d 10 d 00 d 50 d 40 d 30 d 20 d 10 tab0ccr1 register tab0ccr0 register tab0ccr1 register taa5ccr0 register taa5ccr1 register d 00 d 10 d 20 d 30 d 40 d 50 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 339 of 1817 sep 19, 2011 7.7 simultaneous-start function timer aa and timer ab have a timer-tuned operation function. by using the simultaneous-start functi on, a timer operation in which the operat ion start timing and count up timing of the master timer and slave timer are synchronized can be performed. only the pwm output mode can be used in the simultaneous-start function. the combinations of timers that can use the si multaneous-start function are listed in table 7-10. table 7-10. timer simultaneous-start function master timer slave timer taa1 taa0 taa3 taa2 tab0 taa5 tab1 taa4 figure 7-48 shows an example where individual operation and simultaneous-start operation of taa0 (as the master timer) and taa1 (as the slave timer) are performed in pwm output mode. figure 7-48. differences between indi vidual operation and simultaneous-sta rt operation using taa1 and taa0 taa1 toaa11 (pwm output) 16-bit timer/counter individual operation if pwm operates separately with each timer, the 16-bit counter starts and the pwm output starts at a different timing for each timer. 16-bit capture/compare 16-bit capture/compare toaa10 (square waveform output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare taa0 toaa01 (pwm output) toaa00 (square waveform output) taa1 (master) toaa11 (pwm output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare toaa10 (square waveform output) 16-bit timer/counter 16-bit capture/compare 16-bit capture/compare taa0 (slave) toaa01 (pwm output) simultaneous-start signal toaa00 (square waveform output) simultaneous-start operation with the simultaneous-start function, pwm output operates with the count start timing and the count clock of both timers being synchronized. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 340 of 1817 sep 19, 2011 7.7.1 pwm output mode (sim ultaneous-start operation) in this section, the operation of the si multaneous-start function is shown, where taa1 is used as the master timer and taa0 is used as the slave timer. the master timer (taa1) and slave timer (taa0) start operati ng at the same time when the taa1ctl0.taa0ce bit of master timer is set to 1. the slave timer operates by the count clock supplied from the master timer (taa1). after the slave timer starts operating, however, the 16-bit counter of the slave timer (taa0) is not cleared even if the 16-bit counter of the master timer (taa1) is cleared to 0000h upon a match between the 16-bit counter value of the master timer (taa1) and the taa1ccr0 register value, because each timer operates individually. in the same manner, if the compare regist er value of the master timer (taa1) is rewritten by batch writing, the compare register of the slave timer is not affected. [initial settings] master timer: taa1ctl0.taa1ce = 0 (operation disabled) slave timer: taa0ctl0.taa0ce = 0 (operation disabled) [initial settings of master timer (taa1)] ? taa1ctl1.taa1md2 to taa1ctl1.taa1md 0 = 100 (setting of pmw output mode) ? taa1ctl1.taa1cks2 to taa1ctl1.taa1cks0 (setting of count clock (any)) ? taa1ccr1, taa1ccr0 (specification of valid edge of capture trigger) ? taa1ioc0 (specification of valid edge of capture trigger) [initial settings of slave timer (taa0)] ? taa0ctl1.taa0sye = 1, taa0sym = 1 (simultaneous-start operation) ? taa0ctl1.taa0md2 to taa0ctl1.taa0md 0 = 100 (setting of pmw output mode) ? taa0ccr0, taa1ccr1 (specification of valid edge of capture trigger) ? taa0ioc0 (specification of valid edge of capture trigger) remark the initial settings of the master timer and slave timer may be performed in any order. [starting counting] <1> set taa1ctl0.taa1ce of the master timer to 1. <2> start counting. <3> changing the setting of the register during operation ? the compare register can be rewritten (anytime write). [end condition] ? set taa1ctl0.taa0ce of the master timer to 0. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 341 of 1817 sep 19, 2011 figure 7-49. timing example of simultaneous -start function (taa1: master, taa0: slave) d 10 d 11 d 00 d 00 d 01 d 01 toaa00 pin output toaa01 pin output toaa11 pin output toaa10 pin output taa1ce bit inttaa0cc0 interrupt inttaa0cc1 interrupt inttaa1cc0 interrupt inttaa1cc1 interrupt ffffh 0000h taa1 16 -bit counter ffffh 0000h taa0 16 -bit counter taa1ccr0 register taa1ccr1 register taa0ccr0 register taa0ccr1 register d 10 d 11 d 00 d 01 d 10 d 11 d 00 d 01 v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 342 of 1817 sep 19, 2011 7.8 cascade connection this section explains an operation of connecting two channe ls of taa in cascade to form a 32-bit capture timer. for cascade connection, the free-running timer mode must be set and all the capture/compar e registers must be set as capture registers (taa0ccsn = 1). combinations of taa channels that can be connec ted in cascade are shown in the following table. table 7-11. cascade connection of taa lower timer (master timer) higher timer (slave timer) taa1 taa0 taa3 taa2 in the following example, taa1 is used as the lower timer (master timer) and taa0 is used as the higher timer (slave timer) to use them as a 32-bit capture timer by cascade connection. figure 7-50. cascade connection example edge detection count clock selection operation enable bit (taa1ce) ffffh detection signal capture signal 1 (tiaa11) capture signal 0 (tiaa10) lower capture interrupt 0 (inttaa1cc0) lower overflow interrupt (inttaa1ov) lower capture interrupt 1 (inttaa1cc1) [lower timer taa1] [higher timer taa0] lower timer counter lower capture register 0 (taa1ccr0) lower capture register 1 (taa1ccr1) higher timer counter higher capture register 0 (taa0ccr0) higher capture register 1 (taa0ccr1) higher overflow interrupt (inttaa0ov) edge detection v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 343 of 1817 sep 19, 2011 the operation of each pin and signal when taa1 and taa0 are connected in cascade is shown below. table 7-12. status in cascade connection name higher/lower function operation tiaa10 pin input lower capture input 0 the value of the lower timer counter is stored in the taa1ccr0 register and the value of the higher timer counter is stored in the taa0ccr0 register when the valid edge of this input is detected. tiaa11 pin input lower capture input 1 the value of the lower timer counter is stored in the taa1ccr1 register and the value of the higher timer counter is stored in the taa0ccr1 register when the valid edge of this input is detected. inttaa1ccr0 interrupt signal lower capture interrupt 0 this interrupt is generated when the valid edge of the tiaa10 pin is detected. inttaa1ccr1 interrupt signal lower capture interrupt 1 this interrupt is generated when the valid edge of the tiaa11 pin is detected. inttaa1ov interrupt signal lower overflow interrupt this interrupt is generated when an overflow of the lower timer counter is detected. tiaa00 pin input higher capture input 0 does not operate. tiaa01 pin input higher capture input 1 does not operate. inttaa0ccr0 interrupt signal higher capture interrupt 0 does not operate. inttaa0ccr1 interrupt signal higher capture interrupt 1 does not operate. inttaa0ov interrupt signal higher overflow interrupt this interrupt is generated when an overflow of the higher timer counter is detected. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 344 of 1817 sep 19, 2011 figure 7-51. operation flow in cascad e connection of taa1 and taa0 (1/2) 32-bit counter ffffffffh 00000000h operation enable bit ( taa1ce) tiaa10 input d 0a0b d 0c0d d 1c1d d 0e0f d 1e1f d 0g0h lower capture register 0 (taa1ccr0) lower capture interrupt 0 (inttaa1cc0) tiaa11 input lower c apture interrupt 1 (inttaa1cc1) overflow interrupt (inttaa0ov) overflow flag (taa0ovf) pulse interval d 1c1d ? d 1a1b pulse interval d 1e1f ? d 1c1d d 1a1b pulse interval d 0c0d ? d 0a0b pulse interval d 0e0f ? d 0c0d pulse interval d 0g0h ? d 0c0d cleared to 0 by clr instruction cleared to 0 by clr instruction d 0b d 0d d 0f d 0h 0000 higher capture register 0 (taa0ccr0) lower capture register 1 (taa1ccr1) higher capture register 1 (taa0ccr1) d 0a d 0c d 0e d 0g 0000 d 1d d 1f d 1b 0000 d 1c d 1e 0000h 0000h 0000h 0000h d 1a 0000 <1> <2> <4> <3> <5> v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 345 of 1817 sep 19, 2011 figure 7-51. operation flow in cascad e connection of taa1 and taa0 (2/2) taa1ce bit = 1 reading taa0opt0 register (checking overflow flag) [lower timer: taa1] taa1ctl0 register (taa1cks0 to taa1cks2 bits), taa1ctl1 register, taa1ioc1 register, taa1ioc2 register, taa1opt0 register [higher timer: taa0] taa0ctl1 register, taa0 ioc1 register, taa0 opt0 register, taa0 opt1 register perform initial setting of these registers before taa1ce bit = 1. taa1cks0 to taa1cks2 bits can be set as soon as counting operation starts (taa1ce bit = 1). start executing instruction that clears taa0ovf bit (clr taa0ovf) <1> count operation start flow <4> overflow flag clear flow taa1ce bit = 0 counter is initialized by stopping counting operation (taa1ce bit = 0). stop <5> count operation stop flow taa0ovf bit = 1 no yes reading taa1ccr0 and taa0ccr0 registers (reading capture register 0) executing instruction that clears taa0ccic0.taa0ccif0 bit ( clr taa0ccif0) calculating pulse interval (captured value ? previously captured value) <2> capture 0 read flow inttaa0ccr0 generated? no yes taa1ccif0 = 0? no yes reading taa1ccr1 and taa0ccr1 registers (reading capture register 0) executing instruction that clears taa0ccic1.taa0ccif1 bit ( clr taa0ccif1) calculating pulse interval (captured value ? previously captured value) inttaa0ccr1 generated? no yes taa0ccif1 = 0? no yes <2> capture 1 read flow register initial setting v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 346 of 1817 sep 19, 2011 figure 7-52. example of basic timing when taa1 and taa0 are connected in cascade 32 -bit counter ffffffffh 00000000h operation enable bit ( taa1ce) tiaa10 input d 0a0b d 0c0d d 1c1d d 0e0f d 1e1f d 1g1h d 0g0h d 0i0j lower capture register 0 (taa1ccr0) lower capture interrupt 0 (inttaa1cc0) tiaa11 input capture interrupt 1 (inttaa1cc1) overflow interrupt (inttaa0ov) overflow flag (taa0ovf) pulse interval d 1c1d ? d 1a1b pulse interval d 1g1h ? d 1c1d pulse interval d 1e1f ? d 1c1d d 1a1b pulse interval d 0c0d ? d 0a0b pulse interval d 0e0f ? d 0c0d pulse interval d 0g0h ? d 0c0d pulse interval d 0i0j ? d 0g0h cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction d 0b d 0d d 0f d 0h d 0j 0000 higher capture register 0 (taa0ccr0) lower capture register 1 (taa1ccr1) higher capture register 1 (taa0ccr1) d 0a d 0c d 0e d 0g d 0i 0000 d 1d d 1f d 1h d 1b 0000 d 1c d 1e d 1g d 1a 0000 the counting operation is star ted when the taa1ctl.taa1ce bit is set to 1 and the count clock is supplied. when the valid edge input to the tiaa10 pin is detected, the count value is stored in the capture register 0 (taa1ccr0 and taa0ccr0), and capture interrupt 0 signal (inttaa1cc0) is issued. the timer counter continues the counting operation in syn chronization with the count clock. when it counts up to ffffffffh, the overflow interrupt (inttaa0ov) is generated at the next cl ock and the overflow flag (taa0ovf) is set to 1. the timer counter is cleared to 00000000h and continues counting up. the overflow flag (taa0ovf) is cleared by an instru ction issued from the cpu t hat writes ?0? to it. because the free-running timer mode is set, the timer c ounter cannot be cleared by detection of the valid edge input to the tiaa10 pin. using toaa10 output is prohibited because it alternately functions as the tiaa10 input. capture register 1 (taa1ccr1 and taa0ccr1) also operates in the same manner. if the lower timer counter (taa1) overflows, an overflow interrupt (taa1ovf) is generated. however, it is recommended to mask this interrupt because it cannot be used as an overflow interrupt of the 32-bit counter. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 347 of 1817 sep 19, 2011 7.9 selector function in the v850es/jh3-e and v850es/jj3-e, t he alternate-function pins of ports or peripheral i/o (taa1, tab0, uartc0, or uartc1) signals can be selected as the capture trigger input of taa1 and tab0. if the signal input from the uartcn pin is selected by the selector function when rxdcn is used, baud rate errors of the lin reception transfer rate of uartcn can be calculated (n = 0, 1). (1) selector operation control register 0 (selcnt0) the selcnt0 register is an 8-bit register that se lects the capture trigger for can0, taa1, and tab0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 selcnt0 0 0 isel4 isel3 0 0 isel0 note 654321 isel4 0 1 selection of tiaa11 capture trigger input signal tiaa11 (alternately functions as p33 ) pin rxdc1 (alternately functions as p24 ) pin isel3 0 1 selection of tiaa10 capture trigger input signal tiaa10 (alternately functions as p32 ) pin rxdc0 (alternately functions as p31 ) pin isel0 note 0 1 selection of tiab02 capture trigger input signal tiab02 (alternately functions as p20 ) pin can0 tsout signal after reset: 00h r/w address: fffff308h <7> 0 note pd70f3783 and 70f3786 only cautions 1. to set the isel4, isel3, and isel0 bits to 1, set the corresponding function pin to the capture input mode. 2. set the isel4, isel3, and isel0 bits when the operation of taa1, tab0, and uartc0, uartc1, and can0 are stopped. 3. be sure to set bits 7 to 5, 2, and 1 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 7 16-bit timer/event counter aa (taa) r01uh0290ej0300 rev.3.00 page 348 of 1817 sep 19, 2011 7.10 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh , not 0000h, may be captured in the taanccr0 and taanccr1 registers if the c apture trigger is input immediately after the taance bit is set to 1. (a) free-running timer mode count clock 0000h ffffh taance bit taanccr0 register ffffh 0001h 0000h tiaan0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock taance bit taanccr0 register tiaan0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input remark n = 0 to 5 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 349 of 1817 sep 19, 2011 chapter 8 16-bit timer/ event counter ab (tab) timer ab (tab) is a 16-bit timer/event counter. the v850es/jh3-e and v850es/jj3-e have tab0 and tab1. 8.1 overview an outline of tabn is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 4 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer counters: 1 ? capture/compare registers: 4 ? capture/compare match interrupt request signals: 4 ? timer output pins: 4 remark n = 0, 1 8.2 functions tabn has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? triangular wave pwm output ? timer-tuned operation function ? simultaneous-start function remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 350 of 1817 sep 19, 2011 8.3 configuration tabn includes the following hardware. table 8-1. configuration of tabn item configuration registers 16-bit counter tabn capture/compare registers 0 to 3 (tabnccr0 to tabnccr3) tabn counter read buffer register (tabncnt) ccr0 to ccr3 buffer registers tabn control registers 0, 1 (tabnctl0, tabnctl1) tabn i/o control registers 0 to 2 (tabnioc0 to tabnioc2, tabnioc4) tabn option register 0 (tabnopt0) timer inputs note 1 4 (tiabn0 note 2 to tiabn3 note 3 pins), evtab1, trgab1 timer outputs note 1 4 (toabn0 to toabn3 note 3 pins) notes 1. when using the functions of the tiabn0 to tiabn3 and toabn0 to toabn3 pins, see table 4-18 using port pin as alternate-function pin . 2. the tiab00 pin functions alternat ely as a capture trigger input signal, external event count input signal, and external trigger input signal. 3. the tiab03 and toab03 pins are not provided in the v850es/jh3-e. figure 8-1. block diagram of tabn tabncnt tabnccr0 tabnccr1 tabnccr2 toabn0 inttabnov ccr2 buffer register tabnccr3 ccr3 buffer register toabn1 toabn2 toabn3 note 2 inttabncc0 inttabncc1 inttabncc2 inttabncc3 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tiabn0 note 1 tiabn1 tiabn2 tiabn3 note 2 selector internal bus internal bus selector edge detector ccr0 buffer register ccr1 buffer register 16-bit counter output controller clear notes 1. tab1: evtab1 pin and trgab1 pin 2. the tiab03 and toab03 pins are not provided in the v850es/jh3-e. remarks 1. f xx : main clock frequency 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 351 of 1817 sep 19, 2011 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tabncnt register. when the tabnctl0.tabnce bit = 0, the va lue of the 16-bit counter is ffffh. if the tabncnt register is read at this time, 0000h is read. reset sets the tabnce bit to 0. theref ore, the 16-bit counter is set to ffffh. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tabnccr0 register is used as a compare regist er, the value written to the tabnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter ma tches the value of the ccr0 buffer register, a compare match interrupt request signal (inttabncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after re set, as the tabnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tabnccr1 register is used as a compare regist er, the value written to the tabnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter ma tches the value of the ccr1 buffer register, a compare match interrupt request signal (inttabncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after re set, as the tabnccr1 register is cleared to 0000h. (4) ccr2 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tabnccr2 register is used as a compare regist er, the value written to the tabnccr2 register is transferred to the ccr2 buffer register. when the count va lue of the 16-bit counter ma tches the value of the ccr2 buffer register, a compare match interrupt request signal (inttabncc2) is generated. the ccr2 buffer register cannot be read or written directly. the ccr2 buffer register is cleared to 0000h after re set, as the tabnccr2 register is cleared to 0000h. (5) ccr3 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tabnccr3 register is used as a compare regist er, the value written to the tabnccr3 register is transferred to the ccr3 buffer register. when the count va lue of the 16-bit counter ma tches the value of the ccr3 buffer register, a compare match interrupt request signal (inttabncc3) is generated. the ccr3 buffer register cannot be read or written directly. the ccr3 buffer register is cleared to 0000h after re set, as the tabnccr3 register is cleared to 0000h. (6) edge detector this circuit detects the valid edges input to the tiabn0 to tiabn3 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tabnioc1 and tabnioc2 registers. the tiab03 pin is not provi ded in the v850es/jh3-e. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 352 of 1817 sep 19, 2011 (7) output controller this circuit controls the output of the toabn0 to toabn3 pi ns. the output controller is controlled by the tabnioc0 register. note that the toab03 pin is not provided in the v850es/jh3-e. (8) selector this selector selects the count clock for the 16-bit counter. eight types of internal clocks or an external event can be selected as the count clock. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 353 of 1817 sep 19, 2011 8.4 registers the registers that control tabn are as follows. ? tabn control register 0 (tabnctl0) ? tabn control register 1 (tabnctl1) ? tabn i/o control register 0 (tabnioc0) ? tabn i/o control register 1 (tabnioc1) ? tabn i/o control register 2 (tabnioc2) ? tabn i/o control register 4 (tabnioc4) ? tabn option register 0 (tabnopt0) ? tabn capture/compare register 0 (tabnccr0) ? tabn capture/compare register 1 (tabnccr1) ? tabn capture/compare register 2 (tabnccr2) ? tabn capture/compare register 3 (tabnccr3) ? tabn counter read buffer register (tabncnt) remarks 1. when using the functions of the tiabn0 to tiabn3 and toabn0 to toabn3 pins, see table 4-18 using port pin as alternate-function pin . 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 354 of 1817 sep 19, 2011 (1) tabn control register 0 (tabnctl0) the tabnctl0 register is an 8-bit register that controls the operation of tabn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. software can be used to always write the same value to the tabnctl0 register. tabnce tabn operation disabled (tabn reset asynchronously note ). tabn operation enabled. tabn operation started. tabnce 0 1 tabn operation control tabnctl0 (n = 0, 1) 0000 tabncks2 tabncks1 tabncks0 654321 after reset: 00h r/w address: tab0ctl0 fffff540h, tab1ctl0 fffff560h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tabncks2 0 0 0 0 1 1 1 1 internal count clock selection tabncks1 0 0 1 1 0 0 1 1 tabncks0 0 1 0 1 0 1 0 1 note tabnopt0.tabnovf bit, 16-bit counter, timer output (toabn0 to toabn3 pins) cautions 1. set the tabncks2 to tabncks 0 bits when the tabnce bit = 0. when the value of the tabnce bi t is changed from 0 to 1, the tabncks2 to tabncks0 bits can be set simultaneously. 2. be sure to set bits 3 to 6 to ?0?. remark f xx : main clock frequency v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 355 of 1817 sep 19, 2011 (2) tabn control register 1 (tabnctl1) the tabnctl1 register is an 8-bit register that controls the operation of tabn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tabnest 0 1 software trigger control tabnctl1 (n = 0, 1) tabnest tabneee 00 tabnmd2 tabnmd1 tabnmd0 654321 after reset: 00h r/w address: tab0ctl1 fffff541h, tab1ctl1 fffff561h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tabnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tabnest bit as the trigger. 7 0 ? disable operation with external event count input. (perform counting with the count clock selected by the tabnctl0.tabnck0 to tabnctl0.tabnck2 bits.) tabneee 0 1 count clock selection the tabneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode triangular wave pwm mode tabnmd2 0 0 0 0 1 1 1 1 timer mode selection tabnmd1 0 0 1 1 0 0 1 1 tabnmd0 0 1 0 1 0 1 0 1 enable operation with external event count input. (perform counting at the valid edge of the external event count input signal.) cautions 1. the tabnest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. in any other mode, writing 1 to this bit is ignored. 2. be sure to set bits 3, 4, and 7 to ?0?. 3. external event count input is select ed in the external event count mode regardless of the value of the tabneee bit. 4. set the tabneee and tabnmd 2 to tabnmd0 bits when the tabnctl0.tabnce bit = 0. (the sam e value can be written when the tabnce bit = 1.) the operation is not guaranteed when rewriting is performed with the tabnce bit = 1. if rewriting was mistakenly performed, clear the tabnce bit to 0 and then set the bits again. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 356 of 1817 sep 19, 2011 (3) tabn i/o control register 0 (tabnioc0) the tabnioc0 register is an 8-bit register that c ontrols the timer output (toabn0 to toabn3 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tabnol3 note 1 tabnolm 0 1 toabnm pin output level setting (m = 0 to 3) note 2 toabnm pin high level start toabnm pin low level start tabnioc0 (n = 0, 1) tabnoe3 note 1 tabnol2 tabnoe2 tabnol1 tabnoe1 tabnol0 tabnoe0 <6> 5 <4> 3 <2> 1 after reset: 00h r/w address: tab0ioc0 fffff542h, tab1ioc0 fffff562h tabnoem 0 1 toabnm pin output setting (m = 0 to 3) timer output disabled ? when tabnolm bit = 0: low level is output from the toabnm pin ? when tabnolm bit = 1: high level is output from the toabnm pin 7 <0> timer output enabled (a square wave is output from the toabnm pin). notes 1. the toab03 pin is not provided in the v850es/jh3-e. set the tab0ol3 and tab0oe3 bits to 0. 2. the output level of the timer output pin (toabnm) specified by the tabnolm bit is shown below. tabnce bit toabnm output pin 16-bit counter ? when tabnolm bit = 0 tabnce bit toabnm output pin 16-bit counter ? when tabnolm bit = 1 cautions 1. rewrite the tabnol m and tabnoem bits when the tabnctl0.tabnce bit = 0. (the same value can be written when the tabnce bit = 1.) if rewriting was mistakenly performed, clear the tabnce bi t to 0 and then set the bits again. 2. even if the tabnolm bit is manipulated when the tabnce and tabnoem bits are 0, the toabnm pin output level varies. remark m = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 357 of 1817 sep 19, 2011 (4) tabn i/o control register 1 (tabnioc1) the tabnioc1 register is an 8-bit regist er that controls the valid edge of t he capture trigger input signals (tiabn0 to tiabn3 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tabnis7 note tabnis7 0 0 1 1 tabnis6 0 1 0 1 capture trigger input signal (tiabn3 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tabnioc1 (n = 0, 1) tabnis6 note tabnis5 tabnis4 tabnis3 tabnis2 tabnis1 tabnis0 654321 after reset: 00h r/w address: tab0ioc1 fffff543h, tab1ioc1 fffff563h tabnis5 0 0 1 1 tabnis4 0 1 0 1 capture trigger input signal (tiabn2 pin) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tabnis3 0 0 1 1 tabnis2 0 1 0 1 capture trigger input signal (tiabn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tabnis1 0 0 1 1 tabnis0 0 1 0 1 capture trigger input signal (tiabn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges note the tiab03 pin is not provided in the v850es/jh3-e. set the tab0is7 and tab0is6 bits to 0 when using the v850es/jh3-e. cautions 1. rewrite the tabnis 7 to tabnis0 bits when the tabnctl0.tabnce bit = 0. (the same value can be written when the tabnce bit = 1.) if rewriting was mistakenly performed, clear th e tabnce bit to 0 and then set the bits again. 2. the tabnis7 to tabnis0 bi ts are valid only in the free- running timer mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 358 of 1817 sep 19, 2011 (5) tabn i/o control register 2 (tabnioc2) the tabnioc2 register is an 8-bit regi ster that controls the va lid edge of the external event count input signal (tiab00/evtab1 pin) and external trigger input signal (tiab00/trgab1 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tabnees1 0 0 1 1 tabnees0 0 1 0 1 external event count input signal (tiab00/evtab1 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tabnioc2 (n = 0, 1) 000 tabnees1 tabnees0 tabnets1 tabnets0 654321 after reset: 00h r/w address: tab0ioc2 fffff544h, tab1ioc2 fffff564h tabnets1 0 0 1 1 tabnets0 0 1 0 1 external trigger input signal (tiab00/trgab1 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the t abnees1, tabnees0, tabnets1, and tabnets0 bits when the tabn ctl0.tabnce bit = 0. (the same value can be written when the tabnce bit = 1.) if rewriting was mistakenly perf ormed, clear the tabnce bit to 0 and then set the bits again. 2. the tabnees1 and tabnees0 bits are valid only when the tabnctl1.tabneee bit = 1 or when the external event count mode (tabnctl1.tabnmd2 to tabnctl1.tabnmd0 bits = 001) has been set. 3. the tabnets1 and tabnets0 bits are valid only when the external trigger pulse output mode (tabnctl1.tabnmd2 to tabnctl1.tabnmd0 bits = 010) or the one-shot pulse output mode (tabnctl1.tabnmd2 to tabnctl1.tabnmd0 = 011) is set. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 359 of 1817 sep 19, 2011 (6) tabn i/o control register 4 (tabnioc4) the tabnioc4 register is an 8-bit regi ster that controls the timer output. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. this register is not reset by stopping the timer operation (tabnctl0.tabnce = 0). cautions 1. accessing the tabnioc4 register is prohib ited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates on the subclock and the main clock oscillation is stopped ? when the cpu operates on the internal oscillation clock 2. the tabnioc4 register can be set only in the interval timer mode and free-running timer mode. be sure to set the tabnioc4 regist er to 00h in all other modes (f or details of the mode setting, see 8.4 (2) tabn control register 1 (tabnctl1)). even in free-running timer mode, if the tabnccr0 to tabnccr3 registers are set to the capture function, the setting of the tabnioc4 register becomes invalid. tabnos3 note tabnioc4 (n = 0, 1) tabnor3 note tabnos2 tabnor2 tabnos1 tabnor1 tabnos0 tabnor0 654321 7 0 after reset: 00h r/w address: tab0ioc4 fffff550h, tab1ioc4 fffff570h tabnosm 0 0 1 1 tabnorm 0 1 0 1 toggle control of toabnm pin (m = 0 to 3) no request. normal toggle operation. reset request fix to inactive level upon next match between value of 16-bit counter and value of taanccrm register. set request fix to active level upon next match between value of 16-bit counter and value of taanccrm register. keep request keep the current output level. note the toab03 pin is not provided in the v850es/jh3-e. set the tab0os3 and tab0or3 bits to 0. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 360 of 1817 sep 19, 2011 (7) tabn option register 0 (tabnopt0) the tabnopt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tabnccs3 note 1 tabnccsm 0 1 tabnccrm register capture/compare selection the tabnccsm bit setting is valid only in the free-running timer mode. compare register selected capture register selected tabnopt0 (n = 0, 1) tabnccs2 tabnccs1 tabnccs0 0 tab1cms note 2 tabncuf tabnovf 654321 after reset: 00h r/w address: tab0opt0 fffff545h, tab1opt0 fffff565h tabnovf set (1) reset (0) tabn overflow detection ? the tabnovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an interrupt request signal (inttabnov) is generated at the same time that the tabnovf bit is set to 1. the inttabnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tabnovf bit is not cleared even when the tabnovf bit or the tabnopt0 register are read when the tabnovf bit = 1. ? the tabnovf bit can be both read and written, but the tabnovf bit cannot be set to 1 by software. writing 1 has no effect on the operation of tabn. overflow occurred tabnovf bit 0 written or tabnctl0.tabnce bit = 0 7 <0> notes 1. the tiab03 pin is not provided in the v850es/jh3-e. set the tab0ccs3 bit to 0. 2. the tab1cms bit is used for the mo tor control function. for details, see chapter 11 motor control function . cautions 1. rewrite the tabnccs 3 to tabnccs0 bits when the tabnctl0.tabnce bit = 0. (the same value can be written when the tabnce bit = 1.) if rewriting was mistakenly performed, clear th e tabnce bit to 0 and then set the bits again. 2. be sure to set bit 3 to ?0?. when the motor control function is not used, be sure to also set bit 2 to ?0?. remark m = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 361 of 1817 sep 19, 2011 (8) tabn capture/compare register 0 (tabnccr0) the tabnccr0 register can be used as a capture regi ster or a compare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, according to the setting of the tabnopt0.tabnccs0 bit. in the pulse width measurement mode, the tabnccr0 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the tabnccr0 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tabnccr0 register is prohibite d in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates on the subclock a nd the main clock oscillation is stopped ? when the cpu operates on the internal oscillation clock tabnccr0 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr0 fffff546h, tab1ccr0 fffff566h 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 362 of 1817 sep 19, 2011 (a) function as compare register the tabnccr0 register can be rewritten even when the tabnctl0.tabnce bit = 1. the set value of the tabnccr0 register is transferred to the ccr0 buffer register. when the value of the 16- bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttabncc0) is generated. if toabn0 pin output is enab led at this time, the output of the toabn0 pin is inverted. when the tabnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse out put mode, pwm output mode, or triangular wave pwm mode, the value of the 16-bit counter is cleared (0000h) if its count value matches the value of the ccr0 buffer register. (b) function as capture register when the tabnccr0 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the tabnccr0 register if the valid edge of the captur e trigger input pin (tiabn0 pin) is detected. in the pulse width measurement mode, the count value of the 16-bit counter is stored in the tabnccr0 register and the 16-bit counter is cleared (000 0h) if the valid edge of the capture trigger input pin (tiabn0 pin) is detected. even if the capture operation and reading the tabnccr0 register conflict, the correct value of the tabnccr0 register can be read. remark n = 0, 1 the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 8-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? triangular wave pwm mode compare register batch write v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 363 of 1817 sep 19, 2011 (9) tabn capture/compare register 1 (tabnccr1) the tabnccr1 register can be used as a capture regi ster or a compare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, according to the setting of the tabnopt0.tabnccs1 bit. in the pulse width measurement mode, the tabnccr1 register can be used only as a capture register. in an y other mode, this register can be used only as a compare register. the tabnccr1 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tabnccr1 register is prohibite d in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates on the subclock a nd the main clock oscillation is stopped ? when the cpu operates on the internal oscillation clock tabnccr1 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr1 fffff548h, tab1ccr1 fffff568h 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 364 of 1817 sep 19, 2011 (a) function as compare register the tabnccr1 register can be rewritten even when the tabnctl0.tabnce bit = 1. the set value of the tabnccr1 register is transferred to the ccr1 buffer register. when the value of the 16- bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttabncc1) is generated. if toabn1 pin output is enabled at this time , the output of the toabn1 pin is inverted. (b) function as capture register when the tabnccr1 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the tabnccr1 register if the valid edge of the captur e trigger input pin (tiabn1 pin) is detected. in the pulse width measurement mode, the count value of the 16-bit counter is stored in the tabnccr1 register and the 16-bit counter is cleared (000 0h) if the valid edge of the capture trigger input pin (tiabn1 pin) is detected. even if the capture operation and reading the tabnccr1 register conflict, the correct value of the tabnccr1 register can be read. remark n = 0, 1 the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 8-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? triangular wave pwm mode compare register batch write v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 365 of 1817 sep 19, 2011 (10) tabn capture/compare register 2 (tabnccr2) the tabnccr2 register can be used as a capture regi ster or a compare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, according to the setting of the tabnopt0.tabnccs2 bit. in the pulse width measurement mode, the tabnccr2 register can be used only as a capture register. in any ot her mode, this register can be used only as a compare register. the tabnccr2 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tabnccr2 register is prohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tabnccr2 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr2 fffff54ah, tab1ccr2 fffff56ah 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 366 of 1817 sep 19, 2011 (a) function as compare register the tabnccr2 register can be rewritten even when the tabnctl0.tabnce bit = 1. the set value of the tabnccr2 register is transferred to the ccr2 buffer register. when the value of the 16- bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (inttabncc2) is generated. if toabn2 pin output is enabled at this time , the output of the toabn2 pin is inverted. (b) function as capture register when the tabnccr2 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the tabnccr2 register if the valid edge of the captur e trigger input pin (tiabn2 pin) is detected. in the pulse width measurement mode, the count value of the 16-bit counter is stored in the tabnccr2 register and the 16-bit counter is cleared (000 0h) if the valid edge of the capture trigger input pin (tiabn2 pin) is detected. even if the capture operation and reading the tabnccr2 register conflict, the correct value of the tabnccr2 register can be read. remark n = 0, 1 the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 8-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? triangular wave pwm mode compare register batch write v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 367 of 1817 sep 19, 2011 (11) tabn capture/compare register 3 (tabnccr3) the tabnccr3 register can be used as a capture register or a compare r egister depending on the mode. (note that the tiab03 pin is not provided in the v850es/jh3-e. theref ore, when using the v850es/jh3-e, the tab0ccr3 register can be used only as a compare register.) this register can be used as a capt ure register or a compare register only in the free-running timer mode, according to the setting of the tabnopt0.tabnccs3 bit. in the pulse width measurement mode, the tabnccr3 register can be used only as a capture register. in any ot her mode, this register can be used only as a compare register. the tabnccr3 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tabnccr3 register is prohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tabnccr3 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr3 fffff54ch, tab1ccr3 fffff56ch 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 368 of 1817 sep 19, 2011 (a) function as compare register the tabnccr3 register can be rewritten even when the tabnctl0.tabnce bit = 1. the set value of the tabnccr3 register is transferred to the ccr3 buffer register. when the value of the 16- bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (inttabncc3) is generated. if toabn3 pin output is enabled at this time , the output of the toabn3 pin is inverted. (b) function as capture register when the tabnccr3 register is used as a capture register in the free-runni ng timer mode, the count value of the 16-bit counter is stored in the tabnccr3 register if the valid edge of the captur e trigger input pin (tiabn3 pin) is detected. in the pulse width measurement mode, the count value of the 16-bit counter is stored in the tabnccr3 register and the 16-bit counter is cleared (000 0h) if the valid edge of the capture trigger input pin (tiabn3 pin) is detected. even if the capture operation and reading the tabnccr3 register conflict, the correct value of the tabnccr3 register can be read. remark n = 0, 1 the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 8-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write one-shot pulse output compare register anytime write pwm output compare register batch write free-running timer capture/compare register anytime write pulse width measurement capture register ? triangular wave pwm mode compare register batch write v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 369 of 1817 sep 19, 2011 (12) tabn counter read bu ffer register (tabncnt) the tabncnt register is a read buffer register t hat can read the count va lue of the 16-bit counter. if this register is read when the tabnctl0.tabnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only in 16-bit units. the value of the tabncnt register is cleared to 0000h when the tabnce bit = 0. if the tabncnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tabncnt register is cleared to 0000 h after reset, as the tabnce bit is cleared to 0. caution accessing the tabncnt register is prohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tabnccr0 (n = 0, 1) 12 10 8 6 4 2 after reset: 0000h r/w address: tab0ccr0 fffff546h, tab1ccr0 fffff566h 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 370 of 1817 sep 19, 2011 8.5 operation tabn can perform the following operations. operation tabnctl1.tabnest bit (software trigger bit) tiabn0 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable triangular wave pwm mode invalid invalid compare only batch write notes 1. to use the external event count mode, specify that t he valid edge of the tiabn0 pin capture trigger input is not detected (by clearing the tabnioc1.tabnis1 and tabnioc1.tabnis0 bits to ?00?). 2. when using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tabnctl1.tabneee bit to 0). remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 371 of 1817 sep 19, 2011 8.5.1 interval timer mode (t abnmd2 to tabnmd0 bits = 000) in the interval timer mode, an interrupt request signal (i nttabncc0) is generated at the specified interval if the tabnctl0.tabnce bit is set to 1. a square wave whose half cycle is equal to the interval can be output from the toabn0 pin. usually, the tabnccr1 to tabnccr3 registers are not used in the interval timer mode. figure 8-2. configuration of interval timer 16-bit counter output controller ccr0 buffer register tabnce bit tabnccr0 register count clock selection clear match signal toabn0 pin inttabncc0 signal remark n = 0, 1 figure 8-3. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tabnce bit tabnccr0 register toabn0 pin output inttabncc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 372 of 1817 sep 19, 2011 when the tabnce bit is set to 1, the value of the 16-bi t counter is cleared from ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the output of the toabn0 pin is inverted. additionally, the set value of the tabnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the toabn0 pin is inverted, and a compare match interrupt request signal (inttabncc0) is generated. the interval can be calculated by the following expression. interval = (set value of tabnccr0 register + 1) count clock cycle figure 8-4. register setting for in terval timer mode operation (1/2) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce (b) tabn control register 1 (tabnctl1) 0 0 0/1 note 00 tabnctl1 0, 0, 0: interval timer mode 000 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest tabnsye 0: operate on count clock selected by bits tabncks0 to tabncks2 1: count with external event count input signal note this bit can be set to 1 only when the interrupt request signals (inttabncc0 and inttabncck) are masked by the interrupt mask flags (tabnccmk0 to tabnccmkk) and the timer output (toabnk) is performed at the same time. however, the tabnccr0 and tabnccrk registers must be set to the same value (see 8.5.1 (2) (d) operation of tabnccr1 to tabnccr3 registers ) (k = 1 to 3). remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 373 of 1817 sep 19, 2011 figure 8-4. register setting for in terval timer mode operation (2/2) (c) tabn i/o control register 0 (tabnioc0) 0/1 note 0/1 note 0/1 0/1 0/1 tabnioc0 0: disable toabn0 pin output 1: enable toabn0 pin output setting of output level with operation of toabn0 pin disabled 0: low level 1: high level 0: disable toabn1 pin output 1: enable toabn1 pin output setting of output level with operation of toabn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tabnoe1 tabnol0 tabnoe0 tabnol1 0: disable toabn2 pin output 1: enable toabn2 pin output setting of output level with operation of toabn2 pin disabled 0: low level 1: high level 0: disable toabn3 pin output 1: enable toabn3 pin output setting of output level with operation of toabn3 pin disabled 0: low level 1: high level tabnoe3 tabnol2 tabnoe2 tabnol3 (d) tabn counter read buffer register (tabncnt) by reading the tabncnt regist er, the count value of the 16-bit counter can be read. (e) tabn capture/compare register 0 (tabnccr0) if the tabnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tabn capture/compare register s 1 to 3 (tabnccr 1 to tabnccr3) usually, the tabnccr1 to tabnccr3 registers are not used in the interval timer mode. however, the set value of the tabnccr1 to tabnccr3 registers is transferred to the ccr1 to ccr3 buffer registers. the compare match interrupt request signals (inttabnccr1 to inttabnccr3) are generated when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 buffer registers. therefore, mask the interrupt requests by using the corresponding interrupt mask flags (tabnccmk1 to tabnccmk3). note the tiab03 pin is not provided in the v850es/jh3- e. set the tab0ol3 and tab0oe3 bits to 0. remarks 1. tabn i/o control register 1 (tabnioc1), tabn i/o control register 2 (tabnioc2), and tabn option register 0 (tabnopt0) are not used in the interval timer mode. 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 374 of 1817 sep 19, 2011 (1) interval timer mode operation flow figure 8-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tabnce bit tabnccr0 register toabn0 pin output inttabncc0 signal d 0 d 0 d 0 d 0 <1> <2> tabnce bit = 1 tabnce bit = 0 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits) tabnctl1 register, tabnioc0 register, tabnccr0 register the initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time when counting has been started (tabnce bit = 1). the counter is initialized and counting is stopped by clearing the tabnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 375 of 1817 sep 19, 2011 (2) interval timer mode operation timing (a) operation if tabnccr0 register is set to 0000h if the tabnccr0 register is set to 0000h, the in ttabncc0 signal is generated at each count clock subsequent to the first count clock, and t he output of the toabn0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tabnce bit tabnccr0 register toabn0 pin output inttabncc0 signal 0000h interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0, 1 (b) operation if tabnccr0 register is set to ffffh if the tabnccr0 register is set to ffffh, the 16-bit counter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing . the inttabncc0 signal is generated and the output of the toabn0 pin is inverted. at this time, an overfl ow interrupt request signal (inttabnov) is not generated, nor is the overflow flag (tabnopt0.tabnovf bit) set to 1. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register toabn0 pin output inttabncc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 376 of 1817 sep 19, 2011 (c) notes on rewriting tabnccr0 register to change the value of the tabnccr0 register to a sm aller value, stop counting once and then change the set value. if the value of the tabnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register tabnol0 bit toabn0 pin output inttabncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0, 1 if the value of the tabnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tabnccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttabncc0 signal is generated and the output of the toabn0 pin is inverted. therefore, the inttabncc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 377 of 1817 sep 19, 2011 (d) operation of tabnccr 1 to tabnccr3 registers figure 8-6. configuration of tabnccr1 to tabnccr3 registers ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttabncc0 signal toabn3 pin note inttabncc3 signal toabn0 pin tabnccr1 register ccr1 buffer register match signal toabn1 pin inttabncc1 signal tabnccr3 register ccr3 buffer register match signal toabn2 pin inttabncc2 signal tabnccr2 register ccr2 buffer register match signal output controller count clock selection output controller output controller output controller 16-bit counter note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 378 of 1817 sep 19, 2011 if the set value of the tabnccrk register is less than the set value of the tabnccr0 register, the inttabncck signal is generated once per cycle. at the same time, the output of the toabnk pin is inverted. the toabnk pin outputs a square wave with the same cycle as that output by the toabn0 pin. remark k = 1 to 3, n = 0, 1 figure 8-7. timing chart when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register toabn0 pin output inttabncc0 signal tabnccr1 register toabn1 pin output inttabncc1 signal tabnccr2 register toabn2 pin output inttabncc2 signal tabnccr3 register toabn3 pin output note inttabncc3 signal note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 379 of 1817 sep 19, 2011 if the set value of the tabnccrk register is greater than the set value of the tabnccr0 register, the count value of the 16-bit counter does not match the va lue of the tabnccrk register. consequently, the inttabncck signal is not generated, nor is the output of the toabnk pin changed. remark k = 1 to 3, n = 0, 1 figure 8-8. timing chart when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register toabn0 pin output inttabncc0 signal tabnccr1 register toabn1 pin output inttabncc1 signal tabnccr2 register toabn2 pin output inttabncc2 signal tabnccr3 register toabn3 pin output note inttabncc3 signal note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 380 of 1817 sep 19, 2011 8.5.2 external event count mode (tabnmd2 to tabnmd0 bits = 001) in the external event count mode, the valid edge of the external event count input is counted when the tabnctl0.tabnce bit is set to 1, and an interrupt request signal (inttabncc0) is generated each time the specified number of edges have been counted. the toabn0 pin cannot be used. usually, the tabnccr1 to tabnccr3 registers are not used in the external event count mode. figure 8-9. configuration in external event count mode 16-bit counter ccr0 buffer register tabnce bit tabnccr0 register edge detector clear match signal inttabncc0 signal tiab00 pin note (external event count input) note tab1: evtab1 pin figure 8-10. basic timing in external event count mode ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal d 0 d 0 d 0 d 0 16-bit counter tabnccr0 register inttabncc0 signal external event count input (tiab00 pin input) note d 0 external event count interval (d 0 + 1) d 0 ? 1d 0 0000 0001 external event count interval (d 0 + 1) external event count interval (d 0 + 1) note tab1: evtab1 pin remark this figure shows the basic timing when the rising edg e is specified as the va lid edge of the external event count input. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 381 of 1817 sep 19, 2011 when the tabnce bit is set to 1, the value of the 16-bit c ounter is cleared from ffffh to 0000h. the counter counts each time the valid edge of the external event count input is detected. additionally, the set value of the tabnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (inttabncc0) is generated. the inttabncc0 signal is generated each time the valid edge of the external event count input has been detected (set value of tabnccr0 register + 1) times. figure 8-11. register setting for operati on in external event count mode (1/2) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 0: stop counting 1: enable counting 000 tabncks2 tabncks1 tabncks0 tabnce (b) tabn control register 1 (tabnctl1) 00000 tabnctl1 0, 0, 1: external event count mode 001 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest tabnsye (c) tabn i/o control register 0 (tabnioc0) 00000 tabnioc0 0: disable toabn0 pin output 0: disable toabn1 pin output 000 tabnoe1 tabnol0 tabnoe0 tabnol1 tabnoe3 tabnol2 tabnoe2 tabnol3 0: disable toabn2 pin output 0: disable toabn3 pin output (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external event count input 0/1 0 0 tabnees0 tabnets1 tabnets0 tabnees1 remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 382 of 1817 sep 19, 2011 figure 8-11. register setting for operati on in external event count mode (2/2) (e) tabn counter read buffer register (tabncnt) the count value of the 16-bit counter can be read by reading the tabncnt register. (f) tabn capture/compare register 0 (tabnccr0) if d 0 is set to the tabnccr0 register, the counter is cleared and a compare match interrupt request signal (inttabncc0) is generated when the num ber of external event counts reaches (d 0 + 1). (g) tabn capture/compare register s 1 to 3 (tabnccr1 to tabnccr3) usually, the tabnccr1 to tabnccr3 registers are not used in the external event count mode. however, the set value of the tabnccr1 to tabnccr3 registers are transferred to the ccr1 to ccr3 buffer registers. when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 buffer registers, compare match interrupt request signals (inttabncc1 to inttabncc3) are generated. therefore, mask the interrupt signals by using the interrupt mask flags (tabnccmk1 to tabnccmk3). caution for tab0, when an external clock is used as the count clock, the external clock can be input only from the tiab00 pin. at th is time, set the tab0ioc1.tab0is1 and tab0ioc1.tab0is0 bits to 00 (capture trigge r input (tiab00 pin): no edge detection). remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the external event count mode. 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 383 of 1817 sep 19, 2011 (1) external event count mode operation flow figure 8-12. flow of software processing in external event count mode ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal d 0 d 0 d 0 d 0 <1> <2> tabnce bit = 1 tabnce bit = 0 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits) tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnccr0 register the initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time when counting has been started (tabnce bit = 1). the counter is initialized and counting is stopped by clearing the tabnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 384 of 1817 sep 19, 2011 (2) operation timing in external event count mode cautions 1. in the external event count mode , do not set the tabnc cr0 register to 0000h. 2. in the external event count mode, use of th e timer output is disabled. if performing timer output using external event count input, set the interval timer mode, and select the operation enabled by the external event count input for the count clock (tabnctl1.tabnmd2 to tabnctl1.tabnmd0 bits = 000, tabnctl1.tabneee bit = 1). (a) operation if tabnccr0 register is set to ffffh if the tabnccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-b it counter is cleared to 0000h in synchronization with the next count-up timing, and the inttabncc0 signal is generated. at this time, the tabnopt0.tabnovf bit is not set. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal ffffh external event count signal interval external event count signal interval external event count signal interval remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 385 of 1817 sep 19, 2011 (b) notes on rewriting the tabnccr0 register to change the value of the tabnccr0 register to a sm aller value, stop counting once and then change the set value. if the value of the tabnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count signal interval (1) (d 1 + 1) external event count signal interval (ng) (10000h + d 2 + 1) external event count signal interval (2) (d 2 + 1) remark n = 0, 1 if the value of the tabnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tabnccr0 register has been rewritten. consequently, the value that is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttabncc0 signal is generated. therefore, the inttabncc0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be generated at the valid edge count of ?(10000h + d 2 + 1) times?. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 386 of 1817 sep 19, 2011 (c) operation of tabnccr1 to tabnccr3 registers figure 8-13. configuration of tabnccr1 to tabnccr3 registers ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttabncc0 signal inttabncc3 signal tiab00 pin note tabnccr1 register ccr1 buffer register match signal inttabncc1 signal tabnccr3 register ccr3 buffer register match signal inttabncc2 signal tabnccr2 register ccr2 buffer register match signal 16-bit counter edge detector note tab1: evtab1 pin remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 387 of 1817 sep 19, 2011 if the set value of the tabnccrk register is smalle r than the set value of the tabnccr0 register, the inttabncck signal is generated once per cycle. remark k = 1 to 3, n = 0, 1 figure 8-14. timing chart when d 01 d k1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal tabnccr1 register inttabncc1 signal tabnccr2 register inttabncc2 signal tabnccr3 register inttabncc3 signal remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 388 of 1817 sep 19, 2011 if the set value of the tabnccrk register is greater than the set value of t he tabnccr0 register, the inttabncck signal is not generated because the coun t value of the 16-bit counter and the value of the tabnccrk register do not match. remark k = 1 to 3, n = 0, 1 figure 8-15. timing chart when d 01 < d k1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal tabnccr1 register inttabncc1 signal tabnccr2 register inttabncc2 signal tabnccr3 register inttabncc3 signal remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 389 of 1817 sep 19, 2011 8.5.3 external trigger pulse output m ode (tabnmd2 to tabnmd0 bits = 010) in the external trigger pulse output mode, tabn waits for a trigger when the tabnctl0.tabnce bit is set to 1. when the valid edge of the external trigger in put signal is detected, tabn starts count ing, and outputs a pwm waveform from the toabn1 to toabn3 pins. pulses can also be output by generating a software trigger inst ead of using the external trigger. when using a software trigger, a square wave that has one cycle of the pwm waveform as half its cycle can also be output from the toabn0 pin. figure 8-16. configuration in external trigger pulse output mode ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttabncc0 signal toabn3 pin note 2 inttabncc3 signal toabn0 pin tiab00 pin note 1 transfer s r tabnccr1 register ccr1 buffer register match signal toabn1 pin inttabncc1 signal transfer transfer s r tabnccr3 register ccr3 buffer register match signal transfer toabn2 pin inttabncc2 signal s r tabnccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller output controller (rs-ff) output controller notes 1. tab1: trgab1 pin 2. the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 390 of 1817 sep 19, 2011 figure 8-17. basic timing in exte rnal trigger pulse output mode d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 1 d 2 d 3 active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 3 ) active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) wait for trigger active level width (d 3 ) cycle (d 0 + 1) ffffh 16-bit counter 0000h tabnce bit external trigger input (tiab00 pin input) note 1 tabnccr0 register inttabncc0 signal toabn0 pin output (only when software trigger is used) tabnccr1 register inttabncc1 signal toabn1 pin output tabnccr2 register inttabncc2 signal toabn2 pin output tabnccr3 register inttabncc3 signal toabn3 pin output note 2 active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) d 0 d 1 d 3 d 2 d 0 d 0 d 0 d 0 notes 1. tab1: trgab1 pin 2. the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 391 of 1817 sep 19, 2011 tabn waits for a trigger when the tabnce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting at the same time, and output s a pwm waveform from the toabnk pin. if the trigger is generated again while the counter is op erating, the counter is cleared to 00 00h and restarted. (the output of the toabn0 pin is inverted. the toabnk pin outputs a high leve l regardless of the status (high/low) when a trigger is generated.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tabnccrk register) count clock cycle cycle = (set value of tabnccr0 register + 1) count clock cycle duty factor = (set value of tabnccrk register)/(set value of tabnccr0 register + 1) the compare match request signal (inttabncc0) is generat ed when the 16-bit counter counts up next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is clear ed to 0000h. the compare match interrupt request signal (inttabncck) is generated when the count value of the 16-bi t counter matches the value of the ccrk buffer register. the value set to the tabnccrm register is transferred to t he ccrm buffer register when the count value of the 16-bit counter matches the value of the ccr0 buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of the external trigger input signal or setti ng the software trigger (tabnctl1.tabnest bit) to 1 is used as the trigger. remark k = 1 to 3, m = 0 to 3, n = 0, 1 figure 8-18. setting of registers in exte rnal trigger pulse output mode (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce note the setting is invalid when the tabnctl1.tabneee bit = 1. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 392 of 1817 sep 19, 2011 figure 8-18. setting of registers in exte rnal trigger pulse output mode (2/3) (b) tabn control register 1 (tabnctl1) 0 0/1 0/1 0 0 tabnctl1 generate software trigger when 1 is written 010 tabnmd2 tabnmd1 tabnmd0 tabnest 0, 1, 0: external trigger pulse output mode tabneee tabnsye 0: operate on count clock selected by tabncks0 to tabncks2 bits 1: count by external event input signal (c) tabn i/o control register 0 (tabnioc0) 0/1 note 1 0/1 note 1 0/1 0/1 0/1 tabnioc0 0: disable toabn0 pin output 1: enable toabn0 pin output setting of output level while operation of toabn0 pin is disabled 0: low level 1: high level 0: disable toabn1 pin output 1: enable toabn1 pin output specification of active level of toabn1 pin output 0: active-high 1: active-low 0/1 0/1 note 2 0/1 note 2 tabnoe1 tabnol0 tabnoe0 tabnol1 toabnk pin output 16-bit counter ? when tabnolk bit = 0 toabnk pin output 16-bit counter ? when tabnolk bit = 1 tabnoe3 tabnol2 tabnoe2 tabnol3 specification of active level of toabn3 pin output 0: active-high 1: active-low 0: disable toabn2 pin output 1: enable toabn2 pin output specification of active level of toabn2 pin output 0: active-high 1: active-low 0: disable toabn3 pin output 1: enable toabn3 pin output notes 1. the toab03 pin is not provided in the v850es/ jh3-e. set the tab0ol3 and tab0oe3 bits to 0. 2. clear this bit to 0 when the toabn0 pin is not used in the external trigger pulse output mode. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 393 of 1817 sep 19, 2011 figure 8-18. setting of registers in exte rnal trigger pulse output mode (3/3) (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external trigger input 0/1 0/1 0/1 tabnets1 tabnets0 tabnees0 tabnees1 select valid edge of external event count input (e) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register. (f) tabn capture/compare register s 0 to 3 (tabnccr 0 to tabnccr3) if d 0 is set to the tabnccr0 register, d 1 to the tabnccr1 register, d 2 to the tabnccr2 register, and d 3 to the tabnccr3 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle toabn1 pin pwm waveform active level width = d 1 count clock cycle toabn2 pin pwm waveform active level width = d 2 count clock cycle toabn3 pin pwm waveform active level width = d 3 count clock cycle remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the external trigger pulse output mode. 2. updating tabn capture/compare register 2 (tabnccr2) and tabn capture/compare register 3 (tabnccr3) is enabled by writing tabn capture/compare register 1 (tabnccr1). 3. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 394 of 1817 sep 19, 2011 (1) operation flow in extern al trigger pulse output mode figure 8-19. software processing flow in ex ternal trigger pulse output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tabnce bit external trigger input (tiab00 pin input) note 1 tabnccr0 register ccr0 buffer register inttabncc0 signal toabn0 pin output (only when software trigger is used) tabnccr1 register ccr1 buffer register inttabncc1 signal toabn1 pin output tabnccr2 register ccr2 buffer register inttabncc2 signal toabn2 pin output tabnccr3 register ccr3 buffer register inttabncc3 signal toabn3 pin output note 2 d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 11 d 20 d 10 notes 1. tab1: trgab1 pin 2. the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 395 of 1817 sep 19, 2011 figure 8-19. software processing flow in ex ternal trigger pulse output mode (2/2) start <1> count operation start flow tabnce bit = 1 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits), tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnccr0 to tabnccr3 registers the initial setting of these registers is performed before setting the tabnce bit to 1. writing the tabnccr1 register must be performed only when the set duty factor is changed after writing the tabnccr2 and tabnccr3 registers. when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer register. writing the same value to the tabnccr1 register is necessary only when the set duty factor of the toabn2 and toabn3 pin outputs is changed. when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer register. the tabnccr1 register only needs to be written, only when the set duty factor of the toabn1 pin output is changed. when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer register. counting is stopped. the tabncks0 to tabncks2 bits can be set at the same time when counting is enabled (tabnce bit = 1). trigger wait status writing the tabnccr1 register must be performed after writing the tabnccr0, tabnccr2, and tabnccr3 registers. when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer registers. writing the same value to the tabnccr1 register is necessary only when the set cycle is changed. <2> tabnccr0 to tabnccr3 register setting change flow <3> tabnccr0 register setting change flow <4> tabnccr1 to tabnccr3 register setting change flow <5> tabnccr2, tabnccr3 register setting change flow <6> tabnccr1 register setting change flow <7> count operation stop flow tabnce bit = 0 setting of tabnccr2, tabnccr3 registers setting of tabnccr1 register setting of tabnccr2, tabnccr3 registers setting of tabnccr1 register stop setting of tabnccr1 register setting of tabnccr0 register setting of tabnccr1 register setting of tabnccr0, tabnccr2, and tabnccr3 registers setting of tabnccr1 register when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer register. remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 396 of 1817 sep 19, 2011 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tabnccr1 register last. rewrite the tabnccrk register after writing the tabnccr1 register after the inttabncc0 signal is detected. ffffh 16-bit counter 0000h tabnce bit external trigger input (tiab00 pin input) note 1 d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tabnccr0 register ccr0 buffer register inttabncc0 signal tabnccr1 register ccr1 buffer register inttabncc1 signal toabn1 pin output tabnccr2 register ccr2 buffer register inttabncc2 signal toabn2 pin output tabnccr3 register ccr3 buffer register inttabncc3 signal toabn3 pin output note 2 toabn0 pin output (only when software trigger is used) d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 notes 1. tab1: trgab1 pin 2. the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 397 of 1817 sep 19, 2011 to transfer data from the tabnccrm register to the ccrm buffer register, the tabnccr1 register must be written. to change both the cycle and active level width of the pw m waveform at this time, first set the cycle to the tabnccr0 register, set the active level width to the tabnccr2 and tabnccr3 registers, and then set the active level to the tabnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tabnccr0 register, and then write the same value to the tabnccr1 register. to change only the active level width (duty factor) of the pwm waveform, first set the active level to the tabnccr2 and tabnccr3 registers and then set the active level to the tabnccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toabn1 pin, only the tabnccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the toabn2 and toabn3 pins, first set the active level width to the tabnccr 2 and tabnccr3 registers, and then write the same value to the tabnccr1 register. after data is written to the tabnccr1 register, the value written to the tabnccrm register is transferred to the ccrm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value to be compared with the 16-bit counter. to write the tabnccr0 to tabnccr3 registers again afte r writing the tabnccr1 register once, do so after the inttabncc0 signal is generated. otherwise, t he value of the ccrm buffer register may become undefined because the timing of transferring data from the tabnccrm register to the ccrm buffer register conflicts with writing the tabnccrm register. remarks 1. the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. 2. m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 398 of 1817 sep 19, 2011 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tabnccrk register to 0000h. if the set value of the tabnccr0 register is ffffh, the inttabncck signal is generated periodically. count clock 16-bit counter tabnce bit tabnccr0 register tabnccrk register inttabncc0 signal inttabncck signal toabnk pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 l remark k = 1 to 3, n = 0, 1 to output a 100% waveform, set a value of ?set value of tabnccr0 register + 1? to the tabnccrk register. if the set value of the tabn ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tabnce bit tabnccr0 register tabnccrk register inttabncc0 signal inttabncck signal toabnk pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 399 of 1817 sep 19, 2011 (c) conflict between trigger detection and match with ccrk buffer register if the trigger is detected immediately after the intt abncck signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of t he toabnk pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccrk buffer register inttabncck signal toabnk pin output external trigger input (tiab00 pin input) note d k d k ? 1 0000 ffff 0000 shortened d k note tab1: trgab1 pin remark k = 1 to 3, n = 0, 1 if the trigger is detected immediately before the intt abncck signal is generated, the inttabncck signal is not generated, and the 16-bit counter is cleared to 00 00h and continues counting. the output signal of the toabnk pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccrk buffer register inttabncck signal toabnk pin output external trigger input (tiab00 pin input) note d k d k ? 2d k ? 1d k 0000 ffff 0000 0001 extended note tab1: trgab1 pin remark k = 1 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 400 of 1817 sep 19, 2011 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the inttabncc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up. therefore, the active period of the toabnk pin is extended by time from generation of the inttabncc0 signal to trigger detection. 16-bit counter ccr0 buffer register inttabncc0 signal toabnk pin output external trigger input (tiab00 pin input) note d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended note tab1: trgab1 pin remark k = 1 to 3, n = 0, 1 if the trigger is detected immediately before the intt abncc0 signal is generated, the inttabncc0 signal is not generated. the 16-bit counter is cleared to 0000h, the toabnk pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttabncc0 signal toabnk pin output external trigger input (tiab00 pin input) note d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened note tab1: trgab1 pin remark k = 1 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab) r01uh0290ej0300 rev.3.00 page 401 of 1817 sep 19, 2011 (e) generation timing of compare match interrupt request signal (inttabncck) the timing of generation of the inttabncck signal in th e external trigger pulse output mode differs from the timing of other inttabncck signals; the inttabncck signa l is generated when the count value of the 16-bit counter matches the value of the ccrk buffer register. count clock 16-bit counter ccrk buffer register toabnk pin output inttabncck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3, n = 0, 1 usually, the inttabncck signal is generated in synchroni zation with the next count-up after the count value of the 16-bit counter matches the value of the ccrk buffer register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of changin g the output signal of the toabnk pin. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 402 of 1817 sep 19, 2011 8.5.4 one-shot pulse output mode (tabnmd2 to tabnmd0 bits = 011) in the one-shot pulse output mode, tabn waits for a trigger when the tabnctl0.tabnce bit is set to 1. when the valid edge of the external trigger input is detected, tabn starts counting, and outputs a one-s hot pulse from the toabn1 to toabn3 pins. instead of the external trigger, a software trigger can al so be generated to output the pulse. when the software trigger is used, the toabn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 8-20. configuration in one-shot pulse output mode ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttabncc0 signal toabn3 pin note 2 inttabncc3 signal toabn0 pin tiab00 pin note 1 transfer s r s r tabnccr1 register ccr1 buffer register match signal toabn1 pin inttabncc1 signal transfer transfer s r tabnccr3 register ccr3 buffer register match signal transfer toabn2 pin inttabncc2 signal s r tabnccr2 register ccr2 buffer register match signal 16-bit counter count clock selection count start control edge detector software trigger generation output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) notes 1. tab1: trgab1 pin 2. the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 403 of 1817 sep 19, 2011 figure 8-21. basic timing in one-shot pulse output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) ffffh 16-bit counter 0000h tabnce bit external trigger input (tiab00 pin input) note 1 tabnccr0 register inttabncc0 signal tabnccr2 register inttabncc2 signal toabn2 pin output tabnccr3 register inttabncc3 signal toabn3 pin output note 2 tabnccr1 register inttabncc1 signal toabn1 pin output toabn0 pin output (only when software trigger is used) notes 1. tab1: trgab1 pin 2. the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 404 of 1817 sep 19, 2011 when the tabnce bit is set to 1, tabn waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting, a nd outputs a one-shot pulse from the toabn k pin. after the one-shot pulse is output, the 16-bit counter is set to ffffh, stops counting, and wa its for a trigger. if a trigger is generated ag ain while the one-shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tabnccrk register) count clock cycle active level width = (set value of tabnccr0 register ? set value of tabnccrk register + 1) count clock cycle the compare match interrupt request signal inttabncc0 is generated when the 16-bit counter counts up after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal (inttabncck) is generated when the count value of the 16-bit counter matches the val ue of the ccrk buffer register. the valid edge of the external trigger input or setting the software trigger (tabnctl1.tabnest bit) to 1 is used as the trigger. remark k = 1 to 3, n = 0, 1 figure 8-22. register setting for operati on in one-shot pulse output mode (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce (b) tabn control register 1 (tabnctl1) 0 0/1 0/1 0 0 tabnctl1 generate software trigger when 1 is written 011 tabnmd2 tabnmd1 tabnmd0 tabnest 0, 1, 1: one-shot pulse output mode tabneee tabnsye 0: operate on count clock selected by tabncks0 to tabncks2 bits 1: count by external event count input signal note the setting is invalid when the tabnctl1.tabneee bit = 1. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 405 of 1817 sep 19, 2011 figure 8-22. register setting for operati on in one-shot pulse output mode (2/3) (c) tabn i/o control register 0 (tabnioc0) toabnk pin output 16-bit counter ? when tabnolk bit = 0 toabnk pin output 16-bit counter ? when tabnolk bit = 1 0/1 note 1 0/1 note 1 0/1 0/1 0/1 tabnioc0 0: disable toabn0 pin output 1: enable toabn0 pin output setting of output level while operation of toabn0 pin is disabled 0: low level 1: high level 0: disable toabn1 pin output 1: enable toabn1 pin output specification of active level of toabn1 pin output 0: active-high 1: active-low 0/1 0/1 note 2 0/1 note 2 tabnoe1 tabnol0 tabnoe0 tabnol1 tabnoe3 tabnol2 tabnoe2 tabnol3 specification of active level of toabn3 pin output 0: active-high 1: active-low 0: disable toabn2 pin output 1: enable toabn2 pin output specification of active level of toabn2 pin output 0: active-high 1: active-low 0: disable toabn3 pin output 1: enable toabn3 pin output (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external trigger input 0/1 0/1 0/1 tabnets1 tabnets0 tabnees0 tabnees1 select valid edge of external event count input (e) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register. notes 1. the tiab03 pin is not provided in the v850es/jh 3-e. set the tab0ol3 and tab0oe3 bits to 0. 2. clear this bit to 0 when the toabn0 pin is not used in the one-shot pulse output mode. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 406 of 1817 sep 19, 2011 figure 8-22. register setting for operati on in one-shot pulse output mode (3/3) (f) tabn capture/compare register s 0 to 3 (tabnccr 0 to tabnccr3) if d 0 is set to the tabnccr0 register and d k to the tabnccrk register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d k + 1) count clock cycle output delay period = (d k ) count clock cycle caution one-shot pulses are not output even in the one-shot pulse out put mode, if the set value of the tabnccrk register is greater than that value of the tabnccr0 register. remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the one-shot pulse output mode. 2. k = 1 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 407 of 1817 sep 19, 2011 (1) operation flow in one-shot pulse output mode figure 8-23. software processing flow in one-shot pulse output mode (1/2) ffffh 16-bit counter 0000h tabnce bit external trigger input (tiab00 pin input) note 1 tabnccr0 register inttabncc0 signal toabn0 pin output (only when software trigger is used) tabnccr1 register inttabncc1 signal toabn1 pin output tabnccr2 register inttabncc2 signal toabn2 pin output tabnccr3 register inttabncc3 signal toabn3 pin output note 2 d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 d 10 d 20 d 30 d 11 d 21 d 31 d 00 d 01 <3> <1> <2> notes 1. tab1: trgab1 pin 2. the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 408 of 1817 sep 19, 2011 figure 8-23. software processing flow in one-shot pulse output mode (2/2) tabnce bit = 1 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits), tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnccr0 to tabnccr3 registers the initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time when counting has been started (tabnce bit = 1). trigger wait status start <1> count operation start flow tabnce bit = 0 count operation is stopped stop <3> count operation stop flow setting of tabnccr0 to tabnccr3 registers as rewriting the tabnccrm register immediately sends the data to the ccrm buffer register, rewriting immediately after the generation of the inttabnccr0 signal is recommended. <2> tabnccr0 to tabnccr3 register setting change flow remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 409 of 1817 sep 19, 2011 (2) operation timing in one-shot pulse output mode (a) notes on rewriting tabnccrm register to change the set value of the tabnccrm register to a smaller value, stop counting once, and then change the set value. if the value of the tabnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. d k0 d k1 d 01 d 01 d 00 d k1 d 01 d k0 d k0 d k1 d 00 d 00 ffffh 16-bit counter 0000h tabnce bit external trigger input (tiab00 pin input) note tabnccr0 register inttabncc0 signal toabn0 pin output (only when software trigger is used) tabnccrk register inttabncck signal toabnk pin output delay (d k0 ) active level width (d 00 ? d k0 + 1) active level width (d 01 ? d k1 + 1) active level width (d 01 ? d k1 + 1) delay (d k1 ) delay (10000h + d k1 ) note tab1: trgab1 pin when the tabnccr0 register is rewritten from d 00 to d 01 and the tabnccrk register from d k0 to d k1 where d 00 > d 01 and d k0 > d k1 , if the tabnccrk register is rewritten when the count value of the 16-bit counter is greater than d k1 and less than d k0 and if the tabnccr0 register is rewri tten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter c ounts up to ffffh and then counts up again from 0000h. when the count value matches d k1 , the counter generates the inttabn cck signal and asserts the toabnk pin. when the count value matches d 01 , the counter generates the inttabncc0 signal, deasserts the toabnk pin, and stops counting. therefore, the counter may output a pu lse with a delay period or active per iod different from that of the one- shot pulse that is originally expected. remark k = 1 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 410 of 1817 sep 19, 2011 (b) generation timing of compare match interrupt request signal (inttabncck) the generation timing of the inttabncck signal in the o ne-shot pulse output mode is different from other inttabncck signals; the inttabncck signal is generated when the count value of t he 16-bit counter matches the value of the tabnccrk register. count clock 16-bit counter tabnccrk register toabnk pin output inttabncck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 usually, the inttabncck signal is generated when the 16-bit counter counts up next time after its count value matches the value of the tabnccrk register. in the one-shot pulse output mode, however, it is gene rated one clock earlier. this is because the timing is changed to match the change timing of the toabnk pin. remark k = 1 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 411 of 1817 sep 19, 2011 8.5.5 pwm output mode (tabnmd 2 to tabnmd0 bits = 100) in the pwm output mode, a pwm waveform is output from the toabn1 to toabn3 pins when the tabnctl0.tabnce bit is set to 1. in addition, a pulse with one cycle of the pwm waveform as half its cycle is output from the toabn0 pin. figure 8-24. configuration in pwm output mode ccr0 buffer register tabnce bit tabnccr0 register clear match signal inttabncc0 signal toabn3 pin note inttabncc3 signal toabn0 pin transfer s r tabnccr1 register ccr1 buffer register match signal toabn1 pin inttabncc1 signal transfer transfer s r tabnccr3 register ccr3 buffer register match signal transfer toabn2 pin inttabncc2 signal s r tabnccr2 register ccr2 buffer register match signal 16-bit counter count clock selection output controller (rs-ff) output controller output controller (rs-ff) output controller (rs-ff) note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 412 of 1817 sep 19, 2011 figure 8-25. basic timing in pwm output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal toabn0 pin output tabnccr1 register inttabncc1 signal toabn1 pin output tabnccr2 register inttabncc2 signal toabn2 pin output tabnccr3 register inttabncc3 signal toabn3 pin output note active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 3 ) active level width (d 3 ) active level width (d 3 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 413 of 1817 sep 19, 2011 when the tabnce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, st arts counting, and outputs a pwm waveform from the toabnk pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tabnccrk register) count clock cycle cycle = (set value of tabnccr0 register + 1) count clock cycle duty factor = (set value of tabnccrk register)/(set value of tabnccr0 register + 1) the pwm waveform can be changed by rewriting the tabnccrm register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the va lue of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal (inttabncc0) is generated when the 16-bit c ounter counts up next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal (inttabncck) is gener ated when the count value of the 16-bit counter matches the value of the ccrk buffer register. remark k = 1 to 3, m = 0 to 3, n = 0, 1 figure 8-26. setting of registers in pwm output mode (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce (b) tabn control register 1 (tabnctl1) 0 0 0/1 0 0 tabnctl1 100 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest tabnsye 1, 0, 0: pwm output mode 0: operate on count clock selected by tabncks0 to tabncks2 bits 1: count by external event count input signal note the setting is invalid when the tabnctl1.tabneee bit = 1. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 414 of 1817 sep 19, 2011 figure 8-26. setting of registers in pwm output mode (2/3) (c) tabn i/o control register 0 (tabnioc0) toabnk pin output 16-bit counter ? when tabnolk bit = 0 toabnk pin output 16-bit counter ? when tabnolk bit = 1 0/1 note 1 0/1 note 1 0/1 0/1 0/1 tabnioc0 0: disable toabn0 pin output 1: enable toabn0 pin output setting of output level while operation of toabn0 pin is disabled 0: low level 1: high level 0: disable toabn1 pin output 1: enable toabn1 pin output specification of active level of toabn1 pin output 0: active-high 1: active-low 0/1 0/1 note 2 0/1 note 2 tabnoe1 tabnol0 tabnoe0 tabnol1 tabnoe3 tabnol2 tabnoe2 tabnol3 specification of active level of toabn3 pin output 0: active-high 1: active-low 0: disable toabn2 pin output 1: enable toabn2 pin output specification of active level of toabn2 pin output 0: active-high 1: active-low 0: disable toabn3 pin output 1: enable toabn3 pin output (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external event count input. 0/1 0 0 tabnees0 tabnets1 tabnets0 tabnees1 (e) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register. notes 1. the tiab03 pin is not provided in the v850es/ jh3-e. set the tab0ol3 and tab0oe3 bits to 0. 2. clear this bit to 0 when the toabn0 pin is not used in the pwm output mode. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 415 of 1817 sep 19, 2011 figure 8-26. register setting in pwm output mode (3/3) (f) tabn capture/compare register s 0 to 3 (tabnccr 0 to tabnccr3) if d 0 is set to the tabnccr0 register and d k to the tabnccrk register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d k count clock cycle remarks 1. tabn i/o control register 1 (tabnioc1) and tabn option register 0 (tabnopt0) are not used in the pwm output mode. 2. updating tabn capture/compare register 2 (tabnccr2) and tabn capture/compare register 3 (tabnccr3) is enabled by writing tabn c apture/compare register 1 (tabnccr1). 3. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 416 of 1817 sep 19, 2011 (1) operation flow in pwm output mode figure 8-27. software processing flow in pwm output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register ccr0 buffer register inttabncc0 signal toabn0 pin output tabnccr1 register ccr1 buffer register inttabncc1 signal toabn1 pin output tabnccr2 register ccr2 buffer register inttabncc2 signal toabn2 pin output tabnccr3 register ccr3 buffer register inttabncc3 signal toabn3 pin output note d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 10 d 20 note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 417 of 1817 sep 19, 2011 figure 8-27. software processing flow in pwm output mode (2/2) start <1> count operation start flow tabnce bit = 1 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits), tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnccr0 to tabnccr3 registers the initial setting of these registers is performed before setting the tabnce bit to 1. writing the tabnccr1 register must be performed only when the set duty factor is changed after writing the tabnccr2 and tabnccr3 registers. when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer register. writing the same value to the tabnccr1 register is necessary only when the set duty factor of toabn2 and toabn3 pin outputs is changed. when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer register. the tabnccr1 register only needs to be written, only when the set duty factor is changed. when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer register. counting is stopped. the tabncks0 to tabncks2 bits can be set at the same time when counting is enabled (tabnce bit = 1). writing the tabnccr1 register must be performed after writing the tabnccr0, tabnccr2, and tabnccr3 registers. when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer registers. writing the same value to tabnccr1 is necessary only when the set cycle is changed. <2> tabnccr0 to tabnccr3 register setting change flow <3> tabnccr0 register setting change flow <4> tabnccr1 to tabnccr3 register setting change flow <5> tabnccr2, tabnccr3 register setting change flow <6> tabnccr1 register setting change flow <7> count operation stop flow tabnce bit = 0 setting of tabnccr2, tabnccr3 registers setting of tabnccr1 register setting of tabnccr2, tabnccr3 registers setting of tabnccr1 register stop setting of tabnccr1 register setting of tabnccr0 register setting of tabnccr1 register setting of tabnccr0, tabnccr2, and tabnccr3 registers setting of tabnccr1 register when the counter is cleared after setting, the value of the tabnccrm register is transferred to the ccrm buffer register. remark k = 1 to 3, m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 418 of 1817 sep 19, 2011 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tabnccr1 register last. rewrite the tabnccrk register after writing the tabnccr1 register after the inttabncc1 signal is detected. ffffh 16-bit counter 0000h tabnce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tabnccr0 register ccr0 buffer register inttabncc0 signal tabnccr1 register ccr1 buffer register inttabncc1 signal toabn1 pin output tabnccr2 register ccr2 buffer register inttabncc2 signal toabn2 pin output tabnccr3 register ccr3 buffer register inttabncc3 signal toabn3 pin output note toabn0 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 note the v850es/jh3-e has the toab13 pin only and doesn?t have the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 419 of 1817 sep 19, 2011 to transfer data from the tabnccrm register to the ccrm buffer register, the tabnccr1 register must be written. to change both the cycle and active leve l of the pwm waveform at this time, first set the cycle to the tabnccr0 register, set the active level width to the tabnccr2 and tabnccr3 registers, and then set the active level width to the tabnccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tabnccr0 register, and then write the same value to the tabnccr1 register. to change only the active level width (duty factor) of the pwm wave, first set the active level to the tabnccr2 and tabnccr3 registers, and then set the ac tive level to the tabnccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toabn1 pin, only the tabnccr1 register has to be set. to change only the active level width (duty factor) of the pwm waveform output by the toabn2 and toabn3 pins, first set the active level width to the tabnccr 2 and tabnccr3 registers, and then write the same value to the tabnccr1 register. after the tabnccr1 register is written, the value writte n to the tabnccrm register is transferred to the ccrm buffer register in synchronization with the timing of clea ring the 16-bit counter, and is used as the value to be compared with the value of the 16-bit counter. to write the tabnccr0 to tabnccr3 registers again afte r writing the tabnccr1 register once, do so after the inttabncc0 signal is generated. otherwise, t he value of the ccrm buffer register may become undefined because the timing of transferring data from the tabnccrm register to the ccrm buffer register conflicts with writing the tabnccrm register. remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 420 of 1817 sep 19, 2011 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tabnccrk register to 0000h. if the set value of the tabnccr0 register is ffffh, the inttabncck signal is generated periodically. count clock 16-bit counter tabnce bit tabnccr0 register tabnccrk register inttabncc0 signal inttabncck signal toabnk pin output d 0 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 l remark k = 1 to 3, n = 0, 1 to output a 100% waveform, set a value of ?set value of tabnccr0 register + 1? to the tabnccrk register. if the set value of the tabn ccr0 register is ffffh, 100% output cannot be produced. count clock 16-bit counter tabnce bit tabnccr0 register tabnccrk register inttabncc0 signal inttabncck signal toabnk pin output d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark k = 1 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 421 of 1817 sep 19, 2011 (c) generation timing of compare match interrupt request signal (inttabncck) the timing of generation of the inttabncck signal in the pwm output mode differs from the timing of other inttabncck signals; the inttabncck signal is generated when the count value of t he 16-bit counter matches the value of the tabnccrk register. count clock 16-bit counter ccrk buffer register toabnk pin output inttabncck signal d k d k ? 2d k ? 1d k d k + 1 d k + 2 remark k = 1 to 3, n = 0, 1 usually, the inttabncck signal is generated in synchroni zation with the next counting up after the count value of the 16-bit counter matches the value of the tabnccrk register. in the pwm output mode, however, it is generated one cl ock earlier. this is because the timing is changed to match the change timing of the out put signal of the toabnk pin. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 422 of 1817 sep 19, 2011 8.5.6 free-running timer mode (tabnmd2 to tabnmd0 bits = 101) in the free-running timer mode, tabn starts counting when t he tabnctl0.tabnce bit is set to 1. at this time, the tabnccrm register can be used as a co mpare register or a capture regist er, according to the setting of the tabnopt0.tabnccs0 and tabnopt0.tabnccs1 bits. remark m = 0 to 3, n = 0, 1 figure 8-28. configuration in free-running timer mode toabn3 pin output note 2 toabn2 pin output toabn1 pin output toabn0 pin output inttabnov signal tabnccs0, tabnccs1 bits (capture/compare selection) inttabncc3 signal inttabncc2 signal inttabncc1 signal inttabncc0 signal tiabn3 pin note 2 (capture trigger input) tabnccr3 note 2 register (capture) tiab00 pin (external event count input note 1 / capture trigger input) internal count clock tabnce bit tiabn1 pin (capture trigger input) tiabn2 pin (capture trigger input) tabnccr0 register (capture) tabnccr1 register (capture) tabnccr2 register (capture) tabnccr3 register (compare) tabnccr2 register (compare) tabnccr1 register (compare) 0 1 0 1 0 1 0 1 16-bit counter tabnccr0 register (compare) output controller output controller output controller output controller count clock selection edge detector edge detector edge detector edge detector edge detector notes 1. tab1: evtab1 pin 2. the tiab03 and toab03 pins are not prov ided in the v850es/jh3-e, and the tab0ccr3 register cannot be used as a capture re gister when using the v850es/jh3-e. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 423 of 1817 sep 19, 2011 when the tabnce bit is set to 1, tabn starts counting, and the output signals of t he toabn0 to toabn3 pins are inverted. when the count value of the 16-bit counter subs equently matches the set value of the tabnccrm register, a compare match interrupt request signal (inttabnccm) is generat ed, and the output signal of the toabnm pin is inverted. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttabnov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tabnopt0.tabnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. the tabnccrm register can be rewritten while the counter is operating. if it is re written, the new value is reflected at that time, and compared with the count value. remark m = 0 to 3, n = 0, 1 figure 8-29. basic timing in free-r unning timer mode (compare function) d 10 d 20 d 30 d 00 d 20 d 31 d 31 d 30 d 00 d 11 d 11 d 21 d 01 d 11 d 21 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h toabn1 pin output tabnccr2 register inttabncc2 signal toabn2 pin output tabnccr3 register inttabncc3 signal toabn3 pin output note inttabnov signal tabnovf bit toabn0 pin output tabnccr1 register inttabncc1 signal tabnce bit tabnccr0 register inttabncc0 signal d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30 note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 424 of 1817 sep 19, 2011 when the tabnce bit is set to 1, the 16 -bit counter starts counting. when t he valid edge input to the tiabnm pin is detected, the count val ue of the 16-bit counter is stor ed in the tabnccrm register, and a capture interrupt request signal (inttabnccm) is generated. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttabnov) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tabnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction by software. remark m = 0 to 3, n = 0, 1 figure 8-30. basic timing in free-r unning timer mode (capture function) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tiabn2 pin input tabnccr2 register inttabncc2 signal tiabn3 pin input note tabnccr3 register note inttabncc3 signal note inttabnov signal tabnovf bit tiabn1 pin input tabnccr1 register inttabncc1 signal tabnce bit tiabn0 pin input tabnccr0 register inttabncc0 signal note the v850es/jh3-e only includes the tiab13 pin; it is not provided with the tiab03 pin. when using the v850es/jh3-e, the tab0ccr3 register and the inttab0ccr3 signal cannot be used. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 425 of 1817 sep 19, 2011 figure 8-31. register setting in free-running timer mode (1/3) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce note the setting is invalid when the tabnctl1.tabneee bit = 1 (b) tabn control register 1 (tabnctl1) 0 0 0/1 0 0 tabnctl1 101 tabnmd2 tabnmd1 tabnmd0 tabneee tabnest tabnsye 1, 0, 1: free-running mode 0: operate with count clock selected by tabncks0 to tabncks2 bits 1: count by external event count input signal (c) tabn i/o control register 0 (tabnioc0) 0/1 note 0/1 note 0/1 0/1 0/1 tabnioc0 0: disable toabn0 pin output 1: enable toabn0 pin output 0: disable toabn1 pin output 1: enable toabn1 pin output setting of output level with operation of toabn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tabnoe1 tabnol0 tabnoe0 tabnol1 tabnoe3 tabnol2 tabnoe2 tabnol3 setting of output level with operation of toabn3 pin disabled 0: low level 1: high level 0: disable toabn2 pin output 1: enable toabn2 pin output setting of output level with operation of toabn2 pin disabled 0: low level 1: high level 0: disable toabn3 pin output 1: enable toabn3 pin output setting of output level with operation of toabn0 pin disabled 0: low level 1: high level note the toab03 pin is not provided in the v850es/jh 3-e. set the tab0ol3 and tab0oe3 bits to 0. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 426 of 1817 sep 19, 2011 figure 8-31. register setting in free-running timer mode (2/3) (d) tabn i/o control register 1 (tabnioc1) 0/1 0/1 0/1 0/1 0/1 tabnioc1 select valid edge of tiabn0 pin input select valid edge of tiabn1 pin input 0/1 0/1 0/1 tabnis2 tabnis1 tabnis0 tabnis3 tabnis6 note tabnis5 tabnis4 tabnis7 note select valid edge of tiabn2 pin input select valid edge of tiabn3 pin input note the tiab03 pin is not provided in the v850es/jh 3-e. set the tab0is7 and tab0is6 bits to 0. (e) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 select valid edge of external event count input 0/1 0 0 tabnees0 tabnets1 tabnets0 tabnees1 (f) tabn option register 0 (tabnopt0) 0/1 note 0/1 note 0/1 0/1 0 tabnopt0 overflow flag specifies if tabnccr0 register functions as capture or compare register specifies if tabnccr1 register functions as capture or compare register 0 0 0/1 tabnccs0 tabnovf tabnccs1 tabnccs2 tabnccs3 specifies if tabnccr2 register functions as capture or compare register specifies if tabnccr3 register functions as capture or compare register note the tab0ccr3 register cannot be used as a capture register in the v850es/jh3-e, so set bits tab0ccs3 and tab0ccs2 to 0. (g) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 427 of 1817 sep 19, 2011 figure 8-31. register setting in free-running timer mode (3/3) (h) tabn capture/compare register s 0 to 3 (tabnccr0 to tabnccr3) these registers function as captur e registers or compare registers according to the setting of the tabnopt0.tabnccsm bit. when the registers function as capture registers, they store the c ount value of the 16-bit counter when the valid edge input to the tiabnm pin is detected. when the registers function as compare registers and when d m is set to the tabnccrm register, the inttabnccm signal is generated when the counter reaches (d m + 1), and the output signal of the toabnm pin is inverted. remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 428 of 1817 sep 19, 2011 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 8-32. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 10 d 20 d 30 d 00 d 10 d 20 d 30 d 00 d 11 d 31 d 01 d 21 d 21 d 11 d 11 d 31 d 01 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal toabn0 pin output tabnccr1 register inttabncc1 signal toabn1 pin output tabnccr2 register inttabncc2 signal toabn2 pin output tabnccr3 register inttabncc3 signal toabn3 pin output note inttabnov signal tabnovf bit d 00 d 10 d 20 d 30 d 01 d 11 d 21 d 31 cleared to 0 by clr instruction set value changed set value changed set value changed set value changed cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 429 of 1817 sep 19, 2011 figure 8-32. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tabnce bit = 1 read tabnopt0 register (check overflow flag). register initial setting tabnctl0 register (tabncks0 to tabncks2 bits), tabnctl1 register, tabnioc0 register, tabnioc2 register, tabnopt0 register, tabnccr0 to tabnccr3 registers the initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time when counting has been started (tabnce bit = 1). start execute instruction to clear tabnovf bit (clr tabnovf). <1> count operation start flow <2> overflow flag clear flow tabnce bit = 0 the counter is initialized and counting is stopped by clearing the tabnce bit to 0. stop <3> count operation stop flow tabnovf bit = 1 no yes remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 430 of 1817 sep 19, 2011 (b) when using capture/compare register as capture register figure 8-33. software processing flow in fr ee-running timer mode (c apture function) (1/2) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 0000 0000 0000 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tabnce bit tiabn2 pin input tabnccr2 register inttabncc2 signal tiabn3 pin input note tabnccr3 register note inttabncc3 signal note inttabnov signal tabnovf bit tiabn1 pin input tabnccr1 register inttabncc1 signal tiabn0 pin input tabnccr0 register inttabncc0 signal note the v850es/jh3-e only includes the tiab13 pin; it is not provided with the tiab03 pin. when using the v850es/jh3-e, the tab0ccr3 register and the inttab0ccr3 signal cannot be used. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 431 of 1817 sep 19, 2011 figure 8-33. software processing flow in fr ee-running timer mode (c apture function) (2/2) tabnce bit = 1 read tabnopt0 register (check overflow flag). register initial setting tabnctl0 register (tabncks0 to tabncks2 bits), tabnctl1 register, tabnioc1 register, tabnopt0 register the initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time when counting has been started (tabnce bit = 1). start execute instruction to clear tabnovf bit (clr tabnovf). <1> count operation start flow <2> overflow flag clear flow tabnce bit = 0 the counter is initialized and counting is stopped by clearing the tabnce bit to 0. stop <3> count operation stop flow tabnovf bit = 1 no yes remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 432 of 1817 sep 19, 2011 (2) operation timing in free-running timer mode (a) interval operation with compare register when tabn is used as an interval timer with the t abnccrm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the inttabnccm signal has been detected. d 00 d 10 d 20 d 01 d 30 d 12 d 03 d 22 d 31 d 21 d 23 d 02 d 13 ffffh 16-bit counter 0000h tabnce bit tabnccr0 register inttabncc0 signal toabn0 pin output tabnccr1 register inttabncc1 signal toabn1 pin output tabnccr2 register inttabncc2 signal toabn2 pin output tabnccr3 register inttabncc3 signal toabn3 pin output note interval period (d 00 + 1) interval period (10000h + d 02 ? d 01 ) interval period (d 01 ? d 00 ) interval period (d 03 ? d 02 ) interval period (d 04 ? d 03 ) d 00 d 01 d 02 d 03 d 04 d 05 interval period (d 10 + 1) interval period (10000h + d 12 ? d 11 ) interval period (d 11 ? d 10 ) interval period (d 13 ? d 12 ) d 10 d 11 d 12 d 13 d 14 interval period (d 20 + 1) interval period (10000h + d 21 ? d 20 ) interval period (10000h + d 23 ? d 22 ) interval period (d 22 ? d 21 ) interval period (d 30 + 1) interval period (10000h + d 31 ? d 30) d 20 d 21 d 22 d 23 d 31 d 30 d 32 d 04 d 11 note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 433 of 1817 sep 19, 2011 when performing an interval operation in the free-running timer mode, four intervals can be set with one channel. to perform the interval operation, the value of the corresponding tabnccrm register must be re-set in the interrupt servicing that is executed when the inttabnccm signal is detected. the set value for re-setting the tabnccrm register c an be calculated by the following expression, where ?d m ? is the interval period. compare register default value: d m ? 1 value set to compare register second and subsequent times: previous set value + d m (if the calculation resu lt is greater than ffffh, subtract 10000h fr om the result and set this value to the register.) remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 434 of 1817 sep 19, 2011 (b) pulse width measurement with capture register when pulse width measurement is performed with the tabnccrm register used as a capture register, software processing is necessary for reading the captur e register each time the inttabnccm signal has been detected and for calculating an interval. d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 32 d 13 d 03 d 22 d 33 d 23 0000 pulse interval (10000h + d 01 ? d 00 ) pulse interval (10000h + d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) d 00 d 01 d 02 d 03 pulse interval (d 00 + 1) 0000 pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (d 13 ? d 12 ) d 10 d 11 d 12 d 13 pulse interval (d 10 + 1) 0000 pulse interval (10000h + d 21 ? d 20 ) pulse interval (20000h + d 22 ? d 21 ) pulse interval (d 23 ? d 22 ) d 20 d 21 d 23 d 22 pulse interval (d 20 + 1) 0000 pulse interval (10000h + d 31 ? d 30 ) pulse interval (10000h + d 32 ? d 31 ) pulse interval (10000h + d 33 ? d 32 ) d 30 d 31 d 32 d 33 pulse interval (d 30 + 1) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tabnce bit tiabn0 pin input tabnccr0 register inttabncc0 signal tiabn2 pin input tabnccr2 register inttabncc2 signal tiabn3 pin input note tabnccr3 register note inttabncc3 signal note inttabnov signal tabnovf bit tiabn1 pin input tabnccr1 register inttabncc1 signal note the v850es/jh3-e only includes the tiab13 pin; it is not provided with the tiab03 pin. when using the v850es/jh3-e, the tab0ccr3 regist er and the inttab0ccr3 signal cannot be used. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 435 of 1817 sep 19, 2011 when executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calculat ed by reading the value of the tabnccrm register in synchronization with the inttabnccm signal, and calculat ing the difference between the value read this time and the previously read value. remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 436 of 1817 sep 19, 2011 (c) processing of overflow when two or more capture registers are used care must be exercised in processing the overflow flag when two or more capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when tw o or more capture registers are used ffffh 16-bit counter 0000h tabnce bit tiabn0 pin input tabnccr0 register tiabn1 pin input tabnccr1 register inttabnov signal tabnovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tabnccr0 register (setting of t he default value of the tiabn0 pin input). <2> read the tabnccr1 register (setting of t he default value of the tiabn1 pin input). <3> read the tabnccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tabnccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). remark n = 0, 1 when two or more capture registers ar e used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two or more capture registers. an example of how to use software is shown below. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 437 of 1817 sep 19, 2011 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tabnce bit inttabnov signal tabnovf bit tabnovf0 flag note tiabn0 pin input tabnccr0 register tabnovf1 flag note tiabn1 pin input tabnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tabnovf0 and tabnovf1 flags are set in the internal ram by software. <1> read the tabnccr0 register (setting of t he default value of the tiabn0 pin input). <2> read the tabnccr1 register (setting of t he default value of the tiabn1 pin input). <3> an overflow occurs. set the tabnovf0 and tabnov f1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tabnccr0 register. read the tabnovf0 flag. if the tabnovf0 flag is 1, clear it to 0. because the tabnovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tabnccr1 register. read the tabnovf1 flag. if the tabnovf1 flag is 1, clear it to 0 (the tabnovf0 flag is cleared in <4>, and the tabnovf1 flag remains 1). because the tabnovf1 flag is 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 438 of 1817 sep 19, 2011 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tabnce bit inttabnov signal tabnovf bit tabnovf0 flag note tiabn0 pin input tabnccr0 register tabnovf1 flag note tiabn1 pin input tabnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tabnovf0 and tabnovf1 flags are set in the internal ram by software. <1> read the tabnccr0 register (setting of t he default value of the tiabn0 pin input). <2> read the tabnccr1 register (setting of t he default value of the tiabn1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tabnccr0 register. read the overflow flag. if the overflow flag is 1, set only the tabnovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tabnccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tabnovf1 flag. if the tabnovf1 flag is 1, clear it to 0. because the tabnovf1 flag is 1, the pul se width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 439 of 1817 sep 19, 2011 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tabnce bit tiabnm pin input tabnccrm register inttabnov signal tabnovf bit d m0 d m1 d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when a long pulse width is measured in the free-running timer mode. <1> read the tabnccrm register (setting of t he default value of the tiabnm pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tabnccrm register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d m1 ? d m0 ) (incorrect). actually, the pulse width must be (20000h + d m1 ? d m0 ) because an overflow occurs twice. remark m = 0 to 3, n = 0, 1 if an overflow occurs twice or more when the capture trigge r interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 440 of 1817 sep 19, 2011 example when capture trigger interval is long ffffh 16-bit counter 0000h tabnce bit tiabnm pin input tabnccrm register inttabnov signal tabnovf bit overflow counter note d m0 d m1 1h 0h 2h 0h d m0 d m1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software in the internal ram. <1> read the tabnccrm register (setting of t he default value of the tiabnm pin input). <2> an overflow occurs. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tabnccrm register. read the overflow counter. when the overflow counter is ?n?, the pulse width can be calculated by (n 10000h + d m1 ? d m0 ). in this example, the pulse width is (20000h + d m1 ? d m0 ) because an overflow occurs twice. clear the overflow counter (0h). remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 441 of 1817 sep 19, 2011 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the t abnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tabnopt0 register. to a ccurately detect an overflow, read the tabnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tabnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tabnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tabnovf bit) overflow flag (tabnovf bit) l h l remark n = 0, 1 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may be erased by writing 0 ((ii) in the above chart). ther efore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clr instruction. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 442 of 1817 sep 19, 2011 8.5.7 pulse width measurement mode (tabnmd2 to tabnmd0 bits = 110) in the pulse width measurement mode, ta bn starts counting when the tabnctl0.tabnce bit is set to 1. each time the valid edge input to the tiabnm pi n has been detected, the count value of the 16-bit counter is stored in the tabnccrm register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be m easured by reading the tabnccrm regist er after a capture interrupt request signal (inttabnccm) occurs. select one of the tiabn0 to tiabn3 pins as the capture trigger input pin. s pecify ?no edge detected? for the unused pins by using the tabnioc1 register. when an external clock is used as the count clock, measur e the pulse width of the tiab0k pin because the external clock is fixed to the tiab00 pin. at this time, clear t he tab0ioc1.tab0is1 and tab0ioc1.tab0is0 bits to 00 (capture trigger input (tiab00 pin): no edge detected). for tab1, the external clock is input from the evtab1 pi n, and the pulse width can be measured by using the tiab10 to tiab13 pins. remark m = 0 to 3, n = 0, 1 k = 1 to 3 figure 8-34. configuration in pulse width measurement mode inttabnov signal inttabncc0 signal inttabncc1 signal inttabncc2 signal inttabncc3 signal note 2 tiabn3 pin note 2 (capture trigger input) tabnccr3 note 2 register (capture) tiab00 pin (external event count input note 1 / capture trigger input) internal count clock tabnce bit tiabn1 pin (capture trigger input) tiabn2 pin (capture trigger input) tabnccr0 register (capture) tabnccr1 register (capture) tabnccr2 register (capture) 16-bit counter clear edge detector edge detector edge detector edge detector edge detector count clock selection notes 1. tab1: evtab1 pin 2. the v850es/jh3-e only includes the tiab13 pin; it is not provided with the tiab03 pin. when using the v850es/jh3-e, the tab0ccr3 regi ster and the inttab0ccr3 signal cannot be used. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 443 of 1817 sep 19, 2011 figure 8-35. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tabnce bit tiabnm pin input tabnccrm register inttabnccm signal inttabnov signal tabnovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark m = 0 to 3, n = 0, 1 when the tabnce bit is set to 1, the 16 -bit counter starts counting. when t he valid edge input to the tiabnm pin is later detected, the count value of the 16 -bit counter is stored in the tabnccrm re gister, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (inttabnccm) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the tiabnm pin even when the 16-bit counte r has counted up to ffffh, an overflow interrupt request signal (inttabnov) is generated at the ne xt count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tabnopt0.tabn ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tabnovf bit setting (1) count + captured value) count clock cycle remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 444 of 1817 sep 19, 2011 figure 8-36. register setting in pu lse width measurement mode (1/2) (a) tabn control register 0 (tabnctl0) 0/1 0 0 0 0 tabnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tabncks2 tabncks1 tabncks0 tabnce note the setting is invalid when the tabneee bit = 1. (b) tabn control register 1 (tabnctl1) 0 0 0/1 0 0 tabnctl1 110 tabnmd2 tabnmd1 tabnmd0 1, 1, 0: pulse width measurement mode tabneee tabnest 0: operate on count clock selected by tabncks0 to tabncks2 bits 1: count by external event count input signal (c) tabn i/o control register 1 (tabnioc1) 0/1 note 0/1 note 0/1 0/1 0/1 tabnioc1 select valid edge of tiabn0 pin input select valid edge of tiabn1 pin input 0/1 0/1 0/1 tabnis2 tabnis1 tabnis0 tabnis3 tabnis6 tabnis5 tabnis4 tabnis7 select valid edge of tiabn2 pin input select valid edge of tiabn3 pin input note the tiab03 pin is not provided in the v850es/jh3- e. set the tab0is7 and tab0is6 bits to 0. (d) tabn i/o control register 2 (tabnioc2) 0 0 0 0 0/1 tabnioc2 0/1 0 0 tabnets1 tabnets0 tabnees0 tabnees1 select valid edge of external event count input remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 445 of 1817 sep 19, 2011 figure 8-36. register setting in pu lse width measurement mode (2/2) (e) tabn option register 0 (tabnopt0) 00000 tabnopt0 overflow flag 0 0 0/1 tabnovf tabnccs0 tabnccs1 tabnccs2 tabnccs3 (f) tabn counter read buffer register (tabncnt) the value of the 16-bit counter can be read by reading the tabncnt register. (g) tabn capture/compare register s 0 to 3 (tabnccr0 to tabnccr3) these registers store the count valu e of the 16-bit counter when the vali d edge input to the tiabnm pin is detected. remarks 1. tabn i/o control register 0 (tabnioc0) is no t used in the pulse width measurement mode. 2. m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 446 of 1817 sep 19, 2011 (1) operation flow in pul se width measurement mode figure 8-37. software processing flow in pulse width measurement mode <1> <2> set tabnctl0 register (tabnce bit = 1) tabnce bit = 0 register initial setting tabnctl0 register (tabncks0 to tabncks2 bits), tabnctl1 register, tabnioc1 register, tabnioc2 register, tabnopt0 register the initial setting of these registers is performed before setting the tabnce bit to 1. the tabncks0 to tabncks2 bits can be set at the same time when counting has been started (tabnce bit = 1). the counter is initialized and counting is stopped by clearing the tabnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tabnce bit tiabn0 pin input tabnccr0 register inttabncc0 signal d 0 0000h 0000h d 1 d 2 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 447 of 1817 sep 19, 2011 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the t abnovf bit to 0 with the clr instruction and by writing 8-bit data (bit 0 is 0) to the tabnopt0 register. to a ccurately detect an overflow, read the tabnovf bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) operation to write 0 (without conflict with setting) (iii) operation to clear to 0 (without conflict with setting) (ii) operation to write 0 (conflict with setting) (iv) operation to clear to 0 (conflict with setting) 0 write signal overflow set signal register access signal overflow flag (tabnovf bit) read write 0 write signal overflow set signal register access signal overflow flag (tabnovf bit) read write 0 write signal overflow set signal 0 write signal overflow set signal overflow flag (tabnovf bit) overflow flag (tabnovf bit) l h l remark n = 0, 1 to clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the clr instruction. if 0 is written to the overflow flag without checking if the flag is 1, the set overflow information may be erased by writing 0 ((ii) in the above chart). ther efore, software may judge that no overflow has occurred even when an overflow actually has occurred. if execution of the clr instruction conf licts with occurrence of an overflow when the overflow flag is cleared to 0 with the clr instruction, the overflow flag remains set even after execution of the clr instruction. v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 448 of 1817 sep 19, 2011 8.5.8 triangular wave pwm mode (tabnmd2 to tabnmd0 bits = 111) in the triangular wave pwm mode, tabn capture/compare register k (tabnccrk) is used to set the duty factor, and tabn capture/compare register 0 (t abnccr0) is used to set the cycle. by using these four registers and operating the timer, triangular wave pwm with a variable cycle is output. the value of the tabnccrm register can be rewritten when tabnce = 1. to stop timer ab, clear tabnce to 0. the pwm waveform is output from the toabnk pin. the toabn0 pin produces a toggle output when the value of the 16- bit counter matches the value of the t abnccr0 register and when the counter underflows. caution in the pwm mode, the capture function of the tabnccrm register cannot be used because this register can be used only as a compare register. remark n = 0, 1, m = 0 to 3, k = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 449 of 1817 sep 19, 2011 figure 8-38. timing of basic operation in triangular wave pwm mode (tabnoe0 = 1, tabnoe1 = 1, tabnoe2 = 1, tabnoe3 = 1, tabnol0 = 0, tabnol1 = 0, tabnol2 = 0, tabnol3 = 0) tabnce = 1 ffffh 16-bit counter toabn0 toabn1 inttabnov inttabncc0 match interrupt inttabncc1 match interrupt tabnccr0 toabn2 toabn3 note inttabncc2 match interrupt inttabncc3 match interrupt 0000h d 00 d 00 d 30 d 30 d 20 d 20 d 10 d 10 tabnccr1 0000h d 10 tabnccr2 0000h d 20 tabnccr3 0000h d 30 d 00 d 30 d 30 d 20 d 20 d 10 d 00 d 30 d 30 d 20 d 20 note the v850es/jh3-e only includes the toab13 pin; it is not provided with the toab03 pin. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 450 of 1817 sep 19, 2011 8.5.9 timer output operations the following table shows the operations and out put levels of the toabn0 to toabn3 pins. table 8-6. timer output control in each mode operation mode toabn0 pin toabn1 pin toabn2 pin toabn3 pin interval timer mode square wave output external event count mode square wave output ? external trigger pulse output mode external trigger pulse output external trigger pulse output external trigger pulse output one-shot pulse output mode one-shot pulse output one-shot pulse output one-shot pulse output pwm output mode square wave output pwm output pwm output pwm output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode ? triangular wave pwm output mode square wave output triangular pwm output triangular pwm output triangular pwm output table 8-7. truth table of toabn0 to toabn3 pins under control of timer output control bits tabnioc0.tabnolm bit tabnioc0.tabnoem bit tabnctl0.tabnce bit level of toabnm pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark m = 0 to 3, n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 451 of 1817 sep 19, 2011 8.6 timer-tuned operation functi on/simultaneous-start function timer aa and timer ab have a timer-tuned operation function/simultaneous-start function. the timers that can be synchronized are listed in table 8-8. table 8-8. timer-tuned operation mode master timer slave timer taa1 taa0 taa3 taa2 tab0 taa5 tab1 tab4 for details of the timer-tun ed operation function, see 7.6 timer-tuned operation function , and for details of the simultaneous-start function, see 7.7 simultaneous-start function . v850es/jh3-e, v850es/jj3-e chapter 8 16-bit timer/event counter ab (tab ) r01uh0290ej0300 rev.3.00 page 452 of 1817 sep 19, 2011 8.7 cautions (1) capture operation when the capture operation is used and a slow clock is selected as the count clock, ffffh , not 0000h, may be captured in the tabnccr0, tabnccr1, tabnccr2, and t abnccr3 registers if the capture trigger is input immediately after the tabnce bit is set to 1. (a) free-running timer mode count clock 0000h ffffh tabnce bit tabnccr0 register ffffh 0001h 0000h tiabn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input (b) pulse width measurement mode 0000h ffffh ffffh 0002h 0000h count clock tabnce bit tabnccr0 register tiabn0 pin input capture trigger input 16-bit counter sampling clock (f xx ) capture trigger input remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 453 of 1817 sep 19, 2011 chapter 9 16-bit timer/event counter t (tmt) timer t (tmt) is a 16-bit timer/event counter. an encoder count function and other functions are added to timer aa (taa). however, tmt does not have a function to operate with an external event count input w hen it operates in the interval timer mode. the v850es/jh3-e and v850es/jj3-e have one tmt channel. 9.1 overview an overview of tmt0 is given below. ? clock selection: 8 types ? capture trigger input pins (tit00, tit01): 2 ? encoder input pins (tenc00 note , tenc01): 2 ? encoder clear input pin (tecr0): 1 ? external trigger input pin: 1 ? external event count input pin: 1 ? timer counter: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 note the tenc00 pin is also used for the capture trigger inpu t, external event count input, and external encoder input signals. 9.2 functions the functions of tmt0 are shown below. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? triangular-wave pwm output ? encoder count v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 454 of 1817 sep 19, 2011 9.3 configuration tmt0 includes the following hardware. table 9-1. configuration of tmt0 item configuration registers 16-bit counter 1 tmt0 capture/compare regist ers 0, 1 (tt0ccr0, tt0ccr1) tmt0 counter read buffer register (tt0cnt) tmt0 counter write register (tt0tcw) ccr0, ccr1 buffer registers tmt0 control registers 0, 1 (tt0ctl0, tt0ctl1) tmt0 control registers 2 (tt0ctl2) tmt0 i/o control registers 0 to 3 (tt0ioc0 to tt0ioc3) tmt0 option register 0 (tt0opt0) tmt0 option register 1 (tt0opt1) tmt noise elimination control register (ttnfc) timer input ? tit00, tit01 (capture trigger input pins) ? tenc00 note (encoder 0 input pin) ? tenc01 (encoder 1 input pin) ? tencr0 (encoder clear input pin) timer output tot00, tot01 note the tenc00 pin is also used for the capture trigger input, external event count input, and external encoder input signals. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 455 of 1817 sep 19, 2011 figure 9-1. block diagram of tmt0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tt0cnt tt0tcw tt0ccr0 tt0ccr1 inttt0ov inttt0cc0 tot00 tot01 inttt0cc1 inttt0ec tit01 tit00 tecr0 tenc00 note tenc01 f xx f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 selector internal bus internal bus ccr1 buffer register 16-bit counter ccr0 buffer register counter control clear selector output controller sampling clock edge detection/ noise eliminator edge detection/ noise eliminator edge detection/ noise eliminator edge detection/ noise eliminator edge detection/ noise eliminator note the tenc00 pin is also used for the capture trigger input, external event count input, and external encoder input signals. remark f xx : peripheral clock v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 456 of 1817 sep 19, 2011 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tt0cnt register. when the tt0ctl0.tt0ce bit = 0, the valu e of the 16-bit counter is ffffh. if t he tt0cnt register is read at this time, 0000h is read. reset sets the tt0ce bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tt0ccr0 register is used as a compare regi ster, the value written to the tt0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter ma tches the value of the ccr0 buffer register, a compare match interrupt request signal (intttcc00) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is set to 0000h after reset, and the tt0ccr0 register is set to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tt0ccr1 register is used as a compare regi ster, the value written to the tt0ccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter ma tches the value of the ccr1 buffer register, a compare match interrupt request signal (intttcc01) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is set to 0000h after reset, and the tt0ccr1 register is set to 0000h. (4) edge detector this circuit detects the valid edges input to the tit00, tit01, tenc00, tenc01, and tecr0 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tt0ioc1, tt0ioc2, and tt0ioc3 registers. (5) output controller this circuit controls the output of the to t00 and tot01 pins via the tt0ioc0 register. (6) selector this selector selects the count clock for the 16-bit counter. eight types of internal clocks or an external event can be selected as the count clock. (7) counter control the count operation is controlled by the ti mer mode selected by the tt0ctl1 register. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 457 of 1817 sep 19, 2011 9.3.1 pin configuration the timer inputs and outputs that configure tmt0 are shared with the followi ng ports. the port functions must be set when using each pin (see table 4-18 using port pin as alternate-function pin ). table 9-2. pin configuration port timer input pin timer ou tput other alternate function p96 tit00 (capture trigger input 0) te cr0 (encoder clear input) tot00 kr6/a6 p97 tit01 (capture trigger input 1) tenc00 note (encoder input) tot01 kr7/a7 p98 ? tenc01 (encoder input) ? intp17/a8 note the tenc00 pin is also used for the capture trigger i nput, external event count input, and external encoder input signals. set each signal for use by using the tt0ioc2 and tt0ioc3 registers after setting the corresponding port. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 458 of 1817 sep 19, 2011 9.4 registers (1) tmt0 control register 0 (tt0ctl0) the tt0ctl0 register is an 8-bit register that controls the operation of tmt0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tt0ctl0 register by software. tt0ce tmt0 operation disabled (tmt0 reset asynchronously note ) tmt0 operation enabled. tmt0 operation start tt0ce 0 1 tmt0 operation control tt0ctl0 0 0 0 0 tt0cks2 tt0cks1 tt0cks0 654321 after reset: 00h r/w address: ffff600h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tt0cks2 0 0 0 0 1 1 1 1 internal count clock selection tt0cks1 0 0 1 1 0 0 1 1 tt0cks0 0 1 0 1 0 1 0 1 note the tt0opt0.tt0ovf bit and 16-bit counter are reset simultaneously. moreover, timer outputs (tot00 and tot01) are reset at the same time as the 16-bit counter. cautions 1. set the tt0cks2 to tt0cks0 bits when the tt0ce bit = 0. when the value of the tt0ce bit is changed from 0 to 1, the tt0cks2 to tt0cks0 bits can be set simultaneously. 2. be sure to set bits 3 to 6 to ?0?. remark f xx : peripheral clock v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 459 of 1817 sep 19, 2011 (2) tmt0 control register 1 (tt0ctl1) the tt0ctl1 register is an 8-bit register that controls the tmt0 operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) 0 tt0ctl1 tt0est tt0eee 0 tt0md3 tt0md2 tt0md1 tt0md0 654321 after reset: 00h r/w address: fffff601h 7 0 tt0est 0 1 software trigger control generates a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tt0est bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tt0est bit as the trigger. disables operation with external event count input (tenc00 pin). (performs counting with the count clock selected by the tt0ctl0.tt0cks0 to tt0ctl0.tt0cks2 bits.) tt0eee 0 1 count clock selection the tt0eee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. enables operation with external event count input (tenc00 pin). (performs counting at every valid edge of the external event count input signal (tenc00 pin).) ? the read value of the tt0est bit is always 0. interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode triangular-wave pwm output mode encoder compare mode setting prohibited timer mode selection tt0md3 0 0 0 0 0 0 0 0 1 other than above tt0md2 0 0 0 0 1 1 1 1 0 tt0md1 0 0 1 1 0 0 1 1 0 tt0md0 0 1 0 1 0 1 0 1 0 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 460 of 1817 sep 19, 2011 (2/2) cautions 1. the tt0est bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. in any other mode, wr iting 1 to this bit is ignored. 2. the tt0eee bit is valid only in the interval timer mode, external trigger pulse output mode, one-shot pulse output mode, pwm output mode , free-running timer mode, pulse width measurement mode, or triangular-wave pwm outp ut mode. in any other mode, writing 1 to this bit is ignored. 3. external event count input (tenc00) or encoder inputs (tenc00, tenc01) is selected in the external event count mode or encoder co mpare mode regardless of the value of the tt0eee bit. 4. set the tt0eee and tt0md3 to tt0md0 bits wh en the tt0ctl0.tt0ce bit = 0. (the same value can be written when the tt0ce bit = 1.) the operation is not guaranteed when rewriting is performed with the tt0ce bit = 1. if rewriting was mistakenly performed, clear the tt0ce bit to 0 and then set the bits again. 5. be sure to set bits 4 and 7 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 461 of 1817 sep 19, 2011 (3) tmt0 control register 2 (tt0ctl2) the tt0ctl2 register is an 8-bit register that controls the encoder count function operation. the tt0ctl2 register is valid only in the encoder compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution for details of each bit of th e tt0ctl2 register, see 9.6.9 (5) c ontrolling bits of tt0ctl2 register. (1/2) tt0ecc tt0ctl2 0 0 tt0lde tt0ecm1 tt0ecm0 tt0uds1 tt0uds0 654321 disables transfer of set value of tt0ccr0 to 16-bit counter in case of underflow. enables transfer of set value of tt0ccr0 to 16-bit counter in case of underflow. tt0lde 0 1 transfer setting to 16-bit counter after reset: 00h r/w address: fffff602h 0 7 the 16-bit counter is not cleared to 0000h when its count value matches value of ccr1 register. the 16-bit counter is cleared to 0000h when the count after a match between the 16-bit counter count value and ccr1 register value is a down-count tt0ecm1 0 1 control of encoder clear operation 1 the 16-bit counter is not cleared to 0000h when its count value matches value of ccr0 register. the 16-bit counter is cleared to 0000h when the count after a match between the 16-bit counter count value and ccr0 register value is an up-count tt0ecm0 0 1 control of encoder clear operation 0 normal operation holds count value of 16-bit counter when tt0 ctl0.tt0ce bit = 0. tt0ecc 0 1 encoder counter control v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 462 of 1817 sep 19, 2011 (2/2) when valid edge of tenc00 input is detected counts down when tenc01 = high level. counts up when tenc01 = low level. counts up when valid edge of tenc00 input is detected. counts down when valid edge of tenc01 input is detected. counts down when rising edge of tenc00 input is detected. counts up when falling edge of tenc00 input is detected. however, count operation is performed only when tenc01 = low level. both rising and falling edges of tenc00 and tenc01 are detected. count operation is automatically identified by combination of edge detection and level detection. tt0uds1 0 0 1 1 up/down count selection tt0uds0 0 1 0 1 cautions 1. the tt0ecc bit is valid only in the encoder compare mode. in any other mode, writing ?1? to this bit is ignored. if the tt0ctl0.tt0ce bit is cleared to 0 while the tt0ecc bit = 1, the values of the timer/counter and capture registers (tt0ccr0 and tt0ccr1), and the tt0opt1, tt0euf, tt0eof, and tt0esf flags are retained. if the tt0ce bit is set from 0 to 1 when the tt0ecc bit = 1, the value of the tt0tcw register is not transf erred to the 16-bit counter. 2. the tt0lde bit is valid only when the tt0ecm1 and tt0ecm0 bits = 00, 01. writing ?1? to this bit is ignor ed when the tt0ecm1 and tt0ecm0 bits = 10, 11. 3. the edge detection of the tenc 00 and tenc01 inputs specified by the tt0ioc3.tt0eis1 and tt0ioc3. tt0eis0 bits is invalid and fixed to both the rising and falling edges when the tt0uds1 and tt0uds0 bits = 10, 11. 4. set the tt0lde, tt0ecm1, tt0ecm0 , tt0uds1, and tt0uds0 bits when the tt0ctl0.tt0ce bit = 0 (the same va lue can be written to these bits when the tt0ce bit = 1). if the valu e of these bits is changed when the tt0ce bit = 1, the operation cannot be guaranteed. if it is changed by mistake, clear the tt0ce bit and then set the correct value. 5. be sure to set bits 5 and 6 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 463 of 1817 sep 19, 2011 (4) tmt0 i/o control register 0 (tt0ioc0) the tt0ioc0 register is an 8-bit register that controls the timer output (tot00, tot01 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 464 of 1817 sep 19, 2011 0 tt0ol1 0 1 tot01 pin output level setting note tot01 pin starts output at high level. tot01 pin starts output at low level. tt0ioc0 0 0 0 tt0ol1 tt0oe1 tt0ol0 tt0oe0 6543<2>1 tt0oe1 0 1 tot01 pin output setting timer output prohibited ? low level is output from the tot01 pin when the tt0ol1 bit = 0. ? high level is output from the tot01 pin when the tt0ol1 bit = 1. timer output enabled (a pulse is output from the tot01 pin.) tt0ol0 0 1 tot00 pin output level setting note tot00 pin starts output at high level. tot00 pin starts output at low level. tt0oe0 0 1 tot00 pin output setting timer output prohibited ? low level is output from the tot00 pin when the tt0ol0 bit = 0. ? high level is output from the tot00 pin when the tt0ol0 bit = 1. timer output enabled (a pulse is output from the tot00 pin.) 7 <0> after reset: 00h r/w address: fffff603h note the output level of the timer output pi ns (tot00 and tot01) specified by the tt0oln bit is shown below (n = 0, 1). tt0ce bit tot0n pin output 16-bit counter tt0ce bit tot0n pin output 16-bit counter ? when tt0oln bit = 0 ? when tt0oln bit = 1 cautions 1. if the setting of the tt0ioc0 register is changed when tot00 and tot01 outputs are set for the port mode, the output of the pins change. set the port in the input mode and make the port go into a high-impedance state, noting changes in the pin status. 2. rewrite the tt0ol1, tt0oe1, tt0ol0, and tt0oe0 bits when the tt0ctl0.tt0ce bit = 0. (the same value can be written when the tt0ce bit = 1.) if rewriting was mistakenly performed, clear the tt0ce bit to 0 and then set the bits again. 3. even if the tt0ol0 or tt0ol1 bit is manipulated when the tt0ce, tt0oe0, and tt0oe1 bits are 0, the output level of the tot00 and tot01 pins changes. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 465 of 1817 sep 19, 2011 (5) tmt0 i/o control register 1 (tt0ioc1) the tt0ioc1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (tit00, tit01 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tt0is3 0 0 1 1 tt0is2 0 1 0 1 capture trigger input signal (tit01 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 0 0 0 tt0is3 tt0is2 tt0is1 tt0is0 654321 tt0is1 0 0 1 1 tt0is0 0 1 0 1 capture trigger input signal (tit00 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tt0ioc1 after reset: 00h r/w address: fffff604h cautions 1. rewrite the tt0is3 to tt0is0 bits when the tt0ctl0.tt0ce bit = 0. (the same value can be written when the tt0ce bit = 1.) if rewriting was mistakenly performed, clear th e tt0ce bit to 0 and then set the bits again. 2. the tt0is3 and tt0is2 bits are valid only in the free-running timer mode (only when the tt0opt0.tt0ccs1 bit = 1) and the pulse width measurement mode. in all other modes, a capture operation is not performed. the tt0is1 and tt0is0 bits are va lid only in the free-running timer mode (only when the tt0opt0. tt0ccs0 bit = 1) and the pulse width measurement mode. in all other modes, a capture operation is not performed. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 466 of 1817 sep 19, 2011 (6) tmt0 i/o control register 2 (tt0ioc2) the tt0ioc2 register is an 8-bit regist er that controls the valid edge for t he external event count input signal (tenc00 pin) and external trigger input signal. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tt0ees1 0 0 1 1 tt0ees0 0 1 0 1 external event count input signal (tenc00 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges 0 0 0 tt0ees1 tt0ees0 tt0ets1 tt0ets0 654321 tt0ets1 0 0 1 1 tt0ets0 0 1 0 1 external trigger input signal (tenc00 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tt0ioc2 after reset: 00h r/w address: fffff605h cautions 1. rewrite the tt0ees1, tt0ees0, tt0ets1, and tt0ets0 bits when the tt0ctl0.tt0ce bit = 0. (the same value can be written when the tt0ce bit = 1.) if rewriting was mistakenly performed, clear the tt0ce bit to 0 and then set the bits again. 2. the tt0ees1 and tt0ees0 bi ts are valid only when the tt0ctl1.tt0eee bit = 1 or when the external event count mode (the tt0ctl1.tt0md3 to tt0 ctl1.tt0md0 bits = 0001) has been set. 3. the tt0ets1 and tt0ets0 bits are valid only in the external trigger pulse mode or one-shot pulse output mode. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 467 of 1817 sep 19, 2011 (7) tmt0 i/o control register 3 (tt0ioc3) the tt0ioc3 register is an 8-bit register that controls the encoder clear function operation. the tt0ioc3 register is valid only in the encoder compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) tt0sce tt0ioc3 tt0zcl tt0bcl tt0acl tt0ecs1 tt0ecs0 tt0eis1 tt0eis0 654321 after reset: 00h r/w address: fffff606h 7 0 tt0sce 0 1 encoder clear selection ? clears the 16-bit counter to 0000h when the valid edge of tecr0 pin specified by the tt0ecs1 and tt0ecs0 bits is detected when the tt0sce bit = 0. ? clears the 16-bit counter to 0000h when the clear level conditions of the tt0zcl, tt0bcl, and tt0acl bits match the input levels of the tecr0, tenc01, and tenc00 pins when tt0sce bit = 1. ? setting of the tt0zcl, tt0bcl, and tt0acl bits is valid and that of the tt0ecs1 and tt0ecs0 bits is invalid when the tt0sce bit = 1. an encoder clear interrupt request signal (inttti0ec) is not generated. ? setting of the tt0zcl, tt0bcl, and tt0acl bits is invalid and setting of the tt0ecs1 and tt0ecs0 bits is valid when the tt0sce bit = 0. the inttti0ec signal is generated when the valid edge specified by the tt0ecs1 and tt0ecs0 bits is detected. ? be sure to set the tt0ctl2.tt0uds1 and tt0ctl2.tt0uds0 bits to 10 or 11 when the tt0sce bit = 1. operation is not guaranteed if the tt0uds1 and tt0uds0 bits = 00 or 01 and the tt0sce bit = 1. clears 16-bit counter on detection of edge of encoder clear signal (tecr0 pin). clears 16-bit counter on detection of clear level condition of the tenc00, tenc01, and tecr0 pins. tt0zcl 0 1 clear level selection of encoder clear signal (tecr0 pin) setting of the tt0 zcl bit is valid only when the tt0 sce bit = 1. clears low level of the tecr0 pin. clears high level of the tecr0 pin. tt0bcl 0 1 clear level selection of encoder input signal (tenc01 pin) setting of the tt0 bcl bit is valid only when the tt0 sce bit = 1. clears low level of the tenc0 1 pin. clears high level of the tenc0 1 pin. tt0acl 0 1 clear level selection of encoder input signal (tenc00 pin) setting of the tt0 acl bit is valid only when the tt0 sce bit = 1. clears low level of the tenc0 0 pin. clears high level of the tenc0 0 pin. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 468 of 1817 sep 19, 2011 (2/2) tt0ecs1 0 0 1 1 tt0ecs0 0 1 0 1 valid edge setting of encoder clear signal (tecr0 pin) detects no edge (clearing encoder is invalid). detects rising edge. detects falling edge. detects both edges. tt0eis1 0 0 1 1 tt0eis0 0 1 0 1 valid edge setting of encoder input signals (tenc00, tenc01 pins) detects no edge (inputting encoder is invalid). detects rising edge. detects falling edge. detects both edges. cautions 1. rewrite the tt0sce, tt0z cl, tt0bcl, tt0acl, tt0ecs1, tt0ecs0, tt0eis1, and tt0eis0 bits when the tt0ctl0.tt0ce bit = 0. (the same value can be written to these bits when the tt0ce bit = 1.) if rewriting was mistakenly performed, clear the tt0ce bit to 0 and then set these bits again. 2. the tt0ecs1 and tt0ecs0 bits ar e valid only when the tt0sce bit = 0 and the encoder compare mode is set. 3. the tt0eis1 and tt0eis0 bits ar e valid only when the tt0ctl2.tt0uds1 and tt0ctl2.tt0uds0 bits = 00 or 01. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 469 of 1817 sep 19, 2011 (8) tmt0 option register 0 (tt0opt0) the tt0opt0 register is an 8-bit register that sets the capture/compare operati on and detects overflows. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tt0ccs1 0 1 tt0ccr1 register capture/compare selection the tt0ccs1 bit setting is valid only in the free-running timer mode. selected as compare register selected as capture register (cleared by the tt0ctl0.tt0ce bit = 0) 0 tt0ccs1 tt0ccs0 0 0 0 tt0ovf 654321 tt0ccs0 0 1 tt0ccr0 register capture/compare selection the tt0ccs0 bit setting is valid only in the free-running timer mode. selected as compare register selected as capture register (cleared by the tt0ctl0.tt0ce bit = 0) tt0ovf set (1) reset (0) tmt0 overflow detection flag ? the tt0ovf bit is set to 1 when the 16-bit counter value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an overflow interrupt request signal (inttt0ov) is generated when the tt0ovf bit is set to 1. the inttt0ov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tt0ovf bit is not cleared to 0 even when the tt0ovf bit or the tt0opt0 register are read when the tt0ovf bit = 1. ? before clearing the tt0ovf bit to 0 after generation of the inttt0ov signal, be sure to confirm (by reading) that the tt0ovf bit is set to 1. ? the tt0ovf bit can be both read and written, but the tt0ovf bit cannot be set to 1 by software. writing 1 has no effect on the operation of tmt0. overflow occurred 0 written to tt0ovf bit or tt0ctl0.tt0ce bit = 0 7 <0> tt0opt0 after reset: 00h r/w address: fffff607h cautions 1. rewrite the tt0ccs1 and tt0ccs0 bits when the tt0ce bit = 0. (the same value can be written when the tt0ce bit = 1.) if rewriting was mistakenly performed, clear the tt0ce bit to 0 and then set these bits again. 2. be sure to set bits 1 to 3, 6, and 7 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 470 of 1817 sep 19, 2011 (9) tmt0 option register 1 (tt0opt1) the tt0opt1 register is an 8-bit register that detects overflows, underflows, and count -up/down operations of the encoder count function. the tt0opt1 register is valid only in the encoder compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. this register can be rewritten even when the tt0ctl0.tt0ce bit = 1. (1/2) 0 tt0opt1 0 0 0 0 tt0euf tt0eof tt0esf 6 5 4 3 <2> <1> after reset: 00h r/w address: fffff608h tt0euf set (1) reset (0) tmt0 underflow detection flag ? the tt0euf bit is set to 1 when the 16-bit counter underflows from 0000h to ffffh in the encoder compare mode. ? when the tt0ctl2.tt0lde bit = 1, the tt0euf bit is set to 1 when the value of the 16-bit counter is changed from 0000h to the set value of the tt0ccr0 register. ? an overflow interrupt request signal (intttov0) is generated as soon as the tt0euf bit is set to 1. ? the tt0euf bit is not cleared to 0 even if the tt0euf bit or tt0opt1 register is read when the tt0euf bit = 1. ? the status of the tt0euf bit is retained even if the tt0ctl0.tt0ce bit is cleared to 0 when the tt0ctl2.tt0ecc bit = 1. ? before clearing the tt0euf bit to 0 after the intttov0 signal is generated, be sure to confirm (read) that the tt0euf bit is set to 1. ? the tt0euf bit can be read or written, but it cannot be set to 1 by software. setting this bit to 1 does not affect the operation of tmt0. underflow occurs. cleared by writing to tt0euf bit or when tt0ctl0.tt0ce bit = 0 7 <0> v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 471 of 1817 sep 19, 2011 (2/2) tt0esf 0 1 tmt0 count-up/-down operation status detection flag ? this bit is cleared to 0 if the tt0ctl0.tt0ce bit = 0 when the tt0ctl2.tt0ecc bit = 0. ? the status of the tt0esf bit is retained even if the tt0ce bit = 0 when the tt0ecc bit = 1. tmt0 is counting up. tmt0 is counting down. tt0eof set (1) reset (0) overflow detection flag for tmt0 encoder function ? the tt0eof bit is set to 1 when the 16-bit counter overflows from ffffh to 0000h in the encoder compare mode. ? as soon as the tt0eof bit has been set to 1, an overflow interrupt request signal (intttov0) is generated. at this time, the tt0opt0.tt0ovf bit is not set to 1. ? the tt0eof bit is not cleared to 0 even if the tt0eof bit or tt0opt1 register is read when the tt0eof bit = 1. ? the status of the tt0eof bit is retained even if the tt0ctl0.tt0ce bit is cleared to 0 when the tt0ctl2.tt0ecc bit = 1. ? before clearing the tt0eof bit to 0 after the intttov0 signal is generated, be sure to confirm (read) that the tt0eof bit is set to 1. ? the tt0eof bit can be read or written, but it cannot be set to 1 by software. writing 1 to this bit does not affect the operation of tmt0. overflow occurs. cleared by writing 0 to the tt0 eof bit or when the tt0 ctl0.tt0ce bit = 0 caution be sure to set bits 3 to 7 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 472 of 1817 sep 19, 2011 (10) tmt0 capture/compare register 0 (tt0ccr0) the tt0ccr0 register is a 16-bit regist er that can be used as a capture regi ster or compare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the tt0opt0.tt0ccs0 bit. in the pulse width measurement mode, the tt0ccr0 register can be used only as a capture register. in any ot her mode, this register can be used only as a compare register. the tt0ccr0 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. tt0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff60ah 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 473 of 1817 sep 19, 2011 (a) function as compare register the tt0ccr0 register can be rewritten even when the tt0ctl0.tt0ce bit = 1. the set value of the tt0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttt0cc0) is generated. if tot00 pin output is enabled at th is time, the output of t he tot00 pin is inverted. when the tt0ccr0 register is used as a cycle register in the interval timer mode, or when the tt0ccr0 register is used as a cycle register in the external event count mode, external trigger pulse output mode, one- shot pulse output mode, pwm output mode, triangula r-wave pwm output mode, or encoder compare mode, the value of the 16-bit counter is cleared (0000h) if its count value matches the value of the ccr0 buffer register. the compare register is not cleared by setting the tt0ctl0.tt0ce bit to 0. (b) function as capture register in the free-running timer mode (when the tt0ccr0 register is used as a capture regi ster), the count value of the 16-bit counter is stored in the tt0cc r0 register if the valid edge of the capture trigger input pin (tit00 pin) is detected. in the pulse width m easurement mode, the count value of t he 16-bit counter is stored in the tt0ccr0 register and the 16-bit counter is cleared (0000h ) if the valid edge of the capture trigger input pin (tit00 pin) is detected. even if the capture operation and reading the tt0ccr0 register conflic t, the correct value of the tt0ccr0 register can be read. the capture register is cleared by setting the tt0ctl0.tt0ce bit to 0. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 9-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode tt0ccr0 register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none triangular-wave wpm output compare register batch write note encoder compare compare register anytime write note writing to the tt0ccr1 register is the trigger. remark for anytime write and batch write, see 9.6 (2) anytime write and batch write . v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 474 of 1817 sep 19, 2011 (11) tmt0 capture/compare register 1 (tt0ccr1) the tt0ccr1 register is a 16-bit regist er that can be used as a capture regi ster or compare register depending on the mode. this register can be used as a capt ure register or a compare register only in the free-running timer mode, depending on the setting of the tt0opt0.tt0ccs1 bit. in the pulse width measurement mode, the tt0ccr1 register can be used only as a capture register. in any ot her mode, this register can be used only as a compare register. the tt0ccr1 register can be read or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. tt0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: ffffff60ch 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 475 of 1817 sep 19, 2011 (a) function as compare register the tt0ccr1 register can be rewritten even when the tt0ctl0.tt0ce bit = 1. the set value of the tt0ccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer r egister, a compare match interrupt request signal (inttt0cc01) is generated. if tot01 pi n output is enabled at this time, the output of the tot01 pin is inverted. the compare register is not cleared by setting the tt0ctl0.tt0ce bit to 0. (b) function as capture register in the free-running timer mode (when the tt0ccr1 register is used as a capture regi ster), the count value of the 16-bit counter is stored in the tt0cc r1 register if the valid edge of the capture trigger input pin (tit01 pin) is detected. in the pulse width m easurement mode, the count value of t he 16-bit counter is stored in the tt0ccr1 register and the 16-bit counter is cleared (0000h ) if the valid edge of the capture trigger input pin (tit01 pin) is detected. even if the capture operation and reading the tt0ccr1 register conflic t, the correct value of the tt0ccr1 register can be read. the capture register is cleared by setting the tt0ctl0.tt0ce bit to 0. the following table shows the functions of the capture/compare register in eac h mode, and how to write data to the compare register. table 9-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode tt0ccr1 register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none triangular-wave pwm output compare register batch write note encoder compare compare register anytime write note writing to the tt0ccr1 register is the trigger. remark for anytime write and batch write, see 9.6 (2) anytime write and batch write . v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 476 of 1817 sep 19, 2011 (12) tmt0 counter write register (tt0tcw) the tt0tcw register is used to set the initial value of the 16-bit counter. the tt0tcw register is valid only in the encoder compare mode. this register can be read or written in 16-bit units. rewrite the tt0tcw register when the tt0ctl0.tt0ce bit = 0. the value of the tt0tcw register is transferred to the 16-bit counter when the tt0ce bit is set (1). reset sets this register to 0000h. tt0tcw 12 10 8 6 4 2 after reset: 0000h r/w address: fffff610h 14 0 13 11 9 7 5 3 15 1 (13) tmt0 counter read buffer register (tt0cnt) the tt0cnt register is a read buffer register t hat can read the count valu e of the 16-bit counter. if this register is read when the tt0ctl0.tt0ce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tt0cnt register is set to 0000h when the tt0ctl2.tt0ecc and tt0ce bits = 0. if the tt0cnt register is read at this time, the value of the 16-bit counter (ffffh) is not read, but 0000h is read. the tt0cnt register is not set to 0000h but the previous value is read when the tt0ecc bit = 1 and tt0ce bit = 0. the tt0ecc and tt0ce bits are set to 0 after reset, and the value of the tt0cnt register is set to 0000h. tt0cnt 12 10 8 6 4 2 after reset: 0000h r address: ffffff60eh 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 477 of 1817 sep 19, 2011 (14) noise elimination control register (ttnfc) digital noise elimination can be select ed for the tit00, tit01, tenc00, tenc01, and tecr0 pins. the noise elimination settings are performed using the ttnfc register. when digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f xx , f xx /4, f xx /8, f xx /16, f xx /32, and f xx /64. sampling is performed 3 times. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution time equal to the sampling clock 3 clocks is required until th e digital noise eliminator is initialized after the sampling cloc k has been changed. if the va lid edge of the tit00, tit01, tenc00, tenc01, and tecr0 pins is input a fter the sampling clock has been changed and before the time of the sampling clock 3 clocks passes, therefore, an interrupt request signal may be generated. therefore, when using the external trigger function, the external event function, the capture trigger f unction, and the encoder function of tmt, enable tmt operation after the sampling clock 3 clocks have elapsed. ttnfen ttnfc 0 0 0 0 ttnfc2 ttnfc1 ttnfc0 f xx f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 ttnfc2 0 0 0 0 1 1 digital sampling clock setting prohibited ttnfc1 0 0 1 1 0 0 ttnfc0 0 1 0 1 0 1 after reset: 00h r/w address: fffff726h digital noise elimination not executed digital noise elimination executed ttnfen 0 1 settings of digital noise elimination other than above < > remarks 1. since sampling is performed three times, the noise width for reliably eliminating noise is 2 sampling clocks. 2. in the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 478 of 1817 sep 19, 2011 a timing example of noise elimination performed by the ti mer t input pin digital filter is shown figure 9-2. figure 9-2. example of digital noise elimination timing noise elimination clock input signal internal signal 3 clocks sampling 3 times 3 clocks 1 clock 1 clock 2 clocks 2 clocks sampling 3 times remark if there are two or fewer noise elimination cloc ks while the tit00, tit01, tenc00, tenc01, and tecr0 input signals are high level (or low level), t he input signal is eliminated as noise. if it is sampled three times or more, the edge is detected as a valid input. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 479 of 1817 sep 19, 2011 9.5 timer output operations the following table shows the operations and output levels of the tot00 and tot01 pins. table 9-5. timer output control in each mode operation mode tot01 pin tot00 pin interval timer mode square wave output external event count mode none external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode none triangular-wave pwm output mode triangular-wave pwm output encoder compare mode none table 9-6. truth table of tot00 and tot01 pins under control of timer output control bits tt0ioc0.tt0oln bit tt0ioc0.tt0oen bit tt0ctl0.tt0ce bit level of tot0n pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 480 of 1817 sep 19, 2011 9.6 operation the functions of tmt0 that can be impl emented differ from one channel to anothe r. the functions of each channel are shown below. table 9-7. tmt0 specifications in each mode operation tt0ctl1.tt0est bit (software trigger bit) tenc00 pin (external trigger input) capture/compare register setting compare register write method interval timer mode invalid invalid compare only anytime write external event count mode invalid invalid compare only anytime write external trigger pulse output mode va lid valid compare only batch write one-shot pulse output mode valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switchable anytime write pulse width measurement mode invalid invalid capture only not applicable triangular-wave pwm output mode invalid invalid compare only batch write encoder compare mode invalid invalid compare only anytime write v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 481 of 1817 sep 19, 2011 (1) basic counter operation this section explains the basic operation of the 16-bit counte r. for details, refer to the description of the operation in each mode. (a) count start operation ? encoder compare mode a count operation is controlled by tenc00 and tenc01 phases. the 16-bit counter initial setting is performed by transfer ring the set value of the tt0tcw register to the 16- bit counter and the count operation is started. (when the tt0ctl2.tt0ecc bi t = 0, the tt0tcw register set value is transferred to the 16-bit counter at the timi ng when the tt0ctl0.tt0ce bit changes from 0 to 1.) ? triangular-wave pwm mode the 16-bit counter starts counting from the initial value ffffh. it counts up ffffh, 0000h, 0001h, 0002h, 0003h, and so on. following the count-up operation, the counter counts down upon a match betw een the 16-bit count value and the ccr0 buffer register. ? mode other than above the 16-bit counter starts counting from the initial value ffffh. it counts up ffffh, 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its value ma tches the value of the compare register, when its value is captured, when the edge of the encoder clear signal is detected, and when the clear level condition of the tenc00, tenc01, and tecr0 pins is detected. the c ount operation from ffffh to 0000h that takes place immediately after the counter has started counting or when the counter overflows is not a clear operation. therefore, the inttt0cc0 and inttt0cc1 interrupt signals are not generated. (c) overflow operation the 16-bit counter overflows when it counts up from ffffh to 0000h in the free-running mode, pulse width measurement mode, and encoder compare mode. if the counter overflows in the free-running mode and pulse width measurement mode, the tt0opt0.tt0ovf bit is se t to 1 and an interrupt request signal (inttt0ov) is generated. if the counter overflows in the encoder compare mode, the tt0opt1.tt0eof bit is set to 1 and an interrupt request signal (inttt0 ov) is generated. note that the inttt0ov signal is not generated under the following conditions. ? immediately after a count operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured and cleared to 0000h in the pulse width measurement mode caution after the overflow interrupt request signal (inttt0ov) has been generated, be sure to check that the overflow flag (tt0ovf, tt0eof bits) is set to 1. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 482 of 1817 sep 19, 2011 (d) count value hold operation the value of the 16-bit counter is held by the tt0ctl2.tt0ecc bit in the encoder compare mode. the value of the 16-bit counter is reset to ffffh when the tt0ecc bit = 0 and tt0ctl0.tt0ce bit = 0. when the tt0ce bit is next set to 1, the set value of the tt0tcw register is transfe rred to the 16-bit counter and a count operation is performed. if the tt0ecc bit = 1 and tt0ce bit = 0, the value of the 16-bit counter is held. when the tt0ce bit is next set to 1, the counter resumes the c ount operation from the held value. (e) counter read operation during count operation the value of the 16-bit counter of tmt0 can be read by us ing the tt0cnt register during the count operation. when the tt0ctl0.tt0ce bit = 1, the value of the 16-bit counter can be read by reading the tt0cnt register. if the tt0cnt register is read when the tt0ctl2.tt0ecc bi t = 0 and tt0ce bit = 0, however, it is 0000h. the held value of the tt0cnt register is read if the register is read when the tt0ecc bit = 1 and tt0ce bit = 0. (f) underflow operation a 16-bit counter underflow occurs at the timing when th e 16-bit counter value changes from 0000h to ffffh in the encoder compare mode. when an underflow occurs, the tt0opt1.tt0euf bit is set to 1 and an interrupt request signal (inttt0ov) is generated. (g) interrupt operation tmt0 generates the following four types of interrupt request signals. ? inttt0cc0 interrupt: this signal func tions as a match interrupt request si gnal of the ccr0 buffer register and as a capture interrupt request signal to the tt0ccr0 register. ? inttt0cc1 interrupt: this signal func tions as a match interrupt request si gnal of the ccr1 buffer register and as a capture interrupt request signal to the tt0ccr1 register. ? inttt0ov interrupt: this signal functions as an overflow interrupt request signal. ? inttt0ec interrupt: this signal functions as a valid edge detection interr upt request signal of the encoder clear input (tecr0 pin). v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 483 of 1817 sep 19, 2011 (2) anytime write and batch write the tt0ccr0 and tt0ccr1 registers in tmt0 can be rewri tten during timer operation (tt0ctl0.tt0ce bit = 1), but the write method (anytime write, bat ch write) of the ccr0 and ccr1 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the tt0ccr0 and tt0ccr1 registers to the ccr0 and ccr1 buffer registers during timer operation (n = 0, 1). figure 9-3. flowchart of basic operation for anytime write start initial settings ? set values to tt0ccrn register ? timer operation enable (tt0ce bit = 1) transfer values of tt0ccrn register to ccrn buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start iinttt0cc1 signal output ttnccrn register rewrite transfer to ccrn buffer register iinttt0cc0 signal output note the 16-bit counter is not cleared upon a match between the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between the 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an exam ple of the operation in the interval timer mode. 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 484 of 1817 sep 19, 2011 figure 9-4. timing of anytime write d 01 d 01 d 01 d 01 0000h tt0ce bit = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter tt0ccr0 register tt0ccr1 register inttt0cc0 signal inttt0cc1 signal ccr0 buffer register ccr1 buffer register 0000h ffffh remarks 1. d 01 , d 02 : set values of tt0ccr0 register d 11 , d 12 : set values of tt0ccr1 register 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 485 of 1817 sep 19, 2011 (b) batch write in this mode, data is transferred all at once from the tt0ccr0 and tt0ccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the tt0ccr1 register. whether to enable or disable the next transfer timing is controlled by writing or not writing to the tt0ccr1 register. in order for the set value when the tt0ccr0 and tt0ccr1 registers are rewritten to become the 16-bit counter comparison value (in other words, in order fo r this value to be transferred to the ccr0 and ccr1 buffer registers), it is necessary to rewrite the tt0 ccr0 register and then write to the tt0ccr1 register before the 16-bit counter value and the ccr0 buffer register va lue match. therefore, the values of the tt0ccr0 and tt0ccr1 registers are transferred to the ccr0 and ccr1 buffer registers upon a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. thus even when wishing only to rewrite the value of the tt0ccr0 register, also write the same value (same as preset value of the tt0ccr1 register) to the tt0ccr1 register. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 486 of 1817 sep 19, 2011 figure 9-5. flowchart of basic operation for batch write start initial settings ? set values to tt0ccrn register ? timer operation enable (tt0ce bit = 1) transfer values of tt0ccrn register to ccrn buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of tt0ccrn register to ccrn buffer register inttt0cc1 signal output tt0ccr0 register rewrite tt0ccr1 register rewrite inttt0cc0 signal output batch write enable note the 16-bit counter is not cleared upon a matc h between the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a ma tch between the 16-bit count er value and the ccr0 buffer register value. caution writing to the tt0ccr1 register include s enabling of batch write. thus, rewrite the tt0ccr1 register after rewriting the tt0ccr0 register. remark the above flowchart illustrates an example of the operation in the pwm output mode. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 487 of 1817 sep 19, 2011 figure 9-6. timing of batch write d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 0000h d 11 tt0ce bit = 1 note 1 d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter tt0ccr0 register tt0ccr1 register inttt0cc0 signal inttt0cc1 signal tot01 pin output tot00 pin output ccr0 buffer register ccr1 buffer register note 1 note 1 note 1 same value write d 02 d 12 0000h d 03 d 12 note 2 note 3 ffffh notes 1. because the tt0ccr1 register was not rewritten, d 03 is not transferred. 2. because the tt0ccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit counter and the value of the tt0ccr0 register (d 01 ). 3. because the tt0ccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit counter and the value of the tt0ccr0 register (d 02 ). remarks 1. d 01 , d 02 , d 03 : set values of tt0ccr0 register d 11 , d 12 : set values of tt0ccr1 register 2. the above timing chart illustrates the opera tion in the pwm output mode as an example. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 488 of 1817 sep 19, 2011 9.6.1 interval timer mode (tt0md3 to tt0md0 bits = 0000) in the interval timer mode, an interr upt request signal (inttt0cc0 ) is generated at the in terval set by the tt0ccr0 register if the tt0ctl0.tt0ce bit is set to 1. a square wave whose half cycle is equal to the interval can be output from the tot00 pin. the tt0ccr1 register is not used in the interval timer m ode. however, the set value of the tt0ccr1 register is transferred to the ccr1 buffer register, and when the count va lue of the 16-bit counter matc hes the value of the ccr1 buffer register, a compare match interrupt request signal (inttt0cc1) is generated. in addition, a square wave, which is inverted when the inttt0cc1 signal is generat ed, can be output from the tot01 pin. the value of the tt0ccr0 and tt0ccr1 registers can be rewritten even while the timer is operating. figure 9-7. configuration of interval timer 16-bit counter output controller ccr0 buffer register tt0ce bit tt0ccr0 register count clock selection clear match signal tot00 pin inttt0cc0 signal figure 9-8. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register tot00 pin output inttt0cc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 489 of 1817 sep 19, 2011 when the tt0ce bit is set to 1, the value of the 16-bit c ounter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter starts count ing. at this time, the output of the to t00 pin is inverted. additionally, the se t value of the tt0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the tot00 pin is inverted, and a compare match interrupt request signal (inttt0cc0) is generated. the interval can be calculated by the following expression. interval = (set value of tt0ccr0 register + 1) count clock cycle figure 9-9. register setting for in terval timer mode operation (1/2) (a) tmt0 control register 0 (tt0ctl0) 0/1 0 0 0 0 tt0ctl0 select count clock 0: stops counting 1: enables counting 0/1 0/1 0/1 tt0cks2 tt0cks1 tt0cks0 tt0ce (b) tmt0 control register 1 (tt0ctl1) 00000 tt0ctl1 0, 0, 0, 0: interval timer mode 000 tt0md2 tt0md3 tt0md1 tt0md0 tt0eee tt0est (c) tmt0 i/o control register 0 (tt0ioc0) 0 0 0 0 0/1 tt0ioc0 0: disables tot00 pin output 1: enables tot00 pin output setting of tot00 pin output level before count operation 0: low level 1: high level 0: disables tot01 pin output 1: enables tot01 pin output setting of tot01 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tt0oe1 tt0ol0 tt0oe0 tt0ol1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 490 of 1817 sep 19, 2011 figure 9-9. register setting for in terval timer mode operation (2/2) (d) tmt0 counter read buffer register (tt0cnt) by reading the tt0cnt register, the count va lue of the 16-bit counter can be read. (e) tmt0 capture/compare register 0 (tt0ccr0) if the tt0ccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (f) tmt0 capture/compare register 1 (tt0ccr1) the tt0ccr1 register is not used in the interval ti mer mode. however, the set value of the tt0ccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, the tot01 pi n output is inverted and a compare match interrupt request signal (inttt0 cc1) is generated. by setting this register to the same value as the value set in the tt0ccr0 register, a square wave can be output from the tot01 pin. when the tt0ccr1 register is not used, it is reco mmended to set its value to ffffh. also mask the register by the interrupt mask flag (tt0ccic1.tt0ccmk1). remark tmt0 control register 2 (tt0ctl2), tmt0 i/o control register 1 (tt0ioc1), tmt0 i/o control register 2 (tt0ioc2), tmt0 i/o control regi ster 3 (tt0ioc3), tmt0 option register 0 (tt0opt0), tmt0 option register 1 (tt0opt1), and tmt0 counter write register (tt0tcw) are not used in the interval timer mode. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 491 of 1817 sep 19, 2011 (1) interval timer mode operation flow figure 9-10. software processing flow in interval timer mode tt0ce bit = 1 tt0ce bit = 0 register initial setting tt0ctl0 register (tt0cks0 to tt0cks2 bits) tt0ctl1 register, tt0ioc0 register, tt0ccr0 register initial setting of these registers is performed before setting the tt0ce bit to 1. the tt0cks0 to tt0cks2 bits can be set at the same time as when counting starts (tt0ce bit = 1). the counter is initialized and counting is stopped by clearing the tt0ce bit to 0. the output level of the tot00 pin is as specified by the tt0ioc0 register. start stop <1> count operation start flow <2> count operation stop flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register tot00 pin output inttt0cc0 signal v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 492 of 1817 sep 19, 2011 (2) interval timer mode operation timing (a) operation if tt0ccr0 re gister is set to 0000h if the tt0ccr0 register is set to 0000h, the inttt0cc0 signal is generated at each count clock, and the output of the tot00 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tt0ce bit tt0ccr0 register tot00 pin output inttt0cc0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 493 of 1817 sep 19, 2011 (b) operation if tt0ccr0 register is set to ffffh if the tt0ccr0 register is set to ffffh, the 16-bit c ounter counts up to ffffh. t he counter is cleared to 0000h in synchronization with the next count-up timing. the inttt0cc0 sign al is generated a nd the output of the tot00 pin is inverted. at this time, an overflow in terrupt request signal (inttt0ov ) is not generated, nor is the overflow flag (tt0opt0 .tt0ovf bit) set to 1. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register tot00 pin output inttt0cc0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 494 of 1817 sep 19, 2011 (c) notes on rewriting tt0ccr0 register if the value of the tt0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting and then change the set value. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register tt0ol0 bit tot00 pin output inttt0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remark interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle if the value of the tt0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tt0ccr0 register has been rewritten. consequently, the value of t he 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttt0cc0 signal is generated and the output of the to t00 pin is inverted. therefore, the inttt0cc0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? as originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock cycle?. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 495 of 1817 sep 19, 2011 (d) operation of tt0ccr1 register figure 9-11. configuration of tt0ccr1 register ccr0 buffer register tt0ccr0 register tt0ccr1 register ccr1 buffer register tot00 pin inttt0cc0 signal tot01 pin inttt0cc1 signal 16-bit counter output controller tt0ce bit count clock selection clear match signal output controller match signal v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 496 of 1817 sep 19, 2011 when the tt0ccr1 register is set to the same val ue as the tt0ccr0 register, the inttt0cc0 signal is generated at the same timing as the inttt0cc1 signal and the to t01 pin output is inverted. in other words, a square wave can be output from the tot01 pin. the following shows the operation when the tt0ccr1 r egister is set to other than the value set in the tt0ccr0 register. if the set value of the tt0ccr1 register is less than the set value of the tt0ccr0 register, the inttt0cc1 signal is generated once per cycle. at the same time, the output of the tot01 pin is inverted. the tot01 pin outputs a square wave after outputting a short-width pulse. figure 9-12. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register tot00 pin output inttt0cc0 signal tt0ccr1 register tot01 pin output inttt0cc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 497 of 1817 sep 19, 2011 if the set value of the tt0ccr1 register is greater than the set value of the tt0ccr0 register, the count value of the 16-bit counter does not matc h the value of the tt0ccr1 register. consequently, the inttt0cc1 signal is not generated, nor is the out put of the tot01 pin changed. when the tt0ccr1 register is not used, it is recommended to set its value to ffffh. figure 9-13. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register tot00 pin output inttt0cc0 signal tt0ccr1 register tot01 pin output inttt0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 498 of 1817 sep 19, 2011 9.6.2 external event count mode (tt0md3 to tt0md0 bits = 0001) in the external event count mode, the valid edge of the external event count input (tenc00) is counted when the tt0ctl0.tt0ce bit is set to 1, and an inte rrupt request signal (inttt0cc0) is ge nerated each time the number of edges set by the tt0ccr0 register have been counted. the tot00 and tot01 pins cannot be used. the tt0ccr1 register is not used in the external event count mode. figure 9-14. configuration in external event count mode 16-bit counter ccr0 buffer register tt0ce bit tt0ccr0 register edge detector note clear match signal inttt0cc0 signal tenc00 pin (external event count input) note set by the tt0ioc2.tt0ees1 and tt0ioc2.tt0ees0 bits. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 499 of 1817 sep 19, 2011 figure 9-15. basic timing in external event count mode ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal d 0 d 0 d 0 d 0 16-bit counter tt0ccr0 register inttt0cc0 signal external event count input (tenc00 pin input) d 0 external event count (d 0 + 1) external event count (d 0 + 1) external event count (d 0 + 1) d 0 ? 1d 0 0000 0001 remark this figure shows the basic timing when the risi ng edge is specified as the valid edge of the external event count input. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 500 of 1817 sep 19, 2011 when the tt0ce bit is set to 1, the value of the 16-bit c ounter is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tt0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt re quest signal (inttt0 cc0) is generated. the inttt0cc0 signal is gene rated each time the valid edge of the exte rnal event count input has been detected ?value set to tt0ccr0 register + 1? times. figure 9-16. register setting for operati on in external event count mode (1/2) (a) tmt0 control register 0 (tt0ctl0) 0/1 0 0 0 0 tt0ctl0 0: stops counting 1: enables counting 000 tt0cks2 tt0cks1 tt0cks0 tt0ce (b) tmt0 control register 1 (tt0ctl1) 00000 tt0ctl1 0, 0, 0, 1: external event count mode 001 tt0md2 tt0md3 tt0md1 tt0md0 tt0eee tt0est (c) tmt0 i/o control register 2 (tt0ioc2) 0 0 0 0 0/1 tt0ioc2 select valid edge of external event count input (tenc00 pin) 0/1 0 0 tt0ees0 tt0ets1 tt0ets0 tt0ees1 (d) tmt0 counter read buffer register (tt0cnt) the count value of the 16-bit counter can be read by reading the tt0cnt register. (e) tmt0 capture/compare register 0 (tt0ccr0) if the tt0ccr0 register is set to d 0 , the count is cleared when the number of external events has reached (d 0 + 1) and the compare match interrupt req uest signal (inttt0cc0) is generated. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 501 of 1817 sep 19, 2011 figure 9-16. register setting for operati on in external event count mode (2/2) (f) tmt0 capture/compare register 1 (tt0ccr1) the tt0ccr1 register is not used in the external ev ent count mode. however, the set value of the tt0ccr1 register is transferred to the ccr1 buffer re gister. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a co mpare match interrupt requ est signal (inttt0cc1) is generated. when the tt0ccr1 register is not used, it is recommended to set its value to ffffh. also mask the register by the interrupt mask flag (tt0ccic1.tt0ccmk1). remark tmt0 control register 2 (tt0ctl2), tmt0 i/o c ontrol register 0 (tt0ioc0), tmt0 i/o control register 1 (tt0ioc1), tmt0 i/o control regi ster 3 (tt0ioc3), tmt0 option register 0 (tt0opt0), tmt0 option register 1 (tt0opt1), and tmt0 counter write register (tt0tcw) are not used in the external event count mode. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 502 of 1817 sep 19, 2011 (1) external event count mode operation flow figure 9-17. software processing flow in external event count mode tt0ce bit = 1 tt0ce bit = 0 register initial setting tt0ctl1 register, tt0ioc2 register, tt0ccr0, tt0ccr1 registers initial setting of these registers is performed before setting the tt0ce bit to 1. the counter is initialized and counting is stopped by clearing the tt0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow d 0 d 0 d 0 d 0 <1> <2> ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 503 of 1817 sep 19, 2011 (2) operation timing in external event count mode (a) operation if tt0ccr0 re gister is set to 0000h when the tt0ccr0 register is set to 0000h, the 16-bit counter is repeatedly cleared to 0000h and generates the inttt0cc0 signal each time it has detected the vali d edge of the external event count signal and its value has matched that of the ccr0 buffer register. the value of the 16-bit counter is always 0000h. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal 0000h inttt0cc0 signal is generated each time the 16-bit counter counts the valid edge of the external event count input. (b) operation if tt0ccr0 register is set to ffffh if the tt0ccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh each time the valid edge of the external event count signal has be en detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the inttt0cc0 signal is generated. at this time, the tt0opt0.tt0ovf bit is not set. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal ffffh external event count: 10000h external event count: 10000h external event count: 10000h v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 504 of 1817 sep 19, 2011 (c) operation with tt0ccr0 set to ffffh and tt0ccr1 register to 0000h when the tt0ccr0 register is set to ffffh, the 16-bit c ounter counts up to ffffh each time it has detected the valid edge of the external event count signal. the c ounter is then cleared to 0000h in synchronization with the next count-up timing and the inttt0cc0 signal is generated. at this time, the tt0opt0.tt0ovf bit is not set. if the tt0ccr1 register is set to 0000h, the inttt0cc1 si gnal is generated when the 16-bit counter is cleared to 0000h. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tt0ccr1 register inttt0cc1 signal ffffh 0000h v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 505 of 1817 sep 19, 2011 (d) notes on rewriting tt0ccr0 register if the value of the tt0ccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting once and then change the set value. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count (1): (d 1 + 1) external event count (ng): (10000h + d 2 + 1) external event count (2): (d 2 + 1) if the value of the tt0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tt0ccr0 register has been rewritten. consequently, the value that is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit counter co unts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the inttt0cc0 signal is generated. therefore, the inttt0cc0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? as originally expected, but may be ge nerated at the valid edge count of ?(10000h + d 2 + 1) times?. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 506 of 1817 sep 19, 2011 (e) operation of tt0ccr1 register figure 9-18. configuration of tt0ccr1 register ccr0 buffer register tt0ce bit tt0ccr0 register 16-bit counter tt0ccr1 register ccr1 buffer register clear match signal match signal inttt0cc0 signal inttt0cc1 signal edge detector note tenc00 pin (external event count input) note set by the tt0ioc2.tt0ees1 and tt0ioc2.tt0ees0 bits. if the set value of the tt0ccr1 regist er is smaller than the set value of the tt0ccr0 regist er, the inttt0cc1 signal is generated once per cycle. figure 9-19. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tt0ccr1 register inttt0cc1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 507 of 1817 sep 19, 2011 if the set value of the tt0ccr1 register is greater t han the set value of the tt0ccr0 register, the inttt0cc1 signal is not generated because the count value of the 16-bit counter and the val ue of the tt0ccr1 register do not match. when the tt0ccr1 register is not used, it is recommended to set its value to ffffh. figure 9-20. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tt0ccr1 register inttt0cc1 signal d 01 d 11 d 01 d 01 d 01 d 01 l v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 508 of 1817 sep 19, 2011 9.6.3 external trigger pulse output m ode (tt0md3 to tt0md0 bits = 0010) in the external trigger pulse output mode, 16-bit timer/ev ent counter t waits for a trigger when the tt0ctl0.tt0ce bit is set to 1. when the valid edge of an external trigger input (tenc00) is detected, 16-bit timer/event counter t starts counting, and outputs a pwm wave form from the tot01 pin. pulses can also be output by generating a software trigger inst ead of using the external trigger. when using a software trigger, a square wave that has the set value of the tt0ccr0 register + 1 as half its cycle can also be output from the tot00 pin. figure 9-21. configuration in external trigger pulse output mode ccr0 buffer register tt0ce bit tt0ccr0 register 16-bit counter tt0ccr1 register ccr1 buffer register clear match signal match signal inttt0cc0 signal output controller (rs-ff) output controller tot01 pin inttt0cc1 signal tot00 pin count clock selection internal count clock count start control edge detector note 2 software trigger generation tenc00 pin note 1 (external trigger input/ external event count input) edge detector note 3 transfer transfer s r notes 1. the external trigger input (tenc00) pin is also used for the external event count input function. in the external trigger pulse output mode, theref ore, the external event count input function cannot be used. 2. edge detector for external trigger input. set by the tt0ioc2.tt0ets1 and tt0ioc2.tt0ets0 bits. 3. edge detector for external event count input. set by the tt0ioc2.tt0 ees1 and tt0ioc2.tt0ees0 bits. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 509 of 1817 sep 19, 2011 figure 9-22. basic timing in exte rnal trigger pulse output mode d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tot00 pin output tt0ccr1 register inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) 16-bit timer/event counter t waits for a trigger when the tt0ce bi t is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counting at the same time, and outputs a pwm waveform from the tot01 pin. if the trigger is generated again while the counter is o perating, the counter is cleared to 0000h and restarted. (the output of the tot00 pin is inverted. th e tot01 pin outputs a high level regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tt0ccr1 register) count clock cycle cycle = (set value of tt0ccr0 register + 1) count clock cycle duty factor = (set value of tt0ccr1 regist er)/(set value of tt0ccr0 register + 1) the compare match request signal (inttt0cc0) is generated the next time the 16-bit counter counts after its count value matches the value of the ccr0 buffer register, and t he 16-bit counter is cleared to 0000h. the compare match interrupt request signal (inttt0cc1) is generated when the c ount value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tt0ccrn register is transferred to the ccrn buffer register when t he count value of the 16-bit counter matches the value of the ccrn buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input (tenc00), or se tting the software trigger (tt0ctl1.tt0est bit) to 1 is used as the trigger (n = 0, 1). v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 510 of 1817 sep 19, 2011 figure 9-23. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmt0 control register 0 (tt0ctl0) 0/1 0 0 0 0 tt0ctl0 select count clock 0: stops counting 1: enables counting 0/1 0/1 0/1 tt0cks2 tt0cks1 tt0cks0 tt0ce (b) tmt0 control register 1 (tt0ctl1) 0 0/1 0 0 0 tt0ctl1 generates software trigger when 1 is written 010 tt0md2 tt0md1 tt0md0 tt0eee tt0est 0, 0, 1, 0: external trigger pulse output mode tt0md3 (c) tmt0 i/o control register 0 (tt0ioc0) 0 0 0 0 0/1 tt0ioc0 0: disables tot00 pin output 1: enables tot00 pin output setting of tot00 pin output level while waiting for external trigger 0: low level 1: high level 0: disables tot01 pin output 1: enables tot01 pin output setting of tot01 pin output level while waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 tt0oe1 tt0ol0 tt0oe0 tt0ol1 tot01 pin output 16-bit counter ? when tt0ol1 bit = 0 tot01 pin output 16-bit counter ? when tt0ol1 bit = 1 (d) tmt0 i/o control register 2 (tt0ioc2) 00000 tt0ioc2 select valid edge of external trigger input (tenc00 pin) note 0 0/1 0/1 tt0ees0 tt0ets1 tt0ets0 tt0ees1 note set the valid edge selection of the unused alter nate external input signals to ?no edge detection?. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 511 of 1817 sep 19, 2011 figure 9-23. setting of registers in exte rnal trigger pulse output mode (2/2) (e) tmt0 counter read buffer register (tt0cnt) the value of the 16-bit counter can be read by reading the tt0cnt register. (f) tmt0 capture/compare regist ers 0 and 1 (tt0ccr0 and tt0ccr1) if d 0 is set to the tt0ccr0 register and d 1 to the tt0ccr1 register, the cycl e and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remark tmt0 control register 2 (tt0ctl2), tmt0 i/o c ontrol register 1 (tt0ioc1), tmt0 i/o control register 3 (tt0ioc3), tmt0 option register 0 ( tt0opt0), tmt0 option register 1 (tt0opt1), and tmt0 counter write register (tt0tcw) are not used in the external trigger pulse output mode. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 512 of 1817 sep 19, 2011 (1) operation flow in extern al trigger pulse output mode figure 9-24. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register ccr0 buffer register inttt0cc0 signal tot00 pin output tt0ccr1 register ccr1 buffer register inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 513 of 1817 sep 19, 2011 figure 9-24. software processing flow in ex ternal trigger pulse output mode (2/2) tt0ce bit = 1 setting of tt0ccr0 register register initial setting tt0ctl0 register (tt0cks0 to tt0cks2 bits) tt0ctl1 register, tt0ioc0 register, tt0ioc2 register, tt0ccr0 register, tt0ccr1 register initial setting of these registers is performed before setting the tt0ce bit to 1. the tt0cks0 to tt0cks2 bits can be set at the same time as when counting is enabled (tt0ce bit = 1). trigger wait status. writing the same value (same as preset value of the tt0ccr1 register) to the tt0ccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the values of the tt0ccrn register are transferred to the ccrn buffer register in a batch. start setting of tt0ccr1 register <1> count operation start flow <2> tt0ccr0 and tt0ccr1 register setting change flow setting of tt0ccr0 register when the counter is cleared after setting, the value of the tt0ccrn register is transferred to the ccrn buffer register. setting of tt0ccr1 register <4> tt0ccr0, tt0ccr1 register setting change flow writing of the tt0ccr1 register must be performed when only the set duty factor is changed. when the counter is cleared after setting, the value of the tt0ccrn register is transferred to the ccrn buffer register. setting of tt0ccr1 register <3> tt0ccr0, tt0ccr1 register setting change flow tt0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 514 of 1817 sep 19, 2011 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tt0ccr1 register last. rewrite the tt0ccrn register after writing the tt0ccr1 regi ster after the inttt0cc0 signal is detected. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register ccr0 buffer register inttt0cc0 signal tot00 pin output tt0ccr1 register ccr1 buffer register inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 515 of 1817 sep 19, 2011 in order to transfer data from the tt0ccrn register to th e ccrn buffer register, the tt0ccr1 register must be written. to change both the cycle and active level width of the pw m waveform at this time, first set the cycle to the tt0ccr0 register and then set the active level width to the tt0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tt0ccr0 register, and then write the same value (same as preset value of t he tt0ccr1 register) to the tt0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tt0ccr1 register has to be set. after data is written to the tt0ccr1 register, the value written to the tt0ccrn register is transferred to the ccrn buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tt0ccr0 or tt0ccr1 register again after writing the tt0ccr1 register once, do so after the inttt0cc0 signal is generated. otherwise, the value of the ccrn buffer regist er may become undefined because the timing of transferring data from the tt0ccrn register to the ccrn buffer register conflicts with writing the tt0ccrn register. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 516 of 1817 sep 19, 2011 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tt0ccr1 register to 0000 h. the 16-bit counter is cleared to 0000h and the inttt0cc0 and inttt0cc1 signals are generated after a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. count clock 16-bit counter tt0ce bit tt0ccr0 register tt0ccr1 register inttt0cc0 signal inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 note note note note note the timing is actually delayed by one operating clock (f xx ). v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 517 of 1817 sep 19, 2011 to output a 100% waveform, set a value of (set value of tt0ccr0 register + 1) to the tt0ccr1 register. if the set value of the tt0ccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tt0ce bit tt0ccr0 register tt0ccr1 register inttt0cc0 signal inttt0cc1 signal tot01 pin output d 0 ? 1d 0 ? 1 external trigger input (tenc00 pin input) note note note the timing is actually delayed by one operating clock (f xx ). v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 518 of 1817 sep 19, 2011 (c) conflict between trigger detection and match with ccr1 buffer register if the trigger is detected immediately after the in ttt0cc1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the tot01 pin is assert ed, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter ccr1 buffer register inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened if the trigger is detected immediatel y before the inttt0cc1 signal is gene rated, the inttt0cc1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. the output signal of the tot01 pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccr1 buffer register inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 519 of 1817 sep 19, 2011 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the inttt0cc0 signal is generated, the 16-bit counter is cleared to 0000h and continues counting up again from that point. therefore, the active period of the tot01 pin is extended by the time from generation of the inttt0cc0 signal to trigger detection. 16-bit counter ccr0 buffer register inttt0cc0 signal tot01 pin output external trigger input (tenc00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended if the trigger is detected immediatel y before the inttt0cc0 signal is gene rated, the inttt0cc0 signal is not generated. the 16-bit counter is cleared to 0000h, t he tot01 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccr0 buffer register inttt0cc0 signal tot01 pin output external trigger input (tenc00 pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 520 of 1817 sep 19, 2011 (e) generation timing of compare match interrupt request signal (inttt0cc1) the timing of generating the inttt0cc1 signal in the external trigger pulse output mode differs from the timing of generating inttt0cc1 signals in other modes; the inttt0cc1 signal is generated when the count value of the 16-bit counter matches the value of the tt0ccr1 register. count clock 16-bit counter tt0ccr1 register tot01 pin output inttt0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). usually, the inttt0cc1 signal is generated in synchroniza tion with the next count-up, after the count value of the 16-bit counter matches the value of the tt0ccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing when the output signal of the tot01 pin changes. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 521 of 1817 sep 19, 2011 9.6.4 one-shot pulse output mode (tt0md3 to tt0md0 bits = 0011) in the one-shot pulse output mode, 16-bit timer/event counte r t waits for a trigger when the tt0ctl0.tt0ce bit is set to 1. when the valid edge of an external trigger input (evtt0 ) is detected, 16-bit timer/even t counter t starts counting, and outputs a one-shot pulse from the tot01 pin. instead of the external trigger input (evtt0), a software tr igger can also be generated to output the pulse. when the software trigger is used, the tot00 pin outputs the active leve l while the 16-bit counter is c ounting, and the inactive level when the counter is stopped (waiting for a trigger). figure 9-25. configuration in one-shot pulse output mode ccr0 buffer register tt0ce bit tt0ccr0 register 16-bit counter tt0ccr1 register ccr1 buffer register clear match signal match signal inttt0cc0 signal output controller (rs-ff) output controller (rs-ff) tot01 pin inttt0cc1 signal tot00 pin count clock selection internal count clock count start control edge detector note 2 software trigger generation edge detector note 3 transfer transfer s r s r tenc00 pin note 1 (external trigger input/ external event count input) notes 1. because the tenc00 pin functions as both an exte rnal trigger input and a external event count input, the external event count input function (evtt0) cannot be used when using an external trigger input. 2. edge detector for external trigger input. set by the tt0ioc2.tt0ets1 and tt0ioc2.tt0ets0 bits. 3. edge detector for external event count input. set by the tt0ioc2.tt0 ees1 and tt0ioc2.tt0ees0 bits. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 522 of 1817 sep 19, 2011 figure 9-26. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tot00 pin output tt0ccr1 register inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) when the tt0ce bit is set to 1, 16-bit timer/event counter t wa its for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, st arts counting, and outputs a one-shot pulse from the tot01 pin. after the one- shot pulse is output, the 16-bit counter is cleared to 0000h, stops counting, and waits for a trigger. when the trigger is generated again, the 16-bit count er starts counting from 0000h. if a trigger is generated again while the one-shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tt0ccr1 register) count clock cycle active level width = (set value of tt0ccr0 register ? set value of tt0ccr1 register + 1) count clock cycle the compare match interrupt request signa l (inttt0cc0) is generated the next time the 16-bit counter counts after its count value matches the va lue of the ccr0 buffer register. the compar e match interrupt reques t signal (inttt0cc1) is generated when the count value of the 16-bit counter matches the val ue of the ccr1 buffer register. the valid edge of an external trigger input (tenc00 pin) or setting the software trigger (tt0ctl1.tt0est bit) to 1 is used as the trigger. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 523 of 1817 sep 19, 2011 figure 9-27. setting of registers in one-shot pulse output mode (1/2) (a) tmt0 control register 0 (tt0ctl0) 0/1 0 0 0 0 tt0ctl0 select count clock note 0: stops counting 1: enables counting 0/1 0/1 0/1 tt0cks2 tt0cks1 tt0cks0 tt0ce note the setting is invalid when the tt0ctl1.tt0eee bit = 1. (b) tmt0 control register 1 (tt0ctl1) 0 0/1 0 0 0 tt0ctl1 generates software trigger when 1 is written 011 tt0md2 tt0md1 tt0md0 tt0eee tt0est 0, 0, 1, 1: one-shot pulse output mode tt0md3 (c) tmt0 i/o control register 0 (tt0ioc0) 0 0 0 0 0/1 tt0ioc0 0: disables tot00 pin output 1: enables tot00 pin output setting of tot00 pin output level while waiting for external trigger 0: low level 1: high level 0: disables tot01 pin output 1: enables tot01 pin output setting of tot01 pin output level while waiting for external trigger 0: low level 1: high level 0/1 0/1 0/1 tt0oe1 tt0ol0 tt0oe0 tt0ol1 tot01 pin output 16-bit counter ? when tt0ol1 bit = 0 tot01 pin output 16-bit counter ? when tt0ol1 bit = 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 524 of 1817 sep 19, 2011 figure 9-27. setting of registers in one-shot pulse output mode (2/2) (d) tmt0 i/o control register 2 (tt0ioc2) 00000 tt0ioc2 select valid edge of external trigger input (tenc00 pin) note 0 0/1 0/1 tt0ees0 tt0ets1 tt0ets0 tt0ees1 note set the valid edge selection of the unused alternate external input signals to ?no edge detection?. (e) tmt0 counter read buffer register (tt0cnt) the value of the 16-bit counter can be read by reading the tt0cnt register. (f) tmt0 capture/compare regist ers 0 and 1 (tt0ccr0 and tt0ccr1) if d 0 is set to the tt0ccr0 register and d 1 to the tt0ccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 0 ? d 1 + 1) count clock cycle output delay period = d 1 count clock cycle remark tmt0 control register 2 (tt0 ctl2), tmt0 i/o control register 1 (tt0ioc1), tmt0 i/o control register 3 (tt0ioc3), tmt0 option register 0 ( tt0opt0), tmt0 option register 1 (tt0opt1), and tmt0 counter write register (tt0tcw) are not used in the one-shot pulse output mode. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 525 of 1817 sep 19, 2011 (1) operation flow in one-shot pulse output mode figure 9-28. software processing flow in one-shot pulse output mode <1> <2> <3> start stop d 10 d 11 d 00 d 01 d 00 d 10 d 11 d 01 setting of tt0ccr0, tt0ccr1 registers <2> tt0ccr0, tt0ccr1 register setting change flow tt0ce bit = 1 tt0ce bit = 0 register initial setting tt0ctl0 register (tt0cks0 to tt0cks2 bits) tt0ctl1 register, tt0ioc0 register, tt0ioc2 register, tt0ccr0 register, tt0ccr1 register initial setting of these registers is performed before setting the tt0ce bit to 1. the tt0cks0 to tt0cks2 bits can be set at the same time as when counting starts (tt0ce bit = 1). trigger wait status count operation is stopped <1> count operation start flow <3> count operation stop flow ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tt0ccr1 register inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) as rewriting the tt0ccrn register immediately forwards to the ccrn buffer register, rewriting immediately after the generation of the inttt0cc0 signal is recommended. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 526 of 1817 sep 19, 2011 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tt0ccrn register if the value of the tt0ccrn register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting and then change the set value. remark n = 0, 1 d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tot00 pin output tt0ccr1 register inttt0cc1 signal tot01 pin output external trigger input (tenc00 pin input) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) when the tt0ccr0 register is rewritten from d 00 to d 01 and the tt0ccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tt0ccr1 register is rewritten when the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tt0ccr0 register is rewritt en when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter counts up to ffffh and t hen counts up again from 0000h. when the count value matches d 11 , the counter generates the inttt0cc1 signal and asserts the tot01 pin. when the count value matches d 01 , the counter generate s the inttt0cc0 signal, deasserts the tot01 pin, and stops counting. therefore, the counter may output a pu lse with a delay period or active per iod different from that of the one- shot pulse that is originally expected. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 527 of 1817 sep 19, 2011 (b) generation timing of compare match interrupt request signal (inttt0cc1) the generation timing of the in ttt0cc1 signal in the on e-shot pulse output mode is different from inttt0cc1 signals in other modes; the inttt0cc1 signal is generated when the co unt value of the 16-bit counter matches the value of the tt0ccr1 register. count clock 16-bit counter tt0ccr1 register tot01 pin output inttt0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). usually, the inttt0cc1 signal is generated the next time the 16-bit counter counts up after its count value matches the value of the tt0ccr1 register. in the one-shot pulse output mode, however, it is gene rated one clock earlier. this is because the timing is changed to match the timing the output signal of the tot01 pin changes. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 528 of 1817 sep 19, 2011 9.6.5 pwm output mode (tt0 md3 to tt0md0 bits = 0100) in the pwm output mode, a pwm waveform is output from the tot01 pin when the tt0ctl0.tt0ce bit is set to 1. in addition, a square wave with the set value of the tt0ccr0 r egister + 1 as half its cycle is output from the tot00 pin. figure 9-29. configuration in pwm output mode ccr0 buffer register tt0ce bit tt0ccr0 register 16-bit counter tt0ccr1 register ccr1 buffer register clear match signal match signal inttt0cc0 signal output controller (rs-ff) output controller tot01 pin inttt0cc1 signal tot00 pin transfer transfer s r count clock selection internal count clock tenc00 pin (external event count input) edge detector note note set by the tt0ioc2.tt0ees1 and tt0ioc2.tt0ees0 bits. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 529 of 1817 sep 19, 2011 figure 9-30. basic timing in pwm output mode ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register ccr0 buffer register inttt0cc0 signal tot00 pin output tt0ccr1 register ccr1 buffer register inttt0cc1 signal tot01 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 - d 10 + 1) when the tt0ce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts counting, and outputs a pwm waveform from the tot01 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tt0ccr1 register) count clock cycle cycle = (set value of tt0ccr0 register + 1) count clock cycle duty factor = (set value of tt0ccr1 regist er)/(set value of tt0ccr0 register + 1) the pwm waveform can be changed by rewriting the tt0ccrn register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the va lue of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signa l (inttt0cc0) is generated the next time the 16-bit counter counts after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is clear ed to 0000h. the compare match interrupt request signal (inttt0cc1 ) is generated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tt0ccrn register is transferred to the ccrn buffer register when t he count value of the 16-bit counter matches the value of the ccrn buffer regi ster and the 16-bit counter is cleared to 0000h. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 530 of 1817 sep 19, 2011 figure 9-31. setting of registers in pwm output mode (1/2) (a) tmt0 control register 0 (tt0ctl0) 0/1 0 0 0 0 tt0ctl0 select count clock note 0: stops counting 1: enables counting 0/1 0/1 0/1 tt0cks2 tt0cks1 tt0cks0 tt0ce note the setting is invalid when the tt0ctl1.tt0eee bit = 1. (b) tmt0 control register 1 (tt0ctl1) 0 0 0/1 0 0 tt0ctl1 100 tt0md2 tt0md1 tt0md0 tt0eee tt0est 0, 1, 0, 0: pwm output mode 0: operates on count clock selected by tt0cks0 to tt0cks2 bits 1: counts with external event count input signal tt0md3 (c) tmt0 i/o control register 0 (tt0ioc0) 0 0 0 0 0/1 tt0ioc0 0: disables tot00 pin output 1: enables tot00 pin output setting of tot00 pin output level before count operation 0: low level 1: high level 0: disables tot01 pin output 1: enables tot01 pin output setting of tot01 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tt0oe1 tt0ol0 tt0oe0 tt0ol1 tot01 pin output 16-bit counter ? when tt0ol1 bit = 0 tot01 pin output 16-bit counter ? when tt0ol1 bit = 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 531 of 1817 sep 19, 2011 figure 9-31. register setting in pwm output mode (2/2) (d) tmt0 i/o control register 2 (tt0ioc2) 0 0 0 0 0/1 tt0ioc2 select valid edge of external event count input (tenc00 pin). 0/1 0 0 tt0ees0 tt0ets1 tt0ets0 tt0ees1 (e) tmt0 counter read buffer register (tt0cnt) the value of the 16-bit counter can be read by reading the tt0cnt register. (f) tmt0 capture/compare regist ers 0 and 1 (tt0ccr0 and tt0ccr1) if d 0 is set to the tt0ccr0 register and d 1 to the tt0ccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remark tmt0 control register 2 (tt0 ctl2), tmt0 i/o control register 1 (tt0ioc1), tmt0 i/o control register 3 (tt0ctl3), tmt0 option register 0 (tt0opt0), tmt0 option register 1 (tt0opt1), and tmt0 counter write register (tt0tcw) are not used in the pwm output mode. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 532 of 1817 sep 19, 2011 (1) operation flow in pwm output mode figure 9-32. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register ccr0 buffer register inttt0cc0 signal tot00 pin output tt0ccr1 register ccr1 buffer register inttt0cc1 signal tot01 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 533 of 1817 sep 19, 2011 figure 9-32. software processing flow in pwm output mode (2/2) tt0ce bit = 1 setting of tt0ccr0 register register initial setting tt0ctl0 register (tt0cks0 to tt0cks2 bits) tt0ctl1 register, tt0ioc0 register, tt0ioc2 register, tt0ccr0 register, tt0ccr1 register initial setting of these registers is performed before setting the tt0ce bit to 1. the tt0cks0 to tt0cks2 bits can be set at the same time as when counting is enabled (tt0ce bit = 1). writing the same value (same as preset value of the tt0ccr1 register) to the tt0ccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tt0ccrn register is transferred to the ccrn buffer register. start setting of tt0ccr1 register <1> count operation start flow <2> tt0ccr0, tt0ccr1 register setting change flow (cycle only) setting of tt0ccr0 register when the counter is cleared after setting, the values of compare register n are transferred to the ccrn buffer register in a batch. setting of tt0ccr1 register <4> tt0ccr0, tt0ccr1 register setting change flow (cycle and duty) only writing of the tt0ccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register n is transferred to the ccrn buffer register. setting of tt0ccr1 register <3> tt0ccr0, tt0ccr1 register setting change flow (duty only) tt0ce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 534 of 1817 sep 19, 2011 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tt0ccr1 register last. rewrite the tt0ccrn register after writing the tt0ccr1 regi ster after the inttt0cc1 signal is detected. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register ccr0 buffer register tt0ccr1 register ccr1 buffer register tot01 pin output inttt0cc0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tt0ccrn register to the ccrn bu ffer register, the tt0ccr1 register must be written. to change both the cycle and active level of the pwm wavefo rm at this time, first set the cycle to the tt0ccr0 register and then set the active level width to the tt0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tt0ccr0 register, and then write the same value (same as preset value of t he tt0ccr1 register) to the tt0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tt0ccr1 register has to be set. after data is written to the tt0ccr1 register, the value written to the tt0ccrn register is transferred to the ccrn buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tt0ccr0 or tt0ccr1 register again after writing the tt0ccr1 register once, do so after the inttt0cc0 signal is generated. otherwise, the value of the ccrn buffer regist er may become undefined because the timing of transferring data from the tt0ccrn register to the ccrn buffer register conflicts with writing the tt0ccrn register. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 535 of 1817 sep 19, 2011 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tt0ccr1 register to 0000 h. the 16-bit counter is cleared to 0000h and the inttt0cc0 and inttt0cc1 signals are generated after a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. count clock 16-bit counter tt0ce bit tt0ccr0 register tt0ccr1 register inttt0cc0 signal inttt0cc1 signal tot01 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 l note note note note note the timing is actually delayed by one operating clock (f xx ). to output a 100% waveform, set a value of (set value of tt0ccr0 register + 1) to the tt0ccr1 register. if the set value of the tt0ccr0 register is ffffh, 100% output cannot be produced. d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 0000 ffff 0000 d 00 0000 0001 count clock 16-bit counter tt0ce bit tt0ccr0 register tt0ccr1 register inttt0cc0 signal inttt0cc1 signal tot01 pin output d 00 ? 1d 00 ? 1 note note note the timing is actually delayed by one operating clock (f xx ). v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 536 of 1817 sep 19, 2011 (c) generation timing of compare match interrupt request signal (inttt0cc1) the timing of generation of the inttt0cc1 signal in the pwm output mode differs from the timing of inttt0cc1 signals in other modes; the inttt0cc1 signal is generated when the co unt value of the 16-bit counter matches the value of the tt0ccr1 register. count clock 16-bit counter tt0ccr1 register tot01 pin output inttt0cc1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 note note note the timing is actually delayed by one operating clock (f xx ). usually, the inttt0cc1 signal is gene rated in synchronization with the next count-up after the count value of the 16-bit counter matches the value of the tt0ccr1 register. in the pwm output mode, however, it is generated one cl ock earlier. this is because the timing is changed to match the timing at which the output signal of the tot01 pin changes. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 537 of 1817 sep 19, 2011 9.6.6 free-running timer mode ( tt0md3 to tt0md0 bits = 0101) in the free-running timer mode, 16-bit timer/event counter t st arts counting when the tt0ctl0.tt0ce bit is set to 1. at this time, the tt0ccr0 and tt0ccr1 registers can be used as compare registers or capture registers, depending on the setting of the tt0opt0.tt0ccs0 and tt0opt0.tt0ccs1 bits. figure 9-33. configuration in free-running timer mode tt0ccr0 register (capture) tt0ce bit tt0ccr1 register (compare) 16-bit counter tt0ccr1 register (compare) tt0ccr0 register (capture) output controller tt0ccs0, tt0ccs1 bits (capture/compare selection) tot00 pin note 1 output output controller tot01 pin note 1 output edge detector note 2 count clock selection edge detector note 3 edge detector note 4 tenc00 pin (external event count input) tit00 pin note 1 (capture trigger input) tit01 pin note 1 (capture trigger input) internal count clock 0 1 0 1 inttt0ov signal inttt0cc1 signal inttt0cc0 signal notes 1. because the capture trigger input pins (tit00, tit01) also f unction as the timer output pins (tot00, tot01), the timer output functions cannot be used when using an capture trigger input. 2. set by the tt0ioc2.tt0ees1 and tt0ioc2.tt0ees0 bits. 3. set by the tt0ioc1.tt0is1 and tt0ioc1.tt0is0 bits. 4. set by the tt0ioc1.tt0is3 and tt0ioc1.tt0is2 bits. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 538 of 1817 sep 19, 2011 ? compare operation when the tt0ce bit is set to 1, 16-bit timer/event counter t starts counting, and the output signal of the tot0n pin is inverted. when the count value of the 16-bit counter late r matches the set value of the tt0ccrn register, a compare match interrupt request signal (inttt0ccn) is generated, and the output signal of t he tot0n pin is inverted. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttt0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tt0opt0.tt0ovf bit) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. the tt0ccrn register can be rewritten whil e the counter is operating. if it is re written, the new value is reflected at that time by anytime write, an d compared with the count value. figure 9-34. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tot00 pin output tt0ccr1 register inttt0cc1 signal tot01 pin output inttt0ov signal tt0ovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 539 of 1817 sep 19, 2011 ? capture operation when the tt0ce bit is set to 1, the 16- bit counter starts counting. when the valid edge input to the tit0n pin is detected, the count value of the 16-bit counter is stored in the tt0ccrn register, and a capture interrupt request signal (inttt0ccn) is generated. the 16-bit counter continues counting in synchronization with the count clock. when it counts up to ffffh, it generates an overflow interrupt request signal (inttt0ov) at the next clock, is cl eared to 0000h, and continues counting. at this time, the overflow flag (tt0opt0.tt0ovf bit) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. figure 9-35. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tt0ce bit tit00 pin input tt0ccr0 register inttt0cc0 signal tit01 pin input tt0ccr1 register inttt0cc1 signal inttt0ov signal tt0ovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 540 of 1817 sep 19, 2011 figure 9-36. register setting in free-running timer mode (1/2) (a) tmt0 control register 0 (tt0ctl0) 0/1 0 0 0 0 tt0ctl0 select count clock note 0: stops counting 1: enables counting 0/1 0/1 0/1 tt0cks2 tt0cks1 tt0cks0 tt0ce note the setting is invalid wh en the tt0ctl1.tt0eee bit = 1 (b) tmt0 control register 1 (tt0ctl1) 0 0 0/1 0 0 tt0ctl1 101 tt0md2 tt0md1 tt0md0 tt0eee tt0est tt0md3 0, 1, 0, 1: free-running timer mode 0: operates with count clock selected by tt0cks0 to tt0cks2 bits 1: counts on external event count input signal (c) tmt0 i/o control register 0 (tt0ioc0) 0 0 0 0 0/1 tt0ioc0 0: disables tot00 pin output 1: enables tot00 pin output setting of tot00 pin output level before count operation 0: low level 1: high level 0: disables tot01 pin output 1: enables tot01 pin output setting of tot01 pin output level before count operation 0: low level 1: high level 0/1 0/1 0/1 tt0oe1 tt0ol0 tt0oe0 tt0ol1 (d) tmt0 i/o control register 1 (tt0ioc1) 0 0 0 0 0/1 tt0ioc1 select valid edge of tit00 pin input select valid edge of tit01 pin input 0/1 0/1 0/1 tt0is2 tt0is1 tt0is0 tt0is3 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 541 of 1817 sep 19, 2011 figure 9-36. register setting in free-running timer mode (2/2) (e) tmt0 i/o control register 2 (tt0ioc2) 0 0 0 0 0/1 tt0ioc2 select valid edge of external event count input (tenc00 pin) 0/1 0 0 tt0ees0 tt0ets1 tt0ets0 tt0ees1 (f) tmt0 option register 0 (tt0opt0) 0 0 0/1 0/1 0 tt0opt0 overflow flag specifies if tt0ccr0 register functions as capture or compare register 0: compare register 1: capture register specifies if tt0ccr1 register functions as capture or compare register 0: compare register 1: capture register 0 0 0/1 tt0ccs0 tt0ovf tt0ccs1 (g) tmt0 counter read buffer register (tt0cnt) the value of the 16-bit counter can be read by reading the tt0cnt register. (h) tmt0 capture/compare regist ers 0 and 1 (tt0ccr0 and tt0ccr1) these registers function as capt ure registers or compare regist ers depending on the setting of the tt0opt0.tt0ccsn bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to t he tit0n pin is detected. when the registers function as compare registers and when d a is set to the tt0ccrn register, the inttt0ccn signal is generated when the counter reaches (d a + 1), and the output signals of the tot00 and tot01 pins are inverted. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 542 of 1817 sep 19, 2011 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 9-37. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tot00 pin output tt0ccr1 register inttt0cc1 signal tot01 pin output inttt0ov signal tt0ovf bit v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 543 of 1817 sep 19, 2011 figure 9-37. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tt0ce bit = 1 read tt0opt0 register (check overflow flag). register initial setting tt0ctl0 register (tt0cks0 to tt0cks2 bits) tt0ctl1 register, tt0ioc0 register, tt0ioc2 register, tt0opt0 register, tt0ccr0 register, tt0ccr1 register initial setting of these registers is performed before setting the tt0ce bit to 1. the tt0cks0 to tt0cks2 bits can be set at the same time as when counting starts (tt0ce bit = 1). start execute instruction to clear tt0ovf bit (clr tt0ovf). <1> count operation start flow <2> overflow flag clear flow tt0ce bit = 0 counter is initialized and counting is stopped by clearing tt0ce bit to 0. stop <3> count operation stop flow tt0ovf bit = 1 no yes v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 544 of 1817 sep 19, 2011 (b) when using capture/compare register as capture register figure 9-38. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tt0ce bit tit00 pin input tt0ccr0 register inttt0cc0 signal tit01 pin input tt0ccr1 register inttt0cc1 signal inttt0ov signal tt0ovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 545 of 1817 sep 19, 2011 figure 9-38. software processing flow in fr ee-running timer mode (c apture function) (2/2) tt0ce bit = 1 read tt0opt0 register (check overflow flag). register initial setting tt0ctl0 register (tt0cks0 to tt0cks2 bits) tt0ctl1 register, tt0ioc1 register, tt0opt0 register initial setting of these registers is performed before setting the tt0ce bit to 1. the tt0cks0 to tt0cks2 bits can be set at the same time as when counting starts (tt0ce bit = 1). start execute instruction to clear tt0ovf bit (clr tt0ovf). <1> count operation start flow <2> overflow flag clear flow tt0ce bit = 0 counter is initialized and counting is stopped by clearing tt0ce bit to 0. stop <3> count operation stop flow tt0ovf bit = 1 no yes v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 546 of 1817 sep 19, 2011 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter t is used as an interval timer with the tt0ccrn register used as a compare register, software processing is necessary for setting a co mparison value to generate the next interrupt request signal each time the inttt0ccn signal has been detected. ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register inttt0cc0 signal tot00 pin output tt0ccr1 register inttt0cc1 signal tot01 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, t he value of the corresponding tt0ccrn register must be re-set in the interrupt servicing that is executed when the inttt0ccn signal is detected. the set value for re-setting the tt0ccrn register can be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation resu lt is greater than ffffh, subtract 10000h fr om the result and set this value to the register.) v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 547 of 1817 sep 19, 2011 (b) pulse width measurement with capture register when pulse width measurement is performed with the tt0 ccrn register used as a capture register, software processing is necessary for reading the capture register each time t he inttt0ccn signal has been detected and for calculating an interval. 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 ffffh 16-bit counter 0000h tt0ce bit tit00 pin input tt0ccr0 register inttt0cc0 signal tit01 pin input tt0ccr1 register inttt0cc1 signal inttt0ov signal tt0ovf bit pulse interval (d 00 ) pulse interval (10000h + d 01 - d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calcul ated by reading the value of the tt0ccrn register in synchronization with the inttt0ccn signal, and calcul ating the difference between the read value and the previously read value. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 548 of 1817 sep 19, 2011 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tt0ce bit tit00 pin input tt0ccr0 register tit01 pin input tt0ccr1 register inttt0ov signal tt0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tt0ccr0 register (setting of t he default value of the tit00 pin input). <2> read the tt0ccr1 register (setting of t he default value of the tit01 pin input). <3> read the tt0ccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tt0ccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtai n the correct pulse width. use software when using two capture registers. an example of how to use software is shown below. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 549 of 1817 sep 19, 2011 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tt0ce bit inttt0ov signal tt0ovf bit tt0ovf0 flag note tit00 pin input tt0ccr0 register tt0ovf1 flag note tit01 pin input tt0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tt0ovf0 and tt0ovf1 flags are set on the internal ram by software. <1> read the tt0ccr0 register (setting of t he default value of the tit00 pin input). <2> read the tt0ccr1 register (setting of t he default value of the tit01 pin input). <3> an overflow occurs. set the tt0ovf0 and tt0ovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tt0ccr0 register. read the tt0ovf0 flag. if the tt0ovf0 flag is 1, clear it to 0. because the tt0ovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tt0ccr1 register. read the tt0ovf1 flag. if the tt0ovf1 flag is 1, clear it to 0 (the tt0ovf0 flag is cleared in <4>, and the tt0ovf1 flag remains 1). because the tt0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 550 of 1817 sep 19, 2011 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tt0ce bit inttt0ov signal tt0ovf bit tt0ovf0 flag note tit00 pin input tt0ccr0 register tt0ovf1 flag note tit01 pin input tt0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tt0ovf0 and tt0ovf1 flags are set on the internal ram by software. <1> read the tt0ccr0 register (setting of t he default value of the tit00 pin input). <2> read the tt0ccr1 register (setting of t he default value of the tit01 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tt0ccr0 register. read the overflow flag. if the overflow flag is 1, set only the tt0ovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tt0ccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tt0ovf1 flag. if the tt0ovf1 flag is 1, clear it to 0. because the tt0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 551 of 1817 sep 19, 2011 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tt0ce bit tit0n pin input tt0ccrn register inttt0ov signal tt0ovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tt0ccrn register (setting of t he default value of the tit0n pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tt0ccrn register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pu lse width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. remark n = 0, 1 if an overflow occurs twice or more when the capture trigge r interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 552 of 1817 sep 19, 2011 example when capture trigger interval is long ffffh 16-bit counter 0000h tt0ce bit tit0n pin input tt0ccrn register inttt0ov signal tt0ovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tt0ccrn register (setting of t he default value of the tit0n pin input). <2> an overflow occurs. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tt0ccrn register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h). remark n = 0, 1 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tt0ovf bit to 0 with the clr instruction after reading the tt0ovf bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the tt0opt0 register after reading the tt0ovf bit when it is 1. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 553 of 1817 sep 19, 2011 9.6.7 pulse width measurement mode (tt0md3 to tt0md0 bits = 0110) in the pulse width measurement mode, 16-bit timer/event counter t starts counting when the tt0ctl0.tt0ce bit is set to 1. each time the valid edge input to the tit0n pin has been detected, the count value of the 16-bit counter is stored in the tt0ccrn register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the tt0ccrn register after a capture interrupt request signal (inttt0ccn) occurs. as shown in figure 9-39, select either t he tit00 or tit01 pin as t he capture trigger input pin and set the unused pins to ?no edge detection? by using the tt0ioc1 register. figure 9-39. configuration in pulse width measurement mode tt0ccr0 register (capture) tt0ce bit tt0ccr1 register (capture) edge detector note 1 count clock selection edge detector note 2 edge detector note 3 tenc00 pin (external event count input) tit00 pin (capture trigger input) tit01 pin (capture trigger input) internal count clock clear inttt0ov signal inttt0cc0 signal inttt0cc1 signal 16-bit counter notes 1. set by the tt0ioc2.tt0ees1 and tt0ioc2.tt0ees0 bits. 2. set by the tt0ioc1.tt0is1 and tt0ioc1.tt0is0 bits. 3. set by the tt0ioc1.tt0is3 and tt0ioc1.tt0is2 bits. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 554 of 1817 sep 19, 2011 figure 9-40. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tt0ce bit tit0n pin input tt0ccrn register inttt0ccn signal inttt0ov signal tt0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark n = 0, 1 when the tt0ce bit is set to 1, the 16-bit counter starts count ing. when the valid edge input to the tit0n pin is later detected, the count value of the 16-bit counter is stored in the tt0ccrn r egister, the 16-bit counter is cleared to 0000h, and a capture interrupt request si gnal (inttt0ccn) is generated. the pulse width is calculated as follows. pulse width = captured value count clock cycle if the valid edge is not input to the ti t0n pin even when the 16-bit counter counted up to ffffh, an overflow interrupt request signal (inttt0ov) is generated at the next count clock, and the counter is cl eared to 0000h and continues counting. at this time, the overflow flag (tt0opt0.tt0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tt0ovf bit set (1) count + captured value) count clock cycle remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 555 of 1817 sep 19, 2011 figure 9-41. register setting in pu lse width measurement mode (1/2) (a) tmt0 control register 0 (tt0ctl0) 0/1 0 0 0 0 tt0ctl0 select count clock note 0: stops counting 1: enables counting 0/1 0/1 0/1 tt0cks2 tt0cks1 tt0cks0 tt0ce note setting is invalid when the tt0ctl1.tt0eee bit = 1. (b) tmt0 control register 1 (tt0ctl1) 0 0 0/1 0 0 tt0ctl1 110 tt0md2 tt0md1 tt0md0 tt0eee tt0est tt0md3 0, 1, 1, 0: pulse width measurement mode 0: operates with count clock selected by tt0cks0 to tt0cks2 bits 1: counts on external event count input signal (c) tmt0 i/o control register 1 (tt0ioc1) 0 0 0 0 0/1 tt0ioc1 select valid edge of tit00 pin input select valid edge of tit01 pin input 0/1 0/1 0/1 tt0is2 tt0is1 tt0is0 tt0is3 (d) tmt0 i/o control register 2 (tt0ioc2) 0 0 0 0 0/1 tt0ioc2 select valid edge of external event count input (tenc00 pin) 0/1 0 0 tt0ees0 tt0ets1 tt0ets0 tt0ees1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 556 of 1817 sep 19, 2011 figure 9-41. register setting in pu lse width measurement mode (2/2) (e) tmt0 option register 0 (tt0opt0) 00000 tt0opt0 overflow flag 0 0 0/1 tt0ccs0 tt0ovf tt0ccs1 (f) tmt0 counter read buffer register (tt0cnt) the value of the 16-bit counter can be read by reading the tt0cnt register. (g) tmt0 capture/compare regist ers 0 and 1 (tt0ccr0 and tt0ccr1) these registers store the count va lue of the 16-bit counter when the valid edge input to the tit00 and tit01 pins is detected. remark tmt0 control register 2 (tt0 ctl2), tmt0 i/o control register 0 (tt0ioc0), tmt0 i/o control register 3 (tt0ioc3), tmt0 option register 1 (tt0opt1), and tmt0 counter write register (tt0tcw) are not used in the pulse width measurement mode. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 557 of 1817 sep 19, 2011 (1) operation flow in pul se width measurement mode figure 9-42. software processing flow in pulse width measurement mode <1> <2> tt0ce bit = 1 tt0ce bit = 0 register initial setting tt0ctl0 register (tt0cks0 to tt0cks2 bits), tt0ctl1 register, tt0ioc1 register, tt0ioc2 register, tt0opt0 register initial setting of these registers is performed before setting the tt0ce bit to 1. the tt0cks0 to tt0cks2 bits can be set at the same time as when counting starts (tt0ce bit = 1). the counter is initialized and counting is stopped by clearing the tt0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow ffffh 16-bit counter 0000h tt0ce bit tit00 pin input tt0ccr0 register inttt0cc0 signal d 0 0000h 0000h d 1 d 2 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 558 of 1817 sep 19, 2011 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tt0ovf bit to 0 with the clr instruction after reading the tt0ovf bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the tt0opt0 register after reading the tt0ovf bit when it is 1. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 559 of 1817 sep 19, 2011 9.6.8 triangular-wave pwm output mode (tt0md3 to tt0md0 bits = 0111) in the triangular-wave pwm output mode, a triangular-wav e pwm waveform is output fr om the tot01 pin when the tt0ctl0.tt0ce bit is set to 1. a pwm waveform that is inverted when the count value of the 16-bit counter matches t he value of the ccr0 buffer register and when the 16-bit counter is se t to 0000h is output from the tot00 pin. figure 9-43. configuration in triangular-wave pwm output mode ccr0 buffer register tt0ce bit tt0ccr0 register 16-bit counter tt0ccr1 register ccr1 buffer register clear match signal match signal inttt0cc0 signal output controller (rs-ff) output controller tot01 pin inttt0cc1 signal tot00 pin transfer transfer s r count clock selection tenc00 pin (external event count input) internal count clock edge detector note note set by the tt0ioc2.tt0ees1 and tt0ioc2.tt0ees0 bits. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 560 of 1817 sep 19, 2011 figure 9-44. basic timing in triangular-wave pwm output mode ffffh 16-bit counter 0000h tt0ce bit tt0ccr0 register ccr0 buffer register inttt0cc0 signal tot00 pin output tt0ccr1 register ccr1 buffer register inttt0cc1 signal tot01 pin output inttt0ov signal d 10 d 00 d 01 d 02 d 00 d 01 d 10 d 11 d 12 d 10 d 11 d 12 d 02 d 10 d 00 d 12 d 12 d 11 d 11 d 01 d 02 the 16-bit counter is cleared from ffffh and 0000h and starts counting when the tt0ce bit is set to 1. the triangular pwm waveform is output from the tot01 pin. in the triangular-wave pwm output mode, the counter count s up or down. when the 16-bit counter reaches 0000h while it is counting down, an overflow interrupt request signal (in ttt0ov) is generated. at this time, the tt0opt0.tt0ovf bit is not set to 1. if the count value of the 16-bit count er matches the value of the ccr0 buffer register while the counter is counting up, a compare match interrupt request signal (inttt0cc0) is generated. the counting direction is changed from up to down when the value of the 16-bit counter matches that of the ccr0 buffer register, and from down to up when the counter is cleared to 0000h. the pwm waveform can be changed by rewriting the tt0ccrn register during operation. to change the pwm waveform during operation, write the tt0ccr1 register last. the cycle of the triangular pwm waveform is set by the tt0ccr0 register and its duty factor is set by the tt0ccr1 register. set a value to the tt0ccr0 register in a range of ?0 tt0ccr0 fffeh?. the rewritten value is reflected when the 16-bit counter reaches 0000h while it is counting down. even when changing only the cycle of the pwm waveform, fi rst set a period to the tt0ccr0 register, and then write the same value (value same as that set to the tt0ccr1 register) to the tt0ccr1 register. to transfer data from the tt0ccrn register to the ccrn buffer register, the data must be written to the tt0ccr1 register (n = 0, 1). v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 561 of 1817 sep 19, 2011 9.6.9 encoder count function the encoder count function includ es an encoder compare mode (see 9.6.10 encoder compare mode (tt0md3 to tt0md0 bits = 1000) ). mode tt0ccr0 register tt0ccr1 register encoder compare mode compare only compare only (1) count-up/-down control counting up or down by the 16-bit counter is controlled by the phase of input encoder signals (tenc00 and tenc01) and settings of the tt0ctl2.tt0uds1 and tt0ctl2.tt0uds0 bits. when the encoder count function is used, the internal count clock and external event count input (tenc00) cannot be used. set the tt0ctl0.tt0cks2 to tt0ctl0.tt0ck s0 bits to 000 and the tt0ctl1.tt0eee bit to 0. (2) setting initial value of 16-bit counter the initial count value set to the tt0tcw register when the tt0ctl2.tt0ecc bit = 0 is transferred to the 16-bit counter immediately after the counter st arts its operation (tt0ctl0.tt0ce bit = 0 1), and the counter starts the operation after it detects the valid edge of the encoder input signal (tenc00 or tenc01). (3) basic operation the tt0ccrn register generates a compare match interrup t request signal (inttt0ccn ) when the count value of the 16-bit counter matches the value of the ccrn buffer register. (4) clear operation the 16-bit counter is cleared when the following condit ions are satisfied in the encoder compare mode. ? when the value of the 16-bit counter matches the value of the compare register (the tt0ctl2.tt0ecm1 and tt0ctl2.tt0ecm0 bits are set) ? when the edge of the encoder clear input signal (tecr0 ) is detected (the tt0ecs1 and tt0ecs0 bits are set when the tt0ioc3.tt0sce bit = 0) ? when the clear level condition of the tenc00, tenc01, and tecr0 pins is detected (the tt0zcl, tt0bcl, and tt0acl bits are set when the tt0sce bit = 1) remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 562 of 1817 sep 19, 2011 (5) controlling bits of tt0ctl2 register the setting of the tt0ctl2 register in the encoder compare mode is shown below. table 9-8. setting of tt0ctl2 register mode tt0uds1, tt0uds0 bits (<1>) tt0ecm1 bit (<2>) tt0ecm0 bit (<2>) tt0lde bit (<3>) counter clear (target compare register) transfer to counter 0 ? 0 1 ? possible 0 ? 0 1 1 tt0ccr0 possible note 0 invalid tt0ccr1 ? encoder compare mode can be set to 00, 01, 10, or 11. 1 1 invalid tt0ccr0, tt0ccr1 ? note the counter can operate in a range from 0000h to the set value of the tt0ccr0 register. (a) outline of each bit <1> the tt0uds1 and tt0uds0 bits identify the counting di rection (up or down) of the 16-bit counter by the phase input from the encoder input pin (tenc00 or tenc01). <2> the tt0ecm1 and tt0ecm0 bits control clearing of the 16-bit counter when its count value matches the value of the ccr0 or ccr1 buffer register. <3> the tt0lde bit controls a function to transfer the set value of the tt0ccr0 register to the 16-bit counter when the counter underflows. the tt0lde bit is va lid only when the tt0ecm1 and tt0ecm0 bits are 00 and 01, respectively. it is invalid when these bits are set to any other values. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 563 of 1817 sep 19, 2011 (b) detailed explanation of each bit <1> tt0uds1 and tt0uds0 bits: count-up/-down selection whether the 16-bit counter is count ing up or down is identified by t he phase input from the tenc00 or tenc01 pin and depending on the settings of the tt0uds1 and tt0uds0 bits. these bits are valid only in the encoder compare mode. ? when tt0uds1 and tt0uds0 bits = 00 tenc00 pin tenc01 pin count operation rising edge falling edge both edges high level count down rising edge falling edge both edges low level count up remark detecting the edge of the tenc00 pin is s pecified by the tt0ioc3.tt0eis1 and tt0eis0 bits. figure 9-45. operation example (when valid edge of tenc00 pin is specified to be rising edge and no edge is specified as valid edge of tenc01 pin) 0007h tenc00 tenc01 16-bit counter 0006h count down count up 0005h 0004h 0005h 0006h 0007h v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 564 of 1817 sep 19, 2011 ? when tt0uds1 and tt0uds0 bits = 01 tenc00 pin tenc01 pin count operation rising edge falling edge low level both edges rising edge falling edge high level both edges count down rising edge falling edge both edges high level rising edge falling edge both edges low level count up simultaneous input to tenc00 and tenc01 pins counter does not perform count operation but holds value immediately before. remark detecting the edges of the tenc00 and tenc01 pins is specified by the tt0ioc3.tt0eis1 and tt0io c3.tt0eis0 bits. figure 9-46. operation example (when rising edge is specified as valid edges of tenc00 and tenc01 pins) 0006h tenc00 tenc01 16-bit counter 0007h 0008h count up value held count down 0007h 0006h 0005h v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 565 of 1817 sep 19, 2011 ? when tt0uds1 and tt0uds0 bits = 10 tenc00 pin tenc01 pin count operation low level falling edge counter does not perform count operation but holds value immediately before. rising edge low level count down high level rising edge falling edge rising edge high level high level falling edge counter does not perform count operation but holds value immediately before. falling edge low level count up low level rising edge falling edge rising edge counter does not perform count operation but holds value immediately before. rising edge count down falling edge falling edge count up caution specification of the valid edges of the tenc00 and tenc01 pins is invalid. figure 9-47. operation example (cou nt operation when valid edges of te nc00 and tenc01 pins do not overlap) 0007h tenc00 tenc01 16-bit counter 0006h count down count up count down count up count down count up 0005h 0006h 0005h 0005h 0006h 0006h 0007h figure 9-48. operation example (count operation when valid edges of tenc00 and tenc01 pins overlap) 0007h tenc00 tenc01 16-bit counter 0006h count down value held count down count up 0005h 0006h 0007h v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 566 of 1817 sep 19, 2011 ? when tt0uds1 and tt0uds0 bits = 11 tenc00 pin tenc01 pin count operation low level falling edge rising edge low level high level rising edge falling edge count down rising edge high level high level falling edge falling edge low level low level rising edge count up simultaneous input to tenc00 and tenc01 pins counter does not perform count operation but holds value immediately before. caution specification of the valid edges of the tenc00 and tenc01 pins is invalid. figure 9-49. operation example (cou nt operation when valid edges of te nc00 and tenc01 pins do not overlap) count up tenc00 tenc01 16-bit counter 0004h 0003h 0006h 0005h 0008h 0007h 000ah 0009h 0008h 0009h 0006h 0007h 0005h count down figure 9-50. operation example (count operation when valid edges of tenc00 and tenc01 pins overlap) count up count up count up value held value held tenc00 tenc01 16-bit counter 0004h 0003h 0005h 0008h 0007h 0006h 0007h 0006h 0006h 0005h count down v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 567 of 1817 sep 19, 2011 <2> tt0ecm1 and tt0ecm0 bits: timer/counter clear function upon match of the compare register the 16-bit counter performs its count operation in ac cordance with the set value of the tt0ecm1 and tt0ecm0 bits when the count value of the counter matches the value of the ccrn buffer register. ? when tt0ecm1 and tt0ecm0 bits = 00 the 16-bit counter is not cleared when its count va lue matches the value of the ccrn buffer register. ? when tt0ecm1 and tt0ecm0 bits = 01 the 16-bit counter performs a count operation under the following condition when its count value matches the value of the ccr0 buffer register. next count operation description count up 16-bit counter is cleared to 0000h. count down count value of 16-bit counter is counted down. ? when tt0ecm1 and tt0ecm0 bits = 10 the 16-bit counter performs a count operation under the following condition when its count value matches the value of the ccr1 buffer register. next count operation description count up count value of 16-bit counter is counted up. count down 16-bit counter is cleared to 0000h. ? when tt0ecm1 and tt0ecm0 bits = 11 the 16-bit counter performs a count operation under the following condition when its count value matches the value of the ccr0 buffer register. next count operation description count up 16-bit counter is cleared to 0000h. count down count value of 16-bit counter is counted down. the 16-bit counter performs a count operation under the following condition when its count value matches the value of the ccr1 buffer register. next count operation description count up count value of 16-bit counter is counted up. count down 16-bit counter is cleared to 0000h. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 568 of 1817 sep 19, 2011 <3> tt0lde bit: transfer function of the set value of the tt0ccr0 register to the 16-bit counter when the counter underflows when the tt0lde bit = 1, the set value of the tt0ccr0 register can be transferred to the 16-bit counter when the counter underflows. the tt0lde bit is valid only in the encoder compare mode. ? count operation in range from 0000h to set value of the tt0ccr0 register if the 16-bit counter performs a count operati on when the tt0lde bit = 1 and tt0ecm1 and tt0ecm0 bits = 01, and when the count value of the counter matches the set value of the ccr0 buffer register when the tt0ecm0 bit = 1, the 16-bit counter is cleared to 0000h if the next count operation is counting up. if the 16-bit counter underflows when the tt0lde bit = 1, the set value of the tt0ccr0 register is transferred to the counter. therefore, the c ounter can operate in a range from 0000h to the set value of the tt0ccr0 register in which the upper-limit count value is the set value of the tt0ccr0 register and the lower-limit value is 0000h. figure 9-51. operation example (count operation in range from 0000h to set value of tt0ccr0 register) 16-bit counter is cleared to 0000h. set value of tt0ccr0 register is transferred to 16-bit counter. 16-bit counter underflows. count up count down count value of 16-bit counter matches value of ccr0 buffer register. 16-bit counter set value of tt0ccr0 register (n) 0000h v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 569 of 1817 sep 19, 2011 figure 9-52. operation timing (count operation in range from 0000h to set value of tt0ccr0 register) peripheral clock tt0esf bit tt0cnt register tt0ccr0 register inttt0cc0 signal tt0eof bit tt0euf bit inttt0ov signal count timing signal n 0002h h = down counting l 0001h 0000h n n ? 1 remark tt0esf bit: bit 0 of tmt0 option register 1 (tt0opt1) tt0eof bit: bit 1 of tmt0 option register 1 (tt0opt1) tt0euf bit: bit 2 of tmt0 option register 1 (tt0opt1) v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 570 of 1817 sep 19, 2011 (6) function to clear counter to 0000h by encoder clear signal (tecr0 pin) the 16-bit counter can be cleared to 0000h by the input si gnal of the tecr0 pin in two ways which are selected by the tt0ioc3.tt0sce bit. the tt0sce bit also cont rols, depending on its setting, the tt0ioc3.tt0zcl, tt0ioc3.tt0bcl, tt0ioc3.tt0 acl, tt0ioc3.tt0esc1, and tt0ioc3.tt0ecs0 bits. the counter can be cleared by the methods descr ibed below only in the encoder compare mode. table 9-9. relationship between tt0sce bit and tt 0zcl, tt0bcl, tt0acl, tt0 ecs1, and tt0ecs0 bits clearing method tt0sce bit tt0zcl bit tt0bc l bit tt0acl bit tt0ecs1, tt0ecs0 bits <1> 0 invalid invalid invalid valid <2> 1 valid valid valid invalid (a) clearing method <1>: by detecting edge of en coder clear signal (tecr0 pin) (tt0sce bit = 0) when the tt0sce bit = 0, the 16-bit counter is cleared to 0000h in synchronization with the peripheral clock if the valid edge of the tecr0 pin specif ied by the tt0ecs1 and tt0ecs0 bits is detected. at this time, an encoder clear interrupt request signa l (inttt0ec) is generated. when the tt0sce bit = 0, the settings of the tt0zcl, tt0bcl, and tt0acl bits is invalid. figure 9-53. operation example (when tt0sce bit = 0, tt0ecs1 and tt0ecs0 bi ts = 01, and tt0uds1 and tt0uds0 bits = 11) peripheral clock tt0cnt register encoder input (tenc00 pin input) encoder input (tenc01 pin input) encoder clear input (tecr0 pin input) count timing signal n + 1 n counter clear 0000h 0001h 0002h inttt0ec interrupt v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 571 of 1817 sep 19, 2011 (b) clearing method <2>: by detecting clear level condition of the tenc00, tenc01, and tecr0 pins (tt0sce bit = 1) when the tt0sce bit = 1, the 16-bit counter is cleared to 0000h if the clear level condition of the tecr0, tenc00, or tenc01 pin specified by the tt0zcl, tt0bcl, and tt0acl bits is detected. at this time, the encoder clear interrupt request si gnal (inttt0ec) is not generated. the settings of the tt0ecs1 and tt0ecs0 bits is invalid when the tt0sce bit = 1. table 9-10. 16-bit counter clear ing condition when tt0sce bit = 1 clear level condition setting input level of encoder pin tt0zcl bit tt0bcl bit tt0acl bit tecr0 pin tenc01 pin tenc00 pin 0 0 0 l l l 0 0 1 l l h 0 1 0 l h l 0 1 1 l h h 1 0 0 h l l 1 0 1 h l h 1 1 0 h h l 1 1 1 h h h caution the 16-bit counter is cleare d to 0000h when the clear level c ondition of the tt0zcl, tt0bcl, and tt0acl bits match the input level of the tecr0, tenc01, or tenc00 pin. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 572 of 1817 sep 19, 2011 figure 9-54. operation example (when tt0sce bit = 1, tt0zc l bit = 1, tt0bcl bit = 0, tt0acl bit = 1, tt0uds1 and tt0uds0 bits = 11, tecr0 = high level, tenc01 = low level, and tenc00 = high level) (1/3) (i) if inputting the high level to the tecr0 pin lags behind inputting the low level to the tenc01 pin while the counter is counting up, the co unter is cleared after it counts up. peripheral clock clear signal tt0cnt register tt0ccr0 register inttt0cc0 signal tt0ccr1 register inttt0cc1 signal tt0ccr0 register inttt0cc0 signal encoder input (tenc00 pin input) encoder input (tenc01 pin input) encoder clear input (tecr0 pin input) count timing signal n + 1 n compare match interrupt request signal is not generated. h l h 0000h n + 1 (when tt0ccr0 register is set to n + 1) n (when tt0ccr0 register is set to n) 0000h (when tt0ccr1 register is set to 0000h) v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 573 of 1817 sep 19, 2011 figure 9-54. operation example (when tt0sce bit = 1, tt0zc l bit = 1, tt0bcl bit = 0, tt0acl bit = 1, tt0uds1 and tt0uds0 bits = 11, tecr0 = high level, tenc01 = low level, and tenc00 = high level) (2/3) (ii) if the high level is input to the tecr0 pin at the same time as the low level is input to the tecn01 pin while the counter is counting up, the counter is cleared without counting up. peripheral clock clear signal tt0cnt register encoder input (tenc00 pin input) encoder input (tenc01 pin input) encoder clear input (tecr0 pin input) count timing signal 0000h n h l h (iii) if the high level is input to the tecr0 pin earlier than the low level is input to the tenc01 pin while the counter is counting up, the count er is cleared without counting up. peripheral clock clear signal tt0cnt register encoder input (tenc00 pin input) encoder input (tenc01 pin input) encoder clear input (tecr0 pin input) count timing signal 0000h n h l h v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 574 of 1817 sep 19, 2011 figure 9-54. operation example (when tt0sce bit = 1, tt0zc l bit = 1, tt0bcl bit = 0, tt0acl bit = 1, tt0uds1 and tt0uds0 bits = 11, tecr0 = high level, tenc01 = low level, and tenc00 = high level) (3/3) (iv) if the high level is input to the tecr0 pin later than the low level is input to the tenc01 pin while the counter is counting up, the counter is cleared after it counts up. peripheral clock clear signal tt0cnt register tt0ccr0 register inttt0cc0 signal tt0ccr1 register inttt0cc1 signal tt0ccr0 register inttt0cc0 signal encoder input (tenc00 pin input) encoder input (tenc01 pin input) encoder clear input (tecr0 pin input) count timing signal n ? 1 n compare match interrupt request signal is not generated. h l h 0000h n ? 1 (when tt0ccr0 register is set to n ? 1) n (when tt0ccr0 register is set to n) 0000h (when tt0ccr1 register is set to 0000h) if the counter is cleared in this way, a miscount does not occur even if inputting the signal to the tecr0 pin is late, because the clear level condition of the tecr0, tenc01, and tenc00 pins is set and the 16-bit counter is cleared to 0000h when the clear level condition is detected. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 575 of 1817 sep 19, 2011 (7) notes on using encoder count function (a) if compare match interrupt is not gene rated immediately after operation is started if a value which is the same as that of the tt0tcw r egister is set to the tt0ccr0 or tt0ccr1 register and the counter operation is st arted when the tt0ctl2.tt0ecc bit = 0, an d if the count value (tt0tcw) of the 16-bit counter matches the value of the ccrn buffer regi ster immediately after the start of the operation, the match is masked and the compare match interrupt request signal (inttt0ccn) is not generated (n = 0, 1). in addition, the 16-bit counter is not cleared to 0000h by setting the tt0ctl2.tt0ecm1 and tt0ctl2.tt0ecm0 bits. tt0cnt register tt0ccr1 register inttt0cc1 signal count clock tt0ce bit peripheral clock count timing signal count up/down signal tt0tcw ? 1 ffffh h = count down tt0tcw tt0tcw match does not occur. 16-bit counter is not cleared. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 576 of 1817 sep 19, 2011 (b) if overflow does not occur i mmediately after start of operation if the count operation is resumed when the tt0ctl2.tt0ecc bi t = 1, the 16-bit counter does not overflow if its count value that has been held is ffffh and if the next count opera tion is counting up. after the counter starts operating an d counts up from a count value (value of tt0tcw register = ffffh), the counter overflows from ffffh to 0000h. however, det ection of the overflow is masked, the overflow flag (tt0eof) is not set, and the overflow interr upt request signal (inttt0ov) is not generated. tt0ecc bit tt0cnt register tt0tcw register inttt0ov signal tt0eof bit count clock tt0ce bit peripheral clock count timing signal count up/down signal 0000h ffffh l = count up hold h tt0tcw = ffffh ffffh overflow does not occur. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 577 of 1817 sep 19, 2011 9.6.10 encoder compare mode (tt0md3 to tt0md0 bits = 1000) in the encoder compare mode, the enc oder is controlled by using both the tt0ccr0 and tt0ccr1 registers as compare registers and the input pins for encoder count function (tenc00, tenc01, and tecr0). in this mode, the 16-bit counter can be cleared to 0000h in three ways: when the count va lue of the counter matches the value of the ccrn buffer register (compare match interrupt request si gnal (inttt0ccn) is ge nerated), when the edge of the encoder clear input (tecr0 pin) is detected, and when the clear level co ndition of tenc00, tenc01, and tecr0 pins is detected. when the 16-bit counter underflows, the set value of the tt0ccr0 register can be transferred to the counter. (1) encoder compare mode operation flow figure 9-55. encoder compare mode operation flow tt0ce bit = 1 tt0ce bit = 0 encoder compare mode operation processing register initial setting tt0ctl1 register (tt0md3 to tt0md0 bits), tt0ctl2 register (tt0lde, tt0ecm1, tt0ecm0, tt0uds1, tt0uds0 bits), tt0ioc3 register (tt0sce, tt0zcl, tt0acl, tt0bcl, tt0ecs1, tt0ecs0, tt0eis1, tt0eis0 bits), tt0ccr0, tt0ccr1 registers, tt0tcw register start end operation end? yes no : see figure 9-56 encoder compare mode operation processing . v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 578 of 1817 sep 19, 2011 figure 9-56. encoder compar e mode operation processing count up 16-bit counter cleared and started. inttt0cc0 signal generated. 16-bit counter cleared and started. 16-bit counter cleared and started. inttiec0 signal generated. tt0ecm0 = 1? (tt0ctl2) yes no tecr0 edge detected? yes no clear level condition of tenc00, tenc01, and tecr0 pins detected? yes a a no tt0sce = 1? (tt0ioc3) yes no count value matches ccr0 register value? yes no no 16-bit counter cleared and started. inttt0cc1 signal generated. tt0ccr0 set value transferred to 16-bit counter. inttt0cc0 signal generated. valid edge of tenc00, tenc01 detected? yes no which count operation? count down tt0ecm1 = 1? (tt0ctl2) yes no yes tt0lde = 1? (tt0ctl2) yes no underflow? yes no count value matches ccr1 register value? v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 579 of 1817 sep 19, 2011 (2) encoder compare mode operation timing (a) basic timing 1 [register setting conditions] ? tt0ctl2.tt0ecm1 and tt0ctl2.tt0ecm0 bits = 01 the 16-bit counter is cleared to 0000h when its count va lue matches the value of the ccr0 buffer register. ? tt0ctl2.tt0lde bit = 1 the set value of the tt0ccr0 register is transf erred to the 16-bit counter when it overflows. ? tt0ioc3.tt0sce bit = 0, and tt0ioc3.tt 0ecs1 and tt0ioc3.tt0ecs0 bits = 00 specification of clearing the 16-bit counter when the ed ge of the encoder clear input signal (tecr0 pin) is detected (no edge specified) cm 00 cm 00 tt0ccr0 register ccr0 buffer register inttt0cc0 signal tt0ccr1 register ccr1 buffer register inttt0cc1 signal tt0esf bit inttt0ov signal tt0eof bit tt0euf bit 0000h ffffh tt0cnt register clear clear clear transfer cm 00 cm 01 cm 00 cm 10 cm 11 cm 10 l cm 11 cm 12 cm 12 cm 01 cm 02 cm 02 cm 03 cm 03 cm 03 cm 03 cm 11 cm 02 cm 12 cm 01 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 580 of 1817 sep 19, 2011 when the 16-bit counter starts operating (tt0ce bit = 0 1), the set value of the tt0tcw register is transferred to the counter and the 16-bit counter starts operating. when the count value of the counter matches the valu e of the ccr0 buffer register, the compare match interrupt request signal (inttt0cc0) is generated. be cause the tt0ecm0 bit = 1, the 16-bit counter is cleared to 0000h if the next count operation is counting up. when the count value of the 16-bit co unter matches the value of the ccr1 buffer register, the compare match interrupt request signal (inttt0cc1) is generated. because the tt0ecm1 bit = 0, the 16-bit counter is not cleared to 0000h when its value matches that of the ccr1 buffer register. when the tt0lde bit = 1 and tt0ecm0 bit = 1, the counter can operate in a range from 0000h to the set value of the tt0ccr0 register. v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 581 of 1817 sep 19, 2011 (b) basic timing 2 [register setting condition] ? tt0ctl2.tt0ecm1 and tt0ctl2.tt0ecm0 bits = 00 the 16-bit counter is not cleared even when its count va lue matches the value of the ccrn buffer register (a = 0, 1). ? tt0ctl2.tt0lde bit = 0 the set value of the tt0ccr0 register is not transferr ed to the 16-bit counter after the counter underflows. ? tt0ioc3.tt0sce bit = 0, and tt0ioc3.tt 0ecs1 and tt0ioc3.tt0ecs0 bits = 00 specification of clearing the 16-bit counter when the ed ge of the encoder clear input signal (tecr0 pin) is detected (no edge specified) cm 10 cm 00 cm 00 tt0ccr0 register ccr0 buffer register inttt0cc0 signal tt0ccr1 register ccr1 buffer register inttt0cc1 signal tt0esf bit inttt0ov signal tt0eof bit tt0euf bit 0000h ffffh tt0cnt register underflow overflow cm 00 cm 01 cm 00 cm 10 cm 11 cm 10 cm 11 cm 12 cm 12 cm 01 cm 02 cm 02 cm 11 cm 02 cm 12 cm 01 cm 01 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 582 of 1817 sep 19, 2011 when the 16-bit counter starts operating (tt0ce bit = 0 1), the set value of the tt0tcw register is transferred to the 16-bit counter and the counter starts operating. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (i nttt0cc0) is generated. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (i nttt0cc1) is generated. the 16-bit counter is not cleared to 0000h even when it s count value matches the value of the ccrn buffer register because the tt0ecm1 and tt0ecm0 bits = 00 (n = 0, 1). v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 583 of 1817 sep 19, 2011 (c) basic timing 3 [register setting condition] ? tt0ctl2.tt0ecm1 and tt0ctl2.tt0ecm0 bits = 11 the count value of the 16- bit counter is cleared to 0000h when it s value matches the value of the ccr0 buffer register. the count value of the 16- bit counter is cleared to 0000h when it s value matches the value of the ccr1 buffer register. ? setting of the tt0ctl2.tt0lde bit is invalid. ? tt0ioc3.tt0sce bit = 0, and tt0ioc3.tt 0ecs1 and tt0ioc3.tt0ecs0 bits = 00 specification of clearing the 16-bit counter when the ed ge of the encoder clear input signal (tecr0 pin) is detected (no edge specified) cm 00 cm 01 cm 01 cm 11 cm 10 tt0ccr0 register ccr0 buffer register inttt0cc0 signal tt0ccr1 register ccr1 buffer register inttt0cc1 signal tt0esf bit inttt0ov signal tt0eof bit tt0euf bit 0000h ffffh tt0cnt register clear clear clear clear underflow underflow underflow overflow cm 00 cm 01 cm 00 cm 10 cm 11 cm 10 cm 11 cm 12 cm 12 cm 01 cm 02 cm 02 cm 12 cm 12 cm 02 v850es/jh3-e, v850es/jj3-e chapter 9 16-bit timer/event counter t (tmt) r01uh0290ej0300 rev.3.00 page 584 of 1817 sep 19, 2011 when the 16-bit counter starts operating (tt0ce bit = 0 1), the set value of the tt0tcw register is transferred to the 16-bit counter and the counter starts operating. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttt0cc0) is generated. at this time, the 16-bit counter is cleared to 0000h if the next count operation is counting up. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttt0cc1) is generated. at this time, the 16-bit counter is cleared to 0000h if the next count operation is counting down. v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 585 of 1817 sep 19, 2011 chapter 10 16-bit interval timer m (tmm) the v850es/jh3-e and v850es/jj3-e have four tmm channels (tmmn). 10.1 overview tmmn has the following features. ? interval function ? 8 clocks selectable ? 16-bit counter 1 (the 16-bit counter cannot be read during timer count operation.) ? compare register 1 (the compare register cannot be written during timer counter operation.) ? compare match interrupt 1 tmmn supports only the clear & start mode. the free-running timer mode is not supported. remark n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 586 of 1817 sep 19, 2011 10.2 configuration tmmn includes the following hardware. table 10-1. configuration of tmmn item configuration timer register 16-bit counter register tmmn compare register 0 (tmncmp0) control register tmmn control register 0 (tmnctl0) figure 10-1. block diagram of tmmn tmnctl0 internal bus f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /512 f xx /1024 controller 16-bit counter match clear inttmneq0 tmncmp0 tmnce tmncks2 tmncks1tmncks0 selector note note in tmm0, f xx , f xx /2, f xx /4, f xx /64, f xx /512, f xx /1024, f r , f xt remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 587 of 1817 sep 19, 2011 (1) 16-bit counter this is a 16-bit counter that counts the internal clock. the 16-bit counter cannot be read or written. (2) tmmn compare register 0 (tmncmp0) the tmncmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset sets this register to 0000h. software can be used to always write the same value to the tmncmp0 register. rewriting the tmncmp0 register is prohibited when the tmnctl0.tmnce bit = 1. tmncmp0 (n = 0 to 3) 12 10 8 6 4 2 after reset: 0000h r/w address: tm0cmp0 fffffa84h, tm1cmp0 fffffa94h, tm2cmp0 fffffaa4h, tm3cmp0 fffffab4h 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 588 of 1817 sep 19, 2011 10.3 registers (1) tmmn control register (tmnctl0) the tmnctl0 register is an 8-bit regist er that controls the tmmn operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. software can be used to always write the same value to the tmnctl0 register. remark n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 589 of 1817 sep 19, 2011 tmmn operation disabled (16-bit counter reset asynchronously). operation clock application stopped. tmmn operation enabled. operation clock application started. tmmn operation started. internal clock control and internal circuit reset for tmmn are performed asynchronously using the tmnce bit. when the tmnce bit is cleared to 0, the internal clock of tmmn is disabled (fixed to low level) and 16-bit counter is reset asynchronously. tmnce tmnctl0 (n = 0 to 3) 0 0 0 0 tmncks2 tmncks1 tmncks0 654321 after reset: 00h r/w address: tm0ctl0 fffffa80h, tm1ctl0 fffffa90h, tm2ctl0 fffffaa0h, tm3ctl0 fffffab0h tmnce 0 1 internal clock operation enable/disable specification 0 <7> count clock selection (m = 1 to 3) count clock selection (m = 0) tmmcks2 0 0 0 0 1 1 1 1 tmmcks1 0 0 1 1 0 0 1 1 f xx /2 f xx /4 f xx /8 f xx /16 f xx /64 f xx /256 f xx /512 f xx /1024 f xx = 50 mhz 40.0 ns 80.0 ns 160 ns 320 ns 1.28 s 5.12 s 10.24 s 20.48 s f xx = 48 mhz 41.7 ns 83.3 ns 167 ns 333 ns 1.33 s 5.33 s 10.67 s 21.33 s f xx = 32 mhz 62.5 ns 125 ns 250 ns 500 ns 2.00 s 8.00 s 16.0 s 32.0 s f xx f xx /2 f xx /4 f xx /64 f xx /512 f xx /1024 f r /8 f xt tmmcks2 0 0 0 0 1 1 1 1 tmmcks1 0 0 1 1 0 0 1 1 tmmcks0 0 1 0 1 0 1 0 1 f xx = 50 mhz 20.0 ns 40.0 ns 80.0 ns 1.28 s 10.24 s 20.48 s 36.36 s 30.52 s f xx = 48 mhz 20.8 ns 41.7 ns 83.3 ns 1.33 s 10.7 s 21.33 s 36.36 s 30.52 s f xx = 32 mhz 31.3 ns 62.5 ns 125 ns 2.00 s 16.0 s 32.0 s 36.36 s 30.52 s tmmcks0 0 1 0 1 0 1 0 1 cautions 1. set the tmncks2 to tmncks0 bits when the tmnce bit = 0. when changing the value of tmnce from 0 to 1, it is not possible to set the value of the tmncks2 to tm ncks0 bits simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency f r : internal oscillation clock frequency f xt : subclock frequency v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 590 of 1817 sep 19, 2011 10.4 operation caution do not set the tmncmp0 register to ffffh. 10.4.1 interval timer mode in the interval timer mode, an interrupt request signal (i nttmneq0) is generated at the specified interval if the tmnctl0.tmnce bit is set to 1. figure 10-2. configuration of interval timer 16-bit counter tmncmp0 register tmnce bit count clock selection clear match signal inttmneq0 signal remark n = 0 to 3 figure 10-3. basic timing of oper ation in interval timer mode ffffh 16-bit counter 0000h tmnce bit tmncmp0 register inttmneq0 signal d d d d d interval (d + 1) interval (d + 1) interval (d + 1) interval (d + 1) remark n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 591 of 1817 sep 19, 2011 when the tmnce bit is set to 1, the val ue of the 16-bit counter is cleared from ffffh to 0000h in synchronization with the count clock, and the counter starts counting. when the count value of the 16-bit counter matches the valu e of the tmncmp0 register, the 16-bit counter is cleared to 0000h and a compare match interrupt request signal (inttmneq0) is generated. the interval can be calculated by the following expression. interval = (set value of tmncmp0 register + 1) count clock cycle figure 10-4. register setting for interval timer mode operation (a) tmmn control register 0 (tmnctl0) 0/1 0 0 0 0 tmnctl0 0/1 0/1 0/1 tmncks2 tmncks1 tmncks0 tmnce 0: stop counting 1: enable counting select count clock (b) tmmn compare register 0 (tmncmp0) if the tmncmp0 register is set to d, the interval is as follows. interval = (d + 1) count clock cycle remark n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 592 of 1817 sep 19, 2011 (1) interval timer mode operation flow figure 10-5. software processing flow in interval timer mode ffffh 16-bit counter 0000h tmnce bit tmncmp0 register inttmneq0 signal d d d d <1> <2> tmnce bit = 1 tmnce bit = 0 register initial setting tmnctl0 register (tmncks0 to tmncks2 bits) tmncmp0 register the initial setting of these registers is performed before setting the tmnce bit to 1. the tmncks0 to tmncks2 bits cannot be set at the same time when counting has been started (tmnce bit = 1). the counter is initialized and counting is stopped by clearing the tmnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow remark n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 593 of 1817 sep 19, 2011 (2) interval timer mode operation timing caution do not set the tmncmp0 register to ffffh. (a) operation if tmncmp0 register is set to 0000h if the tmncmp0 register is set to 0000h, the inttm neq0 signal is generated at each count clock. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tmnce bit tmncmp0 register inttmneq0 signal 0000h interval time count clock cycle ffffh 0000h 0000h 0000h 0000h interval time count clock cycle remark n = 0 to 3 (b) operation if tmncmp0 register is set to n if the tmncmp0 register is set to n, the 16-bit counte r counts up to n. the counter is cleared to 0000h in synchronization with the next count-up timing and the inttmneq0 signal is generated. ffffh 16-bit counter 0000h tmnce bit tmncmp0 register inttmneq0 signal n interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle interval time (n + 1) count clock cycle n remark n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 10 16-bit interval timer m (tmm) r01uh0290ej0300 rev.3.00 page 594 of 1817 sep 19, 2011 10.4.2 cautions (1) it takes the 16-bit counter up to the following time to start counting after the tmnctl0.tmnce bit is set to 1, depending on the count clock selected. (n = 0) selected count clock maximum time before counting start f xx 2/f xx f xx /2 3/f xx f xx /4 6/f xx f xx /64 128/f xx f xx /512 1024/f xx f xx /1024 2048/f xx f r /8 16/f r f xt 2/f xt (n = 1 to 3) selected count clock maximum time before counting start f xx /2 4/f xx f xx /4 6/f xx f xx /8 12/f xx f xx 16 32/f xx f xx /64 128/f xx f xx /256 512/f xx f xx /512 1024/f xx f xx /1024 2048/f xx (2) rewriting the tmncmp0 and tmnctl0 regist ers is prohibited while tmmn is operating. if these registers are rewritten while the tmnc e bit is 1, the operation cannot be guaranteed. if they are rewritten by mistake, clear the tm nctl0.tmnce bit to 0, and re-set the registers. remark n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 595 of 1817 sep 19, 2011 chapter 11 motor control function 11.1 functional overview timer ab1 (tab1) and the tab1 option (tab1op0) can be used as an inverter function that controls a motor. it performs a tuning operation with timer aa4 (taa4) and a/d conv ersion of the a/d converter c an be started when the value of tab1 matches the value of taa4. the following operations can be performed as motor control functions. ? 6-phase pwm output function with 16-bit accuracy ? timer tuning operation function (tunable with taa4) ? cycle setting function (cycle can be changed dur ing operation of crest or valley interrupt) ? compare register rewriting: anytime re write, batch rewrite, or intermittent rewrite (selectable during tab1 operation) ? interrupt and transfer culling functions ? dead-time setting function ? a/d trigger timing function of the a/d converter ? 0% output and 100% output available ? 0% output and 100% output selectable by crest interrupt and valley interrupt ? forcible output stop function ? when valid edge detected by external pin input (toab1off, toaa1off) ? when main clock oscillation stop detected by clock monitor function v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 596 of 1817 sep 19, 2011 11.2 configuration the motor control function consists of the following hardware. item configuration timer register dead-time counters compare register tab1 dead-time compare register (tab1dtc register) control registers tab1 option register 1 (tab1opt1) tab1 option register 2 (tab1opt2) tab1 i/o control register 3 (tab1ioc3) high-impedance output control register 0 (hza0ctl0) high-impedance output control register 1 (hza0ctl1) ? 6-phase pwm output can be produced with dead time by using the output of tab1 (toab11, toab12, toab13). ? the output level of the 6-phase pwm output can be set individually. ? the 16-bit timer/counter of tab1 c ounts up/down triangular waves. w hen the timer/counter underflows and when a cycle match occurs, an interrupt is generated. interrupt generation, however, can be suppressed up to 31 times. ? taa4 can execute counting at the same time as tab1 (tim er tuning operation function). taa4 can be set in three ways as it can generate an a/d trigger source (tabtadt0 ) and two types of interrupts: a tab1 underflow interrupt (inttab1ov) and a cycle match interrupt (inttab1cc0). v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 597 of 1817 sep 19, 2011 figure 11-1. block diagram of motor control ? carrier ? 3-phase pwm generation tab1 ? 6-phase pwm generation with dead time from 3-phase pwm ? culling control ? a/d trigger selection tab1 option ? a/d trigger generation in synchronization with tab1 taa4 ? pwm generation taa1 ? interrupt control intc high-impedance output controller toab1t1 toab1b1 toab1t2 toab1b2 toab1t3 toab1b3 toaa11 toab10 intp18/toab1off valley interrupt (inttab1ov) crest interrupt (inttab1cc0) edge detection edge detection noise elimination intp06/toaa1off noise elimination a/d trigger of a/d converter v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 598 of 1817 sep 19, 2011 figure 11-2. tab1 option toab1t1 high-impedance output controller toab1b1 tabndtc (10-bit dead-time value) toab11 note (internal signal) toab12 note (internal signal) toab13 note (internal signal) tab1 channel 2 dead-time counter 1 (10 bits) edge detection channel 1 positive phase f/f active setting clear negative phase f/f active setting level control output control level control output control counter mask count buffer interrupt culling circuit a/d trigger generator 1 number of masks crest/valley interrupt selection culling enable mask control internal bus toab1t2 toab1b2 channel 3 inttaa4cc0 inttaa4cc1 taa4 inttab1ov inttab1cc0 intc toab1t3 toab1b3 tabtadt0 a/d trigger selection (tab1opt2 register) up/down selection toab10 toab10 a/d converter tabticcn0 tabtiovn inttab1ov_base note toab11, toab12, and toab13 functi on alternately as output pins. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 599 of 1817 sep 19, 2011 (1) tab1 dead-time compare register (tab1dtc) the tab1dtc register is a 10-bit compare regi ster that specifies the dead-time value. rewriting this register is prohibit ed when the tab1ctl0.tab1ce bit = 1. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution when generating a dead-time period, set the tab1dtc register to 1 or higher. note, when the operation is stopped (tab1ctl0 .tab1ce bit = 0), a dead-time period is not generated, so the output levels of the toab1t1 to toab1t3 and toab1b1 to toab1b3 pins are in their default states. therefore, for the prot ection of the system, take measures such as making the toab1t1 to toab1t3 and toab1b1 to toab1b3 pins go into a high-impedance state before stopping operation, or setting the output levels of the pins before switching port modes. when a dead-time period is not need ed, set the tab1dtc register to 0. tab1dtc 000000 tab1dtc9 to tab1dtc0 10 9 after reset: 0000h r/w address: fffff584h 15 0 (2) dead-time counters 1 to 3 the dead-time counters are 10-bit counters that count dead time. these counters are cleared or count up at the rising or falling edge of the toab1m output signal of tab1, and are cleared or stopped when their count va lue matches the value of the tab1dtc register. the count clock of these counters is the same as that set by the tab1ct l0.tab1cks2 to tab1ctl0.tab1cks0 bits of tab1. remarks 1. the operation differs when the tab1op t2.tab1dtm bit = 1. for details, see 11.4.2 (4) automatic dead-time width narrowing function (tab1opt2.tab1dtm bit = 1) . 2. m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 600 of 1817 sep 19, 2011 11.3 control registers (1) tab1 option register 1 (tab1opt1) the tab1opt1 register is an 8-bit register that contro ls the interrupt request signal generated by the timer ab1 option function. this register can be rewritten when the tab1ctl0.tab1ce bit is 1. two rewrite modes (batch write m ode and anytime write mode) can be sele cted, depending on the setting of the tab1opt0.tab1cms bit. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. tab1ice tab1ice 0 1 crest interrupt (inttab1cc0 signal) enable do not use inttab1cc0 signal (do not use it as count signal for interrupt culling). use inttab1cc0 signal (use it as count signal for interrupt culling). tab1opt1 tab1ioe 0 tab1id4 tab1id3 tab1id2 tab1id1 tab1id0 <6>54 32 1 tab1ioe 0 1 valley interrupt (inttab1ov signal) enable do not use inttab1ov signal (do not use it as count signal for interrupt culling). use inttab1ov signal (use it as count signal for interrupt culling). after reset: 00h r/w address: fffff580h <7> 0 not culled (all interrupts are output) 1 masked (one of two interrupts is output) 2 masked (one of three interrupts is output) 3 masked (one of four interrupts is output) : 28 masked (one of 29 interrupts is output) 29 masked (one of 30 interrupts is output) 30 masked (one of 31 interrupts is output) 31 masked (one of 32 interrupts is output) tab1id4 0 0 0 0 : 1 1 1 1 number of times of interrupt tab1id3 0 0 0 0 : 1 1 1 1 tab1id2 0 0 0 0 : 1 1 1 1 tab1id1 0 0 1 1 : 0 0 1 1 tab1id0 0 1 0 1 : 0 1 0 1 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 601 of 1817 sep 19, 2011 (2) tab1 option register 2 (tab1opt2) the tab1opt2 register is an 8-bit register that controls the timer ab1 option function. this register can be rewritten when the tab1ctl0.tab1ce bit is 1. however, rewriting the tab1dtm bit is prohibited when the tab1ce bit is 1. the same value can be rewritten. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) tab1rde tab1opt2 tab1dtm tab1atm3 tab1atm2 tab1at3 tab1at2 tab1at1 tab1at0 <6> <5> <4> <3> <2> <1> rewriting the tab1dtm bit is disabled during timer operation. if it is rewritten by mistake, stop the timer operation by clearing the tab1ce bit to 0, and re-set the tab1dtm bit. tab1dtm 0 1 dead-time counter operation mode selection (m = 1 to 3) the dead-time counter counts up normally and, if toab1m output of tab1 is at a narrow interval (toab1m output width < dead-time width), the dead-time counter is cleared and counts up again. the dead-time counter counts up normally and, if toab1m output of tab1 is at a narrow interval (toab1m output width < dead-time width), the dead-time counter counts down and the dead-time control width is automatically narrowed. after reset: 00h r/w address: fffff581h <7> <0> tab1rde 0 1 transfer culling enable do not cull transfer (transfer timing is generated every time at crest and valley). cull transfer at the same interval as interrupt culling set by the tab1opt1 register. cautions 1. when using interrupt culling (the tab1opt1.tab1id4 to tab1opt1.tab1id0 bits are set to other than 00000), be sure to set the tab1rde bit to 1. this means that interrupts and transfers ar e generated at the same timing. interrupts and transfers, cannot be set separately. if interrupts and transf ers are set separately (tab1rde bit = 0), transfers are not performed normally. 2. when generating a dead-time period, set the tab1dtc register to 1 or higher. note, when the operation is stopped (tab 1ctl0.tab1ce bit = 0), a dead-time period is not generated, so the output levels of the toab1t1 to toab1t3 and toab1b1 to toab1b3 pins are in their default states. therefore, for the protection of the system, take measures such as making the toab1t1 to toab1t3 and toab1b1 to toab1b3 pins go into a high-impedance state before stopping operation, or setting the output levels of the pins before switching port modes. when a dead-time period is not need ed, set the tab1dtc register to 0. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 602 of 1817 sep 19, 2011 (2/2) tab1at3 note 0 1 a/d trigger output control 3 disable output of a/d trigger signal (tabtadt0) for inttaa4cc1 interrupt. enable output of a/d trigger signal (tabtadt0) for intraa4cc1 interrupt. tab1at2 note 0 1 a/d trigger output control 2 disable output of a/d trigger signal (tabtadt0) for inttaa4cc0 interrupt. enable output of a/d trigger signal (tabtadt0) for inttaa4cc0 interrupt. tab1at1 note 0 1 a/d trigger output control 1 disable output of a/d trigger signal (tabtadt0) for inttab1cc0 (crest interrupt). enable output of a/d trigger signal (tabtadt0) for inttab1cc0 (crest interrupt). tab1at0 note 0 1 a/d trigger output control 0 disable output of a/d trigger signal (tabtadt0) for inttab1ov (valley interrupt). enable output of a/d trigger signal (tabtadt0) for inttab1ov (valley interrupt). tab1atm3 0 1 tab1atm3 mode selection output a/d trigger signal (tabtadt0) for inttaa4cc1 interrupt while dead-time counter is counting up. output a/d trigger signal (tabtadt0) for inttaa4cc1 interrupt while dead-time counter is counting down. tab1atm2 0 1 tab1atm2 mode selection output a/d trigger signal (tabtadt0) for inttaa4cc0 interrupt while dead-time counter is counting up. output a/d trigger signal (tabtadt0) for inttaa4cc0 interrupt while dead-time counter is counting down. note for the setting of the tab1at3 to tab1at0 bits, see chapter 15 a/d converter . v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 603 of 1817 sep 19, 2011 (3) tab1 i/o control register 3 (tab1ioc3) the tab1ioc3 register is an 8-bit register that c ontrols the output of the timer ab1 option function. to output from the toab1tm pin, set the tab1ioc0. tab1oem bit to 1 and then set the tab1ioc3 register. the tab1ioc3 register can be rewritten on ly when the tab1ctl0.tab1ce bit is 0. rewriting each bit of the tab1ioc3 register is prohibit ed when the tab1ctl0.tab1ce bit is 1; however the same value can be rewritten to each bit of the tab1ioc 3 register when the tab1ctl0.tab1ce bit is 1. this register can be read or written in 8-bit or 1-bit units. reset sets this register to a8h. caution set the tab1ioc3 register to the reset value (a8h) when the time r is used in a mode other than the 6-phase pwm output mode. remarks 1. set the output level of the toab1tm pin by using the tab1ioc0 register. 2. m = 1 to 3 tab1olb3 tab1ioc3 tab1oeb3 tab1olb2 tab1oeb2 tab1olb1tab1oeb1 00 <6> <5> <4> <3> <2> 1 setting of toab1bm pin output level (m = 1 to 3) disable inversion of output of toab1bm pin enable inversion of output of toab1bm pin tab1oebm 0 1 tab1olbm 0 1 toab1bm pin output (m = 1 to 3) disable toab1bm pin output. ? when tab1olbm bit = 0, low level is output from toab1bm pin. ? when tab1olbm bit = 1, high level is output from toab1bm pin. enable toab1bm pin output. after reset: a8h r/w address: fffff582h <7> 0 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 604 of 1817 sep 19, 2011 (a) output from toab1 tm and toab1bm pins the toab1tm pin output is controlled by the tab1ioc0.tab1olm and tab1ioc0.tab1oem bits. the toab1bm pin output is controlled by the ta b1ioc3.tab1olbm and tab1ioc3.tab1oebm bits. the timer output with each setting in the 6- phase pwm output mode is shown below. figure 11-3. output control of toab1tm and toab1bm pins (without dead time) 16-bit counter fixed to low-level output fixed to high-level output toab1tm pin output tab1oem bit = 0, tab1olm bit = 0 (status after reset) tab1oebm bit = 0, tab1olbm bit = 1 (status after reset) tab1oem bit = 1, tab1olm bit = 0 (positive-phase output) tab1oebm bit = 1, tab1olbm bit = 1 (negative-phase output) tab1oem bit = 1, tab1olm bit = 0 (positive-phase output) tab1oebm bit = 1, tab1olbm bit = 0 (positive-phase output) tab1oem bit = 1, tab1olm bit = 1 (negative-phase output) tab1oebm bit = 1, tab1olbm bit = 1 (negative-phase output) toab1bm pin output toab1tm pin output toab1bm pin output toab1tm pin output toab1bm pin output toab1tm pin output toab1bm pin output remark m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 605 of 1817 sep 19, 2011 table 11-1. toab1tm pin output tab1olm bit tab1oem bit tab1ce bit toab1tm pin output 0 x low-level output 0 low-level output 0 1 1 toab1tm positive-phase output 0 x high-level output 0 high-level output 1 1 1 toab1tm negative-phase output remark m = 1 to 3 table 11-2. toab1bm pin output tab1olbm bit tab1oebm bit tab1ce bit toab1bm pin output 0 x low-level output 0 low-level output 0 1 1 toab1bm positive-phase output 0 x high-level output 0 high-level output 1 1 1 toab1bm negative-phase output remark m = 1 to 3 (6) high-impedance output control re gisters 0, 1 (hza0ctl0, hza0ctl1) the hza0ctl0 and hza0ctl1 regi sters are 8-bit registers that control the high-impedance st ate of the output buffer. these registers can be read or written in 8-bit or 1-bit units. however, the hza0dcfn bit is a read-only bit and cannot be written. 16-bit access is not possible. reset sets these registers to 00h. software can be used to always write the same value to the hza0ctln register. the relationship between detection factor an d the control registers is shown below. high-impedance control factor pins subject to high-impedance control external pin control register when toab1t1 to toab1t3 are output when toab1b1 to toab1b3 are output toab1off/intp18 hza0ctl0 when toaa11 is output toaa1off/intp06 hza0ctl1 caution high impedance control is pe rformed only when the target port is specified as a target pin in the above table. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 606 of 1817 sep 19, 2011 (1/2) hza0dcen hza0dcen 0 1 high-impedance output control disable high-impedance output control operation. pins can function as output pins. enable high-impedance output control operation. hza0ctln hza0dcmn hza0dcnn hza0dcpn hza0dctn hza0dccn 0 hza0dcfn <6> 5 4 <3> <2> 1 hza0dcnn 0 0 1 1 hza0dcpn 0 1 0 1 external pin input edge specification no valid edge (setting the hza0dcfn bit by external pin input is prohibited). rising edge of the external pin is valid (abnormality is detected by rising edge input). falling edge of the external pin is valid (abnormality is detected by falling edge input). setting prohibited hza0dcmn 0 1 condition of clearing high-impedance state by hza0dccn bit setting of the hza0dccn bit is valid regardless of the external pin input. setting of the hza0dccn bit is invalid while the external pin input holds a level detected as abnormal (active level). after reset: 00h r/w address: hza0ctl0 fffff590h, hza0ctl1 fffff591h <7> <0> rewrite the hza0dcmn bit when the hza0dcen bit = 0. ? rewrite the hza0dcnn and hza0dcpn bits when the hza0dcen bit is 0. ? for the valid edge specification of the interrupts of the intp06 and intp18 pins, see 25.6.2 (2) external interrupt falling, rising edge specification register 2 (intr2, intf2) and (6) external interrupt falling, rising edge specification register 9h (intr9, intf9) . ? for the edge specification of the external pins, begin with the toab1off and toaa1off pins. then, perform edge specification for the external pins other than the toab1off and toaa1off pins. otherwise, an undefined edge may be detected when the edge for the toab1off and toaa1off pins is specified. ? high-impedance output control is performed when the valid edge is input after the operation is enabled (by setting hza0dcen bit to 1). if the external pin is at the active level when the operation is enabled, therefore, high-impedance output control is not performed. (n = 0, 1) v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 607 of 1817 sep 19, 2011 (2/2) hza0dccn 0 1 high-impedance output control clear bit no operation pins that have gone into a high-impedance state are output-enabled by software and the hza0dcfn bit is cleared to 0. ? pins can function as output pins when the hza0dcm bit = 0, regardless of the status of the external pin. ? if an edge indicating abnormality is input to the external pin (which is set by the hza0dcnn and hza0dcpn bits) when the hza0dcm bit = 1, the hza0dccn bit is invalid even if it is set to 1. ? the hza0dccn bit is always 0 when it is read. ? the hza0dccn bit is invalid even if it is set to 1 when the hza0dcen bit = 0. ? simultaneously setting the hza0dctn and hza0dccn bits to 1 is prohibited. hza0dcfn high-impedance output status flag indicates that output of the pin is enabled. ? this bit is cleared to 0 when the hza0dcen bit = 0. ? this bit is cleared to 0 when the hza0dccn bit = 1. indicates that the pin goes into a high-impedance state. ? this bit is set to 1 when the hza0dctn bit = 1. ? this bit is set to 1 when an edge indicating abnormality is input to the external pin (which is detected according to the setting of the hza0dcnn and hza0dcpn bits). 0 1 hza0dctn 0 1 high-impedance output trigger bit no operation pins are made to go into a high-impedance state by software and the hza0dcfn bit is set to 1. ? if an edge indicating abnormality is input to the external pin (which is detected according to the setting of the hza0dcnn and hza0dcpn bits), the hza0dctn bit is invalid even if it is set to 1. ? the hza0dctn bit is always 0 when it is read because it is a software-triggered bit. ? the hza0dctn bit is invalid even if it is set to 1 when the hza0dcen bit = 0. ? simultaneously setting the hza0dctn and hza0dccn bits to 1 is prohibited. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 608 of 1817 sep 19, 2011 figure 11-4. high-impedance output controller configuration toab1b1 toab1t1 toab1b2 toab1t2 toab1b3 toab1t3 toaa1off/ intp06 toab1off/ intp18 taa1 tab1op toaa11 x1 x2 pll hza0ctl1 hza0ctl0 intp18 intp06 analog filter edge detection edge detection analog filter main oscillator clock monitor circuit remark also see figures 11-1 and 11-2 . v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 609 of 1817 sep 19, 2011 (a) setting procedure (i) setting of high-impedance control operation <1> set the hza0dcmn, hza0dcnn, and hza0dcpn bits. <2> set the hza0dcen bit to 1 (enable high-impedance control). (ii) changing setting after enablin g high-impedance control operation <1> clear the hza0dcen bit to 0 (to stop the high-impedance control operation). <2> change the setting of the hza0 dcmn, hza0dcnn, and hza0dcpn bits. <3> set the hza0dcen bit to 1 (to enable t he high-impedance control operation again). (iii) resuming output when pins are in high-impedance state if the hza0dcmn bit is 1, set the hza0dccn bit to 1 to clear the high-impedance state after the valid edge of the external pin is detected. however, t he high-impedance state cannot be cleared unless this bit is set while the input level of the external pin is inactive. <1> set the hza0dccn bit to 1 (command si gnal to clear the high-impedance state). <2> read the hza0dcfn bit and check the flag status. <3> return to <1> if the hza0dcfn bit is 1. t he input level of the external pin must be checked. the pin can function as an output pin if the hza0dcfn bit is 0. (iv) making pin go into high- impedance state by software the hza0dctn bit must be set to 1 by software to ma ke the pin go into a high-impedance state while the input level of the external pin is inactive. the fo llowing procedure is an example in which the setting is not dependent upon the setting of the hza0dcmn bit. <1> set the hza0dctn bit to 1 (high-impedance output command). <2> read the hza0dcfn bit to check the flag status. <3> return to <1> if the hza0dcfn bit is 0. t he input level of the external pin must be checked. the pin is in a high-impedance state if the hza0dcfn bit is 1. however, if the external pin is not used with the hza0dcpn bit and hza0dcnn bit cleared to 0, the pin goes into a high-impedance state when the hza0dctn bit is set to 1. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 610 of 1817 sep 19, 2011 11.4 operation 11.4.1 system outline (1) outline of 6-phase pwm output the 6-phase pwm output mode is used to generate a 6- phase pwm output wave, by using the timer ab1 (tab1) and the tab1 option (tab1op0) in combination. the 6-phase pwm output mode is enabled by setting the tab1ctl1.tab1md2 to tab1ctl1.tab1md0 bits of tab1 to ?111?. one 16-bit counter and four 16-bit compare registers of tab1 are used to generate a basic 3-phase wave. the functions of the compar e registers are as follows. taa4 can perform a tuning operation with tab1 to generat e a conversion trigger source for the a/d converter. compare register function settable range tab1ccr0 register setting of cycle 0002h m fffeh tab1ccr1 register specifying output width of phase u 0000h i m + 1 tab1ccr2 register specifying output width of phase v 0000h j m + 1 tab1ccr3 register specifying output width of phase w 0000h k m + 1 remark m = set value of tab1ccr0 register i = set value of tab1ccr1 register j = set value of tab1ccr2 register k = set value of tab1ccr3 register a dead-time interval is generated from the basic 3-phase wave generated by using three 10-bit dead-time counters and one compare register to create a wave with a revers e phase to that of the bas ic 3-phase wave. then a 6- phase pwm output wave (u, u, v, v, w, and w) is generated. the 16-bit counter for generating the basic 3-phase wave c ounts up or down. after the operation has been started, this counter counts up. when its count value matches the cycle set to the tab1ccr0 register, the counter starts counting down. when the count value ma tches 0001h, the counter counts up agai n. this means that a value two times higher than the value set to the t ab1ccr0 register + 1 is the carrier cycle. 10-bit dead-time counters 1 to 3, which generate the dead-time interval, count up. therefore, the value set to the tab1 dead-time compare register (tab1dtc) is used as a dead-time value as is. because three counters are used, dead time can be generated independently in phases u, v, and w. however, because there is only one register that specifies a dead-time value (tab1dtc), t he same dead-time value is used in all three phases. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 611 of 1817 sep 19, 2011 figure 11-5. outline of 6-phase pwm output mode tot1 toab1t1 pin output (u) tob1 toab1b1 pin output (u) toab1t2 pin output (v) toab1b2 pin output (v) toab1t3 pin output (w) toab1b3 pin output (w) tot2 tob2 tot3 tob3 16-bit counter up/down selection tab1ccr0 register (carrier cycle) toab11 (internal signal) note 0001h toab12 (internal signal) note toab13 (internal signal) note tab1ccr1 register (phase u output data) tab1ccr2 register (phase v output data) tab1ccr3 register (phase w output data) dead-time counter 1 dead-time counter 2 dead-time counter 3 tab1dtc register (dead-time value) inttab1ov signal (valley interrupt) inttab1cc0 signal (crest interrupt) toab10 pin output inttab1ov_base interrupt culling circuit a/d trigger generator note toab11, toab12, and toab13 functi on alternately as output pins. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 612 of 1817 sep 19, 2011 figure 11-6. timing chart of 6-phase pwm output mode 16-bit counter m (carrier data) tab1ccr0 register 0000h toab11 signal (internal signal) toab12 signal (internal signal) toab13 signal (internal signal) tab1dtc register toab1t1 pin output (u) toab1b1 pin output (u) dead-time counter 1 dead-time counter 2 dead-time counter 3 tab1ccr1 register tab1ccr2 register tab1ccr3 register n (dead-time value) i (phase u data) j (phase v data) k (phase w data) i ii i j j j j k k k k m + 1 m + 1 toab10 pin output basic phase u output width = (m + 1 - i) 2 basic phase v output width = (m + 1 ? j) 2 basic phase w output width = (m + 1 ? k) 2 phase u output width = (m + 1 ? i) 2 ? n phase v output width = (m + 1 ? j) 2 ? n phase w output width = (m + 1 ? k) 2 ? n dead-time width = n phase u output width = (m + 1 ? i) 2 + n carrier cycle = (m + 1) 2 toab1t2 pin output (v) toab1b2 pin output (v) toab1t3 pin output (w) toab1b3 pin output (w) phase v output width = (m + 1 ? j) 2 + n phase w output width = (m + 1 ? k) 2 + n cautions 1. set the value ?m? of th e tab1ccr0 register in a range of 0002h m fffeh in the 6-phase pwm output mode. 2. only a value of up to ?m + 1? can be set to the tab1ccr1, tab1ccr2, and tab1ccr3 registers. 3. the output is 100% if ?0000h? is set to the tab1ccr1, tab1ccr2, and tab1ccr3 registers. the output is 0% if ?m + 1? is set to the tab1ccr1, tab1ccr2, and tab1ccr3 registers. the output (duty 50%) rises at the crest (m + 1) of the 16-bit counter and falls at the valley (0000h) if ?m + 2? or higher is set to the tab1ccr1, tab1ccr2, and tab1ccr3 registers. 4. if the operation value of an equation (suc h as (m + 1 ? i) 2 ? n) of the output width of phases u, v, and w is 0 or lower, it is converge d to 0 (100% output). if the operation value is higher than ?(m + 1) 2?, it is co nverged to (m + 1) 2 (0% output). v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 613 of 1817 sep 19, 2011 (2) interrupt requests two types of interrupt requests are available: the in ttab1cc0 (crest interrupt) signal and inttab1ov (valley interrupt) signal. the inttab1cc0 and inttab1ov signals can be culled by using the tab1opt1 register. for details of culling interrupts, see 11.4.3 interrupt culling function . ? inttab1cc0 (crest interrupt) signal: an interrupt signal indicating a match between the value of the 16-bit counter that counts up and the va lue of the tab1ccr0 register ? inttab1ov (valley interrupt) signal: an interrupt si gnal indicating a match between the value of the 16-bit counter that counts do wn and the value 0001h (3) rewriting registers during timer operation the following registers have a buffer register and can be rewritten in the anytime rewr ite mode, batch rewrite mode, or intermittent batch rewrite mode. related unit register timer aa1 taa1 capture/compare register 0 (taa1ccr0) taa1 capture/compare register 1 (taa1ccr1) timer ab1 tab1 capture/compare register 0 (tab1ccr0) tab1 capture/compare register 1 (tab1ccr1) tab1 capture/compare register 2 (tab1ccr2) tab1 capture/compare register 3 (tab1ccr3) timer ab1 option tab1 option register 1 (tab1opt1) for details of the transfer function of the compare register, see 11.4.4 operation to rewrite register with transfer function . (4) counting-up/down operation of 16-bit counter the operation status of the 16-bit counter can be checked by using the tab1cuf bit of tab1 option register 0 (tab1opt0). status of tab1cuf bit status of 16-bit counter range of 16-bit counter value tab1cuf bit = 0 counting up 0000h ? m tab1cuf bit = 1 counting down (m + 1) ? 0001h remark m = set value of tab1ccr0 register v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 614 of 1817 sep 19, 2011 figure 11-7. interrupt and up/down flag 16-bit counter m (carrier data) tab1ccr0 register 0000h toab1t1 pin output (u) toab1b1 pin output (u) tab1ccr1 register tab1ccr2 register tab1ccr3 register i (phase u data) j (phase v data) k (phase w data) i i i i j j j j k k k k m + 1 m + 1 toab1t2 pin output (v) toab1b2 pin output (v) toab10 pin output inttab1cc0 (crest interrupt) inttab1ov (valley interrupt) tab1cuf (up/down flag) toab1t3 pin output (w) toab1b3 pin output (w) v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 615 of 1817 sep 19, 2011 11.4.2 dead-time control (generat ion of negative-phase wave signal) (1) dead-time control mechanism in the 6-phase pwm output mode, com pare registers 1 to 3 (tab1ccr1, tab1ccr2, and tab1ccr3) are used to set the duty factor, and compare register 0 (tab1ccr0) is us ed to set the cycle. by setting these four registers and by starting the operation of tab1, three types of pwm output waves (basic 3-phase waves) with a variable duty factor are generated. these three pwm output waves are input to the timer ab option unit (tabop) and their inverted signal with dead-time is created to generate three sets of (six) pwm waves. the tabop unit consists of three 10-bit counters (dead-time counters 1 to 3) that operate in synchronization with the count clock of tab1, and a tab1 dead-time compare regi ster (tab1dtc) that specifies dead time. if ?a? is set to the tab1dtc register, the dead-time value is ?a?, and interval ?a? is created between a positive-phase wave and a negative-phase wave. figure 11-8. pwm output wave with dead time (1) (a) when dead time is in serted (tab1dtc register = a) a a 16-bit counter toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output (b) no dead time (t ab1dtc register = 000h) 0 0 0000h 16-bit counter toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output remark m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 616 of 1817 sep 19, 2011 (2) pwm output of 0%/100% the v850es/jh3-e and v850es/jj3-e are capable of 0% wave output and 100% wave output for pwm output. a low level is continuously output from the toab1tm pin as the 0% wave output. a high level is continuously output from the toab1tm pin as the 100% wave output. a 0% wave is output by setting the tab1ccrm regist er to ?m + 1? when the tab1ccr0 register = m. a 100% wave is output by setting the tab1ccrm register to ?0000h?. rewriting the tab1ccrm register is enabled while the timer is operating, and 0% wave output or 100% wave output can be selected at the point of the crest interrupt (inttab1cc0) and valley interrupt (inttab1ov). remark m = 1 to 3 figure 11-9. 0% pwm output waveform (with dead time) i i 0% output i i i i i m i i i m + 1 m + 1 m + 1 m + 1 i i <4> <3> <2> <1> 0000h 0% output 16-bit counter tab1ccr0 register tab1ccr1 register toab1t1 pin output toab1b1 pin output ccr1 buffer register forced timing of timer output <1> 0% output is selected by the valley in terrupt (without a match with the 16-bit counter). the valley interrupt forcibly lowers t he timer output. this produces the 0% output. <2> 0% output is canceled by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this cancels the 0% output. <3> 0% output is selected by the crest inte rrupt (with a match with the 16-bit counter). the crest interrupt forcibly raises the timer outpu t, but lowering the timer output takes precedence when the value of the tab1ccrm register matches the value of the 16-bit counter. as a result, the 0% wave is output. <4> 0% output is canceled by the valley inte rrupt (without a match wit h the 16-bit counter). the valley interrupt forcibly lowers the timer output. this cancels the 0% output. remarks 1. means forcible raising and means forcible lowering. 2. m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 617 of 1817 sep 19, 2011 figure 11-10. 100% pwm output waveform (with dead time) ii i ii i m i i i i 0000h 0000h 0000h 0000h 0000h i <1> <2> <3> <4> i 100% output 100% output 16-bit counter tab1ccr0 register tab1ccr1 register toab1t1 pin output toab1b1 pin output ccr1 buffer register forced timing of timer output <1> 100% output is selected by the valley in terrupt (with a match with the 16-bit counter). the valley interrupt forcibly lowers the timer output, but raising the timer output takes precedence when the value of the tab1ccrm register matches the value of the 16-bit counter. as a result, the 100% output is produced. <2> 100% output is canceled by the valley inte rrupt (without a match with the 16-bit counter). the valley interrupt forcibly lowers the timer output. this cancels the 100% output. <3> 100% output is selected by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this produces the 100% output. <4> 100% output is canceled by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this cancels the 100% output. remarks 1. means forcible raising and means forcible lowering. 2. m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 618 of 1817 sep 19, 2011 figure 11-11. pwm output waveform from 0% to 100% and from 100% to 0% (with dead time) 0% output m 0000h 0000h 0000h 0000h 0000h 0000h m + 1 m + 1 m + 1 m + 1 0000h <1> <1> <2> <2> <1> 100% output 100% output 100% output 16-bit counter tab1ccr0 register tab1ccr1 register toab1t1 pin output toab1b1 pin output ccr1 buffer register forced timing of timer output 0% output <1> the valley interrupt selects 100% 0% or 0% 100% output. output can be selected from 100% 0% or 0% 100% immediately after the timer has been started. <2> the crest interrupt selects 100% 0% output. the crest interrupt selects 100% 0% output by using the timer output forcible raising function and by a match between the 16-bit counter value and the tab1ccr0 register value. (3) output waveform in vicinity of 0% and 100% output if an interrupt is generated because the value of the 16-bit counter matches the value of the compare register while dead time is being counted, the dead-time counter is cleared and starts its count operation again. the output waveform of dead-time control in the vicinity of 0% and 100% output is shown below. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 619 of 1817 sep 19, 2011 figure 11-12. pwm output waveform with dead time (2) (a) 0% output (tab1ccrm register = m + 1, tab1ccr0 register = m, tab1dtc register = a) 16-bit counter 000h (dead-time counter m does not count) h l l 0000h toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output (b) in vicinity of 0% ou tput (tab1ccrm register = i m + 1 ? a/2, tab1ccr0 register = m, tab1dtc register = a) dead-time counter is cleared and counts again negative-phase output width: (m + 1 ? i) 2 + a (e.g., output width is 2 + a where tab1ccrm register = m) l 16-bit counter 0000h toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output 000h (c) in vicinity of 100% output (tab1ccrm register = i a/2, tab1ccr0 register = m, tab1dtc register = a) counter is cleared and counts again positive-phase output width: (m + 1 ? i) 2 ? a) (e.g., output width is 2 ? a where tab1ccrm register = 0001h.) 16-bit counter 0000h toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output 000h (d) 100% output (tab1ccrm register = 0000h, tab1 ccr0 register = m, tab1dtc register = a) 000h (dead-time counter m does not count) 16-bit counter 0000h toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output remark m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 620 of 1817 sep 19, 2011 (4) automatic dead-time width narro wing function (tab1opt2.tab1dtm bit = 1) the dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the tab1opt2.tab1dtm bit to 1. by setting the tab1dtm bit to 1, the dead-time counter is not cleared, but starts down counting if the toab1m (internal signal) output of timer ab changes during dead-time counting. the following timing chart shows the operation of the dea d-time counter when the tab1dtm bit is set to 1. figure 11-13. operation of dead-time counter m (1) (a) in vicinity of 0% output (tab1ccrm register = i m + 1 ? a/2, tab1ccr0 register = m, tab1dtc register = a) dead-time counter m starts counting down negative-phase wave output width: (m + 1 ? i) 4 (e.g., output width is 4 where tab1ccrm = m) 16-bit counter 0000h toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output 000h (b) in vicinity of 100% output (tab1ccrm register = i a/2, tab1ccr0 register = m, tab1dtc register = a) dead-time counter m starts counting down positive-phase wave output width: (m + 1 ? i) 2 ? (i 2) (e.g., output width is m 2 ? 2 where tab1ccrm = 0001h) note 16-bit counter 0000h toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output 000h note the output width of the first wave differs from t hat of the second and subsequent waves immediately after the tab1ctl0.tab1ce bit has been set. the fi rst wave is shorter than the second wave because the dead time is fully counted. remark m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 621 of 1817 sep 19, 2011 (5) dead-time control in case of incorrect setting usually, the toab1m (internal signal) output of tab1 chang es only once during dead-time counting, only in the vicinity of 0% and 100% output. th is section shows an example where the tab1ccr0 register (carrier cycle) and tab1dtc register (dead-time value) are incorrectly set. if these registers are incorrectly set, the toab1m (internal signal) output of tab1 changes twice or three times durin g dead-time counting. the following flowchart shows the 6-phase pwm output wave in this case. figure 11-14. operation of dead-time counter m (2) (a) when tab1opt2.tab1dtm bit = 0, tab1ccr0 register = 0006h, tab1dtc register = 000fh, tab1ccrm register = 0004h counter cleared counter is not cleared but continues counting 000h 001h 002h 003h 004h 005h 006h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 00bh 00ch 00dh 00eh 00fh 000h 001h 16-bit counter toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output (b) when tab1opt2.tab1dtm bit = 1, tab1ccr0 register = 0006h, tab1dtc register = 000fh, tab1ccrm register = 0002h starts counting down. output does not change and dead-time counter m continues counting down 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 009h 008h 007h 006h 005h 004h 003h 002h 001h 001h 002h 003h 004h 003h 002h 001h 000h 000h 16-bit counter toab1m signal (internal signal) dead-time counter m toab1tm pin output toab1bm pin output remark m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 622 of 1817 sep 19, 2011 11.4.3 interrupt culling function ? the interrupts to be culled are inttab1cc0 (cre st interrupt) and inttab1ov (valley interrupt). ? the tab1opt1.tab1ice bit is used to enable output of the inttab1cc0 interrupt and the number of times the interrupt is to be culled. ? the tab1opt1.tab1ioe bit is used to enable output of the inttab1ov interrupt and the number of times the interrupt is to be culled. ? the tab1opt1.tab1id4 to tab1opt1.tab1id0 bits are used to specify the number of counts by which a specified interrupt is to be culled. the interrupt is masked for t he duration of the specified nu mber of counts and is generated at the next interrupt timing. ? the tab1opt2.tab1rde bit is used to specify whether transfer is to be culled or not. if it is specified that transfer is to be culled, transfer is executed at the same timing as the interrupt output after culling . if it is specified that transfer is not to be culled, transfer is executed at the transfer timing after the tab1ccr1 register has been written. ? the tab1opt0.tab1cms bit is used to specify whether the registers with a transfer function are batch rewritten or anytime rewritten. the values of the registers are updated in synchronizati on with transfer when the tab1cms bit is 0. when the tab1cms bit is 1, the values of the r egisters are immediately updated when a ne w value is written to the registers. transfer is performed from the tab1ccrm register to the ccrm buffer register in synchronization with the interrupt culling timing. cautions 1. when using the interrupt culling function in the batch rewrit e mode (transfer mode), execute the function in the intermittent batch re write mode (transfer culling mode). 2. the interrupt is generate d at the timing after culling. remark m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 623 of 1817 sep 19, 2011 (1) interrupt culling operation figure 11-15. interrupt culling operation when t ab1opt1.tab1ice bit = 1, tab1opt1.tab1ioe bit = 1, tab1opt2.tab1rde bit = 1 (cr est/valley interrupt output) 16-bit counter tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00000 (not culled) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00001 (1 mask) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00010 (2 masks) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00011 (3 masks) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00100 (4 masks) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00101 (5 masks) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00110 (6 masks) inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1ov signal inttab1ov signal inttab1ov signal inttab1ov signal inttab1ov signal inttab1ov signal inttab1ov signal remark : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 624 of 1817 sep 19, 2011 figure 11-16. interrupt culling operation when t ab1opt1.tab1ice bit = 1, tab1opt1.tab1ioe bit = 0, tab1opt2.tab1rde bit = 1 (crest interrupt output) 16-bit counter tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00000 (not culled) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00001 (1 mask) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00010 (2 masks) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00011 (3 masks) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00100 (4 masks) inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1ov signal inttab1ov signal inttab1ov signal inttab1ov signal inttab1ov signal remark : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 625 of 1817 sep 19, 2011 figure 11-17. interrupt culling operation when t ab1opt1.tab1ice bit = 0, tab1opt1.tab1ioe bit = 1, tab1opt2.tab1rde bit = 1 (valley interrupt output) 16-bit counter tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00000 (not culled) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00001 (1 mask) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00010 (2 masks) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00011 (3 masks) tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00100 (4 masks) inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1cc0 signal inttab1ov signal inttab1ov signal inttab1ov signal inttab1ov signal inttab1ov signal remark : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 626 of 1817 sep 19, 2011 (2) to alternately output crest interrupt (i nttab1cc0) and valley interrupt (inttab1ov) to alternately output the crest and valley interrupt s, set both the tab1opt1.tab1ice and tab1opt1.tab1ioe bits to 1. figure 11-18. crest/valley interrupt output (a) tab1opt0.tab1cms bit = 0, tab1opt2.tab1 rde bit = 1 (with transfer culling control) 16-bit counter tab1id4 to tab1id0 bits tab1id4 to tab1id0 bits (slave bit) inttab1ov signal 00010 00010 00100 transfer timing of rewriting transfer culling count from 2 to 4 00100 inttab1cc0 signal remarks 1. transfer is performed at the culled interrupt out put timing. the other transfer timing is ignored. 2. : culled interrupt (b) tab1cms bit = 1, tab1rde bit = 0 or 1 (without transfer control) 00010 00010 00100 reflected immediately 00100 timing of rewriting transfer culling count from 2 to 4 16-bit counter tab1id4 to tab1id0 bits tab1id4 to tab1id0 bits (slave bit) inttab1ov signal inttab1cc0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 627 of 1817 sep 19, 2011 (3) to output only crest interrupt (inttab1cc0) set the tab1opt1.tab1ice bit to 1 and cl ear the tab1opt1.tab1ioe bit to 0. figure 11-19. crest interrupt output (a) tab1opt0.tab1cms bit = 0, tab1opt2.tab1 rde bit = 1 (with transfer culling control) 00010 l 00010 00011 transfer 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tab1id4 to tab1id0 bits tab1id4 to tab1id0 bits (slave bit) inttab1ov signal inttab1cc0 signal remarks 1. transfer is performed at the culled interrupt out put timing. the other transfer timing is ignored. 2. : culled interrupt (b) tab1cms bit = 1, tab1rde bit = 0 or 1 (without transfer control) 00010 l reflected immediately 00011 00010 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tab1id4 to tab1id0 bits tab1id4 to tab1id0 bits (slave bit) inttab1ov signal inttab1cc0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 628 of 1817 sep 19, 2011 (4) to output only valley interrupt (inttab1ov) clear the tab1opt1.tab1ice bit to 0 and set the tab1ioe bit to 1. figure 11-20. valley interrupt output (a) tab1opt0.tab1cms bit = 0, tab1opt2.tab1 rde bit = 1 (with transfer culling control) 00010 l 00010 00011 transfer 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tab1id4 to tab1id0 bits tab1id4 to tab1id0 bits (slave bit) inttab1ov signal inttab1cc0 signal remarks 1. transfer is performed at the culled interrupt out put timing. the other transfer timing is ignored. 2. : culled interrupt (b) tab1cms bit = 1, tab1rde bit = 0 or 1 (without transfer control) 00010 l reflected immediately 00011 00010 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tab1id4 to tab1id0 bits tab1id4 to tab1id0 bits (slave bit) inttab1ov signal inttab1cc0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 629 of 1817 sep 19, 2011 11.4.4 operation to rewrite re gister with transfer function the following seven registers are provided with a transfer f unction and are used to control a motor. each of the registers has a buffer register. ? tab1ccr0: register that specifies the cycle of the 16-bit counter (tab) ? tab1ccr1: register that specifies the duty factor of toab1t1 (u) and toab1b1 (u) ? tab1ccr2: register that specifies the duty factor of toab1t2 (v) and toab1b2 (v) ? tab1ccr3: register that specifies the duty factor of toab1t3 (w) and toab1b3 (w) ? tab1opt1: register that specifies the culling of interrupts ? taa4ccr0: register that specifies the a/d conversion start trigger generation timing (taa4 during tuning operation) ? taa4ccr1: register that specifies the a/d conversion start trigger generation timing (taa4 during tuning operation) the following three rewrite modes are provided in the registers with a transfer function. ? anytime rewrite mode this mode is set by setting the tab1opt0.tab1cms bit to 1. the specification of the tab1opt2.tab1rde bit is ignored. in this mode, each compare register is updated independe ntly, and the value of the com pare register is updated as soon as a new value is written to it. ? batch rewrite mode (transfer mode) this mode is set by clearing the tab1opt0.tab1cms bit to 0, the tab1opt1.tab1id4 to tab1opt1.tab1id0 bits to 00000, and the tab1opt2.tab1rde bit to 0. when data is written to the tab1ccr1 register, data in the sev en registers are transferred to the buffer register all at once at the next transfer timing. unless the tab1ccr1 regi ster is rewritten, the trans fer operation is not performed even if the other six registers are rewritten. the transfer timing is the timing of each crest (match between the 16-bit counter value and tab1ccr0 register value) and valley (match between the 16-bit counter value and 0001h) regardless of the interrupt. ? intermittent batch rewrite mode (transfer culling mode) this mode is set by clearing the tab1opt0.tab1cms bi t to 0 and setting the tab1opt2.tab1rde bit to 1. when data is written to the tab1ccr1 regist er, data from the seven registers is trans ferred to the buffer register all at once at the next transfer timing. unless the tab1ccr1 regi ster is rewritten, the trans fer operation is not performed even if the other six registers are rewritten. if interrupt culling is specified by the tab1 opt1 register, the transfer timing is also culled as the interrupts are culled, and data from the seven registers is transferred all at once at the culled timing of the crest interrupt (match between the 16-bit counter value and tab1ccr0 register value) or valley interrupt (match between the 16-bit counter value and 0001h). for details of the interrupt culling function, see 11.4.3 interrupt culling function . v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 630 of 1817 sep 19, 2011 (1) anytime rewrite mode this mode is set by setting the tab1opt0.tab1cms bit to 1. the se tting of the tab1opt2.tab1rde bit is ignored. in this mode, the value written to each register with a tr ansfer function is immediately transferred to an internal buffer register and compared with the valu e of the counter. if a register with tr ansfer function is rewritten in this mode after the count value of the 16-bit counter matches the value of the tab1ccrm register, the rewritten value is not reflected because the next match is ignored after the first match has occurred. if the register is rewritten during counting up, the new register value becomes valid after the counter has started counting down. figure 11-21. timing of reflecting rewritten value operating clock (f xx /2) tab1ccr0 register ba ccr0 buffer register ba note note after the register (tab1ccr0, tab1ccr2, tab1ccr3, tab1opt1, taa4ccr0, or taa4ccr1) has been written, the written value is transferred to an inter nal buffer register after four clocks of the operating clock. however, the value of the tab1ccr1 register is transferred after 5 clocks. (a) rewriting tab1ccr0 register even if the tab1ccr0 register is rewritten in the anyt ime rewrite mode, the new value may not be reflected in some cases. figure 11-22. example of rewriting tab1ccr0 register 16-bit counter <1> <2> <1> <2> rewriting during period <1> (rewriting during counting up) if the newly rewritten value is greater than the value of the 16-bit counter, there is no problem because it will match the value of the 16-bit counter. if the new value is less than the va lue of the 16-bit counter, it will not match the value of the counter. as a result, the 16-bit counter overflows and continues counting up from 0000h until it matches the register value again , and the correct pwm waveform is not output. rewriting during period <2> (rewriting during counting down) a match with the value of the 16-bit counter is ignored du ring counting down. therefore, the rewritten period value is reflected as the match point star ting from counting up in the next cycle. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 631 of 1817 sep 19, 2011 (b) rewriting tab1ccrm register figure 11-24 shows the timing of rewriting before the va lue of the 16-bit counter matches the value of the tab1ccrm register (<1> in figure 11-23), and figure 11-25 shows the timing of rewriting after the value of the 16-bit counter matches the value of the t ab1ccrm register (<2> in figure 11-23). figure 11-23. basic operation of 16- bit counter and tab1ccrm register (a) basic figure 16-bit counter tab1ccrm register <1> <2> <1> <2> <1> <2> <1> <2> i ii ii remarks 1. i = set value of tab1ccrm register 2. m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 632 of 1817 sep 19, 2011 figure 11-24. example of rewriting tab1ccr1 to t ab1ccr3 registers (rewriting before match occurs) (a) if the tab1ccrm register is rewritten before its value matc hes the value of the 16-bit counter, the register value will match the value of the 16-b it counter after the register has been rewritten. consequently, the new register value is immediately reflected. 16-bit counter ccrm buffer register tab1ccrm register toab1tm pin output i k k i k k ik (b) if a value less than the value of the 16- bit counter (greater if the counter is counting down) is written to the tab1ccrm register, the output waveform is as follows because the register value do es not match the counter value. i i r r r r ir 16-bit counter ccrm buffer register tab1ccrm register toab1tm pin output if the register value does not match the counter value, the toab1tm pin output does not change. even if the value of the 16-bit counter does not match the value of the tab1ccr m register, the toab1tm pin output always changes to the high level if the crest interrupt oc curs and to the low level if the valley interrupt occurs. this is a function provided for 0% output and 100% output. for details, see 11.4.2 (2) pwm output of 0%/100% . remarks 1. i, r, k = set values of tab1ccrm register 2. m = 1 to 3 v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 633 of 1817 sep 19, 2011 figure 11-25. example of rewriting tab1ccr1 to tab1ccr3 registers (rewriting after match occurs) ccrm buffer register 16-bit counter tab1ccrm register inttab1ccm signal toab1tm pin output i k k i i k k ik <1> <3> <2> <1> matching of the count value of the 16-bit counter and the value of t he tab1ccrm register as a result of rewriting the register is ignored after a matc h signal has been generated, and the pwm output does not change. <2> even if the pwm output does not change, the interrupt generat ed upon a match between the 16-bit counter value and the tab1ccrm regi ster value (inttab1ccm) is output. <3> the next match between the 16-bit counter and tab1 ccrm register is valid after the counter has changed its counting direction to up or down, and the pwm output changes. if the tab1ccrm register is rewritten after its value matc hes the value of the 16-bit counter, the next match is ignored after the first match occurs and the rewritten value is not reflected in the to ab1tm pin output. if the register is rewritten while the counter is counting down, the match that occu rs after the counter starts counting down is valid (the match that occurs after the counter has started counting up is valid if the register is rewritten while the counter is counting up). remarks 1. i, r, k = set value of tab1ccrm register 2. m = 1 to 3 (c) rewriting tab1opt1 register the interrupt culling counter is cleared when the tab1op t1 register is written. when the interrupt culling counter has been cleared, the measured number of times the interrupt has occurred is discarded. consequently, the interrupt generation interval is temporarily extended. to avoid this operation, rewrite the tab1opt1 register in the intermittent batch rewrite mode (transfer culling mode). for details of rewriting the tab1opt1 register, see 11.4.3 interrupt culling function . v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 634 of 1817 sep 19, 2011 (2) batch rewrite mode (transfer mode) this mode is set by clearing the tab1opt0.tab1cms bi t to 0, the tab1opt1.tab1 id4 to tab1opt1.tab1id0 bits to 00000, and the tab1opt2.tab1rde bit to 0. in this mode, the values written to each compare register ar e transferred to the internal buffer register all at once at the transfer timing and compared with the counter value. (a) rewriting procedure if data is written to the tab1ccr1 register, the va lues set to the tab1ccr0 to tab1ccr3, tab1opt1, taa4ccr0, and taa4ccr1 registers are transferred all at onc e to the internal buffer register at the next transfer timing. therefore, write to the tab1ccr1 register last. writing to the register is prohibited after the tab1ccr1 register has been written and before the tr ansfer timing is generated (until the crest (match between the 16-bit counter value and tab1ccr0 regist er value) or the valley (match between the 16-bit counter value and 0001h)). the op eration procedure is as follows. <1> rewriting the tab1ccr0, tab1ccr2, tab1ccr3, tab1opt1, taa4ccr0, and taa4ccr1 registers do not rewrite registers that do not have to be rewritten. <2> rewriting the tab1ccr1 register rewrite the same value to the register even when it is not necessary to rewrite the tab1ccr1 register. <3> holding the next rewriting pending until the transfer timing is generated rewrite the register next time after the in ttab1ov or inttab1cc0 interrupt has occurred. <4> return to <1>. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 635 of 1817 sep 19, 2011 figure 11-26. basic operation in batch mode inttab1ov signal inttab1cc0 signal ccr2 buffer register ccr3 buffer register opt1 buffer register tab1ccr2 register tab1ccr3 register tab1opt1 register 16-bit counter (tab1) transfer timing tab1ccr0 register tab1ccr1 register ccr0 buffer register ccr1 buffer register v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 636 of 1817 sep 19, 2011 (b) rewriting tab1ccr0 register when rewriting the tab1ccr0 register in the batch re write mode, the output waveform differs depending on whether transfer occurs at the crest (match between the 16 -bit counter value and tab1ccr0 register value) or at the valley (match between the 16 -bit counter value and 0001h). usua lly, it is recommended to rewrite the tab1ccr0 register while the 16-bit counter is counting do wn, and transfer the register value at the transfer timing of the crest timing. figure 11-28 shows an example of rewriting the tab1ccr0 register while the 16-bi t counter is counting up (during period <1> in figure 11-27). figure 11-29 shows an example of rewriting the tab1ccr0 register while the counter is counting down (during period <2> in figure 11-27). figure 11-27. basic operation of 16-bit counter <1> <2> <1> <2> 16-bit counter v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 637 of 1817 sep 19, 2011 the transfer timing in figure 11-28 is at the point wher e the crest timing occurs. while the 16-bit counter is counting down, the cycle changes and an asymmetrical tri angular wave is output. because the cycle changes, rewrite the duty factor (voltage data value). figure 11-28. example of rewriting t ab1ccr0 register (during counting up) (a) m > n 16-bit counter transfer timing ccr0 buffer register tab1ccr0 register tab1ccr1 register ccr1 buffer register toab1t1 pin output inttab1cc0 signal inttab1ov signal kk k k i k k n + 1 n + 1 n n m m 0000h 0000h m i i k k (b) m < n 16-bit counter transfer timing ccr0 buffer register tab1ccr0 register tab1ccr1 register ccr1 buffer register toab1t1 pin output inttab1cc0 signal inttab1ov signal kk i n + 1 n + 1 n n m m 0000h 0000h m i i k k remarks 1. if transfer (match between the value of the 16- bit counter and the value of the ccr0 buffer register) occurs in the 6-phase pwm output mode, the value of t he tab1ccr0 register plus 1 is loaded to the 16-bit counter. in this way, t he expected wave can be output even if the cycle value is changed at the transfer timing of the cres t (match between the 16-bit counter value and the tab1ccr0 register value) timing. 2. m: value of ccr0 buffer register before rewriting n: value of ccr0 buffer register after rewriting v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 638 of 1817 sep 19, 2011 figure 11-29. example of rewriting tab1 ccr0 register (during counting down) 16-bit counter transfer timing tab1ccr0 register tab1ccr1 register ccr1 buffer register ccr0 buffer register toab1t1 pin output inttab1cc0 signal inttab1ov signal k kk k ii n n m m + 1 n + 1 0000h 0000h m i i k k because the next transfer timing is at the point of the valley (match between the 16-bit counter value and 0001h), the cycle value changes from the next cycle and output of a symmetrical triangular wave is maintained. because the cycle changes, rewrite the duty value (voltage data value) as required. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 639 of 1817 sep 19, 2011 (c) rewriting tab1ccrm register figure 11-30. example of rewriting tab1ccrm register transfer timing tab1ccrm register 16-bit counter ccrm buffer register toab1tm register inttab1ccm signal k k k i i rr r r i 0000h <1> <2> <1> <2> rewriting during period <1> (rewriting during counting up) because the tab1ccrm register value is transferred at the transfer timing of the crest (match between the 16-bit counter value and tab1ccrm register value), an asymmetrical triangular wave is output. rewriting during period <2> (rewriting during counting down) because the tab1ccrm register value is transferred at the transfer timing of the valley (match between the 16-bit counter value and 0001h), a symmetrical triangular wave is output. remark m = 1 to 3 (d) transferring tab1opt1 register value do not set the tab1opt1.tab1id4 to tab1opt1.tab1id0 bits to other than 00000. when using the interrupt culling function, rewrite the tab1opt1 register in the intermittent batch rewrite mode (transfer culling mode). for details of rewriting the tab1opt1 register, see 11.4.3 interrupt culling function . v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 640 of 1817 sep 19, 2011 (3) intermittent batch rewrit e mode (transfer culling mode) this mode is set by clearing the tab1opt0.tab1cms bi t to 0 and setting the tab1opt2.tab1rde bit to 1. in this mode, the values written to each compare register are transferred to the internal buffer register all at once after the culled transfer timing and compared with the counter value. the transfer timing is the timing at which an interrupt is generated (inttab1cc0, in ttab1ov) by interrupt culling. for details of the interrupt culling function, see 11.4.3 interrupt culling function . (a) rewriting procedure if data is written to the tab1ccr1 register, the da ta of the tab1ccr0 to tab1ccr3, tab1opt1, taa4ccr0, and taa4ccr1 registers are transferred all at once to the in ternal buffer register at the next transfer timing. therefore, write to the tab1ccr1 register last. writ ing to the register is prohibited after the tab1ccr1 register has been written until the transfer timing is ge nerated (until the inttab1ov or inttab1cc0 interrupt occurs). the operation procedure is as follows. <1> rewrite the tab1ccr0, tab1ccr2, tab1ccr3, tab1opt1, taa4ccr0, and taa4ccr1 registers. do not rewrite registers that do not have to be rewritten. <2> rewrite the tab1ccr1 register. rewrite the same value to the register even when it is not necessary to rewrite the tab1ccr1 register. <3> hold the next rewriting pending until the transfer timing is generated. perform the next rewrite after the inttab1 ov or inttab1cc0 inte rrupt has occurred. <4> return to <1>. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 641 of 1817 sep 19, 2011 figure 11-31. basic operation in intermittent batch rewrite mode inttab1ov signal inttab1cc0 signal ccr2 buffer register ccr3 buffer register opt1 buffer register tab1ccr2 register tab1ccr3 register tab1opt1 register v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 642 of 1817 sep 19, 2011 (b) rewriting tab1ccr0 register when rewriting the tab1ccr0 register in the intermi ttent batch mode, the output waveform differs depending on where the occurrence of the crest or valley interrup t is specified by the interrupt culling setting. the following figure illustrates the change of the out put waveform when interrupts are culled. figure 11-32. rewriting tab1ccr0 regi ster (when crest interrupt is set) 16-bit counter transfer timing tab1ccr0 register tab1ccr1 register ccr0 buffer register ccr1 buffer register inttab1cc0 signal toab1t1 pin output inttab1ov signal i l i m m 0000h 0000h m n n k k k k kk n + 1 i i i the transfer timing is generated when the crest interr upt occurs, the cycle of counting up and counting down changes, and an asymmetrical triangular wave is output. remarks 1. this is an example of the operation when the tab1opt1.tab1ice bit = 1, tab1opt1.tab1ioe bit = 0, and tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00001. 2. : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 643 of 1817 sep 19, 2011 figure 11-33. rewriting tab1ccr0 regi ster (when valley interrupt is set) i l i i m 0000h 0000h m n n k k kk m + 1 m + 1 n + 1 i i i 16-bit counter transfer timing tab1ccr0 register tab1ccr1 register ccr0 buffer register ccr1 buffer register inttab1cc0 signal toab1t1 pin output inttab1ov signal the transfer timing is generated when the valley interr upt occurs, the cycle of counting up becomes same as cycle of counting down, and a symmetrical triangular wave is output. remarks 1. this is an example of the operation when the tab1opt1.tab1ice bit = 0, tab1opt1.tab1ioe bit = 1, and tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00001. 2. : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 644 of 1817 sep 19, 2011 (c) rewriting tab1ccr1 to tab1ccr3 registers ? transfer at crest when crest interrupt is set because the register is transferred at the transfer ti ming of the crest interrupt, an asymmetrical triangular wave is output. figure 11-34. rewriting tab1ccr1 register (tab1o pt1.tab1ice bit = 1, tab1opt1.tab1ioe bit = 0, tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00001) 16-bit counter transfer timing tab1ccr1 register ccr1 buffer register toab1t1 pin output i i i r ik transfer at crest interrupt k k i inttab1cc0 signal inttab1ov signal remark : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 645 of 1817 sep 19, 2011 ? transfer at valley when valley interrupt is set because the register is transferred at the transfer timing of the valley interrupt, a symmetrical triangular wave is output. figure 11-35. rewriting tab1ccr1 register (tab1o pt1.tab1ice bit = 1, tab1opt1.tab1ioe bit = 1, tab1opt1.tab1id4 to tab1opt1.tab1id0 bits = 00001) 16-bit counter transfer timing tab1ccr1 register ccr1 buffer register toab1t1 pin output i i r ik transfer at valley interrupt transfer at valley interrupt r k k k i inttab1cc0 signal inttab1ov signal remark : culled interrupt (d) rewriting tab1opt1 register because a new interrupt culling value is transferred when the value of the interrupt culling counter matches the value of the 16-bit counter, the next interrupt and those that follow occur at the set interval. for details of rewriting the tab1opt1 register, see 11.4.3 interrupt culling function . v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 646 of 1817 sep 19, 2011 (4) rewriting tab1opt0.tab1cms bit the tab1cms bit can select the anytim e rewrite mode and batch rewrite mode. this bit can be rewritten during timer operation (when tab1ctl0.tab1ce bit = 1). however, the operation and caution illustrated in figure 11-36 are necessary. if the tab1ccr1 register is written when the tab1cms bit is cleared to 0, a transfer request signal (internal signal) is set. when the transfer request signal is set, the register is transferred at the next transfer timing, and the transfer request signal is cleared. this transfer request signal is also cleared when the tab1cms bit is set to 1. figure 11-36. rewriting tab1cms bit 16-bit counter transfer request signal transfer timing <1> <2> <3> <4> <5> <6> tab1ccr1 register 0000h ccr1 buffer register write signal of tab1ccr1 clear clear tab1cms bit ir rs s k i <1> if the tab1ccr1 register is rewritten when the tab1cms bit is 0, the transfer request signal is set. if the tab1cms bit is set to 1 in this st atus, the transfer request signal is cleared. <2> the register is not transferred because the tab1cm s bit is set to 1 and the transfer request signal is cleared. <3> the transfer request signal is not set even if the t ab1ccr1 register is written when the tab1cms bit is 1. <4> the transfer request signal is not set even if the tab1 ccr1 register is written when the tab1cms bit is 1, so even if the tab1cms bit is cleared to 0, transfer does not occur at the subsequent transfer timing. <5> the transfer request signal is set if the tab1ccr1 register is written when the tab1cms bit is 0. transfer is performed at the subsequent transfer timing and the transfer request signal is cleared. <6> once transfer has been performed, the transfer re quest signal is cleared. therefore, transfer is not performed at the next transfer timing. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 647 of 1817 sep 19, 2011 11.4.5 taa4 tuning operation for a/d co nversion start trigger signal output this section explains the tuning operation of taa4 and tab1 in the 6-phase pwm output mode. in the 6-phase pwm output mode, the tu ning operation is performed with tab1 serving as the master and taa4 as a slave. the conversion start trigger signal of the a/d conver ter can be set as the a/d conversion start trigger source by the inttaa4cc0 and inttaa4cc1 signals of taa4 and th e inttab1ov and inttab1cc0 signals of tab1. (1) tuning operation starting procedure the taa4 and tab1 registers should be set using the following procedure to perform the tuning operation. (a) setting of taa4 register (st op the operations of tab1 and taa4 (by clearing the tab1ctl0.tab1ce bit and taa4ctl0.taa4ce bit to 0)). ? set the taa4ctl1 register to 85h (set the tuni ng operation slave mode and free-running timer mode). ? clear the taa4opt0 register to 00h (select the compare register). ? set an appropriate value to the taa4ccr0 and taa4c cr1 registers (set the default value for comparison for starting the operation). (b) setting of tab1 register ? set the tab1ctl1 register to 07h (master mode and 6-phase pwm output mode). ? set an appropriate value to the tab1ioc0 register (set the output mode of toab1t1 to toab1t3). however, clear the tab1ol0 bit to 0 and set the tab1oe 0 bit to 1 (enable positive phase output). unless this setting is made, the crest interrupt (inttab1cc0 ) and valley interrupt (inttab1ov) do not occur. consequently, the conversion start trigger signal of the a/d converter is not correctly generated. ? set the tab1ioc1 and tab1ioc2 registers to 00h (the tiab10 to tiab13, evtb1, and trgb1 pins of tab1 are not used). ? clear the tab1opt0 register to 00h (select the compare register). ? set an appropriate value to the tab1ccr0 to tab1ccr3 registers (set the default value for comparison for starting the operation). ? set the tab1ctl0 register to 0xh (clear the tab1 ce bit to 0 and set the operating clock of tab1). ? the operating clock of tab1 se t by the tab1ctl0 register is al so supplied to taa4, and the count operation is performed at the same timing. the operating clock of taa4 set by the taa4ctl0 register is ignored. (c) setting of tab1op (tab1 option) register ? set an appropriate value to the tab1opt1 and tab1opt2 registers. ? set an appropriate value to the tab1ioc3 register (set toab1b1 to toab1b3 in the output mode). ? set an appropriate value to the tab1dtc register (set the default value for comparison for starting the operation). (d) setting of alternate function ? set the port to alternate function mode using the port control mode setting. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 648 of 1817 sep 19, 2011 (e) set the taa4ce bit to 1 and set the tab1ce bit to 1 immediately after that to start the 6-phase pwm output operation rewriting the tab1ctl0, tab1ctl1, tab1ioc1, tab1ioc 2, taa4ctl0, and taa4ctl1 registers is prohibited during operation. the operation and the pwm output wavefo rm are not guaranteed if any of these registers is rewritten during operation. however, rewriting the tab1ct l0.tab1ce bit to clear it is permitted. manipulating (reading/writing) the other tab1, taa4 , and tab1 option registers is prohi bited until the taa4ctl0.taa4ce bit is set to 1 and then the tab1ce bit is set to 1. (2) tuning operation clearing procedure to clear the tuning operation and exit the 6-phase pwm output mode, set the taa4 and tab1 registers using the following procedure. <1> clear the tab1ctl0.tab1ce bit to 0 and stop the timer operation. <2> clear the taa4ctl0.taa4ce bit to 0 so that taa4 can be separated. <3> stop the timer output by using the tab1ioc0 register. <4> clear the taa4ctl1.taa4sye bit to 0 to clear the tuning operation. caution manipulating (reading/writing) the other tab1, taa4, and tab1 option registers is prohibited until the tab1ce bit is set to 1 and th en the taa4ce bit is set to 1. (3) when not tuning taa4 when the match interrupt signal of taa4 is not necessary as the conversion trigger s ource that starts the a/d converter, taa4 can be used independently as a separate timer without being tuned. in this case, the match interrupt signal of taa4 cannot be used as a trigger source to start a/d conversi on in the 6-phase pwm output mode. therefore, fix the tab1opt2.tab1 at0 to tab1opt2.tab1at3 bits to 0. the other control bits can be used in t he same manner as when taa4 is tuned. if taa4 is not tuned, the compare r egisters (taa4ccr0 and taa4ccr1) of taa4 are not affected by the setting of the tab1opt0.tab1cms and tab1opt2.tab1rde bit. for t he initialization procedure when taa4 is not tuned, see (b) to (e) in 11.4.5 (1) tuning operation starting procedure . (a) is not necessary because it is a step used to set taa4 for the tuning operation. (4) basic operation of taa4 during tuning operation the 16-bit counter of taa4 only counts up. the 16-bit counter is cleared by the set cycle value of the tab1ccr0 register and starts counting from 0000h again. the count value of this counter is the same as the value of the 16- bit counter of tab1 when it counts up. however, it is not the same when the 16-bit counter of taa4 counts down. ? when tab1 counts up (same value) 16-bit counter of tab1: 0000h m (counting up) 16-bit counter of taa4: 0000h m (counting up) ? when tab1 counts down (not same value) 16-bit counter of tab1: m + 1 0001h (counting down) 16-bit counter of taa4: 0000h m (counting up) v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 649 of 1817 sep 19, 2011 figure 11-37. taa4 during tuning operation r s r s r s r s 16-bit counter of tab1 16-bit counter of taa4 m (carrier data) tab1ccr0 register toab0t1 pin output (u) toab1b1 pin output (u) tab1ccr1 register taa4ccr0 register taa4ccr1 register inttaa4cc0 signal inttaa4cc1 signal tab1ccr2 register tab1ccr3 register i (phase u data) s (a/d conversion start trigger timing 2) r (a/d conversion start trigger timing 3) j (phase v data) k (phase w data) i ii i j j j j k k k k m + 1 m + 1 toab1t2 pin output (v) toab1b2 pin output (v) toab1t3 pin output (w) tabtadt0 signal toab1b3 pin output (w) note note m m m note the tabtadt0 signal is masked by the tab1 opt2.tab1atm2 and tab1opt2.tab1atm3 bits. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 650 of 1817 sep 19, 2011 11.4.6 a/d conversion start trigger output function the v850es/jh3-e and v850es/jj3-e have a function to select four trigger sour ces (inttab1ov, inttab1cc0, inttaa4cc0, inttaa4cc1) to generate the a/d co nversion start trigger signal (tabtadt0). the trigger sources are specified by the tab1opt2.tab1at0 to tab1opt2.tab1at3 bits. ? tab1at0 bit = 1: a/d conversion start trigger signal generated when inttab1ov (counter underflow) occurs. ? tab1at1 bit = 1: a/d conversion start trigger signal generat ed when inttab1cc0 (cycle match) occurs. ? tab1at2 bit = 1: a/d conversion start trigger signal generated when in ttaa4cc0 (match of taa4ccr0 register of taa4 during tuning operation) occurs. ? tab1at3 bit = 1: a/d conversion start trigger signal generated when in ttaa4cc1 (match of taa4ccr1 register of taa4 during tuning operation) occurs. the a/d conversion start trigger signals selected by the tab1at0 to tab1at3 bits are ored and output. therefore, two or more trigger sources can be specified at the same time. the inttab1ov and inttab1cc0 signals selected by the tab1at0 and tab1at1 bits are culled interrupt signals. therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled (by the tab1opt1.tab1ice and tab1opt1.tab1ioe bits), the a/d conversion start trigger signal is not output. the trigger sources (inttaa4cc0 and inttaa4cc1) from t aa4 have a function to mask the a/d conversion start trigger signal depending on the count-up/count-down status of the 16-bit counter, if so set by the tab1at2 and tab1at3 bits. ? tab1atm2 bit: corresponds to the tab1at2 bit and c ontrols inttaa4cc0 (match interrupt signal) of taa4. ? tab1atm2 bit = 0: the a/d conversion start tri gger signal is output when the 16-bit counter counts up (tab1opt0.tab1cuf bit = 0), and the a/d conver sion start trigger signal is not output when the 16-bit counter counts down (tab1opt0.tab1cuf bit = 1). ? tab1atm2 bit = 1: the a/d conversion start tri gger signal is output when the 16-bit counter counts up (tab1opt0.tab1cuf bit = 1), and the a/d conver sion start trigger signal is not output when the 16-bit counter counts down (tab1opt0.tab1cuf bit = 0). ? tab1atm3 bit: corresponds to the tab1at3 bit and c ontrols inttaa4cc1 (match interrupt signal) of taa4. ? tab1atm3 bit = 0: the a/d conversion start tri gger signal is output when the 16-bit counter counts up (tab1opt0.tab1cuf bit = 0), and the a/d conver sion start trigger signal is not output when the 16-bit counter counts down (tab1opt0.tab1cuf bit = 1). ? tab1atm3 bit = 1: the a/d conversion start tri gger signal is output when the 16-bit counter counts up (tab1opt0.tab1cuf bit = 1), and the a/d conver sion start trigger signal is not output when the 16-bit counter counts down (tab1opt0.tab1cuf bit = 0). the tab1atm3, tab1atm2, and tab1at3 to tab1at0 bits can be rewritten while the timer is operating. if the bit that sets the a/d conversion start trigger signal is rewritten while the timer is operating, the new setting is immediately reflecte d in the output status of the a/d conversion start trigger signal. these control bits do not have a transfer function and can be used only in the anytime rewrite mode. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 651 of 1817 sep 19, 2011 cautions 1. the a/d conversion start trigger signal output that is set by the tab1at2 and tab1at3 bits can be used only when taa4 is performing a tuning opera tion as the slave timer of tab1. if tab1 and taa4 are not performing a tuning operation, or if a mode other than the 6-phase pwm output mode is used, the output cannot be guaranteed. 2. the tab1 signal output is internally used to id entify whether the 16-bit counter is counting up or down. therefore, enable toab10 pin output by clearing the tab1ioc0.tab1ol0 bit to 0 and setting the tab1ioc0.tab1oe0 bit to 1. v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 652 of 1817 sep 19, 2011 figure 11-38. example of a/d conversion start trigger (tabtadt0) signal output (tab1opt1.tab1ice bit = 1, tab1opt1.tab1ioe bit = 1, tab1opt1.tab1id4 to tab1opt1.tab1id0 bi ts = 00000: without in terrupt culling) 16-bit counter inttab1ov signal inttaa4cc0 signal inttaa4cc1 signal tab1cuf bit tabtadt0 signal tabtadt0 signal tabtadt0 signal tabtadt0 signal tabtadt0 signal tabtadt0 signal tabtadt0 signal tabtadt0 signal tab1at3 to tab1at0 bits = 0001 (inttab1ov signal output) tab1at3 to tab1at0 bits = 0010 (inttab1cc0 signal output) tab1at3 to tab1 at0 bits = 0100, tab1atm2 bit = 0 (inttaa4cc0 signal output during counting up) tab1at3 to tab1 at0 bits = 0100, tab1atm2 bit = 1 (inttaa4cc0 signal output during counting down) tab1at3 to tab1 at0 bits = 1000, tab1atm3 bit = 1 (inttaa4cc1 signal output during counting down) tab1at3 to tab1at0 bits = 0011 (setting to output a/d conversion start trigger signal when both crest and valley interrupts occ ur) tab1at3 to tab1at0 bits = 1100, tab1atm3 bit = 1, tab1atm2 bit = 0 (inttaa4cc0 and inttaa4cc1 signals ored for output. setting to output a/d conversion start trigger signal when match interrupt of taa4 occurs when counter is counting up or down) tab1at3 to tab1 at0 bits = 1000, tab1atm3 bit = 0 (inttaa4cc1 signal output during counting up) inttab1cc0 signal v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 653 of 1817 sep 19, 2011 figure 11-39. example of a/d conversion start trigger (tabtadt0) signal output (tab1opt1.tab1ice bit = 0, tab1opt1.tab1ioe bit = 1, tab1opt1.tab1id4 to tab1opt1.tab1id0 bi ts = 00010: with interrupt culling) (1) 16-bit counter inttab1ov signal tabtadt0 signal tab1at3 to tab1at0 bits = 0011 (both inttab1cc0 and inttab1ov signals are selected but crest interrupt (inttab1cc0) is not output because interrupt culling is not specified) inttab1cc0 signal l remark : culled interrupt figure 11-40. example of a/d conversion start trigger (tabtadt0) signal output (tab1opt1.tab1ice bit = 0, tab1opt1.tab1ioe bit = 1, tab1opt1.tab1id4 to tab1opt1.tab1id0 bi ts = 00010: with interrupt culling) (2) 16 -bit counter inttab1ov signal tabtadt0 signal tab1at3 to tab1at0 bits = 0101, tab1atm2 bit = 1 tab1cuf bit intaa4cc1 signal intaa4cc0 signal inttab1cc0 signal l caution the inttab1cc0 si gnal is culled but the in ttaa4cc0 signal is not. remark : culled interrupt v850es/jh3-e, v850es/jj3-e chapter 11 motor control function r01uh0290ej0300 rev.3.00 page 654 of 1817 sep 19, 2011 (1) operation under boundary condition (operation when 16-bit counter matches inttaa4cc0 signal) table 11-3. operation when tab1ccr0 register = m, tab1at2 bit = 1, tab1atm2 bit = 0 (counting up period selected) value of taa4ccr0 register value of 16-bit counter of tab1 value of 16-bit counter of taa4 status of 16-bit counter of tab1 tabtadt0 signal output by inttaa4cc0 signal 0000h 0000h 0000h ? output 0000h m + 1 0000h ? not output 0001h 0001h 0001h count-up output 0001h m 0001h count-down not output m m m count-up output m 0001h m count-down not output table 11-4. operation when tab1ccr0 register = m, tab1at2 bit = 1, tab1atm2 bit = 1 (counting down period selected) value of taa4ccr0 register value of 16-bit counter of tab1 value of 16-bit counter of taa4 status of 16-bit counter of tab1 tabtadt0 signal output by inttaa4cc0 signal 0000h 0000h 0000h ? not output 0000h m + 1 0000h ? output 0001h 0001h 0001h count-up not output 0001h m 0001h count-down output m m m count-up not output m 0001h m count-down output caution the taa4ccrm register enables the setting of ?0 ? to ?m? when the tab1ccr0 register = m. setting a value of ?m + 1? or higher is prohibited. if a value of ?m + 1? or higher is set, the 16-bit counter of taa4 is cleared by ?m?. therefore, the tabtadt0 signal is not output. remark m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 655 of 1817 sep 19, 2011 chapter 12 real-time counter 12.1 functions the real-time counter (rtc) has the following features. ? counting up to 99 years using year, month, day-of-w eek, day, hour, minute, and second sub-counters provided ? year, month, day-of-week, day, hour, minute, and second counter display using bcd codes note 1 ? alarm interrupt function ? constant-period interrupt function (period: 1 month to 0.5 second) ? interval interrupt function (period: 1.95 ms to 125 ms) ? pin output function of 1 hz ? pin output function of 32.768 khz ? pin output function of 512 hz or 16.384 khz ? watch error correction function ? subclock operation or main clock operation note 2 selectable notes 1. a bcd (binary coded decimal) code expresses each digit of a decimal number in 4-bit binary format. 2. use the baud rate generator dedicated to the real-time counter to divide the main clock frequency to 32.768 khz for use. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 656 of 1817 sep 19, 2011 12.2 configuration the real-time counter includes the following hardware. table 12-1. configuration of real-time counter item configuration control registers real-time counter control register 0 (rc1cc0) real-time counter control register 1 (rc1cc1) real-time counter control register 2 (rc1cc2) real-time counter control register 3 (rc1cc3) sub-count register (rc1subc) second count register (rc1sec) minute count register (rc1min) hour count register (rc1hour) day count register (rc1day) day-of-week count register (rc1week) month count register (rc1month) year count register (rc1year) watch error correction register (rc1subu) alarm minute register (rc1alm) alarm hour register (rc1alh) alarm week register (rc1alw) prescaler mode register 0 (prsm0) prescaler compare register 0 (prscm0) v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 657 of 1817 sep 19, 2011 figure 12-1. block diagram of real-time counter count enable/ disable circuit sub-counter (16-bit) second counter (7-bit) second counter write buffer minute counter write buffer hour counter write buffer day counter write buffer week counter write buffer minute counter (7-bit) hour counter (6-bit) day counter (3-bit) day-of week counter (3-bit) intrtc0 intrtc1 1 minute 1 hour 1 day 1 month count clock = 32.768 khz f xt f xt /2 6 f xt /2 f xt /2 6 f xt /2 7 f xt /2 8 f xt /2 9 f xt /2 10 f xt /2 11 f xt /2 12 f brg note1 month counter write buffer year counter write buffer month counter (5-bit) year counter (8-bit) minute alarm ict2 to ict0 hour alarm day-of-week alarm 12-bit counter ckdiv rinte intrtc2 rtcdiv note2 cloe2 rtccl note2 cloe0 rtc1hz note2 cloe1 selector selector selector selector note for detail of f brg , refer to 12.3 (17) prescaler mode register 0 (prsm0) and 12.3 (18) prescaler compare register 0 (prscm0) . remark f brg : real-time counter count clock frequency f xt : subclock frequency intrtc0: real-time counter fixed-cycle interrupt signal intrtc1: real-time counter alarm match interrupt signal intrtc2: real-time counter interval interrupt signal v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 658 of 1817 sep 19, 2011 12.2.1 pin configuration the rtc outputs included in the real-time counter are alternatively used as shown in table 12-2. the port function must be set when using each pin (see table 4-18 settings when pins are used for alternate functions ). table 12-2. pin configuration pin number v850es/jh3-e v850es/jj3-e port rtc output other alternate function 40 40 p22 rtc1hz tiab01/toab01/intp02 39 39 p21 rtcdiv tiab00/toab00/rtccl 39 39 p21 rtccl tiab00/toab00/rtcdiv 12.2.2 interrupt functions the rtc includes the following three types of interrupt signals. (1) intrtc0 a fixed-cycle interrupt signal is generated every 0.5 second, second, minute, hour, day, or month. (2) intrtc1 alarm interrupt signal (3) intrtc2 an interval interrupt signal of a cycle of f xt /2 6 , f xt /2 7 , f xt /2 8 , f xt /2 9 , f xt /2 10 , f xt /2 11 , or f xt /2 12 is generated. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 659 of 1817 sep 19, 2011 12.3 registers the real-time counter is controlle d by the following 18 registers. (1) real-time counter control register 0 (rc1cc0) the rc1cc0 register selects the real-time counter input clock. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. rc1pwr stops real-time counter operation. enables real-time counter operation. rc1pwr 0 1 real-time counter operation control rc1cc0 rc1cks 0 0 0 0 0 0 654321 selects f xt as operation clock. selects f brg as operation clock. rc1cks 0 1 operation clock selection 0 7 after reset: 00h r/w address: fffffaddh cautions 1. follow the description in 12.4.8 initializing real-time counter when stopping (rc1pwr = 1 0) the real-time counter while it is operating. 2. the rc1cks bit can be rewritten only when t he real-time counter is stopped (rc1pwr bit = 0). furthermore, rewriting the rc1cks bit at the same time as setting the rc1pwr bit from 0 to 1 is prohibited. (2) real-time counter control register 1 (rc1cc1) the rc1cc1 register is an 8-bit regi ster that starts or stops the real -time counter, controls the rtccl and rtc1hz pins, selects the 12-hour or 24-hour system , and sets the fixed-cycle interrupt function. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 660 of 1817 sep 19, 2011 rtce stops counter operation. enables counter operation. rtce 0 1 control of operation of each counter rc1cc1 0 cloe1 cloe0 ampm ct2 ct1 ct0 654321 disables rtc1hz pin output (1 hz) enables rtc1hz pin output (1 hz) cloe1 0 1 rtc1hz pin output control disables rtccl pin output (32.768 khz) enables rtccl pin output (32.768 khz) cloe0 0 1 rtccl pin output control 12-hour system (a.m. and p.m. are displayed.) 24-hour system ampm 0 1 12-hour system/24-hour system selection 0 7 after reset: 00h r/w address: fffffadeh does not use fixed-cycle interrupts once in 0.5 second (synchronous with second count-up) once in 1 second (simultaneous with second count-up) once in 1 minute (every minute at 00 seconds) once in 1 hour (every hour at 00 minutes 00 seconds) once in 1 day (every day at 00 hours 00 minutes 00 seconds) once in 1 month (one day every month at 00 hours 00 minutes 00 seconds a.m.) ct2 0 0 0 0 1 1 1 fixed-cycle interrupt (intrtc0) selection ct1 0 0 1 1 0 0 1 ct0 0 1 0 1 0 1 cautions 1. writing 0 to the rtce bi t while the rtce bit is 1 is prohibited. clear the rtce bit by clearing the rc1pwr bit according to 12.4.8 initializing real-time counter . 2. the rtc1hz output operates as follows when the cloe1 bit setting is changed. ? when changed from 0 to 1: the rtc1hz output outputs a 1 hz pulse after two clocks or less (2 32.768 khz). ? when changed from 1 to 0: the rtc1hz out put is stopped (fixed to low level) after two clocks or less (2 32.768 khz). 3. see 12.4.1 initial settings and 12.4.2 rewriting each counter during real-time counter operation for setting or changing the ampm bit. furthermore, re-set the rc1hour register when the ampm bit is rewritten. 4. see 12.4.4 changing intrtc0 interrupt setti ng during real-time counter operation when rewriting the ct2 to ct0 bits while the re al-time counter operates (rc1pwr bit = 1). v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 661 of 1817 sep 19, 2011 (3) real-time counter control register 2 (rc1cc2) the rc1cc2 register is an 8-bit regi ster that controls the alarm interr upt function and waiting of counters. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. wale does not generate interrupt upon alarm match. generates interrupt upon alarm match. wale 0 1 alarm interrupt (intrtc1) operation control rc1cc2 0000 0 rwst rwait 654321 counter operating counting up of second to year counters stopped (reading and writing of counter values enabled) rwst 0 1 real-time counter wait state this is a status flag indicating whether the rwait bit setting is valid. read or write counter values after confirming that the rwst bit is 1. sets counter operation. stops count operation of second to year counters. (counter value read/write mode) rwait 0 1 real-time counter wait control this bit controls the operation of the counters. be sure to write 1 to this bit when reading or writing counter values. if the rc1subc register overflows while the rwait bit is 1, the overflow information is retained internally and the rc1sec register is counted up after two clocks or less (2 32.768 khz) after 0 is written to the rwait bit. however, if the second counter value is rewritten while the rwait bit is 1, the retained overflow information is discarded. 0 7 after reset: 00h r/w address: fffffadfh cautions 1 . see 12.4.5 changing intrtc1 interrupt setti ng during real-time counter operation when rewriting the wale bit while the real-t ime counter operates (rc1pwr bit = 1). 2. confirm that the rwst bit is set to 1 when reading or writing each counter value. 3. the rwst bit does not become 0 while each counter is being written, even if the rwait bit is set to 0. it becomes 0 when writing to each counter is completed. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 662 of 1817 sep 19, 2011 (4) real-time counter control register 3 (rc1cc3) the rc1cc3 register is an 8-bit register that cont rols the interval interrupt function and rtcdiv pin. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. rinte does not generate interval interrupt. generates interval interrupt. rinte 0 1 interval interrupt (intrtc2) control rc1cc3 cloe2 ckdiv 00 ict2 ict1 ict0 654321 disables rtcdiv pin output. enables rtcdiv pin output. cloe2 0 1 rtcdiv pin output control outputs 512 hz (1.95 ms) from rtcdiv pin. outputs 16.384 khz (0.061 ms) from rtcdiv pin. ckdiv 0 1 rtcdiv pin output frequency selection 0 7 after reset: 00h r/w address: fffffae0h 2 6 /f xt (1.953125 ms) 2 7 /f xt (3.90625 ms) 2 8 /f xt (7.8125 ms) 2 9 /f xt (15.625 ms) 2 10 /f xt (31.25 ms) 2 11 /f xt (62.5 ms) 2 12 /f xt (125 ms) ict2 0 0 0 0 1 1 1 interval interrupt (intrtc2) selection ict1 0 0 1 1 0 0 1 ict0 0 1 0 1 0 1 cautions 1 . see 12.4.7 changing intrtc2 interrupt setti ng during real-time counter operation when rewriting the rinte bit during real-time counter operation (rc1pwr bit = 1). 2. the rtcdiv output operates as follows wh en the cloe2 bit setting is changed. ? when changed from 0 to 1: a pulse set by t he ckdiv bit is output after two clocks or less (2 32.768khz). ? when changed from 1 to 0: output of t he rtcdiv output is stopped after two clocks or less (fixed to low level, 2 32.768khz)). 3. see 12.4.7 changing intrtc2 interrupt setti ng during real-time counter operation when rewriting the ict2 to ict0 bits while the real-time counter operates (rc1pwr bit = 1). v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 663 of 1817 sep 19, 2011 (5) sub-count register (rc1subc) the rc1subc register is a 16-bit regi ster that counts the reference time of 1 second of the real-time counter. it takes a value of 0000h to 7fffh and counts one second with a cl ock of 32.768 khz. this register is read-only, in 16-bit units. reset sets this register to 0000h. cautions 1 when a correction is made by using the rc1subu register, the value may become 8000h or more. 2. this register is also cleared by writing to the second count register. 3. the value read from this register is not gu aranteed if it is read during operation, because a changing value is read. rc1subc 12 1 08 6 42 after reset: 0000h r address: fffffad0h 14 0 1 3 11 9 7 53 1 5 1 (6) second count register (rc1sec) the rc1sec register is an 8-bit register that takes a valu e of 0 to 59 (decimal) and indicates the count value of seconds. it counts up when the sub-counter overflows. when data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after one period. this register can be read or written in 8-bit units. reset sets this register to 00h. caution setting the rc1sec register to va lues other than 00 to 59 is prohibited. remark see 12.4.1 initial settings , 12.4.2 rewriting each counter dur ing real-time counter operation , and 12.4.3 reading each counter duri ng real-time counter operation when reading or writing the rc1sec register. 0 rc1sec after reset: 00h r/w address: fffffad2h v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 664 of 1817 sep 19, 2011 (7) minute count register (rc1min) the rc1min register is an 8-bit register that takes a value of 0 to 59 (decim al) and indicates the count value of minutes. it counts up when the second counter overflows. when data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. this register can be read or written 8-bit units. reset sets this register to 00h. caution setting a value other than 00 to 59 to the rc1min register is prohibited. remark see 12.4.1 initial settings , 12.4.2 rewriting each counter dur ing real-time counter operation , and 12.4.3 reading each counter duri ng real-time counter operation when reading or writing the rc1min register. 0 rc1min after reset: 00h r/w address: fffffad3h (8) hour count register (rc1hour) the rc1hour register is an 8-bit register that takes a value of 0 to 23 or 1 to 12 (decimal) and indicates the count value of hours. it counts up when the minute counter overflows. when data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. this register can be read or written 8-bit units. reset sets this register to 12h. however, the value of this register is 00h if the ampm bit is set to 1 after reset. cautions 1. bit 5 of the rc1hour re gister indicates a.m. (0) or p.m. (1) if ampm = 0 (if the 12-hour system is selected). 2. setting a value other than 01 to 12, 21 to 32 (ampm bit= 0), or 00 to 23 (ampm bit = 1) to the rc1hour register is prohibited. remark see 12.4.1 initial settings , 12.4.2 rewriting each counter dur ing real-time counter operation , and 12.4.3 reading each counter duri ng real-time counter operation when reading or writing the rc1hour register. 00 rc1hour after reset: 12h r/w address: fffffad4h v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 665 of 1817 sep 19, 2011 table 12-3 shows the relationship among the ampm bit setting value, rc1hour register value, and time. table 12-3. time digit display 12-hour display (ampm bit = 0) 24-hour display (ampm bit = 1) time rc1hour register value time rc1hour register value 0:00 a.m. 12 h 0:00 00h 1:00 a.m. 01 h 1:00 01 h 2:00 a.m. 02 h 2:00 02 h 3:00 a.m. 03 h 3:00 03 h 4:00 a.m. 04 h 4:00 04 h 5:00 a.m. 05 h 5:00 05 h 6:00 a.m. 06 h 6:00 06 h 7:00 a.m. 07 h 7:00 07 h 8:00 a.m. 08 h 8:00 08 h 9:00 a.m. 09 h 9:00 09 h 10:00 a.m. 10 h 10:00 10 h 11:00 a.m. 11 h 11:00 11 h 0:00 p.m. 32 h 12:00 12 h 1:00 p.m. 21 h 13:00 13 h 2:00 p.m. 22 h 14:00 14 h 3 :00 p.m. 23 h 15:00 15 h 4:00 p.m. 24 h 16:00 16 h 5:00 p.m. 25 h 17:00 17 h 6:00 p.m. 26 h 18:00 18 h 7:00 p.m. 27 h 19:00 19 h 8:00 p.m. 28 h 20:00 20 h 9:00 p.m. 29 h 21:00 21 h 10:00 p.m. 30 h 22:00 22 h 11:00 p.m. 31 h 23:00 23 h the rc1hour register value is displayed in 12 hour-format if the ampm bit is 0 and in 24-hour format when the ampm bit is 1. in 12-hour display, a.m. or p.m. is indicated by t he fifth bit of rchour: 0 indicating before noon (a.m.) and 1 indicating noon or afternoon (p.m.). v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 666 of 1817 sep 19, 2011 (9) day count register (rc1day) the rc1day register is an 8-bit register that takes a valu e of 1 to 31 (decimal) and indicates the count value of days. it counts up when the hour counter overflows. this counter counts as follows. ? 01 to 31 (january, march, may, july, august, october, december) ? 01 to 30 (april, june, september, november) ? 01 to 29 (february in leap year) ? 01 to 28 (february in normal year) when data is written to this register, it is written to a bu ffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 31 to this register in bcd code. this register can be read or written in 8-bit units. reset sets this register to 01h. caution setting a value other than 01 to 31 to the rc1day register is prohibited. setting a value outside the above-mentioned count range, such as ?february 30? is also prohibited. remark see 12.4.1 initial settings , 12.4.2 rewriting each counter dur ing real-time counter operation , and 12.4.3 reading each counter duri ng real-time counter operation when reading or writing the rc1day register. 00 rc1day after reset: 01h r/w address: fffffad6h v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 667 of 1817 sep 19, 2011 (11) day-of-week count register (rc1week) the rc1week register is an 8-bit regist er that takes a value of 0 to 6 ( decimal) and indicates the day-of-week count value. it counts up in synchronization with the day counter. when data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 06 to this register in bcd code. this register can be read or written in 8-bit units. reset sets this register to 00h. 00000 rc1week after reset: 00h r/w address: fffffad5h cautions 1. setting a value other than 00 to 06 to the rc1week register is prohibited. 2. values corresponding to the month count register and day count register are not automatically stored to the day-of-week register. be sure to set as follows after reset. day of week rc1week sunday 00h monday 01h tuesday 02h wednesday 03h thursday 04h friday 05h saturday 06h remark see 12.4.1 initial settings , 12.4.2 rewriting each counter dur ing real-time counter operation , and 12.4.3 reading each counter duri ng real-time counter operation when reading or writing the rc1week register. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 668 of 1817 sep 19, 2011 (11) month count register (rc1month) the rc1month register is an 8-bit regist er that takes a value of 1 to 12 ( decimal) and indicates the count value of months. it counts up when the day counter overflows. when data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 01 to 12 to this register in bcd code. this register can be read or written in 8-bit units. reset sets this register to 01h. caution setting a value other than 01 to 12 to the rc1month register is prohibited. remark see 12.4.1 initial settings , 12.4.2 rewriting each counter dur ing real-time counter operation , and 12.4.3 reading each counter duri ng real-time counter operation when reading or writing the rc1month register. 000 rc1month after reset: 01h r/w address: fffffad7h (12) year count re gister (rc1year) the rc1year register is an 8-bit register that takes a va lue of 0 to 99 (decimal) and indicates the count value of years. it counts up when the month counter overflows. values 00, 04, 08, ?, 92, and 96 indicate a leap year. when data is written to this register , it is written to a buffer and then to the counter up to 2 clocks (2 32.768 khz) later. set a decimal value of 00 to 99 to this register in bcd code. this register can be read or written in 8-bit units. reset sets this register to 00h. caution setting a value other than 00 to 99 to the rc1year register is prohibited. remark see 12.4.1 initial settings , 12.4.2 rewriting each counter dur ing real-time counter operation , and 12.4.3 reading each counter duri ng real-time counter operation when reading or writing the rc1year register. rc1year after reset: 00h r/w address: fffffad8h v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 669 of 1817 sep 19, 2011 (13) watch error correction register (rc1subu) the rc1subu register is an 8-bit re gister that can be used to correct the watch with high accuracy when the watch is early or late, by changing the value (referenc e value: 7fffh) overflowing from the sub-count register (rsubc) to the second counter register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. remarks 1. the rc1subu register can be rewritten only when the real-time counter is set to its initial values. be sure to see 12.4.1 initial settings . 2. see 12.4.9 watch error correction example of real-time counter for details of watch error correction. dev corrects watch errors when rc1sec (second counter) is at 00, 20, or 40 seconds (every 20 seconds). corrects watch errors when rc1sec (second counter) is at 00 seconds (every 60 seconds). dev 0 1 setting of watch error correction timing rc1subu f6 f5 f4 f3 f2 f1 f0 654321 increments the rc1subc count value by the value set using the f5 to f0 bits (positive correction). expression for calculating increment value: (setting value of f5 to f0 bits ? 1) 2 decrements the rc1subc count value by the value set using the f5 to f0 bits (negative correction). expression for calculating decrement value: (inverted value of setting value of f5 to f0 bits + 1) 2 f6 0 1 setting of watch error correction value if the f6 to f0 bit values are {1/0, 0, 0, 0, 0, 0, 1/0}, watch error correction is not performed. 0 7 after reset: 00h r/w address: fffffad9h v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 670 of 1817 sep 19, 2011 (14) alarm minute setting register (rc1alm) the rc1alm register is an 8-bit register that is used to set minutes of alarm. this register can be read or written in 8-bit units. reset sets this register to 00h. caution set a decimal value of 00 to 59 to this register in bcd code. if a value outside the range is set, the alarm is not detected. 0 rc1alm after reset: 00h r/w address: fffffadah (15) alarm hour setting register (rc1alh) the rc1alh register is an 8-bit register that is used to set hours of alarm. this register can be read or written in 8-bit units. reset sets this register to 12h. cautions 1. set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. if a value outside the range is set, the alarm is not detected. 2. bit 5 of the rc1alh register indicates a.m. (0) or p.m. (1) if the ampm bit = 0 (12-hour system) is selected. 00 rc1alh after reset: 12h r/w address: fffffadbh v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 671 of 1817 sep 19, 2011 (16) alarm day-of-week setting register (rc1alw) the rc1alw register is an 8-bit register that is used to set the day-of-week of the alarm. this register can be read or written in 8-bit units. reset sets this register to 00h. caution see 12.4.5 changing intrtc1 interrupt se tting during clock operation when rewriting the rc1alw register while the real-time counter operates (rc1pwr bit = 1). 0 rc1alw6 rc1alw5 rc1alw4 rc1alw3 rc1alw2 rc1alw1 rc1alw0 saturday friday thursday wednesday tuesday monday sunday rc1alw after reset: 00h r/w address: fffffadch does not generate alarm interrupt if rc1week = 06h (saturday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 06h (saturday). rc1alw6 0 1 alarm interrupt day-of-week bit 6 does not generate alarm interrupt if rc1week = 05h (friday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 05h (friday). rc1alw5 0 1 alarm interrupt day-of-week bit 5 does not generate alarm interrupt if rc1week = 04h ( thursday ). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 04h (thursday). rc1alw4 0 1 alarm interrupt day-of-week bit 4 does not generate alarm interrupt if rc1week = 03h (wednesday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 03h (wednesday). rc1alw3 0 1 alarm interrupt day-of-week bit 3 does not generate alarm interrupt if rc1week = 02h ( tues day). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 02h (tuesday). rc1alw2 0 1 alarm interrupt day-of-week bit 2 does not generate alarm interrupt if rc1week = 01h (monday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 01h ( monday ). rc1alw1 0 1 alarm interrupt day-of-week bit 1 does not generate alarm interrupt if rc1week = 00h (sunday). generates an alarm interrupt if the time specified by using the rc1alm and rc1alh registers is reached while rc1week is set to 00h (sunday). rc1alw0 0 1 alarm interrupt day-of-week bit 0 v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 672 of 1817 sep 19, 2011 (a) alarm interrupt setting examples (rc1 alm, rc1alh, and rc1alw setting examples) tables 12-4 and 12-5 show setting examples if sunday is rc1week = 00, monday is rc1week = 01, tuesday is rc1week = 02, , and saturday is rc1week = 06. table 12-4. alarm setting example if ampm = 0 (rc1hour register 12-hour display) register alarm setting time rc1alw rc1alh rc1alm sunday, 7:00 a.m. 01h 07h 00h sunday/monday, 00:15 p.m. 03h 32h 15h monday/tuesday/friday, 5:30 p.m. 26h 25h 30h everyday, 10:45 p.m. 7fh 30h 45h table 12-5. alarm setting example if ampm = 1 (rc1hour register 24-hour display) register alarm setting time rc1alw rc1alh rc1alm sunday, 7:00 01h 07h 00h sunday/monday, 12:15 03h 12h 15h monday/tuesday/friday, 17:30 26h 17h 30h everyday, 22:45 7fh 22h 45h (17) prescaler mode register 0 (prsm0) the prsm0 register is an 8-bit regist er that controls the generation of the real time counter count clock (f brg ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled enabled bgce0 0 1 main clock operation enable f x f x /2 f x /4 f x /8 5 mhz 200 ns 400 ns 800 ns 1.6 s 4 mhz 250 ns 500 ns 1 s 2 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 selection of real time counter source clock(f bgcs ) after reset : 00h r/w address : fffff8b0h < > cautions 1. do not change the values of the bg cs00 and bgcs01 bits during real time counteroperation. 2. set the prsm0 register befo re setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock frequency that is used so as to obtain an f brg frequency of 32.768 khz. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 673 of 1817 sep 19, 2011 (18) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset sets this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 re gister during real ti me counter operation. 2. set the prscm0 register before setting the prsm0.bgce0 bit to 1. 3. set the prsm0 and prscm0 registers accordi ng to the main clock frequency that is used so as to obtain an f brg frequency of 32.768 khz. the calculation for f brg is shown below. f brg = f bgcs /2n remark f bgcs : watch timer source clock set by the prsm0 register n: set value of the prscm0 register = 1 to 256 however, n = 256 when the prscm0 register is set to 00h. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 674 of 1817 sep 19, 2011 12.4 operation 12.4.1 initial settings the initial settings are set when operating the watch f unction and performing a fixed-cycle interrupt operation. figure 12-2. initial setting procedure setting ampm and ct2 to ct0 rc1cc0.rc1pwr bit = 0 start intrtc intrrupt generated? stops counter operation. selects 12-hour system or 24-hour system and interrupt (intrtc0). rc1cc0.rc1pwr bit = 1 enables real-time counter (rtc) internal clock operation. sets each count register. setting rc1subu sets watch error correction. setting rc1cks selects real-time counter (rtc) operation clock. no yes clearing interrupt if flag clears interrupt request flag (rtc0if) clearing interrupt mk flag clears interrupt mask flag (rtc0mk) rc1cc1.rtce bit = 1 starts counter operation. reading counter setting rc1sec (clearing rc1subc) setting rc1min setting rc1hour setting rc1week setting rc1day setting rc1month setting rc1year v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 675 of 1817 sep 19, 2011 12.4.2 rewriting each counter du ring real-time counter operation set as follows when rewriting each counter (rc1 sec, rc1min, rc1hour, rc1week, rc1day, rc1month, rc1year) during real-time counter operation (rc1pwr = 1). figure 12-3. rewriting each counter during real-time counter operation start rc1cc2.rwait bit = 1 stops rc1sec to rc1year counters. counter value write/read mode setting ampm writing rc1sec writing rc1min writing rc1hour writing rc1week writing rc1day writing rc1month setting rc1year writes to each count register. selects watch counter display method. rc1cc2.rwait bit = 0 sets rc1sec to rc1year counter operation. rc1cc2.rwst bit = 0? no yes checks counter wait status. checks whether previous writing to rc1sec to rc1year counters is completed. end rc1cc2.rwst bit = 1? note no yes note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of operations for setting rwait to 1 to clearing rwait to 0 within 1 second. if rwait = 1 is set, the operation of rc1sec to rc1year is stopped. if a carry occurs from rc1subc while rwait = 1, one carry can be inte rnally retained. however, if two or more carries occur, the number of carries cannot be retained. remark rc1sec, rc1min, rc1hour, rc1week, rc1day, rc1month, and rc1year may berewrite in any sequence. all the registers do not have to be set and only some registers may be read. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 676 of 1817 sep 19, 2011 12.4.3 reading each counter durin g real-time counter operation set as follows when reading each counter (rc1sec, rc1min, rc1hour, rc1w eek, rc1day, rc1month, rc1year) during real-time counter operation (rc1pwr = 1, rtce = 1). figure 12-4. reading each counter during real-time counter operation start rc1cc2.rwait bit = 1 stops rc1sec to rc1year counters. counter value write/read mode rc1cc2.rwait bit = 0 sets rc1sec to rc1year counter operation. rc1cc2.rwst bit = 0? no yes checks counter wait status. checks whether previous writing to rc1sec to rc1year is completed. end rc1cc2.rwst bit = 1? note no yes reading rc1sec reading rc1min reading rc1hour reading rc1week reading rc1day reading rc1month setting rc1year reads each count register. note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of operations for setting rwait to 1 to clearing rwait to 0 within 1 second. if rwait = 1 is set, the operation of rc1sec to rc1year is stopped. if a carry occurs from rc1subc while rwait = 1, one carry can be inte rnally retained. however, if two or more carries occur, the number of carries cannot be retained. remark rc1sec, rc1min, rc1hour, rc1week, rc1da y, rc1month, and rc1year may be read in any sequence. all the registers do not have to be set and only some registers may be read. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 677 of 1817 sep 19, 2011 12.4.4 changing intrtc0 interrupt setti ng during real-time counter operation if the setting of the intrtc0 interrupt (fixed-cycle interr upt) signal is changed while the real-time counter clock operates (pc1pwr = 1, rtce =1), the intrct0 interrupt waveform may include whiskers and unintended signals may be output. set as follows when changing the setting of the intrtc0 interrupt signal during real-time counter operation (rc1pwr = 1), in order to mask the whiskers. figure 12-5. changing intrtc0 interrupt setting during real-time counter operation start setting rtc0mk bit masks intrtc0 interrupt signal. setting rc1cc1.ct2 to rc1cc1.ct0 changes intrtc0 interrupt signal setting. end clearing rtc0if flag clears interrupt request flag. clearing rtc0mk flag unmasks intrtc0 interrupt signal. remark see 25.3.4 interrupt control register (xxicn) for details of the rtc0if and rtc0mk bits. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 678 of 1817 sep 19, 2011 12.4.5 changing intrtc1 interrupt setti ng during real-time counter operation if the setting of the intrtc1 interrupt (alarm interrupt) signal is changed while the real-time counter operates (rc1pwr = 1, rtce = 1), the intrct1 interrupt waveform may include whiskers and unintended signals may be output. set as follows when changing the setting of the intrtc1 interr upt signal during real-time count er operation (pc1pwr = 1, rtce = 1), in order to mask the whiskers. figure 12-6. changing intrtc1 interrupt setting during real-time counter operation start setting rtc1mk bit masks interrupt signal (intrtc1). rc1cc2.wale bit = 0 disables alarm interrupt. rc1cc2.wale bit = 1 enables alarm interrupt. end clearing rtc1if flag clears interrupt pending bit. setting rc1alm setting rc1alh setting rc1alw sets alarm minute register. sets alarm hour register sets alarm day-of-week register clearing rtc1mk flag unmasks interrupt signal (intrtc1). remark see 25.3.4 interrupt control register (xxicn) for details of the rtc1if and rtc1mk bits. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 679 of 1817 sep 19, 2011 12.4.6 initial intrtc2 interrupt settings set as follows to set the intrtc 1 interrupt (interval interrupt). figure 12-7. intrtc2 interrupt setting start rc1cc0.rc1pwr bit = 1 enables counter operation. setting rc1cc3.ict2 to rc1cc3.ict0 bits <1> selects intrtc2 (interval) interrupt interval. end rc1cc3.rinte bit = 1 <2> enables intrtc2 (interval) interrupt. caution set <1> and <2> simultaneously or set <1> first. unintended waveform interrupts may occur if <2> is set first. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 680 of 1817 sep 19, 2011 12.4.7 changing intrtc2 interrupt setti ng during real-time counter operation if the setting of the intrtc2 interrupt (interval interrupt) is changed while the real -time counter clock operates (pc1pwr = 1, rtce = 1), the intrct2 interrupt waveform may include whiskers and unintended signals may be output. set as follows when changing the setting of the intrtc2 interr upt signal during real-time count er operation (pc1pwr = 1, rtce = 1), in order to mask the whiskers. figure 12-8. changing intrtc2 interrupt setting during real-time counter operation start setting rtc2mk bit masks interrupt signal (intrtc2). setting rc1cc3.ict2 to rc1cc3.ict0 bits selects intrtc2 (interval) interrupt interval. end rc1cc3.rinte bit = 1 enables intrtc2 (interval) interrupt. clearing rtc2if flag clears interrupt pending bit. clearing rtc2mk flag unmasks interrupt signal (intrtc2). remark see 25.3.4 interrupt control register (xxicn) for details of the rtc2if and rtc2mk bits. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 681 of 1817 sep 19, 2011 12.4.8 initializing real-time counter the procedure for initializing the real-time counter is shown below. figure 12-9. initializing real-time counter start setting rtcnmk bit masks interrupt signal (intrtcn) end rc1cc0.rc1pwr bit = 0 initializes real-time counter (rtc). rtcdiv interrupt disable processing rtc1hz interrupt disable processing rtccl interrupt disable processing rc1cc3.cloe2 bit = 0 rc1cc1.cloe1 bit = 0 rc1cc1.cloe0 bit = 0 clearing rtcnif flag clears interrupt request bit. clearing rtcnmk flag unmasks interrupt signal (intrtcn). remarks 1. see 25.3.4 interrupt control register (xxicn) for details of the rtcnif and rtcnmk bits. 2. n = 0 to 2 v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 682 of 1817 sep 19, 2011 12.4.9 watch error correction example of real-time counter the watch error correction function corrects deviation in the oscillation frequency of a resonator connected to the v850es/jx3-e. deviation, here, refers to steady-state deviation, which is deviation in the frequency when the resonator is designed. next, the timing chart when an error has occurred in the input clock intended to be 32.768 khz but a 32.7681 khz resonator has been connected when designing the system, and the rc1subc and rc1sec count operations to correct the error are shown below. figure 12-10. watch error correction example rtcclk (32.768 khz) rc1subc watch count (32.768 khz) watch count (32.7681 khz /no error correction ) watch count (32.7681 khz /error correction (dev bit = 0, f6 bit = 0, f5 to f0 bit = 000010)) rc1sec 01 01 00 00 7fffh 0000h 7fffh 0000h 7fffh 0000h 7fffh 7fffh 0000h 0000h 20 20 19 19 rtcclk (32.7681 khz) rc1subc rc1sec 7fffh 7fffh 0000h 0000h 0000h 7fffh 7fffh 0000h 7fffh 8000h 8001h 8000h 8001h 0000h 0000h rtcclk (32.7681 khz) rc1subc rc1sec 20 seconds note 3 00 20 2 count numbers are added. 2 count numbers are added. 20 seconds note 1 19.99994 seconds note 2 01 19 7fffh 0000h 0000h 7fffh 7fffh 7fffh 0000h notes 1. the rc1sec counter counts 20 seconds every 32, 768 cycles (0000h to 7 fffh) of the 32.768 khz clock. 2. when 32,768 cycles (0000h to 7 fffh) of the 32.7681 khz clock are input, the time counted by the rc1sec counter is calculated as follows: 32,768/3,268.1 ? 0.999997 seconds if this counting continues 20 times, the time is calculated as follows: (32,768/32,768.1) x 20 ? 19.99994 seconds, which causes an error of 0.00006 seconds. 3. to precisely count 20 seconds by using a 32.7681 khz clock, clear the dev and f6 bits to 0 and set the f5 to f0 bits to 2h (000010 b) in the rc1subu register. as a result, two additional cycles are counted every 20 seconds (when the rc1sec counter count is 00, 20, and 40 seconds), so that the number of cycles counted at these points is not 32,768, but 32,770 (0000h to 8001h), which is exactly 20 seconds. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 683 of 1817 sep 19, 2011 as shown in figure 12-10, the watch can be accurately counted by incrementing the rc1subc count value, if a positive error faster than 32.768 khz occurs at the resonator. similarly, if a ne gative error slower than 32.768 khz occurs at the resonator, the watch can be accurately c ounted by decrementing the rc1subc count value. the rc1subc correction value is determined by using the rc1subu.f6 to rc1subu.f0 bits. the f6 bit is used to determine whether to increment or de crement rc1subc and the f5 to f0 bits to determine the rc1subc value. (1) incrementing the rc1subc count value the rc1subc count value is incremented by the value set using the f5 to f0 bits, by setting the f6 bit to 0. expression for calculating the increment value: (f5 to f0 bit value ? 1) 2 [example of incrementing the rc1subc count value: f6 bit = 0] if 15h (010101b) is set to the f5 to f0 bits (15h ? 1) 2 = 40 (increments the rc1subc count value by 40) rc1subc count value = 32,768 + 40 = 32,808 (2) decrementing the rc1subc count value the rc1subc count value is decremented by an inverted value of the value set using the f5 to f0 bits, by setting the f6 bit to 1. expression for calculating the decrement value: (inverted value of f5 to f0 bit value + 1) 2 [example of decrementing the rc1subc count value: f6 bit = 1] if 15h (010101b) is set to the f5 to f0 bits inverted data of 15h (010101b) = 2ah (101010b) (2ah + 1) 2 = 86 (decrements the rc1subc count value by 86) rc1subc count value = 32,768 ? 86 = 32,682 v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 684 of 1817 sep 19, 2011 (3) dev bit the dev bit determines when the setting by the f6 to f0 bits is enabled. the value set by the f6 to f0 bits is reflected upon the ne xt timing, but not to the rc1subc count value every time. table 12-6. dev bit setting dev bit value timing of reflecting value to rc1subc 0 when rc1sec is 00, 20, or 40 seconds. 1 when rc1sec is 00 seconds. [example when 0010101b is set to f6 to f0 bits] ? if the dev bit is 0 the rc1subc count value is 32,808 at 00, 20, or 40 seconds. otherwise, it is 32,768. ? if dev bit is 1 the rc1subc count value is 32,808 at 00 seconds. otherwise, it is 32,768. as described above, the rc1subc count value is correct ed every 20 seconds or 60 seconds, instead of every second, in order to match the rc1subc count value with the deviation width of the resonator. the range in which the resonator frequency can be actually corrected is shown below. ? if the dev bit is 0: 32.76180000 khz to 32.77420000 khz ? if the dev bit is 1: 32.76593333 khz to 32.77006667 khz the range in which the frequency can be corrected when the dev bit is 0 is three times wider than when the dev bit is 1. however, the accuracy of setting the frequency when the dev bit is 1 is three times that when the dev bit is 0. tables 12-7 and 12-8 show the setting values of the dev, and f6 to f0 bits, and the corresponding frequencies that can be corrected. v850es/jh3-e, v850es/jj3-e chapter 12 real-time counter r01uh0290ej0300 rev.3.00 page 685 of 1817 sep 19, 2011 table 12-7. range of frequencies tha t can be corrected when dev bit = 0 f6 f5 to f0 rc1subc correction value frequency of connected clock (including steady-state deviation) 0 000000 no correction ? 0 000001 no correction ? 0 000010 increments rc1subc count value by 2 once every 20 seconds 32.76810000 khz 0 000011 increments rc1subc count value by 4 once every 20 seconds 32.76820000 khz 0 000100 increments rc1subc count value by 6 once every 20 seconds 32.76830000 khz . . . . 0 111011 increments rc1subc count value by 120 once every 20 seconds 32.77400000 khz 0 111110 increments rc1subc count value by 122 once every 20 seconds 32.77410000 khz 0 111111 increments rc1subc count value by 124 once every 20 seconds 32.77420000 khz (upper limit) 1 000000 no correction ? 1 000001 no correction ? 1 000010 decrements rc1subc count value by 124 once every 20 seconds 32.76180000 khz (lower limit) 1 000011 decrements rc1subc count value by 122 once every 20 seconds 32.76190000 khz 1 000100 decrements rc1subc count value by 120 once every 20 seconds 32.76200000 khz . . . . 1 11011 decrements rc1subc count value by 6 once every 20 seconds 32.76770000 khz 1 11110 decrements rc1subc count value by 4 once every 20 seconds 32.76780000 khz 1 11111 decrements rc1subc count value by 2 once every 20 seconds 32.76790000 khz table 12-8. range of frequencies tha t can be corrected when dev bit = 1 f6 f5 to f0 rc1subc correction value frequency of connected clock (including steady-state deviation) 0 000000 no correction ? 0 000001 no correction ? 0 000010 increments rc1subc count value by 2 once every 60 seconds 32.76803333 khz 0 000011 increments rc1subc count value by 4 once every 60 seconds 32.76806667 khz 0 000100 increments rc1subc count value by 6 once every 60 seconds 32.76810000 khz . . . . 0 111011 increments rc1subc count value by 120 once every 60 seconds 32.77000000 khz 0 111110 increments rc1subc count value by 122 once every 60 seconds 32.77003333 khz 0 111111 increments rc1subc count value by 124 once every 60 seconds 32.77006667 khz (upper limit) 1 000000 no correction ? 1 000001 no correction ? 1 000010 decrements rc1subc count value by 124 once every 60 seconds 32.76593333 khz (lower limit) 1 000011 decrements rc1subc count value by 122 once every 60 seconds 32.76596667 khz 1 000100 decrements rc1subc count value by 120 once every 60 seconds 32.76600000 khz . . . . 1 11011 decrements rc1subc count value by 6 once every 60 seconds 32.76790000 khz 1 11110 decrements rc1subc count value by 4 once every 60 seconds 32.76793333 khz 1 11111 decrements rc1subc count value by 2 once every 60 seconds 32.76796667 khz v850es/jh3-e, v850es/jj3-e chapter 13 functions of watchdog timer 2 r01uh0290ej0300 rev.3.00 page 686 of 1817 sep 19, 2011 chapter 13 functions of watchdog timer 2 13.1 functions watchdog timer 2 has the following functions. ? default-start watchdog timer note 1 reset mode: reset operation upon overflow of wa tchdog timer 2 (generation of wdt2res signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note 2 ? input from main clock, internal oscillation cl ock, and subclock selectable as the source clock notes 1. watchdog timer 2 automatically starts in the reset mode following reset release. when watchdog timer 2 is not used, ei ther stop its operation before reset is executed via this function, or clear watchdog timer 2 once and stop it within the next interval time. also, write to the wdtm2 register for verification purposes once, even if the default settings (reset mode, interval time: f r /2 19 ) do not need to be changed. 2. for the non-maskable interrupt servicing due to a no n-maskable interrupt request signal (intwdt2), see 25.2.2 (2) from intwdt2 signal . v850es/jh3-e, v850es/jj3-e chapter 13 functions of watchdog timer 2 r01uh0290ej0300 rev.3.00 page 687 of 1817 sep 19, 2011 13.2 configuration the following shows the block diagram of watchdog timer 2. figure 13-1. block diag ram of watchdog timer 2 f xx /2 10 clock input controller output controller wdt2res (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 19 to f xx /2 26 , f xt /2 9 to f xt /2 16 , f r /2 12 to f r /2 19 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear f r /2 3 remark f xx : main clock frequency f xt : subclock frequency f r : internal oscillation clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdtres2: watchdog timer 2 reset signal watchdog timer 2 includes the following hardware. table 13-1. configuration of watchdog timer 2 item configuration control registers watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) v850es/jh3-e, v850es/jj3-e chapter 13 functions of watchdog timer 2 r01uh0290ej0300 rev.3.00 page 688 of 1817 sep 19, 2011 13.3 registers (1) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and operation clock of watchdog timer 2. this register can be read or written in 8-bit units. th is register can be read any number of times, but it can be written only once following reset release. reset sets this register to 67h. caution accessing the wdtm2 register is prohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates on the subclock and the main clock oscillation is stopped ? when the cpu operates on the internal oscillation clock 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2 signal) reset mode (generation of wdt2res signal) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. for details of the wdcs20 to w dcs24 bits, see table 13-2 watchdog timer 2 clock selection. 2. although watchdog timer 2 can be stopped just by stopping operation of the internal oscillator, clear the wdtm2 register to 00h to securely stop the timer (to avoid selection of the main clock or subclock due to an erroneous write operation). 3. if the wdtm2 register is rewritten twice afte r reset, an overflow signal is forcibly generated and the counter is reset. 4. to intentionally generate an overflow signa l, write data to the wdtm2 register twice, or write a value other than ?ach? to the wdte register once. however, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is not generated even if data is written to the wdtm2 register twice, or a value other than ?ach? is written to the wdte register once. 5. to stop the operation of watchdog timer 2, set the rcm.rstop bit to 1 (to stop the internal oscillator) and write 00h in the wdtm 2 register. if the rcm.rstop bit cannot be set to 1, set the wdcs23 bit to 1 (2 n /f xx is selected and the clock can be stopped in the idle1, idlw2, sub-idle, and subclock operation modes). v850es/jh3-e, v850es/jj3-e chapter 13 functions of watchdog timer 2 r01uh0290ej0300 rev.3.00 page 689 of 1817 sep 19, 2011 table 13-2. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs 20 selected clock 100 khz (min.) 220 khz (typ.) 400 khz (max.) 0 0 0 0 0 2 12 /f r 41.0 ms 18.6 ms 10.2 ms 0 0 0 0 1 2 13 /f r 81.9 ms 37.2 ms 20.5 ms 0 0 0 1 0 2 14 /f r 163.8 ms 74.5 ms 41.0 ms 0 0 0 1 1 2 15 /f r 327.7 ms 148.9 ms 81.9 ms 0 0 1 0 0 2 16 /f r 655.4 ms 297.9 ms 163.8 ms 0 0 1 0 1 2 17 /f r 1,310.7 ms 595.8 ms 327.7 ms 0 0 1 1 0 2 18 /f r 2,621.4 ms 1191.6 ms 655.4 ms 0 0 1 1 1 2 19 /f r (default value) 5,242.9 ms 2383.1 ms 1,310.7 ms f xx = 50 mhz f xx = 48 mhz f xx = 32 mhz 0 1 0 0 0 2 19 /f xx 10.5 ms 10.9 ms 16.4 ms 0 1 0 0 1 2 20 /f xx 21.0 ms 21.8 ms 32.8 ms 0 1 0 1 0 2 21 /f xx 41.9 ms 43.7 ms 65.5 ms 0 1 0 1 1 2 22 /f xx 83.9 ms 87.4 ms 131.1 ms 0 1 1 0 0 2 23 /f xx 167.8 ms 174.8 ms 262.1 ms 0 1 1 0 1 2 24 /f xx 335.5 ms 349.5 ms 524.3 ms 0 1 1 1 0 2 25 /f xx 671.1 ms 699.1 ms 1048.6 ms 0 1 1 1 1 2 26 /f xx 1342.2 ms 1398.1 ms 2097.2 ms f xt = 32.768 khz 1 0 0 0 2 9 /f xt 15.625 ms 1 0 0 1 2 10 /f xt 31.25 ms 1 0 1 0 2 11 /f xt 62.5 ms 1 0 1 1 2 12 /f xt 125 ms 1 1 0 0 2 13 /f xt 250 ms 1 1 0 1 2 14 /f xt 500 ms 1 1 1 0 2 15 /f xt 1,000 ms 1 1 1 1 2 16 /f xt 2,000 ms v850es/jh3-e, v850es/jj3-e chapter 13 functions of watchdog timer 2 r01uh0290ej0300 rev.3.00 page 690 of 1817 sep 19, 2011 (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cleared and counting restarted by wr iting ?ach? to the wdte register. the wdte register can be read or written in 8-bit units. reset sets this register to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other than ?ach? is writ ten to the wdte register, an overflow signal is forcibly output. 2. when a 1-bit memory mani pulation instruction is executed for the wdte register, an overflow signal is forcibly output. 3. to intentionally generate an overflow signa l, write a value other than ?ach? to the wdte register once, or write data to the wdtm2 register twice. however, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is not generated even if data is written to the wdtm2 register twice, or a value other than ?ach? is written to the wdte register once. 4. the read value of the wdte register is ?9 ah? (which differs from written value ?ach?). 13.4 operation watchdog timer 2 automatically starts in t he reset mode following reset release. the wdtm2 register can be written to only once following rese t using byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm2 register us ing an 8-bit memory manipulation instruction. after this, the operation of watchdog ti mer 2 cannot be stopped. the wdtm2.wdcs24 to wdtm2.wdcs20 bits are used to select the watchdog timer 2 loop det ection time interval. writing ach to the wdte register clear s the counter of watchdog timer 2 and star ts the count operation again. after the count operation has started, write ach to wdte within the loop detection time interval. if the time interval expires without ach being written to the wdte register, a reset signal (wdt2res) or a non- maskable interrupt request signal (intwdt2) is generated , depending on the set values of the wdtm2.wdm21 and wdtm2.wdm20 bits. when the wdtm2.wdm21 bit is set to 1 (reset mode), if a wd t overflow occurs during oscillation stabilization after a reset or standby is released, no internal reset will occur and the cpu clock will switch to the internal oscillation clock. to not use watchdog timer 2, write 00h to the wdtm2 register. for the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 23.2.2 (2) from intwdt2 signal . v850es/jh3-e, v850es/jj3-e chapter 14 real-time output function (rto) r01uh0290ej0300 rev.3.00 page 691 of 1817 sep 19, 2011 chapter 14 real-time output function (rto) 14.1 function the real-time output function tr ansfers the data preset to the rtbl0 and rtbh0 register s to the output latches via hardware and outputs the data to an external device, at the same time as a timer in terrupt occurs. the pins through which the data is output to an external device consti tute a port called the real-time output (rto) port. because signals without jitter can be output by using rto, it is suitable for controlling a stepper motor. one 6-bit real-time output port channel is provided in the v850es/jh3-e and one 8-bit real-time output port channel is provided in the v850es/jj3-e. the real-time output port can be se t to the port mode or real-time output port mode in 1-bit units. v850es/jh3-e, v850es/jj3-e chapter 14 real-time output function (rto) r01uh0290ej0300 rev.3.00 page 692 of 1817 sep 19, 2011 14.2 configuration the block diagram of rto is shown below. figure 14-1. block diagram of rto inttaa0cc0 inttaa5cc0 inttaa4cc0 rtpoe0 rtpeg0 byte0 extr0 4 4 rtp04 to rtp07 rtp00 to rtp03 real-time output buffer register 0h (rtbh0) real-time output latch 0h selector real-time output latch 0l real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) real-time output port mode register 0 (rtpm0) internal bus real-time output buffer register 0l (rtbl0) note note rtpm05 rtpm07 rtpm06 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 4 4 note v850es/jj3-e only rto includes the following hardware. table 14-1. configuration of rto item configuration registers real-time output buffer registers 0l, 0h (rtbl0, rtbh0) control registers real-time output port mode register 0 (rtpm0) real-time output port control register 0 (rtpc0) v850es/jh3-e, v850es/jj3-e chapter 14 real-time output function (rto) r01uh0290ej0300 rev.3.00 page 693 of 1817 sep 19, 2011 (1) real-time output buffer registers 0l, 0h (rtbl0, rtbh0) the rtbl0 and rtbh0 registers are 4-bit re gisters that hold output data in advance. these registers are each mapped to independent addresses in t he peripheral i/o register area. these registers can be read or wr itten in 8-bit or 1-bit units. reset sets these registers to 00h. if an operation mode of 4 bits 1 channel, 2 bits 1 channel, or 4 bits 2 channels is specified (rtpc0.byte0 bit = 0), data can be set individually to the rtbl0 and rtbh0 register s. the data of both thes e registers can be read at once by specifying the address of either of these registers. if an operation mode of 6 bits 1 channel is specified (byte0 bit = 1), 8-bit data can be set to both the rtbl0 and rtbh0 registers by writing the data to ei ther of these registers. moreover, t he data of both these registers can be read at once by specifying the addre ss of either of these registers. table 14-2 shows the operation when the rt bl0 and rtbh0 register s are manipulated. rtbh07 note rtbl0 rtbh0 rtbh06 note rtbh05 rtbh04 rtbl03 rtbl02 rtbl01 rtbl00 after reset: 00h r/w address: rtbl0 fffff6e0h, rtbh0 fffff6e2h note v850es/jj3-e only caution accessing the rtbl0 and rtbh0 regi sters is prohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates on the subclo ck and the main clock oscillation is stopped ? when the cpu operates on the internal oscillation clock table 14-2. operation during manipul ation of rtbl0 and rtbh0 registers operation mode read write note v850es/jh3-e v850es/jj3-e register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl0 rtbh0 rtbl0 invalid rtbl0 4 bits 1 channel, 2 bits 1 channel 4 bits 2 channels rtbh0 rtbh0 rtbl0 rtbh0 invalid rtbl0 rtbh0 rtbl0 rtbh0 rtbl0 6 bits 1 channel 8 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 rtbl0 note after setting the real-time output port, set output data to the rtbl0 and rtbh0 registers by the time a real-time output trigger is generated. v850es/jh3-e, v850es/jj3-e chapter 14 real-time output function (rto) r01uh0290ej0300 rev.3.00 page 694 of 1817 sep 19, 2011 14.3 registers rto is controlled using the following two registers. ? real-time output port mode register 0 (rtpm0) ? real-time output port control register 0 (rtpc0) (1) real-time output port mode register 0 (rtpm0) the rtpm0 register selects t he real-time output port mode or port mode in 1-bit units. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. rtpm07 note rtpm0m 0 1 real-time output disabled real-time output enabled control of real-time output port (m = 0 to 7) rtpm0 rtpm06 note rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 after reset: 00h r/w address: rtpm0 fffff6e4h note v850es/jj3-e only cautions 1. by enabling the real-time output operation (rtpc0.rtpoe0 bit = 1), the bits enabled for real-time output among the rt p00 to rtp07 signals perform real- time output, and the bits set to port mode output 0. 2. if real-time output is disabled (rtpoe0 bit = 0), the real-time output pins (rtp00 to rtp07) all output 0, regardless of the rtpm0 register setting. 3. in order to use this register for th e real-time output pins (rtp00 to rtp07), set these pins as real-time output port pins using the pmc and pfc registers. v850es/jh3-e, v850es/jj3-e chapter 14 real-time output function (rto) r01uh0290ej0300 rev.3.00 page 695 of 1817 sep 19, 2011 (2) real-time output port control register 0 (rtpc0) the rtpc0 register is a register that sets the operat ion mode and output trigger of the real-time output port. the relationship between the operation mode and output trigger of the real-time output port is as shown in table 14-4. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. rtpoe0 disables operation note 1 enables operation rtpoe0 0 1 control of real-time output operation rtpc0 rtpeg0 byte0 extr0 0 0 0 0 falling edge note 2 rising edge valid edge of inttp0cc0 signal 4 bits 1 channel, 2 bits 1 channel (v850es/jh3-e) 4 bits 2 channels (v850es/jj3-e) byte0 0 1 rtpeg0 0 1 specification of channel configuration for real-time output after reset: 00h r/w address: fffff6e5h < > 6 bits 1 channel (v850es/jh3-e) 8 bits 1 channel (v850es/jj3-e) notes 1. when the real-time output operation is disa bled (rtpoe0 bit = 0), all real-time output pins (rtp00 to rtp07) output ?0?. 2. the inttaa0cc0 signal is output for 1 clock of the count clock selected by taa0. caution set the rtpeg0, byte0, and extr0 bits only when th e rtpoe0 bit = 0. table 14-3. operation modes and output trigge rs of real-time output port (v850es/jh3-e) byte0 extr0 operation mode rtbh0 (rtp04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttaa5cc0 inttaa4cc0 0 1 4 bits u 1 channel, 2 bits u 1 channel inttaa4cc0 inttaa0cc0 0 inttaa4cc0 1 1 6 bits u 1 channel inttaa0cc0 table 14-4. operation modes and output trig gers of real-time output port (v850es/jj3-e) byte0 extr0 operation mode rtbh0 (rtp04 to rtp07) rtbl0 (rtp00 to rtp03) 0 inttaa5cc0 inttaa4cc0 0 1 4 bits u 2 channel inttaa4cc0 inttaa0cc0 0 inttaa4cc0 1 1 8 bits u 1 channel inttaa0cc0 v850es/jh3-e, v850es/jj3-e chapter 14 real-time output function (rto) r01uh0290ej0300 rev.3.00 page 696 of 1817 sep 19, 2011 14.4 operation if the real-time output operatio n is enabled by setting the rtpc0.rtpoe0 bi t to 1, the data of the rtbh0 and rtbl0 registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the rtpc0.extr0 and rt pc0.byte0 bits). of the transferred data, only the data of the bits for which real-time output is enabled by the rtpm0 r egister is output from the rtp00 to rtp07 bits . the bits for which real-time output is disabled by the rtpm0 register output 0. if the real-time output operation is disa bled by clearing the rtpoe0 bit to 0, the rtp00 to rtp07 signals output 0 regardless of the setting of the rtpm0 register. figure 14-2. example of operation timing of rto0 (when extr0 bit = 0, byte0 bit = 0) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttaa5cc0 (internal) inttaa4cc0 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by inttaa5cc0 interrupt request (rtbh0 write) b: software processing by inttaa4cc0 interrupt request (rtbl0 write) remark for the operation during standby, see chapter 27 standby function . v850es/jh3-e, v850es/jj3-e chapter 14 real-time output function (rto) r01uh0290ej0300 rev.3.00 page 697 of 1817 sep 19, 2011 14.5 usage (1) disable real-time output. clear the rtpc0.rtpoe0 bit to 0. (2) perform initialization as follows. ? set the alternate-function pins of port 4 after setting the pfc4.pfc4m bit and pfce4.pfce4m bit to the rto pin, set the pmc4.pmc4m bit to 1 (m = 0 to 5: v850es/jh3-e, m = 0 to 7: v850es/jj3-e). ? specify the real-time output port mode or port mode in 1-bit units. set the rtpm0 register. ? channel configuration: select the trigger and valid edge. set the rtpc0.extr0, rtpc0. byte0, and rtpc0.rtpeg0 bits. ? set the initial values to the rtbh0 and rtbl0 registers note 1 . (3) enable real-time output. set the rtpoe0 bit = 1. (4) set the next output value to the rtbh0 and rtbl0 regi sters by the time the selected transfer trigger is generated note 2 . (5) sequentially set the next real-t ime output value to the rtbh0 and rtbl0 registers via interrupt servicing corresponding to the selected trigger. notes 1. if the rtbh0 and rtbl0 registers are written when t he rtpoe0 bit = 0, that value is transferred to real-time output latches 0h and 0l. 2. even if the rtbh0 and rtbl0 registers are written wh en the rtpoe0 bit = 1, data is not transferred to real-time output latches 0h and 0l. 14.6 cautions (1) prevent the following conflicts by software. ? conflict between real-time output disable/enable switching (rtpoe0 bi t) and the selected real-time output trigger. ? conflict between writing to the rt bh0 and rtbl0 registers in the re al-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoe0 bit = 0). (3) once real-time output has been disabled (rtpoe0 bit = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1). v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 698 of 1817 sep 19, 2011 chapter 15 a/d converter 15.1 overview the a/d converter converts analog input signals into digital values and has a resolution of 10 bits. the a/d converter of the v850es/jx3-e has the following number of ani channels and ani pins. part name v850es/jh3-e v850es/jj3-e number of ani channels (m) 10 ch (m = 10) 12 ch (m = 12) ani pin number (n) ani0 to ani9 (n = 0 to 9) ani0 to ani11 (n = 0 to 11) in this chapter, ?m? indicates the number of ani channels and ?n? indicates the ani pin (analog input pin) number. the a/d converter has the following features. { 10-bit resolution { successive approximation method { operating voltage: av ref0 = 3.0 to 3.6 v { analog input voltage: 0 v to av ref0 { the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot select mode ? one-shot scan mode { the following functions are provided as trigger modes. ? software trigger mode ? external trigger mode (external, 1) ? timer trigger mode { power-fail monitor function (conversion result compare function) 15.2 functions (1) 10-bit resolution a/d conversion an analog input channel is selected from anin, and an a/d conversion operation is repeated at a resolution of 10 bits. each time a/d conversion has been completed, an interrupt request signal (intad) is generated. (2) power-fail detection function this function is used to detect a drop in the battery volt age. the result of a/d conversion (the value of the ada0crnh register) is compared with the value of the ada0pft register, and the intad signal is generated only when a specified comparison condition is satisfied. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 699 of 1817 sep 19, 2011 15.3 configuration the block diagram of the a/d converter is shown below. figure 15-1. block diagram of a/d converter ani0 : : : : : ani1 ani2 ani11 note 1 ada0m2 ada0m1 ada0m0 ada0s ada0pft controller voltage comparator ada0pfm ada0cr0 ada0cr1 : : ada0cr09 ada0cr10 note 3 ada0cr11 note 3 internal bus av ref0 ada0ce bit av ss intad edge detection adtrg controller sample & hold circuit ada0ets0 bit ada0ets1 bit ada0ce bit ada0tmd1 bit ada0tmd0 bit selector selector ada0pfe bit ada0pfc bit sar voltage comparator & compare voltage generation dac inttaa2cc0 inttaa2cc1 tabtadt0 note 2 notes 1. ani00 to ani09 in the v850es/jh3-e 2. the timer trigger signal from 6-phase pwm output circuit (tabop) 3. ada0cr00 to ada0cr09 in the v850es/jh3-e the a/d converter includes the following hardware. table 15-1. configuration of a/d converter item configuration analog inputs m channels (anin pins) registers successive approximation register (sar) a/d conversion result registers n (ada0crn) a/d conversion result registers nh (ada 0crnh): only higher 8 bits can be read control registers a/d converter mode registers 0 to 2 (ada0m0 to ada0m2) a/d converter channel specification register 0 (ada0s) power fail compare mode register (ada0pfm) power fail compare threshold value register (ada0pft) v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 700 of 1817 sep 19, 2011 (1) successive approximation register (sar) the sar compares the voltage value of the analog input signal with the output voltage of the compare voltage generation dac (compare voltage), and holds the comparison re sult starting from the most significant bit (msb). when the comparison result has been held down to the leas t significant bit (lsb) (i.e., when a/d conversion is complete), the contents of the sar are transferred to the ada0crn register. (2) a/d conversion result register n (ada0crn), a/d conversion result register nh (ada0crnh) the ada0crn register is a 16-bit regist er that stores the a/d conversion re sult. ada0arn cons ist of 12 registers and the a/d conversion result is stored in the 10 higher bits of the ad0crn register corresponding to analog input. (the lower 6 bits are fixed to 0.) (3) a/d converter mode register 0 (ada0m0) this register specifies the operation mode and cont rols the conversion operation by the a/d converter. (4) a/d converter mode register 1 (ada0m1) this register sets the conversion time of the analog input signal to be converted. (5) a/d converter mode register 2 (ada0m2) this register sets the hardware trigger mode. (6) a/d converter channel specification register (ada0s) this register sets the input port that inputs the analog voltage to be converted. (7) power-fail compare m ode register (ada0pfm) this register sets the power-fail monitor mode. (8) power-fail compare threshol d value register (ada0pft) the ada0pft register sets the threshold value that is co mpared with the value of a/d conversion result register nh (ada0crnh). the 8-bit data set to the ada0pft register is compared with the higher 8 bits of the a/d conversion result register (ada0crnh). (9) controller the controller compares the result of the a/d conversion (the value of the ada0crnh register) with the value of the ada0pft register when a/d conversion is completed or when the power-fail detection function is used, and generates the intad signal only when a spec ified comparison condition is satisfied. (10) sample & hold circuit the sample & hold circuit samples each of the analog i nput signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (11) voltage comparator the voltage comparator compares a vo ltage value that has been sampled and he ld with the output voltage of the compare voltage generation dac. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 701 of 1817 sep 19, 2011 (12) compare voltage generation dac this compare voltage generati on dac is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (13) anin pins these are analog input pins for the m a/d converte r channels and are used to input analog signals to be converted into digital signals. pins other than the one selected as the analog input by the ada0s register can be used as input port pins. caution make sure that the voltages input to the anin pins do not exceed the rated values. in particular if a voltage of av ref0 or higher is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. (14) av ref0 pin this is the pin used to input the refere nce voltage of the a/d conv erter. always make the potential at this pin the same as that at the v dd pin even when the a/d converter is not used. the signals input to the anin pins are converted to digital signals based on the voltage applied between the av ref0 and av ss pins. (15) av ss pin this is the ground potential pi n of the a/d converter. alwa ys make the potential at this pin the same as that at the v ss pin even when the a/d converter is not used. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 702 of 1817 sep 19, 2011 15.4 registers the a/d converter is controlled by the following registers. ? a/d converter mode registers 0, 1, 2 (ada0m0, ada0m1, ada0m2) ? a/d converter channel specification register 0 (ada0s) ? power-fail compare mode register (ada0pfm) the following registers are also used. ? a/d conversion result register n (ada0crn) ? a/d conversion result register nh (ada0crnh) ? power-fail compare threshold value register (ada0pft) (1) a/d converter mode register 0 (ada0m0) the ada0m0 register is an 8-bit register that specif ies the operation mode and controls conversion operations. this register can be read or written in 8-bit or 1-bit units. however, the ada0ef bit is read-only. reset sets this register to 00h. (1/2) ada0ce ada0ce 0 1 stops a/d conversion enables a/d conversion a/d conversion control ada0m0 0 ada0md1 ada0md0 ada0ets1 ada0ets0 ada0tmd ada0ef ada0md1 0 0 1 1 ada0md0 0 1 0 1 continuous select mode continuous scan mode one-shot select mode one-shot scan mode specification of a/d converter operation mode after reset: 00h r/w address: fffff200h < > < > ada0ets1 0 0 1 1 ada0ets0 0 1 0 1 no edge detection falling edge detection rising edge detection detection of both rising and falling edges specification of external trigger (adtrg pin) input valid edge v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 703 of 1817 sep 19, 2011 (2/2) ada0tmd 0 1 software trigger mode external trigger mode/timer trigger mode trigger mode specification ada0ef 0 1 a/d conversion stopped a/d conversion in progress a/d converter status display cautions 1. accessing the ada0m0 register is pr ohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on- chip peripheral i/o registers. ? when the cpu operates on the subclock a nd the main clock oscillation is stopped ? when the cpu operates on the internal oscillation clock 2. a write operation to bit 0 is ignored. 3. changing the ada0m1.ada0fr2 to ada0 m1.ada0fr0 bits is prohibited while a/d conversion is enabled (ada0ce bit = 1). 4. in the following modes, write data to the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft registers while a/d conversion is stopped (ada0ce bit = 0), and then enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written in other modes during a/d conversion (ada0ef bit = 1), the following will be performed according to the mode. ? in software trigger mode a/d conversion is stopped and started again from the beginning. ? in hardware trigger mode a/d conversion is stopped, and th e trigger standby status is set. 5. to select the external trigger mode/timer trigger mode (ada0tmd bit = 1), set the high- speed conversion mode (ada0m1.ada0hs1 bi t = 1). do not input a trigger during stabilization time that is inserted once af ter the a/d conversion operation is enabled (ada0ce bit = 1). 6. when not using the a/d converter, stop th e operation by setting the ada0ce bit to 0 to reduce the power consumption. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 704 of 1817 sep 19, 2011 (2) a/d converter mode register 1 (ada0m1) the ada0m1 register is an 8-bit regist er that specifies the conversion time. this register can be read or written in 8-bit or 1-bit units. reset sets this bit to 00h. ada0hs1 ada0m1 0 00 ada0fr2 ada0fr3 ada0fr1 ada0fr0 after reset: 00h r/w address: fffff201h ada0hs1 0 1 normal conversion mode high-speed conversion mode specification of normal conversion mode/high-speed mode (a/d conversion time) cautions 1. changing the ada0m1 register is prohibited while a/d conversion is enabled (ada0m0.ada0ce bit = 1). 2. to select the external trigger mode/timer trigger mode (ada0m0.ada0tmd bit = 1), set the high-speed conversion mode (ada0hs1 bi t = 1). do not input a trigger during the stabilization time that is inserted once af ter the a/d conversion operation is enabled (ada0ce bit = 1). 3. be sure to clear bits 6 to 4 to ?0?. remark for a/d conversion time setting examples, see tables 15-2 and 15-3 . v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 705 of 1817 sep 19, 2011 table 15-2. conversion time selection in normal conversion mode (ada0hs1 bit = 0) a/d conversion time ada0fr3 to ada0fr0 bits stabilization time + conversion time + wait time 50mhz 48 mhz 32 mhz 24 mhz 0000 26/f xx + 52/f xx + 54/f xx setting prohibited setting prohi bited setting prohibited 5.50 s 0001 52/f xx + 104/f xx + 106/f xx 5.24 s 5.46 s 8.19 s setting prohibited 0010 78/f xx + 156/f xx + 158/f xx 7.84 s 8.17 s setting prohibited setting prohibited 0011 100/f xx + 208/f xx + 210/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 0100 100/f xx + 260/f xx + 262/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 0101 100/fxx + 312/fxx + 314/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 0110 100/fxx + 364/fxx + 366/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 0111 100/f xx + 416/f xx + 418/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 1000 100/f xx + 468/f xx + 470/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 1001 100/f xx + 520/f xx + 522/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 1010 100/f xx + 572/f xx + 574/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 1011 100/f xx + 624/f xx + 626/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 1100 100/f xx + 676/f xx + 678/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 1101 100/f xx + 728/f xx + 730/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 1110 100/f xx + 780/f xx + 782/f xx setting prohibited setting prohibited s etting prohibited setting prohibited 1111 100/f xx + 832/f xx + 834/f xx setting prohibited setting prohibited s etting prohibited setting prohibited other than above setting prohibited remark stabilization time: a/d converter setup time (1 s or longer) conversion time: actual a/d conversion time (2.16 to 3.12 s) wait time: wait time inserted before the next conversion f xx : main clock frequency in the normal conversion mode, the conversion is st arted after the stabilization time elapses after the ada0m0.ada0ce bit is set to 1, and a/d conversion is performed only during the conversion time (2.16 to 3.12 s). operation is stopped after the conversion ends and the a/d conversion end interrupt request signal (intad) is generated after the wait time elapses. because the conversion operation is stopped during the wait time, operating current can be reduced. cautions 1. set as 2.6 s conversion time 3.12 s. 2. during a/d conversion, if the ada0 m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written or a trigger is input, reconversion is carried out. however, if the stabilization time end timing conf licts with writing to these registers, or if the stabilization time end timing conflicts with the trigger input, a stabilization time of 64 clocks is reinserted. if a conflict occurs again with the reinserte d stabilization time end timing, the stabilization time is reinserted. therefore do not set the tr igger input interval and control register write interval to 64 clocks or lower. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 706 of 1817 sep 19, 2011 table 15-3. conversion time selection in hi gh-speed conversion mode (ada0hs1 bit = 1) a/d conversion time ada0fr3 to ada0fr0 bits conversion time (+ stabilization time) 50mhz 48 mhz 32 mhz 24 mhz 0000 52/f xx (+26/f xx ) setting prohibited setting prohi bited setting prohibited 2.17 s 0001 104/f xx (+52/f xx ) setting prohibited 2.17 s 3.25 s 4.33 s 0010 156/f xx (+78/f xx ) 3.12 s 3.25 s 4.88 s 6.50 s 0011 208/f xx (+100/f xx ) 4.16 s 4.33 s 6.50 s 8.67 s 0100 260/f xx (+100/f xx ) 5.20 s 5.42 s 8.13 s setting prohibited 0101 312/f xx (+100/f xx ) 6.24 s 6.50 s 9.75 s setting prohibited 0110 364/f xx (+100/f xx ) 7.28 s 7.58 s setting prohibited setting prohibited 0111 416/f xx (+100/f xx ) 8.32 s 8.67 s setting prohibited setting prohibited 1000 468/f xx (+100/f xx ) 9.36 s 9.75 s setting prohibited setting prohibited 1001 520/f xx (+100/f xx ) setting prohibited setting prohibited setting prohibited setting prohibited 1010 572/f xx (+100/f xx ) setting prohibited setting prohibited setting prohibited setting prohibited 1011 624/f xx (+100/f xx ) setting prohibited setting prohibited setting prohibited setting prohibited 1100 676/f xx (+100/f xx ) setting prohibited setting prohibited setting prohibited setting prohibited 1101 728/f xx (+100/f xx ) setting prohibited setting prohibited setting prohibited setting prohibited 1110 780/f xx (+100/f xx ) setting prohibited setting prohibited setting prohibited setting prohibited 1111 832/f xx (+100/f xx ) setting prohibited setting prohibited setting prohibited setting prohibited other than above setting prohibited remark stabilization time: a/d converter setup time (1 s or longer) conversion time: actual a/d conversion time (2.17 to 9.36 s) f xx : main clock frequency in the high-speed conversion mode, the conversion is started after the stabilization time elapses after the ada0m0.ada0ce bit is set to 1, and a/d conversion is performed only during the conversion time (2.17 to 9.36 s). the a/d conversion end interrupt request signal (intad) is generated immediately after the conversion ends. in continuous conversion mode, the stabilization time is inserted only before the first conversion, and not inserted after the second conversion (the a/d converter remains running). cautions 1. set as 2.17 s conversion time 9.36 s . 2. in the high-speed conver sion mode, rewriting of the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers and trigger input ar e prohibited during the stabilization time. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 707 of 1817 sep 19, 2011 (3) a/d converter mode register 2 (ada0m2) the ada0m2 register specifies the hardware trigger mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0m2 0 0 0 00 ada0tmd1 ada0tmd0 ada0tmd1 0 0 1 1 ada0tmd0 0 1 0 1 specification of hardware trigger mode external trigger mode (when adtrg pin valid edge is detected) timer trigger mode 0 (when inttaa2cc0 interrupt request is generated) timer trigger mode 1 (when inttaa2cc1 interrupt request is generated) timer trigger mode 2 (tabtadt0 signal) after reset: 00h r/w address: fffff203h 6543210 7 cautions 1. in the following modes, write data to the ada0m2 register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode 2. be sure to clear bits 7 to 2 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 708 of 1817 sep 19, 2011 (4) analog input channel specification register 0 (ada0s) the ada0s register specifies the pin that inputs the analog voltage to be converted into a digital signal. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ada0s 0 0 0 ada0s3 ada0s2 ada0s1 ada0s0 after reset: 00h r/w address: fffff202h ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 note ani11 note ani0 ani0, ani1 ani0 to ani2 ani0 to ani3 ani0 to ani4 ani0 to ani5 ani0 to ani6 ani0 to ani7 ani0 to ani8 ani0 to ani9 ani0 to ani10 note ani0 to ani11 note ada0s3 0 0 0 0 0 0 0 0 1 1 1 1 ada0s2 0 0 0 0 1 1 1 1 0 0 0 0 ada0s1 0 0 1 1 0 0 1 1 0 0 1 1 ada0s0 0 1 0 1 0 1 0 1 0 1 0 1 select mode scan mode note v850es/jj3-e only cautions 1. in the following modes, write data to the ada0s register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode 2. be sure to clear bits 7 to 4 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 709 of 1817 sep 19, 2011 (5) a/d conversion result regist ers n, nh (ada0crn, ada0crnh) the ada0crn and ada0crnh registers store the a/d conversion results. these registers are read-only, in 16-bit or 8-bit units. however, the ada0crn register is used for 16-bit access and the ada0crnh register for 8-bit access. the 10 bits of th e conversion result are read to the higher 10 bits of the ada0crn register, and 0 is read to the lower 6 bits. the higher 8 bits of the conversion result are read to the ada0crnh register. caution accessing the ada0crn and ada0crnh regist ers is prohibited in the following statuses. for details, see 3.4.9 (2) accessing speci fic on-chip peripheral i/o registers. ? when the cpu operates on the subclock and the main clock oscillation is stopped ? when the cpu operates on the internal oscillation clock after reset: undefined r address: ada0cr0 fffff210h, ada0cr1 fffff212h, ada0cr2 fffff214h, ada0cr3 fffff216h, ada0cr4 fffff218h, ada0cr5 fffff21ah, ada0cr6 fffff21ch, ada0cr7 fffff21eh, ada0cr8 fffff220h, ada0cr9 fffff222h, ada0cr10 note fffff224h, ada0cr11 note fffff226h ada0crn ad9 ad8 ad7 ad6 ad0000000 ad1 ad2 ad3 ad4 ad5 ad9 ada0crnh ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: ada0cr0h fffff211h, ada0cr1h fffff213h, ada0cr2h fffff215h, ada0cr3h fffff217h, ada0cr4h fffff219h, ada0cr5h fffff21bh, ada0cr6h fffff21dh, ada0cr7h fffff21fh, ada0cr8h fffff221h, ada0cr9h fffff223h, ada0cr10h note fffff225h, ada0cr11h note fffff227h note v850es/jj3-e only caution a write operation to the ada0m0 and ada0s registers may cause the contents of the ada0crn register to become undefined. afte r the conversion, read the conversion result before writing to the ada0m0 and ada0s regi sters. correct conversion results may not be read at a timing other than the above. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 710 of 1817 sep 19, 2011 the relationship between the analog voltage input to the analog input pins (anin) and the a/d conversion result (ada0crn register) is as follows. v in sar = int ( av ref0 1,024 + 0.5) ada0cr note = sar 64 or, av ref0 av ref0 (sar ? 0.5) 1,024 v in < (sar + 0.5) 1,024 int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref0 : av ref0 pin voltage ada0cr: value of ada0crn register note the lower 6 bits of the ada0crn register are fixed to 0. the following shows the relationship between the analo g input voltage and the a/d conversion results. figure 15-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results ada0crn sar ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 711 of 1817 sep 19, 2011 (6) power-fail compare m ode register (ada0pfm) the ada0pfm register is an 8-bit register that sets the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pfe power-fail compare disabled power-fail compare enabled ada0pfe 0 1 selection of power-fail compare enable/disable ada0pfm ada0pfc 00 00 0 0 generates an interrupt request signal (intad) when ada0crnh ada0pft generates an interrupt request signal (intad) when ada0crnh < ada0pft ada0pfc 0 1 selection of power-fail compare mode after reset: 00h r/w address: fffff204h <7>6543210 cautions 1. in the select mode, the 8-bit data set to the ada0pft regist er is compared with the value of the ada0crnh register specified by the ada0s register. if the result matches the condition specified by the ada0pfc bit, the conversion result is stored in the ada0crn register and the intad signal is ge nerated. if it does not match, however, the interrupt signal is not generated. 2. in the scan mode, the 8-bit data set to the ada0pft register is compared with the contents of the ada0cr0h register. if the result matches the c ondition specified by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, however, the intad signal is not generated. regardless of the comparison r esult, the scan operati on is continued and the conversion result is st ored in the ada0crn register until the scan operation is completed. however, the intad signal is not generated after th e scan operation has been completed. 3. in the following modes, write data to the ada0pfm register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 712 of 1817 sep 19, 2011 (7) power-fail compare thres hold value register (ada0pft) the ada0pft register sets the compare value in the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ada0pft after reset: 00h r/w address: fffff205h 76 54 321 0 caution in the following modes, write data to the ada0pft register while a/d conversion is stopped (ada0m0.ada0ce bit = 0), and then enable the a/d conversion operation (ada0ce bit = 1). ? normal conversion mode ? one-shot select mode/one-shot scan mode in high-speed conversion mode v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 713 of 1817 sep 19, 2011 15.5 operation 15.5.1 basic operation <1> set the operation mode, trigger mode, and conversion time for executing a/d conversion by using the ada0m0, ada0m1, ada0m2, and ada0s registers. when the ada0ce bit of the ada0m0 register is set, conversion is started in the software trigger mode and the a/d converter wa its for a trigger in the external or timer trigger mode. <2> when a/d conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when the sample & hold circuit samples the input channel for a specific time, it ent ers the hold status, and holds the input analog voltage until a/d conversion is complete. <4> set bit 9 of the successive approximation register (sar), and set the compare voltage generation dac to (1/2) av ref0 . <5> the voltage difference between the voltage of the compare voltage genera tion dac and the analog input voltage is compared by the voltage comparator. if the analog input voltage is higher than (1/2) av ref0 , the msb of the sar remains set. if it is lower than (1/2) av ref0 , the msb is reset. <6> next, bit 8 of the sar is automatically set and the next comparison is started. depen ding on the value of bit 9, to which a result has been already set, the compare vo ltage generation dac is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 this compare voltage and the analog input voltage ar e compared and, depending on the result, bit 8 is manipulated as follows. analog input voltage compare voltage: bit 8 = 1 analog input voltage compare voltage: bit 8 = 0 <7> this comparison is continued to bit 0 of the sar. <8> when comparison of the 10 bits is complete, the valid di gital result remains in the sar, and is then transferred to and stored in the ada0crn register. after that, an a/d conversion end interrupt request signal (intad) is generated. <9> in one-shot select mode, conversion is stopped note . in one-shot scan mode, conversion is stopped after scanning once note . in continuous select mode, repeat steps <2> to <8 > until the ada0m0.ada0ce bit is cleared to 0. in continuous scan mode, repeat steps <2> to <8> for each channel. note in the external trigger mode, timer trigger mode 0, or timer trigger mode 1, the trigger standby status is entered. remark the trigger standby status me ans the status after the stabilization time has elapsed. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 714 of 1817 sep 19, 2011 15.5.2 conversion op eration timing figure 15-3. conversion operation timing (continuous conversion) (1) operation in normal conversion mode (ada0hs1 bit = 0) ada0m0.ada0ce bit processing state setup stabilization time conversion time wait time sampling first conversion second conversion setup sampling wait a/d conversion intad signal 2/f xx (max.) 0.5/f xx sampling time (2) operation in high-speed con version mode (ada0hs1 bit = 1) ada0m0.ada0ce bit processing state setup conversion time sampling first conversion second conversion sampling a/d conversion a/d conversion intad signal 0.5/f xx stabilization time 2/f xx (max.) sampling time remark the above timings are applicable when a trigger is generated within the stabilization time. if a trigger is generated after the stabilization time has elapsed, a trigger response time is inserted. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 715 of 1817 sep 19, 2011 15.5.3 trigger mode the timing of starting the conversion oper ation is specified by setting the trigger mode. the trigger mode includes the software trigger mode and hardware trigger modes. the hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. the ada0m0.ada0tmd bit is used to set the trigger mode. the hardware trigger modes are set by the ada0m2.ada0tmd1 and ada0m2.ada0tmd0 bits. (1) software trigger mode when the ada0m0.ada0ce bit is set to 1, the signal of the analog input pin (anin pin) specified by the ada0s register is converted. when conversion is complete, the resu lt is stored in the ada0crn r egister. at the same time, the a/d conversion end interrupt request signal (intad) is generated. if the operation mode specified by the ada0m0.ada0md1 and ada0m0.ada0md0 bits is the continuous select/scan mode, the next conversion is repeated, unless the ada0ce bit is cleared to 0 after completion of the conversion. conversion is performed once and ends if the operation mode is the one-shot select/scan mode. when conversion is started, the ada0m0.ada0ef bit is set to 1 (indicating that conversion is in progress). if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft regi ster is written during conv ersion, the conversion is aborted and started again from the beginning. however, writing to these registers is prohibited in the normal conversion mode and one-shot select mode/one-s hot scan mode in the high-speed conversion mode. (2) external trigger mode in this mode, converting the signal of the analog input pin (anin) specified by the ada0 s register is started when an external trigger is input (to the adtrg pin). which edge of the external trigger is to be detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the ada0m0.ada0ets1 and ada0m0.ata0ets0 bits. when the ada0ce bit is set to 1, the a/d converter waits for the trigger, and starts conversion after the external trigger has been input. when conversion is completed, the result of conversion is stored in the ada0crn register, regardless of whether the continuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ada0md1 and ada0md0 bits. at the same time, the intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conversion operati on, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft regi ster is written during the conversion operation, the conversion is aborted, and the a/d converter waits for the tr igger again. however, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. caution to select the external trigger mode, set the high-speed conversion mode. do not input a trigger during the stabilization time that is inserted on ce after the a/d conversion operation is enabled (ada0m0.ada0ce bit = 1). remark the trigger standby status me ans the status after the st abilization time has elapsed. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 716 of 1817 sep 19, 2011 (3) timer trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani11) specified by the ada0s register is started by the compare match interrupt request signal (inttaa2cc0 or inttaa2cc1 ) of the capture/compare register connected to the timer. the inttaa2cc0 or inttaa2cc1 signal is selected by the ada0tmd1 and ada0tmd0 bits, and conversion is started at the rising edge of the specified compare match interrupt request signal. when the ada0ce bit is set to 1, the a/d converter waits for a trigger, and starts conversion when the compare match interrupt request signal of the timer is input. when conversion is completed, regardless of whether the c ontinuous select, continuous scan, one-shot select, or one-shot scan mode is set as the operation mode by the ada0 md1 and ada0md0 bits, the result of the conversion is stored in the ada0crn register. at the same time, t he intad signal is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that conversion is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that conversion is stopped). if the valid trigger is input during the conversion operati on, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft regi ster is written during conv ersion, the conversion is stopped and the a/d converter waits for the trigger again. ho wever, writing to these registers is prohibited in the one-shot select mode/one-shot scan mode. caution to select the timer trigger mode, set the hi gh-speed conversion mode. do not input a trigger during the stabilization time that is inserted on ce after the a/d conversion operation is enabled (ada0m0.ada0ce bit = 1). remark the trigger standby status me ans the status after the st abilization time has elapsed. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 717 of 1817 sep 19, 2011 15.5.4 operation mode four operation modes are available as th e modes in which to set the anin pins : continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. the operation mode is selected by the ad a0m0.ada0md1 and ada0m0.ada0md0 bits. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the ada0s register is continuously converted into a digital value. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin corresponds to an ada0crn register on a one-to-one basis. each time a/d conversion is completed, the a/d conversion end interrupt request signal (intad) is generated. after completion of conversion, the next conversion is started, unless th e ada0m0.ada0ce bit is cleared to 0. figure 15-4. timing example of continuous se lect mode operation (ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 (ani1) data 7 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are continuously converted into digital values. the result of each conversion is stored in the ada0crn register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s r egister is complete, the intad signal is generated, and a/d conversion is started again from the ani0 pin, unless the ada0ce bit is cleared to 0. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 718 of 1817 sep 19, 2011 figure 15-5. timing example of continuous s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 note ani11 note . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 note ada0cr11 note . . . note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 719 of 1817 sep 19, 2011 (3) one-shot select mode in this mode, the voltage of one analog input pin specified by the ada0s register is converted into a digital value only once. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin and an ada0crn register correspond on a one-to-one basis. when a/d conversion has been completed once, the intad signal is generated. the a/d conversion operation is stopped after it has been completed. figure 15-6. timing example of one-shot select mode oper ation (ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 6 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 conversion end conversion end (4) one-shot scan mode in this mode, analog input pins are sequentially selected, from the ani0 pin to the pin specified by the ada0s register, and their values are converted into digital values . each conversion result is stored in the ada0crn register corresponding to the analog input pin. when conversion of the analog input pin specified by the ada0s register is complete, the intad signal is generated. a/d conversion is stopped after it has been completed (n = 0 to 11). v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 720 of 1817 sep 19, 2011 figure 15-7. timing example of one-shot s can mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 (ani2) data 4 ( ani3) data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 note ani11 note . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 note ada0cr11 note . . . note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 721 of 1817 sep 19, 2011 15.5.5 power-fail compare mode the a/d conversion end interrupt reques t signal (intad) can be controlled as follows by the ada0pfm and ada0pft registers. ? when the ada0pfm.ada0pfe bit = 0, the intad signal is generated each time conversion is completed (normal use of the a/d converter). ? when the ada0pfe bit = 1 and when the ada0pfm.ada0pf c bit = 0, the value of the ada0crnh register is compared with the value of the ada0pft register when co nversion is completed, and the intad signal is generated only if ada0crnh ada0pft. ? when the ada0pfe bit = 1 and when the ada0pfc bit = 1, the value of the ada0crnh register is compared with the value of the ada0pft register when conversion is completed, and t he intad signal is generated only if ada0crnh < ada0pft. in the power-fail compare mode, four modes are available as modes in which to set the anin pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 722 of 1817 sep 19, 2011 (1) continuous select mode in this mode, the result of converti ng the voltage of the analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0crn register, and the intad signal is not generated. after completion of the first conversion, t he next conversion is started, unless the ada0m0.ada0ce bit is cleared to 0. figure 15-8. timing example of continuous select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 ( ani1) data 7 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 2 ( ani1) data 3 ( ani1) data 4 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 ada0pft unmatch ada0pft unmatch ada0pft match ada0pft match ada0pft match conversion start set ada0ce bit = 1 (2) continuous scan mode in this mode, the results of converti ng the voltages of the analog input pins sequentially selected from the ani0 pin to the pin specified by the ada0s regi ster are stored, and the set value of the ada0cr0h register of channel 0 is compared with the value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in th e ada0cr0 register, and the intad signal is generated. if it does not match, the conversion result is stored in th e ada0cr0 register, and the intad signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of sequentially converting the voltages on the analog input pins up to the pin specified by the ada0s register are continuously stored. after completion of conversion, the next conversion is started from the ani0 pin again, unless the ada0ce bit is cleared to 0. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 723 of 1817 sep 19, 2011 figure 15-9. timing example of continuous scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) data 7 ( ani2) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ada0pft unmatch ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 note ani11 note . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 note ada0cr11 note . . . note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 724 of 1817 sep 19, 2011 (3) one-shot select mode in this mode, the result of converti ng the voltage of the analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0crn register, and the intad signal is not generated. conversion is stoppe d after it has been completed. figure 15-10. timing example of on e-shot select mode operation (when power-fail comparison is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 6 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 ada0pft match conversion end ada0pft unmatch conversion end (4) one-shot scan mode in this mode, the results of converti ng the voltages of the analog input pins sequentially selected from the ani0 pin to the pin specified by the ada0s regi ster are stored, and the set value of the ada0cr0h register of channel 0 is compared with the set value of the ada0pft register. if the result of power-fail comparison matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 r egister, and the intad0 signal is not generated. after the result of the first conversion ha s been stored in the ada0cr0 register, the results of converting the signals on the analog input pins specified by the ada0s register are sequentially stored. the conversion is stopped after it has been completed. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 725 of 1817 sep 19, 2011 figure 15-11. timing example of on e-shot scan mode operation (when power-fail comparison is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ada0pft match ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 note ani11 note . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 note ada0cr11 note . . . note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 726 of 1817 sep 19, 2011 15.6 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consumpt ion can be reduced by clearing the ada0m0.ada0ce bit to 0. (2) input range of anin pins input the voltage within the specified range to the anin pins. if a voltage equal to or higher than av ref0 or equal to or lower than av ss (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conv ersion value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit resolution, the anin pins must be effectively protected from noise. the effect of noise increases as the output impedance of t he analog input source becomes higher. to lower the noise, connecting an external capacitor as shown in figure 15-12 is recommended. figure 15-12. processing of analog input pin av ref0 v dd v ss av ss clamp with a diode with a low v f (0.3 v or less) if noise equal to or higher than av ref0 or equal to or lower than av ss may be generated. anin (4) alternate i/o the analog input pins (anin) function alternately as port pi ns. when selecting one of the anin pins to execute a/d conversion, do not execute an instru ction to read an input port or write to an output port during conversion as the conversion resolution may drop. also the conversion resolution may drop at the pins se t as output port pins during a/d conversion if the output current fluctuates due to the ef fect of the external circuit connected to the port pins. if a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the a/d conversion value may not be as expected due to the effect of coupling noise. therefore, do not apply a pulse to a pin adjacent to the pin undergoing a/d conversion. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 727 of 1817 sep 19, 2011 (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the ada0s register are changed. if the analog input pin is changed during a/d conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end in terrupt request flag may be set immediately before the ada0s register is rewritten. if the adif flag is read immedi ately after the ada0s register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion is stopped, clear the adif flag before resuming conversion. figure 15-13. generation timing of a/d conversion end interrupt request ada0s rewriting (ania conversion start) ada0s rewriting (anib conversion start) adif is set, but anib conversion does not end a/d conversion ada0crn intad ania ania anib anib anib ania ania anib remark a = 0 to 9: v850es/jh3-e, a = 0 to 11: v850es/jj3-e b = 0 to 9: v850es/jh3-e, b = 0 to 11: v850es/jj3-e (6) internal equivalent circuit the following shows the equivalent circuit of the analog input block. figure 15-14. internal equi valent circuit of anin pin anin c in r in r in c in 14 k 8.4 pf remark the above values are reference values. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 728 of 1817 sep 19, 2011 (7) av ref0 pin (a) the av ref0 pin is used as the power supply pin of the a/d converter and also supplies power to the alternate- function ports. in an application where a backup power su pply is used, be sure to supply the same potential as v dd to the av ref0 pin as shown in figure 15-15. (b) the av ref0 pin is also used as the reference voltage pin of the a/d converter. if the source supplying power to the av ref0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the cu rrent that flows during conversion (especially, immediately after the conversion operation enable bit ada0ce has been set to 1). as a result, the conversion accuracy may drop. to avoid this, it is recommended to connect a capacitor across the av ref0 and av ss pins to suppress the reference voltage fluctuation as shown in figure 15-15. (c) if the source supplying power to the av ref0 pin has a high dc resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the a/d conversion current. figure 15-15. av ref0 pin processing example av ref0 note av ss main power supply note parasitic inductance (8) reading ada0crn register when the ada0m0 to ada0m2, ada0s, ada0pfm, or ada0p ft register is written, t he contents of the ada0crn register may be undefined. read the conversion result a fter completion of conversion and before writing to the ada0m0 to ada0m2, ada0s, ada0pfm, or ada0pft r egister. also, when an external/timer trigger is acknowledged, the contents of the ada0crn register may be undefined. read the conversion result after completion of conversion and before the next external/timer tr igger is acknowledged. the correct conversion result may not be read at a timing different from the above. (9) external trigger mode when using the external trigger mode, the input tr igger during a/d conversion will not be acknowledged. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 729 of 1817 sep 19, 2011 (10) standby mode because the a/d converter stops operating in the stop mode, the conversion results are invalid, so power consumption can be reduced. operatio ns are resumed after the stop mode is released, but the a/d conversion results after the stop mode is released are invalid. when using the a/d converter after the stop mode is released, clear the ada0m0.ada0ce bit to 0 before se tting the stop mode or after releasing the stop mode, then set the ada0ce bit to 1 after releasing the stop mode. in the idle1, idle2, or subclock operation mode, operation continues. to lower the po wer consumption, therefore, clear the ada0m0.ada0ce bit to 0. in the idle1 and idle2 modes, since the analog input voltage value cannot be retained, the a/d conversion results after the idle1 and idle2 modes are released are invalid. the results of conversions before the idle1 and idle2 modes were set are valid. (11) high-speed conversion mode in the high-speed conversion mode, rewriting t he ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers and trigger input during t he stabilization time are prohibited. (12) a/d conversion time the a/d conversion time is the total of the stabilization time, conversion time , wait time, and trigger response time (for details of these times, refer to table 15-2 conversion time sel ection in normal conversion mode (ada0hs1 bit = 0) and table 15-3 conversion time selection in high-speed conversion mode (ada0hs1 bit = 1) ). during a/d conversion in the normal conversion m ode, if the ada0m0, ada0m2, ada0s, ada0pfm, and ada0pft registers are written or a trigger is input, reconv ersion is carried out. however, if the stabilization time end timing conflicts with writing to thes e registers, or if the stabilization ti me end timing conflicts with the trigger input, a stabilization time of 64 clocks is reinserted. if a conflict occurs again with the reinse rted stabilization time end timing, the stabilization time is reinserted. therefore do not set the trigger input interval and cont rol register write interval to 64 clocks or lower. (13) variation of a/d conversion results the results of a/d conversion may vary due to a fluctuation in the supply voltag e or the effect of noise. to reduce this variation, take countermeasures with the progr am such as averaging the a/d conversion results. (14) a/d conversion result hysteresis characteristics the successive comparison type a/d converter holds the analog input voltage in the internal sample & hold capacitor and then performs a/d conversi on. after a/d conversion has finished, the analog input voltage remains in the internal sample & hold capacitor. as a result, the following phenomena may occur. ? when the same channel is used for a/d conversions, if the voltage is higher or lo wer than the previous a/d conversion, then hysteresis characte ristics may appear in which the conv ersion result is affected by the previous value. thus, even if t he conversion is performed at the same potential, the result may vary. ? when switching the analog input channel , hysteresis characteristics may app ear in which the conversion result is affected by the previous channel value. this is because one a/d converter is used for the a/d conversions. thus, even if the conversion is performed at the same potential, the result may vary. v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 730 of 1817 sep 19, 2011 15.7 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that can be recognized, i.e., t he ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref0 ? 0)/100 = av ref0 /100 when the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics ta ble does not include the quantization error. figure 15-16. overall error ideal line overall error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 731 of 1817 sep 19, 2011 (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog valu e is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-scale e rror, full-scale error, integral linearity error, or differential linearity error in the characteristics table. figure 15-17. quantization error quantization error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the actually measured analog input voltage and its theoretic al value when the digital output changes from 0?000 to 0?001 (1/2 lsb). figure 15-18. zero-scale error av ref0 analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 732 of 1817 sep 19, 2011 (5) full-scale error this is the difference between the actually measured analog input voltage and its theoretic al value when the digital output changes from 1?110 to 1?111 (full scale ? 3/2 lsb). figure 15-19. full-scale error av ref0 analog input (lsb) digital output (lower 3 bits) 111 av ref0 ? 3 0 av ref0 ? 2av ref0 ? 1 100 011 010 000 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error i ndicates the difference between the actually measured value and its theoretical value when a specific code is output. this indicates the basic characteristics of the a/d conversion when the voltage appl ied to the analog input pins of the sa me channel is consistently increased bit by bit from av ss to av ref0 . when the input voltage is increased or decreased, or when two or more channels are used, see 15.7 (2) overall error . figure 15-20. differential linearity error ideal width of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref0 analog input digital output v850es/jh3-e, v850es/jj3-e chapter 15 a/d converter r01uh0290ej0300 rev.3.00 page 733 of 1817 sep 19, 2011 (7) integral linearity error this error indicates the extent to which the conversion char acteristics differ from the ideal linear relationship. it indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 15-21. integral linearity error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output ideal line integral linearity error (8) conversion time this is the time required to obtain a digital output after each trigger has been generated. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 15-22. sampling time sampling time conversion time v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 734 of 1817 sep 19, 2011 chapter 16 asynchronous serial interface b with fifo (uartbn) in the v850es/jh3-e and v850es/jj3-e, asynchronous serial interface b with fifo (uartbn) is provided with 2 channels. 16.1 features ? transfer rate: maximum 300 bps to 3.125 mbps (using a dedicated baud rate generator) ? full-duplex communications ? single mode and fifo mode selectable ? single mode: 8-bit 1-stage data register (ubntx r egister or ubnrx register) is used for each of transmission and reception. ? fifo mode transmit fifo: ubntx register (8 bits 16 stages). receive fifo: ubnrxap register (16 bits 16 stages) the higher 8 bits of the ubnrxap register stor e information about errors in the received data. ? two-pin configuration txdbn: transmit data output pin rxdbn: receive data input pin ? reception error detection function ? overflow error (fifo mode only) ? parity error ? framing error ? overrun error (single mode only) ? interrupt sources: 5 types ? reception error interrupt request signal (intubntire) ? reception end interrupt request signal (intubntir) ? transmission enable interrupt request signal (intubntit) ? fifo transmission end interrupt reques t signal (intubntif) (fifo mode only) ? reception timeout interrupt request si gnal (intubntito) (fifo mode only) ? the character length of transmit/receive data is specified according to the ubnctl0 register ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? msb first/lsb first selectable for transfer data ? on-chip dedicated baud rate generator remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 735 of 1817 sep 19, 2011 16.2 configuration the block diagram of the uartbn is shown below. figure 16-1. block diagram of uartbn rxdbn internal bus receive shift register uartbn control register 0 (ubnctl0) uartbn control register 2 (ubnctl2) uartbn status register (ubnstr) uartbnfifo control register 0 (ubnfic0) uartbnfifo control register 1 (ubnfic1) uartbnfifo control register 2 (ubnfic2) uartbnfifo status register 0 (ubnfis0) uartbnfifo status register 1 (ubnfis1) ubnrx receive fifon timeout counter sampling block receive controller transmit controller baud rate generator n reception unit transmission unit baud rate generator n transmit shift register ubntx transmit fifon intubntito txdbn intubntif intubntit intubntir intubntire f xx /2 remark 1. fxx: main clock frequency 2. for the configuration of the baud rate generator, see figure 16-10 . 3. n = 0, 1 uartbn consists of the following hardware units. table 16-1. configuration of uartbn item configuration registers uartbn control register 0 (ubnctl0) uartbn control register 2 (ubnctl2) uartbn status register (ubnstr) uartbn fifo control register 0 (ubnfic0) uartbn fifo control register 1 (ubnfic1) uartbn fifo control register 2 (ubnfic2) uartbn fifo status register 0 (ubnfis0) uartbn fifo status register 1 (ubnfis1) receive shift register uartbn receive data register ap (ubnrxap) uartbn receive data register (ubnrx) transmit shift register uartbn transmit data register (ubntx) v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 736 of 1817 sep 19, 2011 (1) uartbn control register 0 (ubnctl0) this register controls the transfer operation of uartbn. (2) uartbn status register (ubnstr) this register indicates the transfer status during transmission and the contents of a receptio n error. the status flag of this register, which indicates the transfer status during transmission, i ndicates the data ret ention status of the transmit shift register and the transmit data register (t he ubntx register in the single mode or transmit fifo in the fifo mode). each reception error flag is set to 1 when a reception error occurs, and cleared to 0 when 0 is written to the ubnstr register. (3) uartbn control register 2 (ubnctl2) this register is used to specify the division ratio by which to control the baud rate (serial transfer speed) of uartbn. (4) uartbn fifo contro l register 0 (ubnfic0) this register is used to select the operation mode of uartbn, clear the tran smit fifo/receive fifo that becomes valid in the fifo mode, and specify the timing mode in which the transmi ssion enable interrupt request signal (intubntit)/reception en d interrupt request signal (intubntir) occurs. (5) uartbn fifo contro l register 1 (ubnfic1) this register is valid in the fifo m ode. it generates a reception timeout in terrupt request signal (intubntito) if data is stored in the receive fifo w hen the next data does not come (start bi t is not detected) even after the reception wait time of the next data has el apsed after the stop bit has been received. (6) uartbn fifo contro l register 2 (ubnfic2) this register is valid in the fifo m ode. it is used to set the timing to generate the transmission enable interrupt request signal (intubntit)/recepti on end interrupt request signal (int ubntir), using t he number of data transmitted or received as a trigger. (7) uartbn fifo status register 0 (ubnfis0) this register is valid in the fifo mode. the number of bytes of data stored in the rece ive fifo can be read from this register. (8) uartbn fifo status register 1 (ubnfis1) this register is valid in the fifo mode. the number of empty bytes of t he transmit fifo can be read from this register. (9) receive shift register this is a shift register that converts the serial data that was input to the rxdb n pin into parallel data. one byte of data is received, and if a stop bit is detected, the rece ived data is transferred to the receive data register. this register cannot be directly manipulated. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 737 of 1817 sep 19, 2011 (10) uartbn receive data register ap (ubnrx ap), uartbn receive data register (ubnrx) the receive data register holds receive data. in the single mode, the 8-bit 1-stage ubnrx register is used. the 16-bit 16-stage receive fifo (ubnrxap regist er) is used in the fifo mode. the receive data is stored in the lower 8 bits of the receive fifo (ubnrxap register) and the er ror information of the received data is stored in the higher 8 bits (bit 8 and bit 9). if a reception error (such as a parity error or a framing error) occurs in the fifo mode, the error data can be identified by reading the ubnrxap register in 16- bit (halfword) units (error information is appended as ubnp ef bit = 1 or ubnfef bit = 1). when the lower 8 bits of the ubnrxap register are read in 8-bi t (byte) units, the higher 8 bits are di scarded. therefore, if no error has occurred, only the receive dat a of the ubnrxap register c an be read successively by being read in 8-bit (byte) units in the same way as the ubnrx register. when 7-bit length data is received with the lsb first, the re ceived data is transferred to bits 6 to 0 of the receive data register from the lsb (bit 0), wit h the msb (bit 7) always being 0. w hen data is received with the msb first, the received data is transferred to bits 7 to 1 of the rece ive data register from the msb (bit 7), with the lsb (bit 0) always being 0. if an overrun error occurs, the receive data at that time is not tran sferred to the receive data register. while reception is enabled, the received data is transferr ed from the receive shift r egister to the receive data register, in synchronization with the shift-in processing of one frame. a reception end interrupt request signa l (intubntir) is generated by transferri ng the data to the ubnrx register in the single mode, or transferring t he number of receive data set as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits to receive fifo in the fifo m ode. if data is stored in re ceive fifo when the next data does not come (start bit is not detect ed) after the next data reception wait ti me specified by the ubnfic1.ubntc4 to ubnfic1.ubntc0 bits has elapsed in the fifo mode, a reception timeout interrupt request signal (intubntito) is generated. (11) transmit shift register this is a shift register that converts the parallel data that was transferred from the transmit data register into serial data. when one byte of data is transferred from the transmit data register, the transmit shift register data is output from the txdbn pin. this register cannot be directly manipulated. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 738 of 1817 sep 19, 2011 (12) uartbn transmit data register (ubntx) the transmit data register is a buffer for transmit data. the 8-bit 1-stage ubntx register is used as this buffer in the single mode. in the fifo mode, the 8-bit 16-stage transmit fifo is used. when 7-bit length data is transmitted with the lsb first, bits 6 to 0 of the transmit data re gister are transmitted as the transmit data from the lsb (bit 0) with the msb (bit 7) always being 0. when data is transmitted with the msb first, bits 7 to 1 of the transmit data register are transmi tted as the transmit data from the msb (bit 7) with the lsb (bit 0) always being 0. in the single mode, transmission is star ted by writing transmit data to the ub ntx register while transmission is enabled (ubnctl0.ubntxe bit = 1). when writing the tr ansmit data to the ubntx register is enabled (when 1- byte data is transferred from the ubnt x register to the transmit shift regi ster), a transmission enable interrupt request signal (intub ntit) is generated. in the fifo mode, transmission is start ed by writing at least the number of tr ansmit data set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits and 16 bytes or less to transmit fifo and then enabling transmission (ubntxe bit = 1). when the number of transmit data set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits have been transferred from transmit fifo to the transmit shift register (transmit data of the number set as the trigger can be written), a transmiss ion enable interrupt request signal (intubntit) is generated. in the fifo mode, a fi fo transmission enable interrupt reques t signal (intubntif) is generated when there is no more data in transmit fifo and the trans mit shift register (when fifo and the register become empty). (13) timeout counter this counter is used to recognize that data exists (rema ins) in receive fifo when the number of received data does not reach the number set as the tr igger by the ubnfic2.ubnrt3 to ubnf ic2.ubnrt0 bits, and is valid only in the fifo mode. if data is stored in receive fifo when the next data does not come (start bi t is not detected) after the next data reception wait time specified by t he ubnfic1.ubntc4 to ubnfic1.ubntc0 bits has elapsed after the stop bit has been received, a reception timeout interrupt request signal (intubntito) is generated. (14) sampling block this block samples the rxdbn signal at the rising edge of the peripheral clock (f xx ). if the same sampling value is detected two times, output of the match detector changes, and the value is sampled as input data. data of less than one clock width is judged as noise and is not transmitted to the internal circuitry. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 739 of 1817 sep 19, 2011 16.3 switching between uartb and other serial interface modes in the v850es/jh3-e and v850es/jj3-e, rxdb0 and txdb0 for uartb0 are each assigned to two pins, as shown in table 16-2. when using uartb0 in the v850es/jh3-e, use pins 32 and 31 or pins 109 and 108 as a set. do not use pins 32 and 108 or pins 109 and 31 simultaneously. when using uartb0 in the v850es/jj3-e, use pins 32 and 31 or pins 115 and 114 as a set. do not use pins 32 and 114 or pins 115 and 31 simultaneously table 16-2. pin assignment in uartb0 function pin number function v850es/jh3-e v850es/jj3-e alternate function 32 32 p34/sof4/tiaa20/toaa20 rxdb0 109 115 pdh4/a20/sof4 31 31 p33/sif4/tiaa11/toaa11 txdb0 108 114 pdh3/a19/sif4 16.3.1 using uartb0 and csif4 at the same time in the v850es/jh3-e and v850es/jj3-e, uartb0 and csif4 share the same pin in port 3. these function therefore cannot be used at the same time. to switch between uartb0 and csif4, the pmc3, pfc3, and pfce3 registers or the pmdh, pmcdh, and pmfedh registers must be set in advance. figure 16-2 shows an example of port settings when using uartb0 via port 3 and csif4 via port hd. caution the operations related to tr ansmission and reception of uartb0 or csif4 are not guaranteed if the mode is switched during transmissi on or reception. be sure to disable the unit that is not used. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 740 of 1817 sep 19, 2011 figure 16-2. mode switch settings of uartb0 and csif4 (1) uartb0 settings (2) csif4 settings pmcdh pmcdh7 pmcdh6 pmcdh5 1 pmcdh4 pmcdh3 11 sckf4 sof4 sif4 pmcdh2 pmcdh1 pmcdh0 pfcdh pfcdh5 pfcdh4 pfcdh3 11 pfcdh2 pfcdh1 pfcdh0 1 sckf4 sof4 sif4 pfcedh pfcedh4 pfcedh3 00 sof4 sif4 pfce3 pfce37 pfce36 pfce35 pfce34 pfce33 00 pfce32 pfce31 pfce30 rxdb0 txdb0 pfc3 pfc37 pfc36 pfc35 pfc34 pfc33 11 pfc32 pfc31 pfc30 rxdb0 txdb0 pmc3 pmc37 pmc36 pmc35 pmc34 pmc33 11 pmc32 pmc31 pmc30 rxdb0 txdb0 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 741 of 1817 sep 19, 2011 16.3.2 switching between uartb1 and csif3 mode in the v850es/jh3-e and v850es/jj3-e, uartb1 and csif3 shar e the same pin, so thes e functions cannot be used at the same time. to switch between uartb1 and csif 3, the pmc9, pfc9, and pfce9 registers must be set in advance. caution the operations related to tr ansmission and reception of uartb1 or csif3 are not guaranteed if the mode is switched during transmissi on or reception. be sure to disable the unit that is not used. figure 16-3. mode switch settings of uartb1 and csif3 pmc9 (pmc9h) (pmc9l) (pfc9l) (pfce9l) after reset: 0000h r/w address: pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h) after reset: 0000h r/w address: pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 pfce913 0 pfce911 pfce910 pfce99 pfce98 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 (pfce9h) after reset: 0000h r/w address: port i/o mode sof3 (csif3) rxdb1 (uartb1) pmc914 0 1 1 port i/o mode pfce914 0 0 pfc914 0 1 port i/o mode sif3 (csif3) txdb1 (uartb1) pmc913 0 1 1 port i/o mode pfce913 0 0 pfc913 0 1 port i/o mode sckf3 (csif3) pmc915 0 1 operation mode pfce915 0 pfc915 0 pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h remark x = don?t care v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 742 of 1817 sep 19, 2011 16.4 control registers (1) uartbn control register 0 (ubnctl0) the ubnctl0 register controls t he transfer operations of uartbn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. cautions 1. when using uartbn, set the external pins related to the uartbn fu nction in the alternate- function mode, set uartbn cont rol register 2 (ubnctl2). then set the ubnpwr bit to 1 before setting the other bits. 2. be sure to input a high level to the rxdbn pin when setting the external pins related to the uartbn function in the alternate -function mode. if a low level is input, it is judged that a falling edge is input after the ubnrxe bit has b een set to 1, and reception may be started. remarks 1. when reception is disabled, the receive shift regi ster does not detect a start bit. no shift-in processing or transfer processing to the receive dat a register is performed, and the contents of the receive data register are retained. when reception is enabled, the receive shift operation starts, in synchronization with the detection of the start bit, and when the reception of one fram e is completed, the contents of the receive shift register are transferred to the receive data register. a reception end interrupt request signal (intub ntir) is also generated, in synchronization with the transfer to the receive data register (in fifo m ode, transfer triggered by reaching set number of receive data). if data is stored in receive fifo when the next data does not come (start bit is not detected) after the next data reception wait time specified by the ubnfic1.ubntc4 to ubnfic1.ubntc0 bits has elapsed in the fifo mode, a reception timeout inte rrupt request signal (intubntito) is generated. 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 743 of 1817 sep 19, 2011 (1/2) ubnpwr ubnctl0 (n = 1, 0) ubntxe ubnrxe ubndir ubnps1 ubnps0 ubncl ubnsl 32 1 after reset: 10h r/w address: ub0ctl0 fffffb80h, ub1ctl0 fffffba0h 0 <4> <5> <6> <7> transmission is disabled transmission is enabled ubntxe 0 1 transmission enable ? on startup, set the ubnpwr bit to 1 and then set the ubntxe bit to 1. to stop transmission, clear the ubntxe bit to 0 and then the ubnpwr bit to 0. ? when the transmission unit status is to be initialized, the transmission status may not be able to be initialized unless the ubntxe bit is set to 1 again after an interval of two cycles of f xx has elapsed since the ubntxe bit was cleared to 0. stops supply of clocks to uartbn supplies clocks to uartbn ubnpwr 0 1 operation clock control to uartbn ? when the ubnpwr bit is cleared to 0, the uartbn can be asynchronously reset. ? when the ubnpwr bit = 0, uartbn is in a reset state. therefore, to operate uartbn, the ubnpwr bit must be set to 1. ? when the ubnpwr bit is changed from 1 to 0, all registers of uartbn are initialized. when the ubnpwr bit is set to 1 again, the uartbn registers must be set again. ? the txdbn pin output is high level when the ubnpwr bit is cleared to 0. reception is disabled reception is enabled ubnrxe 0 1 reception enable ? on startup, set the ubnpwr bit to 1 and then set the ubnrxe bit to 1. to stop reception, clear the ubnrxe bit to 0 and then the ubnpwr bit to 0. ? when the reception unit status is to be initialized, the reception status may not be able to be initialized unless the ubnrxe bit is set to 1 again after an interval of two cycles of f xx has elapsed since the ubnrxe bit was cleared to 0. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 744 of 1817 sep 19, 2011 (2/2) msb transfer first lsb transfer first ubndir 0 1 specification of transfer direction mode (msb/lsb) ? clear the ubnpwr bit or ubntxe and ubnrxe bits to 0 before rewriting the ubndir bit. do not output a parity bit output 0 parity output odd parity output even parity receive with no parity receive as 0 parity judge as odd parity judge as even parity ubnps1 0 0 1 1 parity selection during transmission parity selection during reception ubnps0 0 1 0 1 ? clear the ubntxe and ubnrxe bits to 0 before overwriting the ubnps1 and ubnps0 bits. ? if ?0 parity? is selected for reception, no parity judgment is made. therefore, no error interrupt is generated because the ubnstr.ubnpe bit is not set to 1. 7 bits 8 bits ubncl 0 1 specification of data character length of 1-frame transmit/receive data clear the ubntxe and ubnrxe bits to 0 before overwriting the ubncl bit. 1 bit 2 bits ubnsl 0 1 specification of stop bit length of transmit data ? clear the ubntxe bit to 0 before overwriting the ubnsl bit. ? since reception always operates by using a single stop bit length, the ubnsl bit setting does not affect receive operations. remark for details of parity, see 16.7.6 parity types and corresponding operation . v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 745 of 1817 sep 19, 2011 (2) uartbn status register (ubnstr) the ubnstr register indicates the tr ansfer status and reception error content s while uartbn is transmitting data. the status flag that indicates the tr ansfer status during transmission indicate s the data retention status of the transmit shift register and transmit data register (the ubntx register in the single mode or transmit fifo in the fifo mode). the status flag that indicates a recept ion error holds its status until it is cleared to 0. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution when the ubnctl0.ubn pwr bit or ubnctl0.ubnrxe bit is set to 0, or when 0 is written to the ubnstr register, the ubnstr.ubnovf, ubnstr.ubnpe, ubnstr.ubnfe, and ubnstr.ubnove bits ar e cleared to 0. (1/2) ubntsf ubnstr (n = 0, 1) 0 0 0 ubnovf ubnpe ubnfe ubnove <3> <2> <1> after reset: 00h r/w address: ub0str fffffb84h, ub1str fffffba4h <0> 4 5 6 <7> overflow did not occur. overflow occurred (during reception). ? in single mode (ubnfic0.ubnmod bit = 0) data to be transferred to the transmit shift register and ubntx register does not exist (cleared (0) when ubnctl0.ubnpwr bit = 0 or ubnctl0.ubntxe bit = 0). ? in fifo mode (ubnfic0.ubnmod bit = 1) data to be transferred to the transmit shift register and transmit fifo does not exist (cleared (0) when ubnctl0.ubnpwr bit = 0 or ubnctl0.ubntxe bit = 0). ? in single mode (ubnfic0.ubnmod bit = 0) data to be transferred to the transmit shift register or ubntx register exists (transmission in progress). ? in fifo mode (ubnfic0.ubnmod bit = 1) data to be transferred to the transmit shift register and transmit fifo exists (transmission in progress). ubnovf 0 1 overflow flag ? the ubnovf bit is valid only in the fifo mode (when ubnfic0.ubnmod bit = 1), and invalid in the single mode (when ubnfic0.ubnmod bit = 0). ? if an overflow occurs, the received data is not written to receive fifo but discarded. the value of the ubntsf bit is reflected after two periods of f xx have elapsed, after the transmit data is written to the ubntx register. therefore, exercise care when referencing the ubntsf bit after transmit data has been written to the ubntx ubntsf 0 1 transfer status flag v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 746 of 1817 sep 19, 2011 (2/2) parity error did not occur. parity error occurred (during reception). ubnpe 0 1 parity error flag ? the ubnpe bit is valid only in the single mode (when ubnfic0.ubnmod bit = 0), and invalid in the fifo mode (when ubnfic0.ubnmod bit = 1). ? the operation of the ubnpe bit differs according to the settings of the ubnctl0.ubnps1 and ubnctl0.ubnps0 bits. framing error did not occur. framing error occurred (during reception). ubnfe 0 1 framing error flag ? the ubnfe bit is valid only in the single mode (when ubnfic0.ubnmod bit = 0), and invalid in the fifo mode (when ubnfic0.ubnmod bit = 1). ? only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. overrun error did not occur. overrun error occurred (during reception). ubnove 0 1 overrun error flag ? the ubnove bit is valid only in the single mode (when ubnfic0.ubnmod bit = 0), and invalid in the fifo mode (when ubnfic0.ubnmod bit = 1). ? when an overrun error occurs, the next receive data value is not written to the ubnrx register and the data is discarded. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 747 of 1817 sep 19, 2011 (3) uartbn control register 2 (ubnctl2) the ubnctl2 register is used to spec ify the division ratio by which to cont rol the baud rate (serial transfer speed) of uartbn. this register can be read or written in 16-bit units. reset sets this register to ffffh. caution when rewriting the ubnbrs 15 to ubnbrs0 bits of this regi ster, set the ubnctl0.ubntxe and ubnctl0.ubnrxe bits to 0 or clear the ubnctl0.ubnpwr bit to 0. ubnbrs15 ubnctl2 (n = 0, 1) ubnbrs14 ubnbrs13 ubnbrs12 ubnbrs11 ubnbrs10 ubnbrs9 ubnbrs8 11 10 9 after reset: ffffh r/w address: ub0ctl2 fffffb82h, ub1ctl2 fffffba2h 8 12 13 14 15 ubnbrs7 ubnbrs6 ubnbrs5 ubnbrs4 ubnbrs3 ubnbrs2 ubnbrs1 ubnbrs0 321 0 4 5 6 7 remark for the ubnbrs15 to ubnbrs0 bits, see table 16-3 division value of 16-bit counter . table 16-3. division value of 16-bit counter ubn brs 15 ubn brs 14 ubn brs 13 ubn brs 12 ubn brs 11 ubn brs 10 ubn brs 9 ubn brs 8 ubn brs 7 ubn brs 6 ubn brs 5 ubn brs 4 ubn brs 3 ubn brs 2 ubn brs 1 ubn brs 0 k output clock selected 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x ? setting prohibited 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 f uclk /k 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 5 f uclk /k 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 6 f uclk /k ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 65530 f uclk /k 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 65531 f uclk /k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 65532 f uclk /k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 65533 f uclk /k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 65534 f uclk /k 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 65535 f uclk /k remarks 1. f uclk : peripheral clock (fxx/2) 2. k: value set by the ubnctl2.ubnbrs15 to ub nctl2.ubnbrs0 bits (k = 4, 5, 6, ?, 65535) 3. x: don?t care v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 748 of 1817 sep 19, 2011 (4) uartbn transmit data register (ubntx) the ubntx register is used to set trans mit data. it functions as the 8-bit 1-stage ubntx register, in the single mode (ubnfic0.ubnmod bit = 0), and as the 8-bit 16-stage transmit fifo in the fifo mode (ubnfic0.ubnmod bit = 1). in the single mode, transmission is started by writing transmit data to the ubntx register when transmission is enabled (ubnctl0.ubntxe bit = 1). when data can be wr itten to the ubntx register (when 1 byte of data is transferred from the ubntx register to the transmit shift register), a transmission enable interrupt request signal (intubntit) is generated. in the fifo mode, transmission is star ted by enabling transmission (ubntxe bit = 1) after writing at least the number of transmit data set as the trig ger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits and 16 bytes or less to transmit fifo. when the number of transmit data set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits have been transferred from transmit fifo to the transmit shift register (transmit data of the number set as the trigger can be written to transmit fifo), a transmission enable interrupt request signal (intubntit) is generated. in the fi fo mode, a fifo transmission enable in terrupt request signal (intubntif) is generated when there is no more data in transmit fi fo and the transmit shift register (when the fifo and register become empty). for the generation timing of the interrupt, see 16.5 interrupt request signals . when 7-bit length data is transmitted with the lsb first, bits 6 to 0 of the transmit data re gister are transmitted as the transmit data from the lsb (bit 0) with the msb (bit 7) always being 0. when data is transmitted with the msb first, bits 7 to 1 of the transmit data register are transmi tted as the transmit data from the msb (bit 7) with the lsb (bit 0) always being 0. this register is write-only in 8-bit units. data is written to the transmit data register. reset sets this register to ffh. ubntd7 ubntx (n = 0, 1) ubntd6 5 ubntd5 ubntd4 3 ubntd3 2 ubntd2 1 ubntd1 ubntd0 0 4 6 7 after reset: ffh w address: ub0tx fffffb88h, ub1tx fffffba8h v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 749 of 1817 sep 19, 2011 (5) uartbn receive data register ap (ubnrx ap), uartbn receive data register (ubnrx) these registers store paralle l data converted by the receive shift r egister. they function as the 8-bit 1-stage ubnrx register, in the single mode (ubn fic0.ubnmod bit = 0), and as the 16-bit 16-stage receive fifo (ubnrxap register) in the fifo m ode (ubnfic0.ubnmod bit = 1). the receive data is stored in the lower 8 bits of the receive fifo (ubnrxap register) and the er ror information of the received data is stored in the higher 8 bits (bit 8 and bit 9). if a reception error (such as a parity error or a framing error) occurs in the fifo mode, the ubnrxap register is read in 16-bit (halfword) units. in this way, the flag of the data stored in receive fifo can be checked (error information is appended as ubnpef bit = 1 or ubnfef bit = 1), so that the error data can be recogn ized (when the lower 8 bits of the ubnrxap register are read in 8-bit (byte) units, the higher 8 bits are discarded. therefore, if no error has occurred, the receive data of the ubnrxap register can be read successively by being read in 8-bit (byte) units in the same way as the ubnrx register). if reception is enabled (ubnctl0.ubnrxe bit = 1), the receiv e data is transferred from the receive shift register to the receive data register, in synchronization with the co mpletion of the shift-in processing of one frame. by transferring the receive data to the ubnrx register in the single mode or by trans ferring the number of receive data set as the trigger by the ubnfic2.ubnrt3 to ubnfic 2.ubnrt0 bits to the receiv e fifo in the fifo mode, a reception end interrupt request signal (intubntir) is generated. if data is stored in receive fifo when the next data does not come (start bit is not detected) even after t he next data reception wait time specified by the ubnfic1.ubntc4 to ubnfic1.ubntc0 bi ts has elapsed in the fifo mode, a reception timeout interrupt request signal (intubntito) is generated. for information about the timing for gener ating these interrupt requests, see 16.5 interrupt request signals . if data is received with the lsb first when the data length is specified as 7 bits , the received data is transferred to bits 6 to 0 of the receive data register from the lsb (bit 0), with the msb (bit 7) always being 0. if data is received with the msb first, it is transferred to bi ts 7 to 1 of the receive data register from the msb (bit 7) with the lsb (bit 0) always being 0. however, if an overrun error occurs, the receive data at that time is not transferred to the receive data register. the ubnrxap register is read-only in 16-bit units. howe ver, the lower 8 bits of the ubnrxap register are read- only in 8-bit units. the ubnrx register is read-only in 8-bit units. in addition to reset input, the value of these registers c an be set to ffh in the single mode or to 00ffh in the fifo mode, by clearing the ubnctl0.ubnpwr bit to 0. cautions 1. the ubnpef and ub nfef bits cannot be read becau se these registers serve as 8-bit registers in the single mode. 2. when no reception error has occurred in the fi fo mode, the receive data of the ubnrxap register can be read successivel y by reading the lower 8 bits of the ubnrxap register in 8- bit (byte) units. an 8-bit access to the higher 8 bits is prohibi ted. if they are accessed, the operation is not guaranteed. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 750 of 1817 sep 19, 2011 cautions 3. do not perform the following operations when debugg ing a system that uses the single mode. ? setting a break for an instruction immediat ely after the ubnrx register is read ? setting a break before dma transfer with the ubnrx register specified as the transfer source is ended ? setting a break before end of reception of the next data after reception of data and reading the ubnrx register, a nd checking the ubnrx register in the i/o register window of the debugger if any of these operations is performed, an overrun error may occur during the subsequent reception. no framing error framing error occurs (wheng reception completed). ubnfef 0 1 framing error flag ? the ubnfef bit is valid only in the fifo mode (ubnfic0.ubnmod bit = 1), and is invalid in the single mode (ubnfic0.ubnmod bit = 0). ? only the first bit of the stop bits of the receive data is checked, regardless of the stop bit length. no parity error parity error occurs (when reception completed). ubnpef 0 1 parity error flag ? the ubnpef bit is valid only in the fifo mode (ubnfic0.ubnmod bit = 1), and is invalid in the single mode (ubnfic0.ubnmod bit = 0). ? the operation of the ubnpef bit differs depending on the set values of the ubnctl0.ubnps1 and ubnctl0.ubnps0 bits. stores receive data. ubnrd7 to ubnrd0 2 ubnrd2 3 ubnrd3 4 ubnrd4 5 ubnrd5 6 ubnrd6 7 ubnrd7 1 ubnrd1 0 ubnrd0 ubnrx after reset: ffh r address: ub0rx fffffb86h, ub1rx fffffba6h 0 ubnrxap (n = 0, 1) (n = 0, 1) 00000 ubnpef ubnfef 11 10 9 after reset: 00ffh r address: ub0rxap fffffb86h, ub1rxap fffffba6h 8 12 13 14 15 321 0 4 5 6 7 ubnrd7 ubnrd6 ubnrd5 ubnrd4 ubnrd3 ubnrd2 ubnrd1 ubnrd0 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 751 of 1817 sep 19, 2011 (6) uartbn fifo contro l register 0 (ubnfic0) the ubnfic0 register is used to select the operation mode of uartbn and t he functions that become valid in the fifo mode (ubnmod bit = 1). in the fifo mode, it cl ears transmit fifo/receive fifo and specifies the timing mode in which the transmission enable interrupt request signal (intubntit)/recept ion end interrupt request signal (intubntir) is generated. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. (1/2) ubnmod ubnfic0 (n = 0, 1) 0 0 0 ubntfc ubnrfc ubnitm ubnirm <3> <2> 1 after reset: 00h r/w address: ub0fic0 fffffb8ah, ub1fic0 fffffbaah 0 4 5 6 <7> normal status clear (this bit automatically returns to 0 after transmit fifo is cleared.) ubntfc 0 1 transmit fifo clear trigger bit ? the ubntfc bit is valid only in the fifo mode (ubnmod bit = 1), and is invalid in the single mode (ubnmod bit = 0). ? when 1 is written to the ubntfc bit, the pointer to transmit fifo is cleared to 0. in the pending mode (ubnitm bit = 0), the interrupt request signal (intubntit) held pending is cleared note . however, bit 7 (ubntitif) of the interrupt control register (ubntitic) is not cleared to 0. clear this bit to 0 as necessary. when 0 is written to the ubntfc bit, the status is retained. no operation, such as clearing or setting, is executed. ? when writing 1 to the ubntfc bit, be sure to clear the ubnctl0.ubntxe bit to 0 (disabling transmission). if 1 is written to the ubntfc bit when the ubntxe bit is 1 (transmission enabled), the operation is not guaranteed. single mode fifo mode ubnmod 0 1 specification of uartbn operation mode note after transmit fifo is cleared (ubntfc bit = 1), acce ssing the registers related to uartbn is prohibited for the duration of four cycles of f xx or until clearing the ubntfc bit (aut omatic recovery) is confirmed by reading the ubnfic0 register. if these registers are accessed, the operat ion is not guaranteed. remark f xx : peripheral clock v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 752 of 1817 sep 19, 2011 (2/2) normal status clear (this bit automatically returns to 0 after receive fifo is cleared.) ubnrfc 0 1 receive fifo (ubnrxap) clear trigger bit in the fifo mode, the intubntit signal is generated as soon as transmit data of the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits have been transferred from transmit fifo to the transmit shift register. after the intubntit signal request has been generated, specify the timing of actually generating the intubntit signal as the pending mode or pointer mode. for details, see 16.6 (2) pending mode/pointer mode . pending mode pointer mode ubnitm 0 1 specification of intubntit interrupt generation timing in fifo mode pending mode pointer mode ubnirm 0 1 specification of intubntir interrupt generation timing in fifo mode ? the ubnrfc bit is valid only in the fifo mode (ubnmod bit = 1), and is invalid in the single mode (ubnmod bit = 0). ? when 1 is written to the ubnrfc bit, the pointer to receive fifo is cleared to 0. in the pending mode (ubnirm bit = 0), the interrupt request signal (intubntir) held pending is cleared note . however, bit 7 (urif) of the interrupt control register (uric) is not cleared to 0. clear this bit to 0 as necessary. when 0 is written to the ubnrfc bit, the status is retained. no operation, such as clearing or setting, is executed. ? when writing 1 to the ubnrfc bit, be sure to clear the ubnctl0.ubnrxe bit to 0 (disabling reception). if 1 is written to the ubnrfc bit when the ubnrxe bit is 1 (reception enabled), the operation is not guaranteed. in the fifo mode, the intubntir signal is generated as soon as receive data of the number set as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits have been transferred from the receive shift register to receive fifo. after the intubntir signal request has been generated, specify the timing of actually generating the intubntir signal as the pending mode or pointer mode. for details, see 16.6 (2) pending mode/pointer mode . note after receive fifo (ubnrxap) is cleared (ubnrfc bit = 1), accessing the registers related to uartbn is prohibited for the dura tion of four cycles of f xx or until clearing the ubnrfc bit (automatic recovery) is confirmed by reading the ubnfic0 register. if thes e registers are accessed, the operation is not guaranteed. remark f xx : peripheral clock v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 753 of 1817 sep 19, 2011 (7) uartbn fifo contro l register 1 (ubnfic1) the ubnfic1 register is valid in t he fifo mode (ubnfic0.ubnmod bit = 1) . it generates a reception timeout interrupt request signal (intubntito) if data is stored in receive fifo w hen the next data does not come (start bit is not detected) after the lapse of the time set by the ubntc4 to ubntc0 bits (next data reception wait time), after the stop bit has been received. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. ubntce ubnfic1 (n = 0, 1) 0 0 ubntc4 ubntc3 ubntc2 ubntc1 ubntc0 654321 after reset: 00h r/w address: ub0fic1 fffffb8bh, ub1fic1 fffffbabh 7 0 32 bytes (32 8/baud rate) 31 bytes (31 8/baud rate) 30 bytes (30 8/baud rate) 29 bytes (29 8/baud rate) ? ? ? 4 bytes (4 8/baud rate) 3 bytes (3 8/baud rate) 2 bytes (2 8/baud rate) 1 byte (1 8/baud rate) ubntc3 0 0 0 0 ? ? ? 1 1 1 1 ubntc4 0 0 0 0 ? ? ? 1 1 1 1 next data reception wait time ubntc2 0 0 0 0 ? ? ? 1 1 1 1 ubntc1 0 0 1 1 ? ? ? 0 0 1 1 disable use of timeout counter function. enable use of timeout counter function. ubntce 0 1 specification of timeout counter function disable/enable when counting up of the reception wait time, set by the ubntc4 to ubntc0 bits, is complete, the count value of the timeout counter is cleared to 0, regardless of the status of the data stored in receive fifo. when the next start bit is later detected, counting is started again from the stop bit of that data. ubntc0 0 1 0 1 ? ? ? 0 1 0 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 754 of 1817 sep 19, 2011 (8) uartbn fifo contro l register 2 (ubnfic2) the ubnfic2 register is valid in t he fifo mode (ubnfic0.ubnmod bit = 1). it sets the timing of generating an interrupt, using the number of transmit/receive data as a trigger. when data is trans mitted, the number of data transferred from transmit fifo is specified as the condit ion of generating the interrupt. when data is received, the number of data stored in receive fifo is spec ified as the interrupt generation condition. this register can be read or written in 16-bit units. when the higher 8 bits of the ubnfic 2 register can be used as the ubnfic2h register and the lower 8 bits, as the ubnfic2l register, thes e registers can be read or written in 8-bit units. reset sets the ubnfic2 register to 0000h and the ubnfic2h and ubnfic2l registers to 00h. caution be sure to set the ubnct l0.ubntxe bit (to disable transmi ssion) and ubnctl0.ubnrxe bit (to disable reception) to 0 before writ ing data to the ubnfic2 register . if data is written to the ubnfic2 register with the ubntxe or ubnrxe bit set to 1, the operation is not guaranteed. (1/2) ubntt2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ubntt3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ubntt1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ubntt0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes pointer mode pending mode ? set the number of transmit fifo transmit data to be the trigger. ? each time data of the specified number has shifted out from transmit fifo to the transmit shift register, the intubntit signal is generated. in the pending mode (ubnfic0.ubnitm bit = 0), the intubntit signal is generated under the conditions of the pending mode. ? in the pointer mode (ubnfic0.ubnitm bit = 1), the number of transmit data set as the trigger can be only 1 byte (ubntt3 to ubntt0 bits = 0000), and other settings are prohibited. if a setting of other than 1 byte is made, the operation is not guaranteed. settable setting prohibited settable number of data of transmit fifo set as trigger 0 ubnfic2h (n = 0, 1) ubnfic2l (n = 0, 1) 0 0 0 ubntt3 ubntt2 ubntt1 ubntt0 11 10 9 8 12 13 14 15 0 0 0 0 ubnrt3 ubnrt2 ubnrt1 ubnrt0 3210 4 5 6 7 after reset: 0000h r/w address: ub0fic2 fffffb8ch, ub0fic2l fffffb8ch, ub0fic2h fffffb8dh, ub1fic2 fffffbach, ub1fic2l fffffbach, ub1fic2h fffffbadh v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 755 of 1817 sep 19, 2011 (2/2) ubnrt2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ubnrt3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ubnrt1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ubnrt0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes ? set the number of receive fifo receive data to be the trigger. ? each time data of the specified number has been stored from the receive shift register to receive fifo, the intubntir interrupt is generated. in the pending mode (ubnfic0.ubnirm bit = 0), the intubntir signal is generated under the conditions of the pending mode. ? in the pointer mode (ubnfic0.ubnirm bit = 1), the number of receive data set as the trigger can be only 1 byte (ubnrt3 to ubnrt0 bits = 0000), and other settings are prohibited. if a setting of other than 1 byte is made, the operation is not guaranteed. pointer mode pending mode settable setting prohibited settable number of data of transmit fifo set as trigger v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 756 of 1817 sep 19, 2011 (9) uartbn fifo status register 0 (ubnfis0) the ubnfis0 register is valid in t he fifo mode (ubnfic0.ubnmod bit = 1). it is used to read the number of bytes of the data stored in receive fifo. this register is read-only in 8-bit units. reset sets this register to 00h. 0 ubnfis0 (n = 0, 1) 0 0 ubnrb4 ubnrb3 ubnrb2 ubnrb1 ubnrb0 654321 after reset: 00h r address: ub0fis0 fffffb8eh, ub1fis0 fffffbaeh 7 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes invalid ubnrb3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 ubnrb4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 receive fifo pointer ubnrb2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ubnrb1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ubnrb0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 other than above indicates the number of bytes (readable bytes) of the data stored in receive fifo as a receive fifo pointer. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 757 of 1817 sep 19, 2011 (10) uartbn fifo status register 1 (ubnfis1) the ubnfis1 register is valid in the fifo mode (ubnfic0.ubnmod bit = 1). this register can be used to read the number of empty bytes of transmit fifo. this register is read-only in 8-bit units. reset sets this register to 10h. caution the values of the ubntb4 to ubntb0 bits are re flected after transmit data has been written to the ubntx register and then time of two cycles of the peripheral clock (f xx ) has passed. therefore, care must be exercised when referenci ng the ubnfis1 register after transmit data has been written to the ubntx register. 0 ubnfis1 (n = 0, 1) 0 0 ubntb4 ubntb3 ubntb2 ubntb1 ubntb0 654321 after reset: 10h r address: ub0fis1 fffffb8fh, ub1fis1 fffffbafh 7 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 9 bytes 10 bytes 11 bytes 12 bytes 13 bytes 14 bytes 15 bytes 16 bytes invalid ubntb3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 ubntb4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 transmit fifo pointer ubntb2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 ubntb1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ubntb0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 setting prohibited indicates the number of empty bytes of transmit fifo (bytes that can be written) as a transmit fifo pointer. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 758 of 1817 sep 19, 2011 16.5 interrupt request signals the following five types of interrupt requests are generated from uartbn. ? reception error interrupt request signal (intubntire) ? reception end interrupt request signal (intubntir) ? transmission enable interrupt request signal (intubntit) ? fifo transmission end interrupt request signal (intubntif) ? reception timeout interrupt request signal (intubntito) the default priorities among these five ty pes of interrupt requests is, from high to low, reception error interrupt request signal, reception end interrupt request signal, transmissi on enable interrupt request signal, fifo transmission end interrupt request signal, and reception timeout interrupt request signal. table 16-4. generated inte rrupts and default priorities interrupt priority reception error 1 reception end 2 transmission enable 3 fifo transmission end 4 reception timeout 5 (1) reception error interrupt request signal (intubntire) (a) single mode when reception is enabled, a reception error interrupt r equest signal is generated according to the logical or of the three types of reception erro rs (parity error, framing error, ov errun error) explained for the ubnstr register. when reception is disabled, no reception erro r interrupt request signal is generated. (b) fifo mode when reception is enabled, a reception error interrupt r equest signal is generated according to the logical or of the three types of reception erro rs (parity error, framing error, ov erflow error) explained for the ubnstr register. when reception is disabled, no reception erro r interrupt request signal is generated. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 759 of 1817 sep 19, 2011 (2) reception end interrupt request signal (intubntir) (a) single mode when reception is enabled, a reception end interrupt re quest signal is generated if data is shifted into the receive shift register and stored in the ubnr x register (if the receive data can be read). when reception is disabled, no reception en d interrupt request signal is generated. (b) fifo mode when reception is enabled, a reception end interrupt re quest signal is generated if data is shifted into the receive shift register and receive data of the number set as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits is transferred to receive fifo (i f receive data of the specified number can be read). when reception is disabled, no reception en d interrupt request signal is generated. (3) transmission enable interrupt request signal (intubntit) (a) single mode the transmission enable interrupt request signal is gener ated if transmit data of one frame, including 7 or 8 bits of characters, is shifted out from the transmit sh ift register and the ubntx register becomes empty (if transmit data can be written). (b) fifo mode the transmission enable interrupt request signal is generat ed if transmit data of the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits is tr ansferred to the transmit shift register from transmit fifo (if transmit data of the s pecified number can be written). (4) fifo transmission end inte rrupt request signal (intubntif) (a) single mode cannot be used. (b) fifo mode the fifo transmission end interrupt reque st signal is generated when no more data is in transmit fifo and the transmit shift register (when the fifo and register become empty). after the fifo transmission end interrupt request signal has occurred, clear the interru pt request signal (intubnt it) held pending in the pending mode (ubnfic0.ubnitm bit = 0) by cl earing the fifo (ubnfic0.ubntfc bit = 1). caution if the fifo transmission end interrupt requ est signal is generated (a ll transmit data are not transmitted) because writing the next transmit da ta to transmit fifo is delayed, do not clear the fifo. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 760 of 1817 sep 19, 2011 (5) reception timeout interrupt request signal (intubntito) (a) single mode cannot be used. (b) fifo mode the reception timeout interrupt request signal is gener ated if data is stored in receive fifo when the next data does not come (start bit is not detected) even after the next data rec eption wait time specified by the ubnfic1.ubntc4 to ubnfic1.ubnt c0 bits has elapsed, when the ti meout counter function is used (ubnfic1.ubntce bit = 1). the reception timeout interrupt request signal is not generated while reception is disabled. if receive data of the number set as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits is not received, the timing of reading the number of receiv e data less than the specified number can be set by the reception timeout interrupt request signal. since the timeout counter starts count ing at start bit detection, a receive timeout interrupt request signal does not occur if data of 1 character has not been received. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 761 of 1817 sep 19, 2011 16.6 control modes (1) single mode/fifo mode the single mode or fifo mode can be se lected by using the ubnfic0.ubnmod bit. (a) single mode ? each of the ubnrx and ubntx registers consists of 8 bits 1 stage. ? when 1 byte of data is received, the intubntir signal is generated. ? if the next reception operation of uartbn is ended before the receive dat a of the ubnrx register is read after the intubntir signal has been generated, the in tubntire signal is generated and an overrun error occurs. (b) fifo mode ? receive fifo (ubnrxap register) consists of 16 bits 16 stages and transmit fifo consists of 8 bits 16 stages. ? receive fifo can recognize error data by reading the 16-bit ubnrxap register only when a reception error (parity error or framing error) occurs. ? transmission is started when transmission is enabl ed (ubnctl0.ubntxe bit = 1) after transmit data of at least the number set as the trigger by the ubnfic2. ubntt3 to ubnfic2.ubntt0 bits and 16 bytes or less are written to transmit fifo. ? the pending mode or pointer mode can be selected for the generation timing of the intubntit and intubntir signals. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 762 of 1817 sep 19, 2011 (2) pending mode/pointer mode the pending mode or pointer mode can be selected by us ing the ubnfic0.ubnitm and ubnfic0.ubnirm bits in the fifo mode (ubnfic0.ubnmod bit = 1). if transmission is started by writing data of more than double the amount set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits to transmit fifo, the transmission enable interrupt request signal (intubntit) may occur more than once. the reception end interrupt request signal (intubntir) may also occur more than once if the number of rece ive data set as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits is 8 bytes or less in receive fifo. in the pending or pointer mode, it can be specified how an interrupt is handled after it has been held pending. (a) pending mode (i) during transmission (w riting to transmit fifo) ? if the data of the first transmission enable interrupt request signal (intubntit) is not written to transmit fifo after the interrupt has occurred, the sec ond intubntit signal does not occur (is held pending) even if the generation condition of the second intubntit signal is sa tisfied (when transmit data of the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits is transferred from transmit fifo to the transmit shift register). when data for the first intubntit signal is late r written to transmit fifo, the pending intubntit signal is generated note . note the number of pending interrupts is as follows. when trigger is set to 1 byte (ubnfic2.ubntt3 to ubnfic2.ubntt0 bits = 0000): 15 times max. when trigger is set to 2 bytes (ubnfic2.ubntt3 to ubnfic2.ubntt0 bits = 0001): 7 times max. : when trigger is set to 6 bytes (ubnfic2.ubntt3 to ubnfic2.ubntt0 bits = 0101): 1 time max. when trigger is set to 7 bytes (ubnfic2.ubntt3 to ubnfic2.ubntt0 bits = 0110): 1 time max. when trigger is set to 8 bytes (ubnfic2.ubntt3 to ubnfic2.ubntt0 bits = 0111): 1 time max. ? in the pending mode, transmit data of the numbe r set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits is always written to tr ansmit fifo when the transmission enable interrupt request signal (intubntit) occurs. writing data to transmit fifo is prohibited if the data is more or less than the specified number. if data more or less than the specified number is written, the operation is not guaranteed. ? fix the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits to 0000 (set number of transmit data: 1 byte) to write transmit data to transmit fifo by dma. if any other setting is m ade, the operation is not guaranteed. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 763 of 1817 sep 19, 2011 (ii) during reception (reading from receive fifo) ? if data for the first reception end interrupt request signal (intubntir) is not read from receive fifo, the second intubntir signal does not occur (is he ld pending) even if the generation condition of the second intubntir is satisfied (if receive dat a of the number set as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits can be re ad from receive fifo). when data for the first intubntir signal is later read from the rece ive fifo, the pending intubn tir signal is generated note . note the number of pending interrupts is as follows. when trigger is set to 1 byte (ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits = 0000): 15 times max. when trigger is set to 2 bytes (ubnfic2.ubnrt 3 to ubnfic2.ubnrt0 bits = 0001): 7 times max. : when trigger is set to 6 bytes (ubnfic2.ubnrt 3 to ubnfic2.ubnrt0 bits = 0101): 1 time max. when trigger is set to 7 bytes (ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits = 0110): 1 time max. when trigger is set to 8 bytes (ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits = 0111): 1 time max. ? in the pending mode, receive data of the number set as the trig ger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits is always read from receiv e fifo when the reception end interrupt request signal (intubntir) occurs. reading data from receiv e fifo is prohibited if the data is more or less than the specified number. if data more or less than th e specified number is r ead, the operation is not guaranteed. ? fix the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits to 0000 (set number of receive data: 1 byte) to read receive data from receive fifo by dma. if any other setting is made, the operation is not guaranteed. (b) pointer mode (i) during transmission (w riting to transmit fifo) ? each time the data of 1 byte is transferred to the transmit shift register from transmit fifo, a transmission enable interrupt request signal (intubntit) occurs. ? in the pointer mode, be sure to fix the ubnfic2.ub ntt3 to ubnfic2.ubntt0 bits to 0000 (set number of transmit data: 1 byte) as the number of transmi t data set as the trigger for transmit fifo when the transmission enable interrupt request signal (intubnt it) occurs. if any other setting is made, the operation is not guaranteed. ? writing transmit data to transmit fifo by dma is prohibited. the operati on is not guaranteed if dma control is used. ? after the transmission enable interrupt request signal (intubntit) has been acknowledged, data of the number of empty bytes of transmit fifo can be written to transmit fifo by referencing the ubnfis1 register. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 764 of 1817 sep 19, 2011 (ii) during reception (reading from receive fifo) ? each time the data of 1 byte is transferred to rece ive fifo from the receive shift register, a reception end interrupt request signal (intubntir) occurs. ? in the pointer mode, be sure to fix the ubnf ic2.ubnrt3 to ubnfic2.ubnrt0 bits to 0000 (set number of receive data: 1 byte) as the number of receive data set as the trigger for receive fifo when the reception end interrupt request signal (intubntir) occurs. if any other setting is made, the operation is not guaranteed. ? reading receive data from receive fifo by dma is prohibited. the operation is not guaranteed if dma control is used. ? after the reception end interrupt request signal (intubntir) has been acknowledged, data of the number of bytes stored in receive fifo can be read from receive fifo by referencing the ubnfis0 register. in some cases, however, data is not stored in receive fifo even though the intubntir signal is generated (ubnfis0.ubnrb4 to ubnfis0. ubnrb0 bits = 00000). in these cases, do not read data from receive fifo. always read data from receive fifo when the number of bytes stored in receive fifo is 1 byte or more (ubnrb4 to ubnrb0 bits = other than 00000). v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 765 of 1817 sep 19, 2011 16.7 operation 16.7.1 data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 16-4. the character bit length within one data fr ame, the type of parity, and the stop bi t length are specified by uartbn control register 0 (ubnctl0). also, data is transferred with lsb first/msb first. remark n = 0, 1 figure 16-4. asynchronous serial interface tran smit/receive data format (lsb-first transfer) 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 766 of 1817 sep 19, 2011 16.7.2 transmit operation in the single mode (ubnfic0.ubnmod bit = 0), transmission is enabled when the ubnctl0.ubntxe bit is set to 1, and transmission is started when transmit da ta is written to the ubntx register. in the fifo mode (ubnfic0.ubnmod bit = 1), transmission is started when transmit data of at least the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits an d 16 bytes or less is written to transmit fifo and then the ubntxe bit is set to 1. caution setting the ubnctl0.ubntxe bit to 1 before writing transmit data to transmit fifo in the fifo mode is prohibited. the opera tion is not guaranteed if this setting is made. (1) transmission enabled state this state is set by the ubnctl0.ubntxe bit. ? ubntxe = 1: transmission enabled state ? ubntxe = 0: transmission disabled state however, because this bit is also used by csifm, enable transmission after setting the cfmctl0.cfmpwr bit to 0 (m = 3, 4). since uartbn does not have a cts (transmission enabled signal) input pin, a port should be used to confirm whether the destination is in the reception enabled state. (2) starting a transmit operation ? in single mode (ubnfic0.ubnmod bit = 0) in the single mode, transmission is started when transm it data is written to the ubntx register while transmission is enabled. ? in fifo mode (ubnfic0.ubnmod bit = 1) in the fifo mode, transmission is star ted when transmit data of at least t he number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits and 16 bytes or less is written to transmit fifo and then transmission is enabled (ubntxe bit = 1). data in the transmit data register (ubntx register in single mode or transmit fifo in the fifo mode) is transferred to the transmit shift register when transmission is started. then, the tran smit shift register outputs data to the txdbn pin sequentially beginning with the ls b (the transmit data is transf erred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 767 of 1817 sep 19, 2011 (3) transmission interrupt request signal (a) transmission enable interr upt request signal (intubntit) ? in single mode (ubnfic0.ubnmod bit = 0) in the single mode, the transmission enable interrupt re quest signal (intubntit) occurs when transmit data can be written to the ubntx register (when 1 byte of data is transferred from the ubntx register to the transmit shift register). ? in fifo mode (ubnfic0.ubnmod bit = 1) in the fifo mode, the intubntit signal occurs when transmit data of the number set as the trigger specified by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits is transferred from transmit fifo to the transmit shift register (if transmit data of t he number set as the trigger can be written). ? if pending mode is specified (ubnfic0.ubnitm bit = 0) in fifo mode if the pending mode is specified in the fifo mode, the second intubntit signal is held pending after the first intubntit signal has occurred, until as many tr ansmit data as the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits are written to transmit fifo, even if the generation condition of the second intubntit signal is satisfied. when as m any transmit data as the number set as the trigger are written to transmit fifo in response to the first intubntit signal, the second pending intubntit signal is generated. ? if pointer mode is specified (ubnfic0.ubnitm bit = 1) in fifo mode if the pointer mode is specified in the fifo mode, the second intubntit signal occurs when the generation condition of the second intubntit signal is satisfied even if as m any transmit data as the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits are not written to transmit fifo when the first in tubntit signal occurs. (b) fifo transmission end interrupt request signal (intubntif) the fifo transmission end interrupt request signal (int ubntif) occurs when no more data is in transmit fifo and the transmit shift register in the fifo m ode (ubnfic0.ubnmod bit = 1). after the intubntif signal has occurred, clear the pending intubntit signal in the pending mode (ubnfic0.ubnitm bit = 0) by clearing the fifo (ubnfic0.ubntfc bit = 1). if t he intubntif signal occurs because writing the next transmit data to transmit fifo is delayed (if all tr ansmit data have not been transmitted), do not clear the fifo. if the data to be transmitted next has not been written to the transmit data register , the transmit operation is suspended. caution in the single mode, the tr ansmission enable interrupt request signal (intubntit) occurs when the ubntx register becomes empty (when 1 byte of data is transferred from the ubntx register to the transmit shift register). in the fifo mode, the fifo transmission end interrupt request signal (intubntif) occurs when data is no lo nger in transmit fifo and the transmit shift register (when the fifo and register are empty) . however, the intubntit signal or intubntif signal is not generated if the transmit data register becomes empty due to reset input. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 768 of 1817 sep 19, 2011 figure 16-5. timing of asynchronous se rial interface transmission enable interrupt request signal (intubntit) start stop d0 d1 d2 d6 d7 parity txdbn (output) intubntit (output) remarks 1. in the fifo mode, the intubntit signal occurs at the above timing when as many transmit data as the number set as the trigger by the ubnfic 2.ubntt3 to ubnfic2.ubntt0 bits are serially transferred. 2. n = 0, 1 figure 16-6. timing of asynchronous serial interf ace fifo transmission end interrupt request signal (intubntif) start stop d0 d1 d2 d6 d7 parity txdbn (output) intubntif (output) remarks 1. the intubntif signal occurs at the above timi ng when data is no longer in transmit fifo and the transmit shift register (when the fifo and register are empty). 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 769 of 1817 sep 19, 2011 16.7.3 continuous transmission operation ? in single mode (ubnfic0.ubnmod bit = 0) in the single mode, the next data can be written to the ubntx register as s oon as the transmit shift register has started a shift operation. the timing of transfer can be identified by the transmission enable interrupt request signal (intubntit). by writing the next transmit data to the ubntx register via the intubntit signal within one data frame transmission period, data can be transmitted without an interval and an efficient communication rate can be realized. caution confirm that the ubnstr.ubntsf bit is 0 be fore executing initialization during transmission processing. if initialization is executed while the ubntsf bit is 1, the transmit data is not guaranteed. ? if pending mode is specified (ubnfic0.ubnitm bit = 0) in fifo mode if transmit data of at least the number set as the transmi t trigger by ubnfic2.ubntt3 to ubnfic2.ubntt0 bits and 16 bytes or less is written to transmit fifo, transmission starts. if the pending mode is specified in the fifo mode, as many of the next tr ansmit data as the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits can be written to transmit fifo as soon as the transmit shift register has started shifting the last data of the specified number of data. the timing of transfer can be identified by the intubntit signal. by writing as many of the next transmit data as the number set as the trigger to transmit fifo or writing the data to the fifo within the transmission period of the data in transmit fifo via the intubntit signal, data can be transmitted without an interval and an efficient communication rate can be realized. caution confirm that the ubnstr.ubntsf bit is 0 be fore executing initialization during transmission processing (this can also be done by the fifo transmission end interrupt request signal (intubntif)). if initialization is executed while the ubntsf bit is 1, the transmit data is not guaranteed. to write transmit data to transmit fifo by dma, set the number of transmit data specified as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits to 1 byte; otherwise the operation will not be guaranteed. ? if pointer mode is specified (ubnfic0.ubnitm bit = 1) in fifo mode if the pointer mode is specified in t he fifo mode, a intubntit signal occu rs and the next data can be written to transmit fifo as soon as the transmit shift register has started shifting the number of transmit data set as the trigger. at this time, as many data as the number of empty bytes of transmit fifo can be written by referencing the ubnfis1 register. the timing of transfer can be identified by the intubntit signal. by writing as many of the next transmit data as the number specified as the trigger to transmit fifo or writ ing the data to the fifo within the transmission period of the data in transmit fifo vi a the intubntit signal, data can be transmitted without an interval and an efficient communication rate can be realized. caution confirm that the ubnstr.ubntsf bit is 0 be fore executing initialization during transmission processing (this can also be done by the fifo transmission end interrupt request signal (intubntif)). if initialization is executed while the ubntsf bit is 1, the transmit data is not guaranteed. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 770 of 1817 sep 19, 2011 16.7.4 receive operation the awaiting reception state is set by setting the ubnc tl0.ubnpwr bit to 1 and then setting the ubnctl0.ubnrxe bit to 1. rxdbn pin sampling begins and a start bit is dete cted. when the start bit is det ected, the receive operation begins, and data is stored sequentially in the receive shift register according to the baud rate that was set. in the single mode (ubnfic0.ubnmod bit = 0), a recepti on end interrupt request signal (intubntir) is generated each time the reception of one frame of data is completed. normally, the rece ive data is transferred from the ubnrx register to memory by this interrupt servicing. in the fifo mode (ubnfic0.ubnmod bit = 1), the intubn tir signal occurs when as many receive data as the number set as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits are transferred to receive fifo. if the pending mode is specified (ubnfic0.ubnirm bit = 0) in the fifo mode, as many receive data as the number set as the trigger by the ubnfic2.ubnrt3 to ubnf ic2.ubnrt0 bits can be read from receive fifo. if the pointer mode is specified (ubnfic0.ubnirm bit = 1) in the fifo mode, as many data as the number of bytes stored in receive fifo (0 bytes or more) can be read from receive fifo by referencing the number of receive data specified as the trigger by the ubnrt3 to ubnrt0 bits (1 byte) or the ubnfis0 register. caution if the pointer mode is specifi ed in the fifo mode and if as many data as the number of bytes stored in receive fifo are read by refere ncing the ubnfis0 register, no data may be stored in receive fifo (ubnfis0.ubnrb4 to ubnfis0.ubn rb0 bits = 00000) even though the reception end interrupt request signal (intubntir) has occurred. in this case, do not read data from receive fifo. be sure to read data from receive fifo a fter confirming that the number of bytes stored in receive fifo = 1 byte or more (ubnrb4 to ubnrb0 bits = other than 00000). (1) reception enabled state this state is set by the ubnctl0.ubnrxe bit. ? ubnrxe = 1: reception enabled state ? ubnrxe = 0: reception disabled state however, because this bit is also used by csifm, enabl e reception after setting the cfmctl0.cfmpwr bit to 0 and disabling the csifm operation (m = 3, 4). in the reception disabled state, the re ception hardware stands by in the initial state. at this time, the reception end interrupt request signal or reception error interrupt request signal does not occu r, and the contents of the receive data register (ubnrx register in the single mode or receive fifo in the fifo mode (ubnrxap register)) are retained. (2) starting a receive operation a receive operation is started by the detection of a start bit. the rxdbn pin is sampled using the serial clo ck from uartbn control register 2 (ubnctl2). remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 771 of 1817 sep 19, 2011 (3) reception interrupt request signal (a) reception end interrupt request signal (intubntir) ? in single mode (ubnfic0.ubnmod bit = 0) when ubnctl0.ubnrxe bit = 1 and the reception of one frame of data is ended (t he stop bit is detected) in the single mode, a reception end interrupt request signal (intubntir) is generat ed and the receive data in the receive shift register is transferred to the ubnrx register at the same time. also, if an overrun error occurs, the receive data at that time is not transferred to the ubnrx register, and a reception error interrupt request signal (intubntire) is generated. if a parity error or framing error occurs during the rece ption operation, the recepti on operation continues up to the position at which the stop bi t is received. after completion of reception, an intubntire signal occurs (the receive data in the receive shift register is transferred to the ubnrx register). if the ubnrxe bit is reset (0) during a receive operation, the receive operation is immediately stopped. at this time, the contents of the ubnrx register rema in unchanged, the content s of the uartbn status register (ubnstr) are cleared, and the intu bntir and intubntire signals do not occur. no intubntir signal is generated when the ubnrxe bit = 0 (reception is disabled). ? in fifo mode (ubnfic0.ubnmod bit = 1) in the fifo mode, the reception end interrupt request signal (intub ntir) occurs when data of one frame has been received (stop bit is detec ted) and when as many receive dat a as the number s pecified as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits are transferred from the receive shift register to receive fifo. if an overflow error occurs, the rece ive data is not transferred to receive fifo and the reception error interrupt request signal (intubntire) occurs. if a parity error or framing error occurs during receptio n, reception continues up to the reception position of the stop bit. after reception has been completed, the intubntire signal occurs and the receive data in the receive shift register is transferred to receive fif o. at this time, error information is appended as the ubnrxap.ubnpef or ubnrxap.ubnfef bit = 1. if t he intubntire signal occurs, the error data can be recognized by reading receive fifo as a 16-bit register, ubnrxap. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 772 of 1817 sep 19, 2011 (b) reception timeout interrupt request signal (intubntito) ( only in fifo mode) when the timeout counter function (ubnfic1.ubntce bi t = 1) is used in the fi fo mode, the reception timeout interrupt request signal (int ubntito) occurs if the next data do es not come even after the next data reception wait time specified by t he ubnfic1.ubntc4 to ubnfic1.ubntc0 bits has elapsed and if data is stored in receive fifo. the intubntito signal does not o ccur while reception is disabled. if as many receive data as the number set as the trig ger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits are not received, the timing of reading less receiv e data than the specified nu mber can be set by the intubntito signal. since the timeout counter starts count ing at start bit detection, a receive timeout interrupt request signal does not occur if data of 1 character has not been received. figure 16-7. timing of asynchronous serial interface recepti on end interrupt request signal (intubntir) start d0 d1 d2 d6 d7 rxdbn (input) intubntir (output) receive data register parity stop cautions 1. be sure to read all the data (the number of data indicated by the ubnfis0.ubnrb4 to ubnfis0.ubnrb0 bits) stored in the receive data register ( ubnrx register in the single mode or receive fifo in the fifo mode (ubn rxap register)) even when a reception error occurs. unless the receive data register is read, an overrun error occurs when the next data is received, causing the reception error status to persist. if the pending mode is specified in the fi fo mode, however, be sure to clear the fifo (ubnfic0.ubnrfc bit = 1) after readi ng the data stored in receive fifo. in the fifo mode, the fifo can be cleared even without read ing the data stored in receive fifo. if a parity error or framing error occurs in the fifo mode, the ubnrxap register can be read in 16-bit (halfword) units. 2. data is always received with one stop bit (1). a second stop bit is ignored. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 773 of 1817 sep 19, 2011 16.7.5 reception error in the single mode (ubnfic0.ubnmod bit = 0), the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. in the fi fo mode (ubnfic0.ubnmod bit = 1), the three types of errors that can occur during a receive operation are a parity error, framing error, and overflow error. as a result of data reception, the ubnstr.ubnpe, ubnstr.u bnfe, or ubnstr.ubnove bit is set to 1 if a parity error, framing error, or overrun error occurs in the single mode. t he ubnstr.ubnovf bit is set to 1 if an overflow error occurs in the fifo mode. the ubnrxap.ubnpef or ubnrxap.ubnfef bit is set to 1 if a parity error or framing error occurs in the fifo mode. at the same time, a reception error interr upt request signal (intubntire) occurs. the contents of the error can be detected by reading the cont ents of the ubnstr or ubnrxap register. the contents of the ubnstr register are reset when 0 is written to the ubnovf, ubnpe, ubnfe, or ubnove bit, or the ubnctl0.ubnpwr or ubnct l0.ubnrxe bit. the contents of the ubnrxap register are reset when 0 is written to the ubnctl0.ubnpwr bit. table 16-5. reception error causes error flag valid operation mode error flag reception error cause ubnpe ubnpe parity error the parity specification during transmission does not match the parity of the receive data ubnfe ubnfe framing error no stop bit detected ubnove single mode ubnove overrun error the recepti on of the next data is ended before data is read from the ubnrx register ubnovf ubnovf overflow error the re ception of the next data is ended while receive fifo is full and before data is read. ubnpef ubnpef parity error the parit y specification during transmission does not match the parity of the data to be received. ubnfef fifo mode ubnfef framing error the stop bit is not detected when the target data is loaded. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 774 of 1817 sep 19, 2011 16.7.6 parity types and corresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used at the transmission and reception sides. (1) even parity (a) during transmission the parity bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1 ? within the transmit data is even: 0 (b) during reception the number of bits with the value ?1 ? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (2) odd parity (a) during transmission in contrast to even parity, the parity bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1 ? within the transmit data is even: 1 (b) during reception the number of bits with the value ?1 ? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (4) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 775 of 1817 sep 19, 2011 16.7.7 receive data noise filter the rxdbn signal is sampled at the rising edge of the peripheral clock (f xx ). if the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 16-9 ). also, since the circuit is configured as shown in figure 16 -8, internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status. figure 16-8. noise filter circuit rxdbn q f xx in ld_en q in internal signal a internal signal b match detector remarks 1. f xx : peripheral clock 2. n = 0, 1 figure 16-9. timing of rx dbn signal judg ed as noise internal signal a f xx rxdbn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match remarks 1. f xx : peripheral clock 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 776 of 1817 sep 19, 2011 16.8 dedicated baud rate generator (brg) a dedicated baud rate generator, which consists of a 16- bit programmable counter, generates serial clocks during transmission/reception in uartbn. the dedicated baud rate gener ator output can be selected as the serial clock for each channel. separate 16-bit counters exist for transmission and for recept ion. the baud rate for transmission/reception is the same at the same channel. (1) baud rate genera tor configuration figure 16-10. baud rate generator configuration clock 16-bit counter match detector baud rate ubnctl2.ubnbrs15 to ubnctl2.ubnbrs0 1/2 ubnpwr, ubntxe (or ubnrxe) f xx output clock remarks 1. f xx : peripheral clock 2. n = 0, 1 (a) base clock (clock) when ubnctl0.ubnpwr bit = 1, the main clock (f xx ) is supplied to the transmission/reception unit. this clock is called the base clock. when the ubnpwr bi t = 0, the clock signal is fixed at low level. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 777 of 1817 sep 19, 2011 (2) serial clock generation a serial clock can be generated according to the settings of the ubnctl2 register. the 16-bit counter divisor value can be selected accord ing to the ubnctl2.ubnbrs 15 to ubnctl2.ubnbrs0 bits. (a) baud rate the baud rate is the value obtained according to the following formula. f uclk baud rate = [bps] 2 k f uclk = f xx /2 (f xx : main clock frequency) k = value set according to ubnctl2.ubnbrs15 to ubnctl2.ubnbrs0 bits (k = 4, 5, 6, ?, 65535) (b) baud rate error the baud rate error is obtained according to the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? = ? ? ? ? ? ? ? ? cautions 1. make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within th e allowable baud rate range during reception, which is described in paragraph (4). example: f uclk = 25 mhz = 25,000,000 hz set value of ubnctl2.ubnbrs15 to ubnctl2.ubnbrs0 bits = 0000000001010001b (k = 81) target baud rate = 153600 bps baud rate = 25 m/(2 81) = 25000000/(2 81) = 154321 [bps] error =(154321/153600 ? 1) 100 = 0.469 [%] when f uclk = 25 mhz and k = 40, the error is 0%. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 778 of 1817 sep 19, 2011 (3) baud rate setting example table 16-6. baud rate generator setting data f xx = 50 mhz f xx = 48 mhz f xx = 32 mhz f xx = 24 mhz baud rate (bps) ubnctl2 err(%) ubnctl2 err (%) ubnctl2 err (%) ubnctl2 err (%) 300 a2c3 0.00 9c40 0.00 682b 0.00 20000 0.00 600 5161 0.00 4e20 0.00 3415 0.00 10000 0.00 1200 28b1 0.00 2710 0.00 1a0b 0.00 5000 0.00 2400 1458 0.01 1388 0.00 0d05 0.01 2500 0.00 4800 0a2c 0.01 09c4 0.00 0683 -0.02 1250 0.00 9600 0516 0.01 04e2 0.00 0341 0.04 625 0.00 19200 028b 0.01 0271 0.00 01a1 -0.08 313 -0.16 31250 0190 0.00 0180 0.00 0100 0.00 192 0.00 38400 0146 -0.15 0139 -0.16 00d0 0.16 156 0.16 76800 00a3 -0.15 009c 0.16 0068 0.16 78 0.16 153600 0051 0.47 004e 0.16 0034 0.16 39 0.16 312500 0028 0.00 0026 1.05 001a -1.54 19 1.05 625000 0014 0.00 0013 1.05 000d -1.54 10 -4.00 1000000 000d -3.85 000c 0.00 0008 0.00 6 0.00 1250000 000a 0.00 000a -4.00 0006 6.67 5 -4.00 2000000 0006 4.17 0006 0.00 0004 0.00 3 0.00 2500000 0005 0.00 0005 -4.00 0003 6.67 2 20.00 3000000 0004 4.17 0004 0.00 0003 -11.11 2 0.00 3125000 0004 0.00 0004 -4.00 0003 -14.67 2 -4.00 caution the maximum allowable fre quency of the peripheral clock (f xx ) is 50 mhz. the maximum transfer speed of the baud rate is 3.125 mbps. remarks 1. f xx : peripheral clock k: settings of ubnctl2.ubnbrs15 to ubnctl2.ubnbrs0 bits err: baud rate error [%] 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 779 of 1817 sep 19, 2011 (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission desti nation?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set the ba ud rate error during reception so that it always is within the allowable error range. figure 16-11. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartbn latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable value maximum allowable value stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0, 1 as shown in figure 16-11, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the ubnctl2 register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. applying this to 11-bit reception is, theoretically, as follows. fl = (brate) ? 1 brate: uartbn baud rate k: ubnctl2 set value fl: 1-bit data length latch timing margin: 2 clocks minimum allowable value: fl k 2 2 k 21 fl k 2 2 k fl 11 flmin + = ? ? = v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 780 of 1817 sep 19, 2011 therefore, the maximum baud rate that can be received at the trans fer destination is as follows. brate 2 21k k 22 (flmin/11) brmax 1 + = = ? similarly, the maximum allowable value can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 flmax 11 10 ? = + ? = 11 fl k 20 2 k 21 flmax ? = therefore, the minimum baud rate that can be received at the transfer destination is as follows. brate 2 21k k 20 (flmax/11) brmin 1 ? = = ? the allowable baud rate error of uartbn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 16-7. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.33 % ? 2.44 8 +3.53 % ? 3.61 16 +4.14 % ? 4.19 32 +4.45 % ? 4.48 64 +4.61 % ? 4.62 128 +4.68 % ? 4.69 256 +4.72 % ? 4.73 512 +4.74 % ? 4.74 1024 +4.75 % ? 4.75 2048 +4.76 % ? 4.76 4096 +4.76 % ? 4.76 8192 +4.76 % ? 4.76 16384 +4.76 % ? 4.76 32768 +4.76 % ? 4.76 65535 +4.76 % ? 4.76 remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: ubnctl2 set value v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 781 of 1817 sep 19, 2011 (5) transfer rate durin g continuous transmission during continuous transmission, the transfer rate from a st op bit to the next start bit is extended two clocks longer than normal. however, on the reception side, the transfer resu lt is not affected since the timing is initialized by the detection of the start bit. figure 16-12. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bi t length by flstp, and the base clock frequency by f xx yields the following equation. flstp = fl + 2/(f xx ) therefore, the transfer rate during co ntinuous transmission is as follows. transfer rate = 11 fl + 2/(f xx ) v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 782 of 1817 sep 19, 2011 16.9 control flow (1) example of continuous tr ansmission processing flow in single mode (cpu control) figure 16-13. example of continuo us transmission processing flow in single mode (cpu control) set uartbn-related registers yes ubntsf = 0? (ubnstr) no start ubntxe = 1 (ubnctl0) : enable transmission write ubntx register : write transmit data ubntxe = 0 (ubnctl0) : disable transmission yes intubntit interrupt = 1? : ubntx register can be written? no yes transmission ended? : all transmit data written? : transmission ended? no end remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 783 of 1817 sep 19, 2011 (2) example of continuous r eception processing flow in si ngle mode (cpu control) figure 16-14. example of continuous reception processing flow in single mode (cpu control) set uartbn-related registers start ubnrxe = 1 (ubnctl0) : enable reception error processing in single mode yes intubntire interrupt = 1? : reception error occurred? yes intubntir interrupt = 1? : 1-byte reception ended? no yes reception ended? : reception ended? no no end read ubnrx register : read receive data ubnrxe= 0 (ubnctl0) : disable reception remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 784 of 1817 sep 19, 2011 (3) example of continuous tr ansmission processing flow in single mode (dma control) figure 16-15. example of continuo us transmission processing flow in single mode (dma control) set uartbn/dmac-related registers note start dtfrm register = 28h : assign dma transfer destination (in the case of intubntit) and clear dfm bit yes dma ended? : dma transfer ended? no yes ubntsf = 0? (ubnstr) : transmission ended? no ubntxe = 0 (ubnctl0) : disable transmission end emm = 1 (dchcm) : enable dma transfer ubntxe = 1 (ubnctl0) : enable transmission write ubntx register : write transmit data note in this control flow example, transmission of the first byte of the data is executed by a cpu write operation. exercise care in setting the number of data for dma transfer (dbcm register) and the source address (dsamh, dsaml registers). remark m = 0 to 3 n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 785 of 1817 sep 19, 2011 (4) example of continuous r eception processing flow in si ngle mode (dma control) figure 16-16. example of continuous reception processing flow in single mode (dma control) set uartbn/dmac-related registers start dtfrm register = 27h : assign dma transfer destination (in the case of intubntir) and clear dfm bit yes dma ended? : dma transfer (reception) ended? no ubnrxe = 0 (ubnctl0) : disable reception end emm = 1 (dchcm) : enable dma transfer ubnrxe = 1 (ubnctl0) : enable reception remark m = 0 to 3 n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 786 of 1817 sep 19, 2011 (5) example of continuous tr ansmission processing flow in fifo mode (cpu control) figure 16-17. example of continuous transmissi on processing flow in fifo mode (cpu control) set uartbn-related registers start write transmit fifo note 1 : write transmit data yes intubntif interrupt = 1? : transmission ended? note 2 yes intubntit interrupt = 1? : writing to transmit fifo enabled? no yes transmission ended? : writing all transmit data ended? no : transmission ended? no end ubntxe = 0 (ubnctl0) write transmit fifo note 3 : disable transmission clear transmit fifo ubntxe = 1 (ubnctl0) : enable transmission yes intubntif interrupt = 1? no notes 1. write more transmit data than the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits to transmit fifo. 2. this is the case where transmission is ended (t ransmit fifo and the transmit shift register become empty) before the next transmit data is written. to continue data transmission, clear the intubntif and intubntit signals and write the next data to transmit fifo. 3. in the pending mode (ubnfic0.ubnitm bit = 0), write as many transmit data as the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubn tt0 bits of to transmit fifo. in the pointer mode (ubnitm bit = 1), reference the ubnfis1.ub ntb4 to ubnfis1.ubntb0 bits and write as many data as the number of empty bytes in transmit fifo to transmit fifo. write 16-byte data to fully use the 8-bit 16-stage fifo function. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 787 of 1817 sep 19, 2011 (6) example of continuous reception processing in fi fo mode (cpu control) figure 16-18. example of continuous recepti on processing in fifo mode (cpu control) set uartbn-related registers start ubnrxe = 1 (ubnctl0) : enable reception yes intubntito interrupt = 1? : reception timeout occurred? yes intubntir interrupt = 1? : reading from receive fifo enabled? no yes reception ended? : reading all receive data ended? no no no intubntire interrupt = 1? : reception error occurred? yes end read receive fifo note 1 : read receive data error processing in fifo mode ubnrxe = 0 (ubnctl0) : disable reception check ubnfis0 register read receive fifo note 2 : read receive data remaining in receive fifo clear receive fifo notes 1. read as many receive data as the number se t as the trigger by the ubnfic2.ubnrt3 to ubnfic2.ubnrt0 bits from receive fifo in the pending mode (ubnfic0.ubnirm bit = 0). in the pointer mode (ubnirm bit = 1), reference the ubnf is0.ubnrb4 to ubnfis0.ubnrb0 bits and read as many data as the number of bytes stored in receive fifo from receive fifo. 2. read as many data (remaining receive data less than the number set as the trigger) as the number of bytes stored in receive fifo from receive fifo by referencing the ubnfis0.ubnrb4 to ubnfis0.ubnrb0 bits. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 788 of 1817 sep 19, 2011 (7) example of continuous tran smission (pending mode) processing in fifo mode (dma control) figure 16-19. example of continuous transmission (pe nding mode) processing in fifo mode (dma control) set uartbn/dmac-related registers note 1 start dtfrm register = 28h : assign dma transfer destination (in the case of intubntit) and clear dfm bit yes dma ended? : dma transfer ended? no yes intubntif interrupt = 1? : transmission ended? no ubntxe = 0 (ubnctl0) : disable transmission end emm = 1 (dchcm) : enable dma transfer ubntxe = 1 (ubnctl0) : enable transmission clear transmit fifo write transmit fifo note 2 : write transmit data notes 1. in this control flow example, transmission of the data described in note 2 is executed by a cpu write operation. exercise care in setting the number of data for dma transfer (dbcm register) and the source address (dsamh, dsaml registers). 2. write as many transmit data as the number set as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits (= 1 byte) to transmit fifo. remark m = 0 to 3 n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 789 of 1817 sep 19, 2011 (8) example of continuous recepti on (pending mode) processing flow in fifo mode (dma control) figure 16-20. example of continuous reception (pending mode) processing flow in fifo mode (dma control) set uartbn/dmac-related registers start dtfrm register = 27h : assign dma transfer destination (in the case of intubntir) and clear dfm bit yes dma ended? : dma transfer (reception) ended? no ubnrxe = 0 (ubnctl0) : disable reception end emm = 1 (dchcm) : enable dma transfer ubnrxe = 1 (ubnctl0) : enable reception clear receive fifo remark m = 0 to 3 n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 790 of 1817 sep 19, 2011 (9) example of reception erro r processing in single mode figure 16-21. example of reception erro r processing flow in single mode start read ubnrx register : extract receive data (error data) end clear error flag read ubnstr register : check error flag caution reception can be continued by completing this contro l flow before recepti on of the next data is ended. if the next data is received before this control fl ow is ended, a reception error interrupt request signal (intubntire) may occur ev en if the data has been received correctly. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 791 of 1817 sep 19, 2011 (10) example of reception error pr ocessing flow in fifo mode (1) figure 16-22. example of reception erro r processing flow in fifo mode (1) start ubnrxe = 0 (ubnctl0) note : stop reception end read ubnfis0 register : check receive fifo pointer read ubnrxap register : extract receive data and check error ubnrfc = 1 (ubnfic0) : clear receive fifo clear error flag read ubnstr register : check error flag note if the error flag is cleared when ubnrxe bit = 0, the ubnctl0 register does not have to be set. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 792 of 1817 sep 19, 2011 (11) example of reception error pr ocessing flow in fifo mode (2) figure 16-23. example of reception erro r processing flow in fifo mode (2) start end read ubnfis0 register : check receive fifo pointer read ubnrxap register : extract receive data and check error clear error flag read ubnstr register : check error flag note reception can be continued by completing this control flow before reception of the next data is ended. extract the receive data and check if a reception error has occurred before receive fifo becomes empty. note that this control flow is valid only when a parity error or a framing error occurs. if an overflow error occurs, receive fifo mu st be cleared (ubnfic0.ubnrfc bit = 1). if the next data is received before this control flow is ended, a reception error interrupt request signal (intubntire) may occur even if the data has been received correctly. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 793 of 1817 sep 19, 2011 16.10 cautions cautions concerning uartbn are shown below. (1) when supply clock to uartbn is stopped when the supply of clocks to uartbn is stopped (for example, idle and stop modes), operation stops with each register retaining the value it had immediately bef ore the supply of clocks was stopped. the txdbn pin output also holds and outputs the val ue it had immediately before the suppl y of clocks was stopped. however, operation is not guaranteed after the supply of clocks is re started. therefore, afte r the supply of clocks is restarted, the circuits should be initialized by setting the ubnpwr bit = 0, ubnrxe bit = 0, and ubntxe bit = 0. (2) caution on setting ubnctl0 register ? when using uartbn, set the external pins related to t he uartbn function to the al ternate function and set the ubnctl2 register. then set the ubnctl0.ubnp wr bit to 1 before setting the other bits. ? be sure to input a high level to the rxdbn pin when setting the external pins related to the uartbn function to the alternate function. if a low level is input, it is j udged that a falling edge is input after the ubnctl0.ubnrxe bit has been set to 1, and reception may be started. (3) caution on setting ubnfic2 register be sure to clear the ubnctl0.ubntxe bit (to dis able transmission) and ubnctl0.ubnrxe bit (to disable reception) to 0 before writing data to the ubnfic2 register. if data is wri tten to the ubnfic2 register with the ubntxe or ubnrxe bit set to 1, the operation is not guaranteed. (4) transmission interrupt request si g nal in the single mode, the transmission enable interrupt request signal (intubntit) occurs when the ubntx register becomes empty (when 1 byte of data is transferred from the ubntx register to the transmit shift register). in the fifo mode, the fifo transmissi on end interrupt request signal (intub ntif) occurs when data is no longer in transmit fifo and the transmit shift register (when th e fifo and register are empty) . however, the intubntit signal or intubntif signal does not occur if the trans mit data register becomes empty due to reset input. (5) initialization during continu ous transmission in single mode confirm that the ubnstr.ubntsf bit is 0 before execut ing initialization during transmission processing. if initialization is executed whil e the ubntsf bit is 1, the transmit data is not guaranteed. (6) initialization during continuous tr ansmission (pending m ode) in fifo mode confirm that the ubnstr.ubntsf bit is 0 before execut ing initialization during trans mission processing (this can also be done by checking the fifo transmission end interr upt request signal (intubntif )). if initialization is executed while the ubntsf bit is 1, the transmit data is not guaranteed. to write transmit data to transmit fifo by dma control, se t the number of transmit data s pecified as the trigger by the ubnfic2.ubntt3 to ubnfic2.ubntt0 bits to 1 byte; otherwise the operation will not be guaranteed. (7) initialization during continuous tran smission (pointer m ode) in fifo mode confirm that the ubnstr.ubntsf bit is 0 before execut ing initialization during trans mission processing (this can also be done by checking the fifo transmission end interr upt request signal (intubntif )). if initialization is executed while the ubntsf bit is 1, the transmit data is not guaranteed. v850es/jh3-e, v850es/jj3-e chapter 16 asynchronous serial interface b with fifo (uartbn) r01uh0290ej0300 rev.3.00 page 794 of 1817 sep 19, 2011 (8) receive operation in fifo m ode (pointer mode specified) if the pointer mode is specified in t he fifo mode and if as many data as t he number of bytes stored in receive fifo are read by referencing the ubnf is0 register, no data may be stored in receive fifo (ubnfis0.ubnrb4 to ubnfis0.ubnrb0 bits = 00000) ev en though the reception end interr upt request signal (intubntir) has occurred. in this case, do not read data from receive fifo. be sure to read data from receive fifo after confirming that the number of bytes st ored in receive fifo = 1 byte or more (ubnrb4 to ubnrb0 bits = other than 00000). remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 795 of 1817 sep 19, 2011 chapter 17 asynchronous ser ial interface c (uartc) in the v850es/jh3-e, asynchronous serial interface c (u artc) is provided with 6 channels, and in the v850es/jj3-e, uartc is provided with 8 channels. 17.1 features { transfer rate: 300 bps to 3.125 mbps (using internal system clock of 24 mhz and dedicated baud rate generator) { full-duplex communication: internal uartcn receive data register (ucnrx) internal uartcn transmit data register (ucntx) { 2-pin configuration: txdcn: transmit data output pin rxdcn: receive data input pin { reception error detection function ? parity error ? framing error ? overrun error { interrupt sources: 2 types ? reception completion interrupt (intucnr): this interrup t occurs upon transfer of receive data from the receive shift register to the receive data register after serial transfer is complete, in the reception enabled status. ? transmission enable interrupt (intucnt): this interr upt occurs upon transfer of transmit data from the transmit data register to the transmit shift register in the transmission enabled status. { character length: 7 to 9 bits { parity function: odd, even, 0, none { transmission stop bit: 1, 2 bits { on-chip dedicated baud rate generator { msb-/lsb-first transfer selectable { transmit/receive data inverted input/output possible { sbf (sync break field) transmission in the lin ( local interconnect network) communication format ? 13 to 20 bits selectable for the sbf transmission ? recognition of 11 bits or more possible for sbf reception ? sbf reception flag provided remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 796 of 1817 sep 19, 2011 17.2 configuration the block diagram of the uartcn is shown below. figure 17-1. block diagram of a synchronous serial interface cn internal bus internal bus receive shift register ucnrx filter selector ucntx transmit shift register transmission controller reception controller selector baud rate generator baud rate generator intucnr intucnt txdcn rxdcn f xx to f xx /2 10 asckc0 note reception unit transmission unit clock selector ucnopt0 ucnctl1 ucnctl2 ucnstr ucnctl0 note uartc0 only remarks 1. n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) 2. for the configuration of the baud rate generator, see figure 17-19 . uartcn includes the following hardware. table 17-1. configuration of uartcn item configuration registers uartcn control register 0 (ucnctl0) uartcn control register 1 (ucnctl1) uartcn control register 2 (ucnctl2) uartcn option control register 0 (ucnopt0) uartcn option control register 1 (ucnopt1) uartcn status register (ucnstr) uartcn receive shift register uartcn receive data register (ucnrx) uartcn transmit shift register uartcn transmit data register (ucntx) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 797 of 1817 sep 19, 2011 (1) uartcn control register 0 (ucnctl0) the ucnctl0 register is an 8-bit register used to specify the uartcn operation. (2) uartcn control register 1 (ucnctl1) the ucnctl1 register is an 8-bit register used to select the input clock for the uartcn. (3) uartcn control register 2 (ucnctl2) the ucnctl2 register is an 8-bit register us ed to control the baud rate for the uartcn. (4) uartcn option control register 0 (ucnopt0) the ucnopt0 register is an 8-bit register used to control serial transfer for the uartcn. (5) uartcn option control register 1 (ucnopt1) the ucnopt1 register is an 8-bit register used to cont rol 9-bit length serial transfer for the uartcn. (6) uartcn status register (ucnstr) the ucnstrn register consists of flags indicating the error contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrence of a reception error. (7) uartcn receive shift register this is a shift register used to conver t the serial data input to the rxdcn pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the rece ive data is transferred to the ucnrx register. this register cannot be manipulated directly. (8) uartcn receive data register (ucnrx) the ucnrx register is an 8-bit register that holds receive data. when 7 characters are received, 0 is stored in the most significant bit (when data is received with the lsb first). in the reception enabled status, receive data is transferre d from the uartcn receive shift register to the ucnrx register in synchronization with the completion of shift-in processing of 1 frame. transfer to the ucnrx register also causes the recept ion completion interrupt request signal (intucnr) to be output. (9) uartcn transmit shift register the transmit shift register is a shift register used to co nvert the parallel data transferred from the ucntx register into serial data. when 1 byte of data is transferred from the ucntx register, the shift register data is output from the txdcn pin. this register cannot be manipulated directly. (10) uartcn transmit data register (ucntx) the ucntx register is an 8-bit transmit data buffer. trans mission starts when transmit data is written to the ucntx register. when data can be written to the ucntx register (w hen data of one frame is transferred from the ucntx register to the uartcn transmit shift register), t he transmission enable interrupt request signal (intucnt) is generated. v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 798 of 1817 sep 19, 2011 17.3 mode switching between uartc and other serial interfaces 17.3.1 mode switching between uartc0 and csif2 in the v850es/jh3-e and v850es/jj3-e, uartc0 and csif2 share the same pin and therefore cannot be used simultaneously. set uartc0 in advance, using the pmc3, pfc3 and pfce3 registers, before use. caution the transmit/receive operation of uartc0 and csif2 is not guaranteed if these functions are switched during transmission or reception. be su re to disable the one that is not used. figure 17-2. uartc0 and csif2 mode switch settings pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 pfce37 pfce36 pfce35 pfce34 pfce33 pfce32 pfce31 pfce30 pfce3 after reset: 00h r/w address: fffff706h port i/o mode asckc0 (uartc0) sckf2 (csif2) pmc32 0 1 1 operation mode pfce32 0 0 pfc32 0 1 port i/o mode rxdc0 (uartc0) sof2 (csif2) pmc31 0 1 1 operation mode pfce31 0 0 pfc31 0 1 port i/o mode txdc0 (uartc0) sif2 (csif2) pmc30 0 1 1 operation mode pfce30 0 0 pfc30 0 1 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 799 of 1817 sep 19, 2011 17.3.2 mode switching between uartc1, csif1 and i 2 c00 in the v850es/jh3-e and v850es/jj3-e, uartc1, csif1 and i 2 c00 share the same pin, so these functions cannot be used simultaneously. set uartc1 in advance, using the pmc2, pfc2 and pfce2 registers. caution the transmit/receive operation of uartc1, csif1, and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-3. uartc1, csif1 and i 2 c00 mode switch settings pmc2 after reset: 00h r/w address: fffff444h pmc27 note pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 pmc20 pfc2 after reset: 00h r/w address: fffff464h pfc27 note pfc26 pfc25 pfc24 pfc23 pfc22 pfc21 pfc20 pfce27 note pfce26 pfce25 pfce24 pfce23 pfce22 pfce21 pfce20 pfce2 after reset: 00h r/w address: fffff704h port i/o mode sof1 (csif1) rxdc1 (uartc1) scl00 (i 2 c00) pmc24 0 1 1 1 operation mode pfce24 0 0 1 pfc24 0 1 0 port i/o mode sckf1 (csif1) pmc25 0 1 operation mode pfce25 0 pfc25 0 port i/o mode sif1 (csif1) txdc1 (uartc1) sda00 (i 2 c00) pmc23 0 1 1 1 operation mode pfce23 0 0 1 pfc23 0 1 0 note v850es/jj3-e only remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 800 of 1817 sep 19, 2011 17.3.3 mode switching between uartc2, i 2 c02, and can0 in the v850es/jh3-e and v850es/jj3-e, uartc2, i 2 c02, and can0 ( pd70f3783 and 70f3786 only) share the same pin and therefore cannot be used simultaneously. set uartc2 in advance, using the pmc3, pfc3, and pfce3 registers, before use. caution the transmit/receive operation of uartc2, i 2 c02, and can0 ( pd70f3783 and 70f3786 only) is not guaranteed if these functions are s witched during transmission or recep tion. be sure to disable the one that is not used. figure 17-4. uartc2, i 2 c02, and can0 mode switch settings pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 pfce37 note pfce36 note pfce35 pfce34 pfce33 pfce32 pfce31 pfce30 pfce3 after reset: 00h r/w address: fffff706h port i/o mode txdc2 (uartc2) sda02 (i 2 c02) ctxd0 (can0) note pmc36 0 1 1 1 operation mode pfce36 note 0 0 1 pfc36 0 1 0 port i/o mode rxdc2 (uartc2) scl02 (i 2 c02) crxd0 (can0) note pmc37 0 1 1 1 operation mode pfce37 note 0 0 1 pfc37 0 1 0 note pd70f3783 and 70f3786 only remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 801 of 1817 sep 19, 2011 17.3.4 mode switching between uartc3, csif0, and i 2 c01 in the v850es/jh3-e and v850es/jj3-e, uartc3, csif0, and i 2 c01 share the same pin and therefore cannot be used simultaneously. set uartc3 in advance, using the pmc4, pfc4, and pfce4 registers, before use. caution the transmit/receive operation of uartc3, csif0, and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-5. uartc3, csif0, and i 2 c01 mode switch settings port i/o mode sif1 (csif0) txdc3 (uartc3) sda01 (i 2 c01) pmc40 0 1 1 1 operation mode pfce40 0 0 1 pfc40 0 1 0 port i/o mode sof0 (csif0) rxdc3 (uartc3) scl01 (i 2 c01) pmc41 0 1 1 1 operation mode pfce41 0 0 1 pfc41 0 1 0 port i/o mode sckf0 (csif0) pmc42 0 1 operation mode pfce42 0 pfc42 0 pmc4 (pmc4h) (pmc4l) (pfc4l) pmc47 note pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0 note 0 note 0 note 0 note 0 note 0 note 0 note pmc48 note 8 9 10 11 12 13 14 15 pfc4 (pfc4h) pfc4 fffff468h, pfc4l fffff468h, pfc4h fffff469h after reset: 0000h r/w address: 0 note 0 note 0 note 0 note 0 note 0 note 0 note pfc48 note pfc47 note pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pmc4 fffff448h, pmc4l fffff448h, pmc4h fffff449h pfce47 note pfce46 note pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 pfce4 after reset: 00h r/w address: fffff708h note v850es/jj3-e only remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 802 of 1817 sep 19, 2011 17.3.5 mode switching between uartc4 and csie0 in the v850es/jh3-e and v850es/jj3-e, uartc4 and csie0 share of the same pin and therefore cannot be used simultaneously. set uartc4 in advance, using t he pmc4, pfc4, and pfce4 registers, before use. caution the transmit/receive operation of uartc4 a nd csie0 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-6. uartc4 and csie0 mode switch settings port i/o mode soe0 (csie0) rxdc4 (uartc4) pmc44 0 1 1 operation mode pfce44 0 0 pfc44 0 1 port i/o mode sie0 (csie0) txdc4 (uartc4) pmc43 0 1 1 operation mode pfce43 0 0 pfc43 0 1 port i/o mode scke0 (csie0) pmc45 0 1 operation mode pfce45 0 pfc45 0 pmc4 pmc47 note pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0 note 0 note 0 note 0 note 0 note 0 note 0 note pmc48 note 8 9 10 11 12 13 14 15 pfc4 pfc4 fffff468h, pfc4l fffff468h, pfc4h fffff469h after reset: 0000h r/w address: 0 note 0 note 0 note 0 note 0 note 0 note 0 note pfc48 note pfc47 note pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pmc4 fffff448h, pmc4l fffff448h, pmc4h fffff449h pfce47 note pfce46 note pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 pfce4 after reset: 00h r/w address: fffff708h note v850es/jj3-e only remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 803 of 1817 sep 19, 2011 17.3.6 mode switching between uartc5, csie1 and i 2 c03 in the v850es/jh3-e and v850es/jj3-e, uartc5, csie1, and i 2 c03 share the same pin and therefore cannot be used simultaneously. set uartc5 in advance, using the pmc9, pfc9, and pfce9 registers, before use. caution the transmit/receive operation of uartc5, csie1, and i 2 c03 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-7. uartc5, csie1, and i 2 c03 mode switch settings pmc9 (pmc9h) (pmc9l) (pfc9l) (pfce9l) after reset: 0000h r/w address: pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h) after reset: 0000h r/w address: pfce9 (pfce9h) after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 pfce913 0 pfce911 pfce910 pfce99 pfce98 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 port i/o mode soe1 (csie1) rxdc5 (uartc5) scl03 (i 2 c03) pmc910 0 1 1 1 operation mode pfce910 0 0 1 pfc910 0 1 0 port i/o mode sie1 (csie1) txdc5 (uartc5) sda03 (i 2 c03) pmc99 0 1 1 1 operation mode pfce99 0 0 1 pfc99 0 1 0 port i/o mode scke1 (csie1) pmc911 0 1 operation mode pfce911 0 pfc911 0 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 804 of 1817 sep 19, 2011 17.3.7 mode switching between uartc6 and csif5 in the v850es/jj3-e, uartc6 and csif5 share of the same pin and therefore cannot be used simultaneously. set uartc6 in advance, using the pmc4, pfc4, and pfce4 registers, before use. caution the transmit/receive operation of uartc6 and csif5 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-8. uartc6 and csif5 mode switch settings port i/o mode sof5 (csif5) rxdc6 (uartc6) pmc47 0 1 1 operation mode pfce47 0 0 pfc47 0 1 port i/o mode sckf5 (csif5) pmc48 0 1 operation mode pfc48 0 pmc4 (pmc4h) (pmc4l) (pfc4l) pmc47 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0000000 pmc48 8 9 10 11 12 13 14 15 pfc4 (pfc4h) pfc4 fffff468h, pfc4l fffff468h, pfc4h fffff469h after reset: 0000h r/w address: 0000000 pfc48 pfc47 pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pmc4 fffff448h, pmc4l fffff448h, pmc4h fffff449h pfce47 pfce46 pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 pfce4 after reset: 00h r/w address: fffff708h port i/o mode sif5 (csif5) txdc6 (uartc6) pmc46 0 1 1 operation mode pfce46 0 0 pfc46 0 1 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 805 of 1817 sep 19, 2011 17.3.8 mode switching between uartc7 and csif6 in the v850es/jj3-e, uartc7 and csif6 share of the same pin and therefore cannot be used simultaneously. set uartc7 in advance, using the pmc5 and pfc5 registers, before use. caution the transmit/receive operation of uartc7 and csif6 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-9. uartc7 and csif6 mode switch settings pmc5 (pmc5h) (pmc5l) pmc57 pmc56 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 000000 pmc59 pmc58 8 9 10 11 12 13 14 15 pfc5 (pfc5h) pfc5 fffff46ah, pfc5l fffff46ah, pfc5h fffff46bh after reset: 0000h r/w address: 000000 pfc59 pfc58 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pmc5 fffff44ah, pmc5l fffff44ah, pmc5h fffff44bh (pfc5l) pfc57 pfc56 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 port i/o mode sof6 (csif6) rxdc7 (uartc7) pmc58 0 1 1 operation mode pfc58 0 1 port i/o mode sckf6 (csif6) pmc59 0 1 operation mode pfc59 0 port i/o mode sif6 (csif6) txdc7 (uartc7) pmc57 0 1 1 operation mode pfc57 0 1 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 806 of 1817 sep 19, 2011 17.4 registers (1) uartcn control register 0 (ucnctl0) the ucnctl0 register is an 8-bit register that c ontrols the uartcn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 10h. (1/2) ucnpwr disable ucrtcn operation (ucrtcn reset asynchronously) enable ucrtcn operation ucnpwr 0 1 ucrtcn operation control ucnctl0 ucntxe ucnrxe ucndir ucnps1 ucnps0 ucncl ucnsl <6> <5> <4> 3 2 1 after reset: 10h r/w address: uc0ctl0 fffffa00h, uc1ctl0 fffffa10h, uc2ctl0 fffffa20h, uc3ctl0 fffffa30h, uc4ctl0 fffffa40h, uc5ctl0 fffffa50h, uc6ctl0 fffffa60h, uc7ctl0 fffffa70h the uartcn operation is controlled by the ucnpwr bit. the txdcn pin output is fixed to high level by clearing the ucnpwr bit to 0 (fixed to low level if ucnopt0.ucntdl bit = 1). disable transmission operation enable transmission operation ucntxe 0 1 transmission operation enable ? to start transmission, set the ucnpwr bit to 1 and then set the ucntxe bit to 1. to stop transmission, clear the ucntxe bit to 0 and then ucnpwr bit to 0. ? to initialize the transmission unit, clear the ucntxe bit to 0, wait for two cycles of the base clock, and then set the ucntxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 17.7 (1) (a) base clock ). disable reception operation enable reception operation ucnrxe 0 1 reception operation enable ? to start reception, set the ucnpwr bit to 1 and then set the ucnrxe bit to 1. to stop reception, clear the ucnrxe bit to 0 and then ucnpwr bit to 0. ? to initialize the reception unit, clear the ucnrxe bit to 0, wait for two periods of the base clock, and then set the ucnrxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 17.7 (1) (a) base clock ). <7> 0 remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 807 of 1817 sep 19, 2011 (2/2) 7 bits 8 bits ucncl 0 1 specification of data character length of 1 frame of transmit/receive data ? this register can be rewritten only when the ucnpwr bit = 0 or the ucntxe bit = the ucnrxe bit = 0. ? when transmission and reception are performed in the lin format, set the ucncl bit to 1. 1 bit 2 bits ucnsl 0 1 specification of length of stop bit for transmit data this register can be rewritten only when the ucnpwr bit = 0 or the ucntxe bit = the ucnrxe bit = 0. ? this register is rewritten only when the ucnpwr bit = 0 or the ucntxe bit = the ucnrxe bit = 0. ? if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, the ucnstr.ucnpe bit is not set. ? when transmission and reception are performed in the lin format, clear the ucnps1 and ucnps0 bits to 00. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check ucnps1 0 0 1 1 parity selection during transmission parity selection during reception ucnps0 0 1 0 1 msb-first transfer lsb-first transfer ucndir 0 1 transfer direction selection ? this register can be rewritten only when the ucnpwr bit = 0 or the ucntxe bit = the ucnrxe bit = 0. ? when transmission and reception are performed in the lin format, set the ucndir bit to 1. remarks 1. for details of parity, see 17.6.9 parity types and operations . 2. n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) (2) uartcn control register 1 (ucnctl1) for details, see 17.7 (2) uartcn control register 1 (ucnctl1) . (3) uartcn control register 2 (ucnctl2) for details, see 17.7 (3) uartcn control register 2 (ucnctl2) . v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 808 of 1817 sep 19, 2011 (4) uartcn option control register 0 (ucnopt0) the ucnopt0 register is an 8-bit register that controls the serial transfer operation of the uartcn register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 14h. (1/2) ucnsrf when the ucnctl0.ucnpwr bit = ucnctl0.ucnrxe bit = 0 are set, or upon normal end of sbf reception. during sbf reception ucnsrf 0 1 sbf reception flag ucnopt0 ucnsrt ucnstt ucnsls2 ucnsls1 ucnsls0 ucntdl ucnrdl 654321 after reset: 14h r/w address: uc0opt0 fffffa03h, uc1opt0 fffffa13h, uc2opt0 fffffa23h, uc3opt0 fffffa33h, uc4opt0 fffffa43h, uc5opt0 fffffa53h, uc6opt0 fffffa63h, uc7opt0 fffffa73h sbf reception trigger ucnsrt 0 1 sbf reception trigger ? sbf (sync brake field) reception is judged during lin communication. ? the ucnsrf bit is held at 1 when an sbf reception error occurs, and then sbf reception is started again. ? the ucnsrf bit is a read-only bit. ? this is the sbf reception trigger bit during lin communication, and when read, ?0? is always read. for sbf reception, set the ucnsrt bit (to 1) to enable sbf reception. ? set the ucnsrt bit after setting the ucnpwr bit = ucnrxe bit = 1. ? this is the sbf transmission trigger bit during lin communication, and when read, ?0? is always read. ? set the ucnstt bit after setting the ucnpwr bit = ucntxe bit = 1. sbf transmission trigger ucnstt 0 1 sbf transmission trigger <7> 0 ? ? caution do not set the ucnsrt and ucnst t bits (to 1) duri ng sbf reception (ucnsrf bit = 1). remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 809 of 1817 sep 19, 2011 (2/2) ucnsls2 1 1 1 0 0 0 0 1 ucnsls1 0 1 1 0 0 1 1 0 ucnsls0 1 0 1 0 1 0 1 0 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output sbf transmission length selection ? the output level of the txdcn pin can be inverted using the ucntdl bit. ? this register can be set when the ucnpwr bit = 0 or when the ucntxe bit = 0. this register can be set when the ucnpwr bit = 0 or when the ucntxe bit = 0. normal output of transfer data inverted output of transfer data ucntdl 0 1 transmit data level bit ? the input level of the rxdcn pin can be inverted using the ucnrdl bit. ? this register can be set when the ucnpwr bit = 0 or the ucnrxe bit = 0. normal input of transfer data inverted input of transfer data ucnrdl 0 1 receive data level bit remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 810 of 1817 sep 19, 2011 (5) uartcn option control register 1 (ucnopt1) the ucnopt1 register is an 8-bit register that cont rols the serial transfer operation of uartcn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution set the ucnebe bit while the operation of uartc is disabled (ucnctl0.ucnpwr = 0). 0 ucnopt1 0 0 0 0 0 0 ucnebe 654321 after reset: 00h r/w address: uc0opt1 fffffa0ah, uc1opt1 fffffa1ah, uc2opt1 fffffa2ah, uc3opt1 fffffa3ah, uc4opt1 fffffa4ah, uc5opt1 fffffa5ah, uc6opt1 fffffa6ah, uc7opt1 fffffa7ah 0 7 extension-bit operation is prohibited. transmission/reception is performed in the data length set by the ucnctl0.ucncl bit. extension-bit operation enabled. transmission/reception can be performed in 9-bit character length. ucnebe 0 1 extension bit enable/disable ? when setting the ucnebe bit to 1, and transmitting in 9-bit data length, be sure to set the following. if this setting is not performed, the setting of ucnebe bit is invalid. ? ucnctl0.ucnps1, ucnps0 = 00 (no parity) ? cnctl0.ucncl = 1 (8-bit character length) ? if transmitting or receiving in the lin communication format, set the ucnebe to 0. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) the following shows the relationship between t he register setting value and the data format. v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 811 of 1817 sep 19, 2011 table 17-2. relationship between register setting and data format register setting data format ucnctl0 ucnopt1 ucncl ucnps1 ucnps0 ucnsl ucnebe d0 to d6 d7 d8 d9 d10 0 0 0 data stop ? ? ? 0 other than 00 data parity stop ? ? 1 0 0 data data stop ? ? 1 other than 00 0 0 data data parity stop ? 0 0 0 data stop stop ? ? 0 other than 00 data parity stop stop ? 1 0 0 data data stop stop ? 1 other than 00 1 0 data data parity stop stop 0 0 0 data stop ? ? ? 0 other than 00 data parity stop ? ? 1 0 0 data data data stop ? 1 other than 00 0 1 data data parity stop ? 0 0 0 data stop stop ? ? 0 other than 00 data parity stop stop ? 1 0 0 data data data stop stop 1 other than 00 1 1 data data parity stop stop remarks 1. data: data bit stop: stop bit parity: parity bit 2. n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 812 of 1817 sep 19, 2011 (6) uartcn status register (ucnstr) the ucnstr register is an 8-bit register that displays t he uartcn transfer status and reception error contents. this register can be read or written in 8-bit or 1-bit un its, but the ucntsf bit is a read-only bit, while the ucnpe, ucnfe, and ucnove bits can both be read and written. however, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). the initialization conditions are shown below. register/bit initialization conditions ucnstr register ? reset ? ucnctl0.ucnpwr = 0 ucntsf bit ? ucnctl0.ucntxe = 0 ucnpe, ucnfe, ucnove bits ? 0 write ? ucnctl0.ucnrxe = 0 remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 813 of 1817 sep 19, 2011 ucntsf ? when the ucnpwr bit = 0 or the ucntxe bit = 0 has been set. ? when, following transfer completion, there was no next data transfer from ucntx register write to ucntx register ucntsf 0 1 transfer status flag ucnstr 0 0 0 0 ucnpe ucnfe ucnove 6 5 4 3 <2> <1> after reset: 00h r/w address: uc0str fffffa04h, uc1str fffffa14h, uc2str fffffa24h, uc3str fffffa34h, uc4str fffffa44h, uc5str fffffa54h, uc6str fffffa64h, uc7str fffffa74h the ucntsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the ucntsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the ucntsf bit = 1. ? when the ucnpwr bit = 0 or the ucnrxe bit = 0 has been set. ? when 0 has been written when parity of data and parity bit do not match during reception. ucnpe 0 1 parity error flag ? the operation of the ucnpe bit is controlled by the settings of the ucnctl0.ucnps1 and ucnctl0.ucnps0 bits. ? the ucnpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained. ? when the ucnpwr bit = 0 or the ucnrxe bit = 0 has been set ? when 0 has been written when no stop bit is detected during reception ucnfe 0 1 framing error flag ? only the first bit of the receive data stop bits is checked, regardless of the value of the ucnctl0.ucnsl bit. ? the ucnfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained . ? when the ucnpwr bit = 0 or the ucnrxe bit = 0 has been set. ? when 0 has been written when receive data has been set to the ucnrx register and the next receive operation is completed before that receive data has been read ucnove 0 1 overrun error flag ? when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. ? the ucnove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the value is retained . <7> <0> remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 814 of 1817 sep 19, 2011 (7) uartcn receive data register l (ucnrxl) and uartcn receive data register (ucnrx) the ucnrxl and ucnrx register are an 8- bit or 9-bit buff er register that stores par allel data converted by the receive shift register. the data stored in the receive shift register is transferred to the ucnrxl and ucnrx register upon completion of reception of 1 byte of data. during lsb-first reception when the data length has been spec ified as 7 bits, the receive data is transferred to bits 6 to 0 of the ucnrxl register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the ucnrxl register and the lsb always becomes 0. when an overrun error (ucnove) occurs, the receive data at this time is not transferred to the ucnrxl and ucnrx register and is discarded. the access unit or reset value differs depending on the character length. ? character length 7/8-bit (ucnopt1.ucnebe = 0) this register is read-only, in 8-bit units. reset or ucnctl0.ucnpwr bit = 0 sets this register to ffh. ? character length 9-bit (ucnopt1.ucnebe = 0) this register is read-only, in 16-bit units. reset or ucnctl0.ucnpwr bit = 0 sets this register to 01ffh. (a) character length 7/8- bit (ucnopt1.ucnebe = 0) ucnrxl 654321 after reset: ffh r address: uc0rxl fffffa06h, uc1rxl fffffa16h, uc2rxl fffffa26h, uc3rxl fffffa36h, uc4rxl fffffa46h, uc5rxl fffffa56h, uc6rxl fffffa66h, uc7rxl fffffa76h 7 0 (b) character length 9-bi t (ucnopt1.ucnebe = 1) after reset: 01ffh r address: uc0rx fffffa06h, uc1rx fffffa16h, uc2rx fffffa26h, uc3rx fffffa36h, uc4rx fffffa46h, uc5rx fffffa56h, uc6rx fffffa66h, uc7rx fffffa76h ucnrx 654321 70 0000000 14 13 12 11 10 9 15 8 remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 815 of 1817 sep 19, 2011 (8) uartcn transmit data register l (ucntx l), uartcn transmit data register (ucntx) the ucntxl and ucntx register is an 8-bit or 9-bit register used to set transmit data. during lsb-first transmission when the data length has been s pecified as 7 bits, the transmit data is transferred to bits 6 to 0 of the ucnrx register. during msb-first transmi ssion, the receive data is transferred to bits 7 to 1 of the ucnrx register. the access unit or reset value differs depending on the character length. ? character length 7/8-bit (ucnopt1.ucnebe = 0) this register can be read or written in 8-bit units. reset sets this register to ffh. ? character length 9-bit (ucnopt1.ucnebe = 0) this register can be read or written in 16-bit units. reset sets this register to 01ffh. cautions 1. in the transmission operation enable status (ucnpwr = 1 and ucntxe = 1), writing to the ucntxl, ucntx register, as operate as trigger of transmission star, if writing the value of as soon as before and save value, before the int ucnt interrupt is occurre d, the same data is transferred at twice. 2. data writing for consecutive transmission, after be generated the intucnt interrupt. if writing the next data before the in tucnt interrupt is occurred, transmission start processing and source of conflict writing the ucntxl, ucntx register, unexpected operations may occur. 3. if perform to write the ucntxl, ucntxlin the disable transmission operation register, can not be used as transmission start trigger. consequently, even if transmission enable status after perform to write the ucntxl, ucntx register in the disable transmission operation status, can not be started transmission. (a) character length 7/8- bit (ucnopt1.ucnebe = 0) ucntxl 654321 after reset: ffh r/w address: uc0txl fffffa08h, uc1txl fffffa18h, uc2txl fffffa28h, uc3txl fffffa38h, uc4txl fffffa48h, uc5txl fffffa58h, uc6txl fffffa68h, uc7txl fffffa78h 7 0 (b) character length 9-bi t (ucnopt1.ucnebe = 1) after reset: 01ffh r/w address: uc0tx fffffa08h, uc1tx fffffa18h, uc2tx fffffa28h, uc3tx fffffa38h, uc4tx fffffa48h, uc5tx fffffa58h, uc6tx fffffa68h, uc7tx fffffa78h ucntx 654321 70 0000000 14 13 12 11 10 9 15 8 remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 816 of 1817 sep 19, 2011 17.5 interrupt request signals the following two interrupt request signals are generated from uartcn. ? reception completion interrupt request signal (intucnr) ? transmission enable interrupt request signal (intucnt) the default priority for these two interrupt request sign als is reception completion interrupt request signal then transmission enable interrupt request signal. table 17-3. interrupts and their default priorities interrupt priority reception complete high transmission enable low (1) reception completion interrupt request signal (intucnr) a reception completion interrupt request signal is output when data is shifted into the receive shift register and transferred to the ucnrx register in the reception enabled status. a reception completion interrupt request signal is also output when a reception error o ccurs. therefore, when a reception completion interrupt request signal is acknowledged and the data is read, read the ucnstr register and check that the reception result is not an error. no reception completion interrupt request signal is generated in the reception disabled status. (2) transmission enable interr upt request signal (intucnt) if transmit data is transferred from the ucntx register to the uartcn transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 817 of 1817 sep 19, 2011 17.6 operation 17.6.1 data format full-duplex serial data reception and transmission is performed. as shown in figure 17-10, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data frame, parity selection, s pecification of the stop bit length, and specification of msb/lsb-first transfer ar e performed using the ucnctl0 register. moreover, control of uart output/inverted output for the txdcn bit is performed using the ucnopt0.ucntdl bit. ? start bit ..................1 bit ? character bits ........7 bits/8 bits ? parity bit ................even parity/odd parity/0 parity/no parity ? stop bit ..................1 bit/2 bits v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 818 of 1817 sep 19, 2011 figure 17-10. uartc transmit/receive data format (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txdcn inversion 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (d) 7-bit data length, lsb first, odd pa rity, 2 stop bits, transfer data: 36h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 parity bit stop bit stop bit (e) 8-bit data length, lsb first, no pa rity, 1 stop bit, transfer data: 87h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 819 of 1817 sep 19, 2011 17.6.2 sbf transmission/reception format the v850es/jh3-e and v850es/jj3-e have an sbf (sync br eak field) transmission/reception control function to enable use of the lin function. remark lin stands for local interconnect network and is a lo w-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to control the switches, act uators, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method a nd is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame wit h baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is 15% or less. figures 17-11 and 17-12 outline the transmission and reception manipulations of lin. figure 17-11. lin transmission manipulation outline lin bus wake-up signal frame sync break field sync field identifier field data field data field check sum field intucnt interrupt txdcn (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. sbf output is performed by har dware. the output width is the bit length set by the ucnopt0.ucnsls2 to ucnopt0. ucnsls0 bits. if even finer output width adjustments are required, such adjustments can be per formed using the ucnctl2.ucnbrs7 to ucnctl2.ucnbrs0 bits. 3. 80h transfer in the 8-bit mode is substituted for the wakeup signal frame. 4. a transmission enable interrupt request signal (intucn t) is output at the star t of each transmission. the intucnt signal is also output at the start of each sbf transmission. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 820 of 1817 sep 19, 2011 figure 17-12. lin reception manipulation outline reception interrupt (intucnr) edge detection capture timer disable disable enable rxdcn (input) enable note 2 13 bits sbf reception note 3 note 4 note 1 sf reception id reception data transmission data transmission note 5 data transmission lin bus wake-up signal frame sync break field sync field identifier field data field data field check sum field notes 1. the wakeup signal is sent by the pin edge detec tor, uartcn is enabled, and the sbf reception mode is set. 2. the receive operation is performed until detection of the stop bit. upon detection of sbf reception of 11 or more bits, normal sbf reception end is judged, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits, an sbf reception error is judged, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. if sbf reception ends normally, an interrupt request signal is output. the timer is enabled by an sbf reception completion interrupt. moreover, error detection for the ucnstr.ucnove, ucnstr.ucnpe, and ucnstr.ucnfe bits is suppres sed and uart communication error detection processing and uartcn receive shift register and data transfer of the ucnrx register are not performed. the uartcn receive shift register holds the initial value, ffh. 4. the rxdcn pin is connected to ti (capture input) of the timer, the tr ansfer rate is calculated, and the baud rate error is calculated. the value of the ucnctl2 register obtained by correcting the baud rate error after dropping uartc enable is set agai n, causing the status to become the reception status. 5. check-sum field distinctions are made by software. uartc is initialized following csf reception, and the processing for setting the sbf reception mode again is performed by software. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 821 of 1817 sep 19, 2011 17.6.3 sbf transmission when the ucnctl0.ucnpwr bit = ucnctl0.ucn txe bit = 1, the transmission enab led status is entered, and sbf transmission is started by setting (to 1) the sbf transmission trigger (ucnopt0.ucnstt bit). thereafter, a low level the width of bi ts 13 to 20 specified by the ucnopt0.ucnsls2 to ucnopt0.ucnsls0 bits is output. a transmission enable interrupt request signal (intuc nt) is generated upon sbf transmission start. following the end of sbf transmission, the ucnstt bit is automatically cleared. thereafter, t he uart transmission mode is restored. transmission is suspended until the data to be transmitted next is written to the ucntx register, or until the sbf transmission trigger (ucnstt bit) is set. figure 17-13. sbf transmission intucnt interrupt txdcn 12345678910111213 stop bit setting of ucnstt bit remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 822 of 1817 sep 19, 2011 17.6.4 sbf reception the reception wait status is enter ed by setting the ucnctl0.ucnpwr bit to 1 and then setting the ucnctl0.ucnrxe bit to 1. the sbf reception wait status is set by setting the sbf reception trigger (ucnop t0.ucnsrt bit) to 1. in the sbf reception wait status, simila rly to the uart reception wait status, the rxdcn pin is monitored and start bit detection is performed. following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, normal processing is judged and a reception completion interrupt request signal (intucnr) is output. the ucnopt0.ucn srf bit is automatically cleared and sbf reception ends. error detection for the ucnstr.ucnove, ucnstr.ucn pe, and ucnstr.ucnfe bits is suppressed and uart communication error detection processing is not performed. moreover, data transfer of the uartcn reception shift register and ucnrx register is not performed and ffh, the init ial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as error proce ssing without outputting an interrupt, and the sbf reception mode is returned to. the ucnsrf bit is not cleared at this time. cautions 1. if sbf is tran smitted during a data recepti on, a framing error occurs. 2. do not set the sbf reception trigger bit (ucnsrt) and sbf transm ission trigger bit (ucnstt) to 1 during an sbf reception (ucnsrf = 1). figure 17-14. sbf reception (a) normal sbf reception (detection of stop bit in more than 10.5 bits) ucnsrf rxdcn 123456 11.5 7 8 9 10 11 intucnr interrupt (b) sbf reception error (detection of stop bit in 10.5 or fewer bits) ucnsrf rxdcn 123456 10.5 78910 intucnr interrupt remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) 17.6.5 uart transmission a high level is output to the txdcn pin by setting the ucnctl0.ucnpwr bit to 1. v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 823 of 1817 sep 19, 2011 next, the transmission enabled status is set by setting the ucnctl0.ucntxe bit to 1, and transmission is started by writing transmit data to the ucntx regi ster. the start bit, parity bit, and stop bit are automatically added. since the cts (transmit enable signal) input pin is not prov ided in uartcn, use a port to check that reception is enabled at the transmit destination. the data in the ucntx register is trans ferred to the uartcn transmit shift r egister upon the start of the transmit operation. a transmission enable interrupt request signal (intucnt) is generated upon completion of transmission of the data of the ucntx register to the uartcn transmit shift register, and thereafter the contents of the ua rtcn transmit shift register are output to the txdcn pin. write of the next transmit data to the ucntx register is enabled afte r the intucnt signal is generated. figure 17-15. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intucnt txdcn remarks 1. lsb first 2. n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 824 of 1817 sep 19, 2011 17.6.6 continuous transmission procedure uartcn can write the next transmit data to the ucntx register when the uartcn transmit shi ft register starts the shift operation. the transmit timing of the ua rtcn transmit shift register can be judged from the transmission enable interrupt request signal (intucnt). an efficient communication rate is realized by writing the data to be transmitted next to the ucntx register during transfer. caution when initializing transmissi ons during the execution of contin uous transmissions, make sure that the ucnstr.ucntsf bit is 0, then perform the initializat ion. transmit data that is initialized when the ucntsf bit is 1 cannot be guaranteed. figure 17-16. continuous transmission processing flow start register settings ucntx write yes yes no no occurrence of transmission interrupt? required number of writes performed? end remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 825 of 1817 sep 19, 2011 figure 17-17. continuous transmission operation timing (a) transmission start start data (1) data (1) txdcn ucntx transmission shift register intucnt ucntsf data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) transmission end start data (n ? 1) data (n ? 1) data (n ? 1) data (n) ff data (n) txdcn ucntx transmission shift register intucnt ucntsf ucnpwr or ucntxe bit parity stop stop start data (n) parity parity stop remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 826 of 1817 sep 19, 2011 17.6.7 uart reception the reception wait status is set by setting the ucnctl0. ucnpwr bit to 1 and then setting the ucnctl0.ucnrxe bit to 1. in the reception wait status, the rxdcn pi n is monitored and start bit detection is performed. start bit detection is performed using a two-step detection routine. first the rising edge of the rxdcn pin is detected and sampling is started at the falling ed ge. the start bit is recognized if the rxdcn pin is low level at the start bit sa mpling point. after a start bit has been recognized, the receive operation starts, and serial data is saved to the uartcn receive shift register according to the set baud rate. when the reception completion interrupt request signal (int ucnr) is output upon reception of the stop bit, the data of the uartcn receive shift register is written to the ucnrx register. however, if an overrun error (ucnstr.ucnove bit) occurs, the receive data at this time is not wr itten to the ucnrx register and is discarded. even if a parity error (ucnstr.ucnpe bit) or a framing erro r (ucnstr.ucnfe bit) occurs during reception, reception continues until the reception position of the first stop bit, and intucnr is out put following reception completion. figure 17-18. uart reception start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intucnr rxdcn ucnrx remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 827 of 1817 sep 19, 2011 cautions 1. be sure to read the ucn rx register even when a reception erro r occurs. if the ucnrx register is not read, an overrun error occurs during reception of the next data, and recep tion errors continue occurring indefinitely. 2. the operation during reception is performed assuming that ther e is only one stop bit. a second stop bit is ignored. 3. when reception is completed, read the ucnrx register after the reception completion interrupt request signal (intucnr) has been generated, and clear the ucnpwr or ucnrxe bit to 0. if the ucnpwr or ucnrxe bit is cleared to 0 before the intucnr signal is generated, the read value of the ucnrx register cannot be guaranteed. 4. if receive completion processing (intucnr signa l generation) of uartcn and the ucnpwr bit = 0 or ucnrxe bit = 0 conflict, the intucnr signal ma y be generated in spite of these being no data stored in the ucnrx register. to complete reception without wa iting for the intucnr signal to be generated, be sure to set (1) the interrupt mask flag (ucnrmk) of the interrupt control register (ucnric), clear (0) the ucnpwr bit or ucnrxe bit, and then clear the interrupt request flag (ucnrif) of the ucnric register. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 828 of 1817 sep 19, 2011 17.6.8 reception errors errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. data reception result error flags are set in the ucnstr register and a recept ion completion interrupt request signal (intucnr) is output when an error occurs. it is possible to ascertain which error occurred during rec eption by reading the contents of the ucnstr register. clear the reception error flag by writing 0 to it after reading it. figure 17-19. receive data read flow start no intucnr signal generated? error occurs? end yes no yes error processing read ucnrx register read ucnstr register caution when an intucnr signal is generated, the ucn str register must be read to check for errors. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 829 of 1817 sep 19, 2011 ? reception error causes error flag reception error cause ucnpe parity error received parity bit does not match the setting ucnfe framing error stop bit not detected ucnove overrun error reception of next data completed before data was read from receive buffer when reception errors occur, perform the followin g procedures depending upon the kind of error. ? parity error if false data is received due to problems such as noise in the reception line, discard the received data and retransmit. ? framing error a baud rate error may have occurred between the reception side and transmission side or the start bit may have been erroneously detected. since this is a fatal error for the communication format, check the operation stop in the transmission side, perform initialization processing ea ch other, and then start the communication again. ? overrun error since the next reception is completed before reading receiv e data, 1 frame of data is di scarded. if this data was needed, do a retransmission. caution if a receive error interrupt occurs during cont inuous reception, read the contents of the ucnstr register must be read before the next recepti on is completed, then pe rform error processing. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 830 of 1817 sep 19, 2011 17.6.9 parity types and operations caution when using the lin function, fix the ucn ctl0.ucnps1 and ucnctl0.ucnps0 bits to 00. the parity bit is used to detect bit errors in the communication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (a) even parity (i) during transmission the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 1 ? even number of bits whose value is ?1? among transmit data: 0 (ii) during reception the number of bits whose value is ?1 ? among the reception data, including t he parity bit, is counted, and if it is an odd number, a parity error is output. (b) odd parity (i) during transmission opposite to even parity, the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so that it is an odd number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 (ii) during reception the number of bits whose value is ?1? among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity e rror occurs, regardless of whether the parity bit is 0 or 1. (d) no parity no parity bit is added to the transmit data. reception is performed assuming that ther e is no parity bit. no parity error occurs since there is no parity bit. v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 831 of 1817 sep 19, 2011 17.6.10 receive data noise filter this filter samples the rxdcn pin using the base clock of the prescaler output. when the same sampling value is read twice, the match dete ctor output changes and the rx dcn signal is sampled as the input data. therefore, data not exceed ing 2 clock width is judged to be noise and is not delivered to the internal circuit (see figure 17-18 ). see 17.7 (1) (a) base clock regarding the base clock. moreover, since the circuit is as shown in figure 17-17, t he processing that goes on within the receive operation is delayed by 3 clocks in relation to the external signal status. figure 17-20. noise filter circuit match detector in base clock (f uclk ) rxdcn qin ld_en q internal signal c internal signal b in q internal signal a remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) figure 17-21. timing of rxdcn signal judged as noise internal signal b base clock rxdcn (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 832 of 1817 sep 19, 2011 17.7 dedicated baud rate generator the dedicated baud rate generator consists of a source cl ock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartcn. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. (1) baud rate generator configuration figure 17-22. configuration of baud rate generator f uclk selector ucnpwr 8-bit counter match detector baud rate ucnctl2: ucnbrs7 to ucnbrs0 1/2 ucnpwr, ucntxen bit s (or ucnrxe bit) ucnctl1: ucncks3 to ucncks0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 f xx /2048 asckc0 note note only uartc0 is valid; setting uartc1 and uartc7 is prohibited. remarks 1. n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) 2. f xx : main clock frequency f uclk : base clock frequency (a) base clock when the ucnctl0.ucnpwr bit is 1, the clock select ed by the ucnctl1.ucncks3 to ucnctl1.ucncks0 bits is supplied to the 8-bit counter. this clock is called the base clock (f uclk ). (b) serial clock generation a serial clock can be generated by setting the ucnctl1 register and the ucnctl2 register (n = 0 to 4). the base clock is selected by ucnctl1.ucncks3 to ucnctl1.ucncks0 bits. the frequency division value for the 8-bit count er can be set using the ucnctl2.ucnbrs7 to ucnctl2.ucnbrs0 bits. v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 833 of 1817 sep 19, 2011 (2) uartcn control register 1 (ucnctl1) the ucnctl1 register is an 8-bit register that selects the uartcn base clock. this register can be read or written in 8-bit units. reset sets this register to 00h. caution clear the ucnctl0.ucn pwr bit to 0 before rewriting the ucnctl1 register. 0 ucnctl1 0 0 0 ucncks3ucncks2 ucncks1 ucncks0 654321 after reset: 00h r/w address: uc0ctl1 fffffa01h, uc1ctl1 fffffa11h, uc2ctl1 fffffa21h, uc3ctl1 fffffa31h, uc4ctl1 fffffa41h, uc5ctl1 fffffa51h, uc6ctl1 fffffa61h, uc7ctl1 fffffa71h 7 0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 external clock note (asckc0 pin) setting prohibited ucncks2 0 0 0 0 1 1 1 1 0 0 0 0 ucncks3 0 0 0 0 0 0 0 0 1 1 1 1 base clock (f uclk ) selection ucncks1 0 0 1 1 0 0 1 1 0 0 1 1 ucncks0 0 1 0 1 0 1 0 1 0 1 0 1 other than above note only uartc0 is valid; setting uart c1 to uartc7 is prohibited. remarks 1. f xx : main clock frequency 2. n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 834 of 1817 sep 19, 2011 (3) uartcn control register 2 (ucnctl2) the ucnctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartcn. this register can be read or written in 8-bit units. reset sets this register to ffh. caution clear the ucnctl0. ucnpwr bit to 0 or clear the ucntxe an d ucnrxe bits to 00 before rewriting the ucnctl2 register. setting prohibited ucnbrs7 ucnctl2 ucnbrs6 ucnbrs5 ucnbrs4 ucnbrs3ucnbrs2 ucnbrs1 ucnbrs0 654321 after reset ffh r/w address: uc0ctl2 fffffa02h, uc1ctl2 fffffa12h, uc2ctl2 fffffa22h, uc3ctl2 fffffa32h, uc4ctl2 fffffa42h, uc5ctl2 fffffa52h, uc6ctl2 fffffa62h, uc7ctl2 fffffa72h 7 0 ucn brs7 0 0 0 0 : 1 1 1 1 1 1 ucn brs6 0 0 0 0 : 1 1 1 1 1 1 ucn brs5 0 0 0 0 : 1 1 1 1 1 1 ucn brs4 0 0 0 0 : 1 1 1 1 1 1 ucn brs3 0 0 0 0 : 0 0 1 1 1 1 ucn brs2 0 1 1 1 : 0 0 1 1 1 1 ucn brs1 0 0 1 : 1 1 0 0 1 1 ucn brs0 0 1 0 : 0 1 0 1 0 1 default (k) 4 5 6 : 250 251 252 253 254 255 serial clock f uclk /4 f uclk /5 f uclk /6 : f uclk /250 f uclk /251 f uclk /252 f uclk /253 f uclk /254 f uclk /255 remarks 1. f uclk : clock frequency selected by the ucnctl1.ucncks3 to ucnctl1.ucncks0 bits 2. n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 835 of 1817 sep 19, 2011 (4) baud rate the baud rate is obtained by the following equation. baud rate = [bps] when using the internal clock, the equation will be as follows (when using the asckc0 pin as clock at uartc0, calculate using the above equation). baud rate = [bps] remark f uclk = frequency of base clock selected by the ucnctl1.ucncks3 to ucnctl1.ucncks0 bits f xx : main clock frequency m = value set using the ucnctl1.ucncks3 to ucnctl1.ucncks0 bits (m = 0 to 10) k = value set using the ucnctl2.ucnbrs7 to ucnctl2.ucnbrs0 bits (k = 4 to 255) the baud rate error is obtained by the following equation. error (%) = ? 1 100 [%] = ? 1 100 [%] when using the internal clock, the equation will be as follows (when using the asckc0 pin input as the clock for uartc0, calculate the baud rate error using the above equation). error (%) = ? 1 100 [%] cautions 1. the baud rate erro r during transmission must be wit hin the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in (5) allowable baud rate range dur ing reception. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) f uclk 2 k actual baud rate (baud rate with error) target baud rate (correct baud rate) f xx 2 m+1 k f uclk 2 k target baud rate f xx 2 m+1 k target baud rate v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 836 of 1817 sep 19, 2011 to set the baud rate, perform the following calculatio n for setting the ucnctl1 and ucnctl2 registers (when using internal clock). <1> set k to fxx/2/(2 target baud rate) and m to 0. <2> if k is 256 or greater (k 256), reduce k to half (k/2) and increment m by 1 (m + 1). <3> repeat step <2> until k becomes less than 256 (k < 256). <4> round off the first decimal point of k to the nearest whole number. if k becomes 256 after round-off, perform step <2> again to set k to 128. <5> set the value of m to ucnctl1 register a nd the value of k to the ucnctl2 register. example : when f xx = 50 mhz and target baud rate = 153,600 bps <1> k = 50,000,000/2/(2 153,600) = 81.380?, m = 0 <2>, <3> k = 81.380? < 256, m = 0 <4> set value of ucnctl2 register: k = 81 = 51h, set value of ucnctl1 register: m = 0 actual baud rate = 50,000,000/2/(2 81) = 154,321 [bps] baud rate error = {50,000,000/2/(2 81 153,600) ? 1} 100 = 0.469 [%] the representative examples of baud rate settings are shown below. table 17-4. baud rate generator setting data f xx = 50 mhz f xx = 48 mhz f xx = 32 mhz f xx = 24 mhz baud rate (bps) ucnc tl1 ucnc tl2 err (%) ucnc tl1 ucnc tl2 err (%) ucnc tl1 ucnc tl2 err (%) ucnc tl1 ucnc tl2 err (%) 300 08h a3h ? 0.15 08h 9ch 0.16 07h d0h 0.16 07h 9ch ? 2.3 600 07h a3h ? 0.15 07h 9ch 0.16 06h d0h 0.16 06h 9ch 0.16 1200 06h a3h ? 0.15 06h 9ch 0.16 05h d0h 0.16 05h 9ch 0.16 2400 05h a3h ? 0.15 05h 9ch 0.16 04h d0h 0.16 04h 9ch 0.16 4800 04h a3h ? 0.15 04h 9ch 0.16 03h d0h 0.16 03h 9ch 0.16 9600 03h a3h ? 0.15 03h 9ch 0.16 02h d0h 0.16 02h 9ch 0.16 19200 02h a3h ? 0.15 02h 9ch 0.16 01h d0h 0.16 01h c0h 0.16 31250 01h c0h ? 0.15 01h c0h 0.00 01h 80h 0.00 01h 9ch 0.00 38400 01h a3h ? 0.15 01h 9ch 0.16 00h d0h 0.16 00h 4eh 0.16 76800 00h a3h ? 0.15 00h 9ch 0.16 00h 68h 0.16 00h 4eh 0.16 153600 00h 51h 0.47 00h 4eh 0.16 00h 34h 0.16 00h 27h 0.16 312500 00h 28h 0.00 00h 26h 1.05 00h 1ah ? 1.54 00h 13h 1.05 625000 00h 14h 0.00 00h 13h 1.05 00h 0dh ? 1.54 00h 0ah ? 4.00 1000000 00h 0dh ? 3.85 00h 0ch 0.00 00h 08h 0.00 00h 06h 0.00 1250000 00h 0ah 0.00 00h 0ah ? 4.00 setting prohibited 00h 05h ? 4.00 2000000 00h 06h 4.17 00h 06h 0.00 00h 04h 0.00 2500000 00h 05h 0.00 00h 05h ? 4.00 3000000 00h 04h 4.17 00h 04h 0.00 setting prohibited setting prohibited remark f xx : main clock frequency err: baud rate error (%) n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 837 of 1817 sep 19, 2011 (5) allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error durin g reception must be set within the allowable error range using the following equation. figure 17-23. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartcn transfer rate start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) as shown in figure 17-23, the receive data latch timi ng is determined by the counter set using the ucnctl2 register following start bit detection. t he transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, t he following is the theoretical result. fl = (brate) ? 1 brate: uartcn baud rate k: set value of ucnctl2.ucnbrs7 to ucnctl2.ucnbrs0 bits fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 838 of 1817 sep 19, 2011 therefore, the maximum baud rate that can be re ceived by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the following maximum allowable transfer rate yields the following. flmax = 11 fl ? fl = fl flmax = fl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartcn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 17-5. maximum/minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.32% ? 2.43% 8 +3.52% ? 3.61% 20 +4.26% ? 4.30% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.72% remarks 1. the reception accuracy depends on the bi t count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: set value of ucnctl2.ucnbrs7 to ucnctl2.ucnbrs0 bits 3. n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2 v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 839 of 1817 sep 19, 2011 (6) transfer rate during continuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. however, timing initialization is performed via st art bit detection by the receiving side, so this has no influence on the transfer result. figure 17-24. transfer rate during continuous transfer start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of 2nd byte start bit bit 0 the following equation can be obtained assuming 1 bit data length: fl; stop bit length: flstp; and base clock frequency: f uclk . flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + (2/f uclk ) v850es/jh3-e, v850es/jj3-e chapter 17 asynchronous serial interface c (uartc) r01uh0290ej0300 rev.3.00 page 840 of 1817 sep 19, 2011 17.8 cautions (1) when the clock supply to uartcn is stopped (for example, in idle1, idle2, or stop mode), the operation stops with each register retaining the value it had immediat ely before the clock supply was stopped. the txdcn pin output also holds and outputs the valu e it had immediately before the clock supply was stopped. however, the operation is not guaranteed after the clock supply is resum ed. therefore, after the clock supply is resumed, the circuits should be initialized by setting the ucn ctl0.ucnpwr, ucnctl0.ucnr xen, and ucnctl0.ucntxen bits to 000. (2) start up the uartcn in the following sequence. <1> set the ucnctl0.ucnpwr bit to 1. <2> set the ports. <3> set the ucnctl0.ucntxe bit to 1, ucnctl0.ucnrxe bit to 1. (3) stop the uartcn in the following sequence. <1> set the ucnctl0.ucntxe bit to 0, ucnctl0.ucnrxe bit to 0. <2> set the ports and set the ucnctl0.ucnpwr bit to 0 (it is not a problem if port setting is not changed). (4) in transmit mode (ucnctl0.ucnpwr bit = 1 and ucnctl0. ucntxe bit = 1), do not overwrite the same value to the ucntx register by software because transmission starts by writing to this register. to transmit the same value continuously, overwrite the same value. (5) in continuous transmission, the communication rate from the stop bit to the next star t bit is extended 2 base clocks more than usual. however, the reception side initializes th e timing by detecting the start bit, so the reception result is not affected. remark n = 0 to 5 (v850es/jh3-e) n = 0 to 7 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 841 of 1817 sep 19, 2011 chapter 18 clocked serial interface e with fifo (csie) in the v850es/jh3-e and v850es/jj3-e, clocked serial inte rface e with fifo (csie) is provided with 2 channels. 18.1 port setting of csie0 and csie1 18.1.1 v850es/jh3-e table 18-1. pin configuration alternate-function pin mode pin name pin no. port pin other functions sie0 6 p43 txdc4/rtp03/hldak soe0 7 p44 rxdc4/rtp04/hldrq csie0 scke0 8 p45 tiaa41/toaa41/rtp05 74 p99 txdc5/sda03/a9 sie1 105 pdh0 a16 75 p910 rxdc5/scl03/a10 soe1 106 pdh1 a17 76 p911 tiaa50/toaa50/a11 csie1 scke1 107 pdh2 a18 cautions 1. do not switch port settings during operat ion. be sure to disable operation of the unit which does not perform the port setting and is not being used. 2. the pins for csie1 (sie1, soe1, and sc ke1) also function as the p99, p910, and p911 pins and the pdh0, pdh1, and pdh2 pins as shown in table 18-1. when specifying the p99, p910, and p911 pins to be used as th e sie1, soe1, and scke1 pins, do not also specify the pdh0, pdh1, and pdh2 pins to be used as the sie1, soe1, and scke1 pins, and vice versa. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 842 of 1817 sep 19, 2011 18.1.2 v850es/jj3-e table 18-2. pin configuration alternate-function pin mode pin name pin no. port alternate function sie0 6 p43 txdc4/rtp03 soe0 7 p44 rxdc4/rtp04 csie0 scke0 8 p45 tiaa41/toaa41/rtp05 80 p99 txdc5/sda03/a9 sie1 111 pdh0 a16 81 p910 rxdc5/scl03/a10 soe1 112 pdh1 a17 82 p911 tiaa50/toaa50/a11 csie1 scke1 113 pdh2 a18 cautions 1. do not switch port settings during operat ion. be sure to disable operation of the unit which does not perform the port setting and is not being used. 2. the pins for csie1 (sie1, soe1, and s cke1) are assigned to po rts p99/p910/p911 and pdh0//pdh1/pdh2 as shown in table 18-2. when using these pins via ports p99/p910/p911, do not use them via ports pdh0//pdh1/pdh2, and vice versa. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 843 of 1817 sep 19, 2011 18.2 features { transfer rate: 5 mbps max. { master mode and slave mode selectable { transfer data length selectable in 1-bit units between 8 and 16 bits { transfer data msb-first/lsb-first switchable { serial clock and data phase switchable { sixteen on-chip 16-bit transmission/reception buffers (csibufn) available { transmission mode, reception mode, and transmission/reception mode specifiable ? transmission mode: transmission is started by wr iting transmit data to the csien transmit buffer register (centx0) while transmission is enabled. ? reception mode: reception is st arted by writing dummy data to the csien transmit buffer register (centx0) while reception is enabled. ? transmission/reception mode: transmission/reception is st arted by writing transmit data to the csien transmit buffer register (centx0) while transmission/reception is enabled. { interrupt request signals ? transmit/receive comple tion interrupt (intcent) ? csibufn overflow interrupt (intcentiof) { 3-wire soen: serial data output sien: serial data input scken: serial clock i/o remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 844 of 1817 sep 19, 2011 18.3 configuration the following shows the block diagram of csien. figure 18-1. block diagram of csien soen scken intcent sien scken transfer control csi data buffer register n (csibufn) brgn prescaler output f xx csien reception data buffer register (cenrx0) 15 0 intcentiof transfer data control csien status register (censtr) csien transmission buffer register (centx0) selector csien control register 1 (cenctl1) cenmdl1 cenmdl0 cencks2 cencks1 cencks0 cenmdl2 internal bus internal bus shift register n (sion) remark 1. n = 0, 1 2. f xx : main clock frequency v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 845 of 1817 sep 19, 2011 csien includes the following hardware. table 18-3. configuration of csien item configuration registers serial i/o shift register n (sion) csien receive data buffer register (cenrx0) csien transmit data buffer register (centx0) csi data buffer register n (csibufn) control registers csien control register 0 (cenctl0) csien control register 1 (cenctl1) csien control register 2 (cenctl2) csien control register 3 (cenctl3) csien status register (censtr) v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 846 of 1817 sep 19, 2011 (1) serial i/o shift registers n (sion) the sion register is an 8-bit register for converting between serial data and parallel data. sion is used for both transmission and reception. data is shifted in (reception) or shifted out (transmissi on) beginning at either the msb side or the lsb side. (2) csien receive data buffer register (cenrx0) the cenrx0 register is a 16-bit buffer register that stores receive data. by consecutively reading this register in the continuous mode (cenctl0.centms bit = 1), the received data in the csibufn register can be sequentially read while the csibufn pointer for reading is incremented. however, if the number of the read value exceeds the receive data co unt in the cenrx0 regist er, the read value becomes undefined. in the single mode (cenctl0.centms bit = 1), received dat a is read by reading the cenrx0 register and it is judged that the cenrx0 register has become empty. the cenrx0 register is read-only, in 16-bit units. when the higher 8 bits of the cenrx0 register are used as the cenrx0h r egister and the lower 8 bits as the cenrx0l register, these registers are read-only, in 8-bit units. when reading in 8-bit units, be sure to read the cenrx0h register and cenrx0l register in that order. the received data is always read from the lower bits, regardless of the transfer direction. if the receiv ed data is 8 bits, read the cenrx0l register only. reset sets this register to 0000h. but, be undefined in the consecutive mode. in addition to reset input, the cenrx0 register can be in itialized by clearing (to 0) the cenctl0.cenpwr bit. caution because the values of the cenflf, cenemp, ce ntsf, censfp3 to censfp0 bits may change at any time during transfer, their values during transfer may differ from the actual values. especially, use the centsf bit independently (do not use this bi t in relation with the other bits). to detect the end of transfer by the censtr register, check to see if the cenemf bit is 1 after the data to be transferred has been writ ten to the csibufn register. after reset: 0000h note r address: cenrx0 (n = 0, 1) ce0rx0 fffffb02h, ce0rx0l fffffb02h, ce0rx0h fffffb03h, ce1rx0 fffffb42h, ce1rx0l fffffb42h, ce1rx0h fffffb43h note in continuous mode (cen ctl0.centms = 1): undefined the following shows the cenrx0 register in reading by each transfer mode. transfer mode cenrx0 single mode (cenctl0.centms bit = 0) reading the data value in reception data buffer consecutive mode (cenctl0.centms bit = 0) reading the reception data value in the csibufn pointer for current read showing (the initial value of the csibufn register by reset is undefined). v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 847 of 1817 sep 19, 2011 (3) csien transmit data bu ffer register (centx0) the centx0 register is a 16-bit buffer register that stores transmit data. when transmit data is written to this register, the data is sequentially stored in the csibufn register while the csibufn pointer for writing is increment ed. writing to the centx register for the number of times exceeding the set value of the cenctl3.censfn3 to cenctl3.censfn0 bits (csien transfer data co unt) during the continuous transfer mode (cenctl0.centms bit = 1) is prohibited. when the data of this register is read, the value of the trans mit data written last is read. the centx0 register can be read or written in 16-bit units. when the higher 8 bits of the centx0 register are used as the centx0h r egister, and the lower 8 bits as the centx0l register, these registers can be read or written in 8-bit units. when reading in 8-bit units, be sure to read the centx0h register and centx0l regist er in that order. in addition, writ e the transmission data from the lower bits, regardless of the transfer direction. if the transmi ssion data is 8 bits, write the centx0l register only. reset sets this register to 0000h. caution accessing the centx0 register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock after reset 0000h r/w address: centx0 ce0tx0 fffffb06h, ce0tx0l fffffb06h, ce0tx0h fffffb07h, ce1tx0 fffffb46h, ce1tx0l fffffb46h, ce1tx0h fffffb47h the following shows the centx0 regist er operation in reading/writing. read/write operation of centx0 register write storing the transmission data in the csibufn register by step read reading the value of transmission data writing at last (4) csi data buffer register n (csibufn) by consecutively writing transmit data to the centx0 register from where it is transferred, up to sixteen 16-bit data can be stored in the csibufn register while the csib ufn pointer for writing is automatically incremented. in the continuous mode, the data received in the cs ibufn register can be sequentially read while the read csibufn pointer is automatically incremented, by continu ously reading the receive data from the cenrx0 register. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 848 of 1817 sep 19, 2011 18.4 control registers the following registers are used to control csien. ? csien control register 0 (cenctl0) ? csien control register 1 (cenctl1) ? csien control register 2 (cenctl2) ? csien control register 3 (cenctl3) ? csien status register (censtr) v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 849 of 1817 sep 19, 2011 (1) csien control register 0 (cenctl0) the cenctl0 register contro ls the operation of csien. these registers can be read or written in 8-bit or 1-bit units. writi ng the centms, cendir, and censit bits is enabled only when centxe bit = 0 and cenrxe bit = 0. reset sets this register to 00h. caution accessing the cenctl0 register is prohibited in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock (1/2) after reset: 00h r/w address: ce0ctl0 fffffb00h, ce1ctl0 fffffb40h cenpwr cenctl0 (n = 0, 1) centxe cenrxe centms censit censit 0 0 < > < > < > < > < > cenpwr disables csien oper ation/specifies inhibited 0 csien operation disables 1 csien operation enables ? the csien unit is reset when the cenpwr bit = 0, and csien is stopped. to operate csien, first set the cenpwr bit to 1. ? when rewriting the cenpwr bit from 0 to 1 or from 1 to 0, simultaneously rewriting the bits other than the cenctl0.cenpwr register is prohibited. when the cenpwr bit = 0, rewriting the bits other than the cenpwr bit of the cenctl0 register, and the centx0, centx0l, and censtr registers is prohibited. centxe enables or disables transmission 0 disables transmission operation. 1 enables transmission operation. ? the centxe bit is reset when the cenpwr bit is cleared to 0. ? when the cenpwr bit = 1, after the centxe bit has been cleared to 0, setting the centxe bit to 1 before 2 cycles of the operation clock (f xx ) elapse is disabled. the transmit operation is enabled after the centxe bit has been set to 1, and 2 cycles of the operation clock (f xx ) have elapsed. caution be sure to clear bits 0 and 1 to ?0?. if these bits are set to 1, the operation is not guaranteed. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 850 of 1817 sep 19, 2011 (2/2) cenrxe enables or disables reception 0 disables reception. 1 enables reception. ? the cenrxe bit is reset when the cenpwr bit is cleared to 0. ? when the cenpwr bit = 1, after the cenrxe bit has been cleared to 0, setting the cenrxe bit to 1 before 2 cycles of the operation clock (f xx ) elapse is disabled. the receive operation is enabled after the cenrxe bit has been set to 1 and 2 cycles of the operation clock (f xx ) have elapsed. centms specifies the transfer mode 0 single mode 1 continuous mode cendir specifies the transfer direction (msb/lsb) 0 msb first 1 lsb first ? specifies the transfer direction when data is written from the centx0 register to the csibufn register or read from the cenrx0 and csibufn registers. censit controls delay of the transmissi on completion interrupt signal (intcent) 0 no delay 1 delay mode (in the continuous mode (trmdn = 1), the next data transfer is delayed half a cycle because a delay of half a cycle is inserted when transfer of 1-bit data is complete.) ? the delay mode (censit bit = 1) is valid only in the master mode (when the cencks2 to cencks0 bits are other than 111). in the slave mode (when the cencks2 to cencks0 bits are 111), do not set the delay mode. even if the delay mode is set, intcent is not affected by the censit bit. ? if the censit bit is set to 1 in the continuous mode (trmdn bit = 1), the intcent interrupt is not output except when the last data set by the cenctl3.censfn3 to cenctl3.censfn0 bits is transferred, but a delay of half a clock (1/2 serial clock) can be inserted between each data transfer. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 851 of 1817 sep 19, 2011 (2) csien control register 1 (cenctl1) the cenctl1 register is an 8-bit register that cont rols the operation clock and operating mode of csien. these registers can be read or written in 8-bit or 1-bit un its. data can be written to the cenctl1 register only when the cenctl0.centxe bit = 0 and cenrxe bit = 0. reset sets this register to 07h. (1/2) cenmdl2 cenctl1 (n = 0, 1) cenmdl1 cenmdl0 cenckp cendap cencks2 cencks1 cencks0 after reset 07h r/w address: ce0ctl1 fffffb01h, ce1ctl1 fffffb41h cenmdl2 cenmdl1 cenmdl0 set value (n) specification the transfer clock (brgn output signal) 0 0 0 ? brgn stop mode (power save) 0 0 1 1 f xclk /2 0 1 0 2 f xclk /4 0 1 1 3 f xclk /6 1 0 0 4 f xclk /8 1 0 1 5 f xclk /10 1 1 0 6 f xclk /12 1 1 1 7 f xclk /14 ? in the slave mode (cencks2 to cencks0 bits = 111), clear the cenmdl2 to cenmdl0 bits to 000 (brgn stop mode). cenckp cendap specification the data transmission/reception timing for scken communication type 1 0 0 d7 d6 d5 d4 d3 d2 d1 d0 scken (i/o) sien capture soen (output) communication type 2 0 1 d7 d6 d5 d4 d3 d2 d1 d0 scken (i/o) sien capture soen (output) communication type 3 1 0 d7 d6 d5 d4 d3 d2 d1 d0 scken (i/o) sien capture soen (output) communication type 4 1 1 d7 d6 d5 d4 d3 d2 d1 d0 scken (i/o) sien capture soen (output) remark f xclk : basic clock selected by cencks2 to cencks0 bit v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 852 of 1817 sep 19, 2011 (2/2) cencks2 cencks1 cencks0 set value (n) base clock (f xclk ) mode 0 0 0 0 f xx /2 master mode 0 0 1 1 f xx /4 master mode 0 1 0 2 f xx /8 master mode 0 1 1 3 f xx /16 master mode 1 0 0 4 f xx /32 master mode 1 0 1 5 f xx /64 master mode 1 1 0 6 f xx /128 master mode 1 1 1 ? external clock (scken) slave mode ? if the cencks2 to cencks0 bits are cleared to 000, setting the cenmdl2 to cenmdl0 bit to 001 is prohibited. remark f xx : main clock frequency v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 853 of 1817 sep 19, 2011 (3) csien control register 2 (cenctl2) the cenctl2 register is used to sele ct the transfer data length of csien. these registers can be read or wr itten in 8-bit or 1-bit units. the cenctl2 register may be transferr ing data when the cenctl0.centxe bit or cenrxe bit is 1. be sure to clear the centxe and cenrxe bits to 0 befor e writing data to the cenctl2 register. reset sets this register to 00h. after reset: 00h r/w address: ce0ctl2 fffffb09h, ce1ctl2 fffffb49h 0 cenctl2 (n = 0, 1) 0 0 0 cendls3 cendls2 cendls1 cendls0 cendls3 cendls2 cendls1 cendls0 specification of transfer bit length 0 0 0 0 16 bits 1 0 0 0 8 bits 1 0 0 1 9 bits 1 0 1 0 10 bits 1 0 1 1 11 bits 1 1 0 0 12 bits 1 1 0 1 13 bits 1 1 1 0 14 bits 1 15 bits other than above setting prohibited ? if a transfer data length other than 16 bits is specified (cendls3 to cendls0 bits = 0000), an undefined value is read to the hi gher excess bits of the cenrx0 and csibufn registers (see 18.6 (3) data tran sfer direction specification function). caution be sure to clear bits 7 to 4 to ?0?. if they are set to 1, the operation is not guaranteed. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 854 of 1817 sep 19, 2011 (4) csien status register (cenctl3) the cenctl3 register is used to set the number of transfer data of csien in the continuous mode (cenctl0.centms bit = 1). rewriting of the cenctl3 register is prohibit ed during transfer in the continuous mode (censtr.centsf bit = 1). these registers can be read or wr itten in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: 0 cenctl3 (n = 0, 1) 0 0 0 censfn3 censfn2 censfn1 censfn0 ce0ctl3 fffffb0ch, ce1ctl3 fffffb4ch censfn3 censfn2 censfn1 censfn0 specification of number of transfer data 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 ? writing data exceeding the value set by the censfn3 to censfn0 bits (number of csien transfer data) to the csibufn register is prohibited. caution be sure to clear bits 7 to 4 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 855 of 1817 sep 19, 2011 (5) csien status register (censtr) these registers indicate the status of t he csibufn register or the transfer status. these registers can be read or written in 8-bit or 1-bit units (however, bi ts 6 to 0 can only be read. they do not change even if they are written). reset sets this register to 20h. in addition to reset input, the censtr register can be initialized by clearing (0) the cenctl0.cenpwr bit. cautions 1. accessing the censtr register is prohibit ed in the following statu ses. for details, refer to 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock 2. because the values of the cenflf, cenemp, centsf, censfp3 to censfp0 bits may change at any time during transfer, their values during transfer may differ from the actual values. especially, use the centsf bit independently ( do not use this bit in relation with the other bits). to detect the end of transfer by the ce nstr register, check to see if the cenemf bit is 1 after the data to be transferred has been written to the csibufn register. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 856 of 1817 sep 19, 2011 (1/2) after reset: 20h r/w address: ce0str fffffb08h, ce1str fffffb48h cenpct censtr (n = 0, 1) cenflf cenemf centsf censfp3 censfp2 censfp1 censfp0 < > < > < > < > cenpct specifies clearing of the csibufn pointer 0 no operation 1 clear all csibufn pointers to 0. ? this bit is always 0 when it is read. ? if 1 is written to the cenpct bit in the middle of transfer, transfer is aborted. because all the csibufn pointers are cleared to 0, the remaining data in the csibufn register is ignored. if 1 is written to the cenpct bit, be sure to read the censtr register to check to see if all the csibufn pointers have been correctly cleared to 0 (cenflf bit = 0, cenemf bit = 1, censfp3 to censfp0 bits = 0000). writing to the cenpct bit is prohibited before confirming that all csibufn pointers have been cleared to 0 without fail. cenflf this flag indicates the full status of the csibufn register 0 csibufn register has a vacancy. 1 csibufn register is full. ? this bit is cleared to 0 when the cenc tl0.cenpwr register is cleared to 0 or when the cenpct bit is set to 1. ? if transfer of 16 data is specified in the continuous mode (cenctl0.centms bit = 1) (cenctl0.centms bit = 0000), the cenflf bit is set to 1 in the same way as in the single mode (cenctl0.centms bit = 1) when 16 data are in the csibufn register. if even one of the data has been completely transferred, the cenflf bit is cleared to 0. however, this does not mean that the csibufn register has a vacancy. in this case, writing the next transmission data to the csibufn register is prohibited. even if the data is wri tten to the csibufn register, it is not transferred. if a data reception process is executed, the received data is overwritten. to execute the next transfer, be sure to wait until all transfers have completed, then write 1 to the cenpct bi t to clear (0) the all csibufn pointers. cenemf this flag indicates the empt y status of the csibufn register 0 data is in csibufn register. 1 csibufn register is empty. ? this flag is set to 1 when the cenctl0.cenpwr register is cleared to 0 or when the cenpct bit is set to 1. ? if the data written to the csibufn register has been transferred, the cenemf bit is set to 1 (even if receive data is stored in the csibufn register). v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 857 of 1817 sep 19, 2011 (2/2) centsf this flag indicates transfer status 0 idle status 1 transfer or transfer start processing in progress ? this flag is cleared to 0 when the cenct l0.cenpwr register is cleared to 0 and the cenpct bit is set to 1, or when the cenctl0.centxe bit = 0 and cenctl0.cenrxe bit = 0 register are cleared to 0. ? this flag is ?1? from when transfer is st arted until there is no more transfer data in the csibufn register in the single mode (cenctl0.centms bit = 0) or until the specified number of data has been transferred in the continuous mode (cenctl0.centms bit = 1). censfp3 to censfp0 ? in the single mode (cenctl0.centms bit = 0), the ?number of transfer data remaining in csibufn register (csibufn pointer value for writing ? csibufn pointer value for sion loading)? can be read. ? in the continuous mode (cenctl0.centms bit = 1), the ?number of data completely transferred (value of csibufn pointer for sion loading/storing)? can be read. if t he censfp3 to censfp0 bits are 0h, however, the number of transferr ed data is as follows, depending on the setting of the cenemf bit. when cenemf bit = 0: number of transferred data = 0 when cenemf bit = 1: number of transferred data = 16 or status before starting transfer (before writing transfer data) ? these bits are cleared to 0 in synchro nization with the oper ating clock when the cenpct bit = 1. however, the values of these bits are held until the cenctl0.cenpwr register is cleared to 0 or the cenpct bit is set to 1. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 858 of 1817 sep 19, 2011 18.5 baud rate generator n (brgn) the transfer clock of csien can be select ed from the output of a dedicated baud rate generator or external clock (n = 0, 1). the serial clock source is specified by the cenctl1 register. in the master mode (cenctl1.cencks2 to cenctl1.cencks0 bits = other than 1 11 in the csien register), brgn is selected as the clock source. (1) transfer clock figure 18-2. transfer clock of csien selector prescaler (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) brgn (1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14) transfer clock f xp sckn cenmdl1 cenmdl0 cencks2 cencks1 cencks0 cenmdl2 f xclk csien control register (cenctl1) remarks 1. n = 0, 1 2. f xx : main clock frequency f xclk : basic clock selected in cenctl1.cencks2 to cenctl1.cencks0 bits v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 859 of 1817 sep 19, 2011 (2) baud rate the baud rate is calculated by the following expression. baud rate = f xx n 2 k+1 [bps] caution if the cenctl1.cencks0 bits are clear ed to 000, setting the cenctl1.cenmdl2 to cenctl1.cenmdl0 bits to 001 is prohibited. remark f xx : main clock frequency k = set value of cenctl1.cencks2 to cenctl1.cencks0 bits (k = 0, 1, 2, ? , 6) n = set value of cenctl1.cenmdl2 to cenc tl1.cenmdl0 bits (n = 1, 2, 3, ? , 7) v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 860 of 1817 sep 19, 2011 18.6 operation (1) operation modes table 18-5. operation modes centms bit cencks2 to cencks0 bits ce ntxe, cenrxe bits cendir bit censit bit master mode enables/disables intcent delay mode single mode slave mode ? master mode enables/disables intcent delay mode consecutive mode slave mode transmission, reception, transmission/reception msb/lsb first ? remarks 1. centxe bit: bit 6 of cenctl0 register cenrxe bit: bit 5 of cenctl0 register centms bit: bit 4 of cenctl0 register cendir bit: bit 3 of cenctl0 register censit bit: bit 2 of cenctl0 register cencks2 to cencks0 bits: bits 2 to 0 of cenctl0 register 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 861 of 1817 sep 19, 2011 (2) function of csi data buffer registers 0, 1 (csibuf0, csibuf1) by consecutively writing the transmit data to the centx0 re gister from where it is tr ansferred, up to sixteen 16-bit data can be stored in the csibufn register while the csib ufn pointer for writing is aut omatically incremented (n = 0, 1). the condition under which transfer is to be started (censtr. cenemf bit = 0) is satisfied when data is written to the lower 8 bits (centx0l register) of t he centx0 register. if a transfer data le ngth of 9 bits or more is specified (cenctl2.cendls3 to cenctl2.cendls 0 bits = 0000 or 1001 to 1111), dat a must be written to the centx0 register in 16-bit units or to the centx0h and centx0l r egisters, in that order, in 8-bit units. if the transfer data length is set to 8 bits (cenctl2.cendls3 to cenct l2.cendls0 bits = 1000), data must be written to the centx0l register in 8-bit units or to t he centx0 register in 16-bit units. (if data is written to the centx0l register in 16-bit units, however, the higher 8 bits of the data (of the centx0h register) are ignored and not transferred). the censtr.cenflf register is set to 1 when 16 data exist in the csibufn register and outputs a csibufn overflow interrupt (intcentiof) when the cenflf bit = 1 and when the 17th transfer data is written (17th transfer data is not written and ignored). sixteen data exist in the csibufn regist er in the single mode (cenctl0.centms bit = 1) when ?csibufn pointer value for writing = csibufn pointer value for sion loading, and censtr.cenflf bit = 1?. when the csibufn pointer for sion loading is incremented after completion of transfer while cenflf bit = 1, the cenflf bit is cleared to 0 and the next transmission data can be written. in the continuous mode (cenctl0.ce ntms bit = 1), when one data has been transferred, the cenflf bit is cleared to 0, but writing the next transmission data is pr ohibited (if a receive operation is processed, the received data is stored in the csibufn r egister. therefore, if the transmission data is written to the register, the received data is overwritten and destroyed). v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 862 of 1817 sep 19, 2011 figure 18-3. function of csi da ta buffer register n (csibufn) csi data buffer register n (csibufn) 15 15 0 0 transfer data 0 transfer data 1 transfer data 2 transfer data 3 transfer data 4 censfp3 to censfp0 70 3 4 incremented sion load csibufn pointer incremented write csibufn pointer centx0h centx0l 15 8 7 0 csien transmission data buffer register (centx0) csien status register (censtr) remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 863 of 1817 sep 19, 2011 (3) data transfer direct ion specification function the data transfer direction can be changed by using the cenctl0.cendir bit (n = 0, 1). (a) msb first (cendir bit = 0) figure 18-4. transfer data length: 8 bits (cen ctl2.cendls3 to cenctl2.cendls0 bits = 1000), transfer direction: msb first (cenctl0.cendir bit = 0) (1/2) (i) transfer direction: msb first di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 scken (i/o) sien (input) soen (output) (ii) writing from centx0 register to csibufn register centx0 csibufn data 00h sion 15 8 7 0 soen sien remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 864 of 1817 sep 19, 2011 figure 18-4. transfer data length: 8 bits (cen ctl2.cendls3 to cenctl2.cendls0 bits = 1000), transfer direction: msb first (cenctl0.cendir bit = 0) (2/2) (iii) reading from cenrx0 register (in single mode (cenctl0.centms bit = 0)) cenrx0 (read value) undefined value data sion 15 8 7 0 soen sien (iv) reading from cenrx0 register (in continuous mode (cenctl0.centms bit = 1)) cenrx0 (read value) csibufn undefined value data sion 15 8 7 0 soen sien remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 865 of 1817 sep 19, 2011 (b) lsb first (cendir bit = 1) figure 18-5. transfer data length: 8 bits (cen ctl2.cendls3 to cenctl2.cendls0 bits = 1000), transfer direction: lsb first (cenctl0.cendir bit = 1) (1/2) (i) transfer direction: lsb first di0 di1 di2 di3 di4 di5 di6 di7 do0 do1 do2 do3 do4 do5 do6 do7 scken (i/o) sien (input) soen (output) (ii) writing from centx0 register to csibufn register centx0 csibufn data 00h sion 15 8 7 0 soen sien remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 866 of 1817 sep 19, 2011 figure 18-5. transfer data length: 8 bits (cen ctl2.cendls3 to cenctl2.cendls0 bits = 1000), transfer direction: lsb first (cenctl0.cendir bit = 1) (2/2) (iii) reading from cenrx0 register (in single mode (cenctl0.centms bit = 0)) cenrx0 (read value) 00h data sion 15 8 7 0 soen sien (iv) reading from cenrx0 register (in continuous mode (cenctl0.centms bit = 1)) cenrx0 (read value) csibufn 00h data sion 15 8 7 0 soen sien remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 867 of 1817 sep 19, 2011 (4) transfer data le ngth changing function the transfer data length can be set from 8 to 16 bits in 1-bit units, by using the cenctl2.cendls3 to cenctl2.cendls0 bits (n = 1, 0). figure 18-6. transfer data length: 16 bits (cen ctl2.cendls3 to cenctl2 .cendls0 bits = 0000), transfer direction: msb first (cenctl0.cendir bit = 0) di15 di14 di13 di12 di2 di1 di0 do15 do14 do13 do12 do2 do1 do0 scken (i/o) sien (input) soen (output) remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 868 of 1817 sep 19, 2011 (5) function to select serial clock and data phase the serial clock and data phase can be changed by using the cenctl1.cenckp, cenctl1.cendap bits (n = 0, 1). figure 18-7. clock timing (a) when cenckp bit = 0, cendap bit = 0 intcent interrupt sien capture scken son d7 d6 d5 d4 d3 d2 d1 d0 (b) when cenckp bit = 0, cendap bit = 1 intcent interrupt sien capture scken soen d7 d6 d5 d4 d3 d2 d1 d0 (c) when cenckp bit = 1, cendap bit = 0 intcent interrupt sien capture scken soen d7 d6 d5 d4 d3 d2 d1 d0 (d) when cenckp bit = 1, cendap bit = 1 intcent interrupt sien capture scken soen d7 d6 d5 d4 d3 d2 d1 d0 remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 869 of 1817 sep 19, 2011 (6) master mode the master mode is set and data is transferred with the serial clock output to the cenctl1.cencks2 to cenctl1.cencks0 bits are set to a value other than 111 (scken pin input is invalid) (n = 0, 1). the default output level of the scken pin is high when the cenctl1.cenckp bit is 0, and low when the cenckp bit is 1. figure 18-8. master mode (cenctl1.c enckp and cenctl1.cendap bits = 00, cenctl2.cendls3 to cenctl2.c endls0 bits = 1000 (transfe r data length: 8 bits)) di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 scken (output) sien (input) soen (output) remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 870 of 1817 sep 19, 2011 (7) slave mode the slave mode is set when the cenctl1.cencks2 to cenctl1.cencks0 bits are set to 111, and data is transferred with the serial clock input to the scken pin (in the slave mode, set the cenctl1.cenmdl2 to cenctl1.cenmdl0 bits to 000) (n = 0, 1). figure 18-9. slave mode (cenctl1.cen ckp and cenctl1.cendap bits = 00, cenctl2.cendls3 to cenctl2.c endls0 bits = 1000 (transfe r data length: 8 bits)) di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 scken (input) sien (input) soen (output) remark n = 0, 1 (8) transfer clock selection function in the master mode (cenctl1.cencks2 to cenctl1.cencks0 bits = other than 111 in the cenctl1 register), the bit transfer rate can be selected by setting t he cenctl1.cencks2 to cenctl1.cencks0, cenmdl2 to cenmdl0 bits (see 18.4 (2) csien control register 1 (cenctl1) ). v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 871 of 1817 sep 19, 2011 (9) single mode the single mode is set when the cenctl0.centms bit is 0 (n = 0, 1). in this mode, transfer is started when the centxe bit or cenrxe bit is set to 1 and when data is in the csibufn register (censtr.cenemf bit = 0). if no data is in the csibufn register (cenemf bit = 1), trans fer is kept waiting until transmit data or dummy data is written to the centx0 register. when data is written to the centx0 regi ster while transmission or reception is enabled (centxe or cenrxe bit is 1), the censtr.centsf bit (transfer status flag) is set to 1. if transfer is not in the wait status, the transfer data indicated by the sion load csibufn pointer is loaded fr om the censtr.centsf bit, and transfer processing is started. if the read operation (cenrx0 register read) of the previously received data has been completed before one data has been transferred in the reception mode or transmission /reception mode, the received data is stored from the sion register to the cenrx0 register, the transmission/r eception completion interrupt (intcent) is output, and the sion load csibufn pointer is incremented. if the read operation of the previously received data has not been completed, the wait status is set and storing the receive data in the ce nrx0 register, outputting the intcent interrupt, and incrementing the sion load csibufn pointer are held pending, until all previously received data is read output from the cenrx0 register. in the transmission mode, the intcent interrupt is outpu t and the sion load pointer is incremented when transfer processing of one data has been completed (the cenrx0 regi ster is always in the read complete status because no data is stored from the sion regi ster to the cenrx0 register). in all modes (transmission, reception, and transmission/recept ion modes), if the csibufn register is empty (write csibufn pointer value = sion load csibufn pointer va lue) when transfer processing of one data has been completed, the centsf bit is cleared to 0. the value of the ?number of remaining data in the csibufn register (write csibufn pointer ? sion load pointer)? can always be read from the censtr.censfp3 to censtr.censfp0 bits. caution be sure to confirm that the censtr.cenflf register is 0 when writing data to the centx0 register. even if data is written to this re gister when cenflf bit is 1, the csibufn overflow interrupt (intcentiof) is output, and the written data is ignored. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 872 of 1817 sep 19, 2011 figure 18-10. single mode sion cenrx0 soen sien csi data buffer register n (csibufn) 15 15 0 0 transfer data 0 transfer data 1 transfer data 2 transfer data 3 transfer data 4 censfp3 to censfp0 70 3 4 incremented sion load csibufn pointer incremented write csibufn pointer centx0h centx0l 15 8 7 0 difference csien transmission data buffer register (centx0) csien status register (censtr) remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 873 of 1817 sep 19, 2011 the transfer start conditions in single mode are shown belo w. csien starts data transfer when these conditions are satisfied. table 18-6. transfer start conditions in single mode transfer mode centxe bit cenrxe bit csibufn register cenrx0 register, sion register scken pin transmission mode 1 0 untransferred data is present (cenemf bit = 0) ? reception mode 0 1 untransferred dummy data is present (cenemf bit = 0) master mode transmission/ reception mode 1 1 untransferred data is present (cenemf bit = 0) received data has been transferred from sion register to cenrx0 register ? transmission mode 1 0 untransferred data is present (cenemf bit = 0) ? reception mode 0 1 untransferred dummy data is present (cenemf bit = 0) slave mode transmission/ reception mode 1 1 untransferred data is present (cenemf bit = 0) received data has been transferred from sion register to cenrx0 register input remarks 1. centxe bit: bit 6 of cenctl0 register cenrxe bit: bit 5 of cenctl0 register cenemf bit: bit 5 of censtr register 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 874 of 1817 sep 19, 2011 (10) continuous mode the continuous mode is set when the ce nctl0.centms bit is 1 (n = 0, 1). in this mode, transfer is started when the centxe bit or cenrxe bit is 1 and when data is in the csibufn register (censtr.cenemf register). at this time, se t the number of transfer data in advance by using the cenctl3.censfn3 to cenctl3.censfn0 bits. if data exc eeding the number of transfer data specified by the cenctl3.censfn3 to cenctl3.censfn0 bits are written to the csibufn register, the excess data are ignored and not transferred. if no data is in the csibufn register (cenemf bit = 1), tr ansfer is kept waiting until transmit data or dummy data is written to the centx0 register. if data is written to the centx0 register when transmissio n or reception is enabled (centxe or cenrxe bit is 1), the censtr.centsf bit (transfer status flag) is set to 1 and the transfer data indica ted by the sion load/store csibufn pointer is loaded from the csibufn register to sion register. then transfer processing is started. when transfer processing of one data is completed in th e reception mode or transmission/reception mode, the received data is overwritten from the sion register to t he transfer data in the csibufn register indicated by the sion load/store csibufn pointer, and then the pointer is incremented. by c onsecutively reading the transfer data from the cenrx0 register after all data in the cs ibufn register have been transferred (when the intcent interrupt has occurred), the receive data can be sequentia lly read while the read csibuf n pointer is incremented. if read operation is executed for the data number exceeding the received dat a count from the cenrx0 register, however, the read value is undefined. in the transmission mode, the sion load/store csibufn point er is incremented when transfer processing of one data has been completed. in all modes (transmission, reception, and transmission/ reception modes), when data has been transferred by the value set by the cenctl3.censfn3 to cenctl3.cens fn0 bits, the centsf bit is cleared to 0 and the transmission/reception completion in terrupt (intcent) is output. to transfer the next data, be sure to write 1 to the ce nstr.cenpct bit and clear all the csibufn pointers to 0. the ?number of transferred data (s ion load/store csibufn pointer va lue)? can always be read from the censtr.censfp3 to ce nstr.censfp0 bits. caution the censtr register is in the same status when transfer data is written (before start of transfer) after the csibufn pointer is cleared (censtr. cenpct bit = 1) and when 16 data have been transferred (censtr.censtr.cenflf bit = 0, censtr.cenemf bit = 1, censtr.censfp3 to censtr.censfp0 bits = 0000). v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 875 of 1817 sep 19, 2011 figure 18-11. continuous mode transfer data 0 cenrx0 soen sien csi data buffer register n (csibufn) 15 15 0 0 transfer data 1 transfer data 2 transfer data 3 censpf3 to censpf0 70 3 4 csien status register (censtr) incremented read csibufn pointer incremented sion load/store csibufn pointer incremented write csibufn pointer centx0h centx0l 15 8 7 0 sion note 1 note 2 note 1 csien transmission data buffer register (centx0) notes 1. reception 2. transmission remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 876 of 1817 sep 19, 2011 the transfer start conditions in continuous mode are show n below. csien starts data transfer when these conditions are satisfied. table 18-7. transfer start conditions in continuous mode transfer mode centxe bit cenrxe bit csibufn register cenrx0 register, sion register scken pin transmission mode 1 0 untransferred data is present (cenemf bit = 0) reception mode 0 1 untransferred dummy data is present (cenemf bit = 0) note master mode transmission/ reception mode 1 1 untransferred data is present (cenemf bit = 0) ? transmission mode 1 0 untransferred data is present (cenemf bit = 0) reception mode 0 1 untransferred dummy data is present (cenemf bit = 0) note slave mode transmission/ reception mode 1 1 untransferred data is present (cenemf bit = 0) ? input note the same amount of dummy data as t he data to be received is required. remarks 1. centxe bit: bit 6 of cenctl0 register cenrxe bit: bit 5 of cenctl0 register cenemf bit: bit 5 of censtr register 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 877 of 1817 sep 19, 2011 (11) transmission mode the transmission mode is set when the cenctl0.centxe bit is set to 1 and the cenrxe bit is cleared to 0. in this mode, transmission is started by a trigger that wr ites transmit data to the centx0 register or sets the centxe bit to 1 when transmit data is in the csibufn register (n = 0, 1). t he value input to the sien pin during transmission is latched in the shift register (sion) but is not transferred to the cenrx0 and csibufn registers at the end of transmission. the transmission/reception completion inte rrupt (intcent) occurs immediately after data is sent out from the sion register. (12) reception mode the reception mode is set when the ce nctl0.centxe bit is cleared to 0 and the cenctl0.cenrxe bit is set to 1. in this mode, reception is start ed by using the processing of writing du mmy data to the centx0 register as a trigger (n = 0, 1). in the single mode (cenctl0.centms bit = 1), however, the condition of starting reception includes that the receive data has been transferred from the sion register to t he cenrx0 register. (if reception to the sion register is completed when the previous receive data is held in the cenrx0 register without being read, the receive data stored in the sion register is transf erred to the cenrx0 register by reading the cenrx0 register.) in the continuous mode, re ception starts by writing dummy data of the number of receive data to the centx0 register with the first dummy dat a write processing taken as a trigger. the soen pin outputs a low level. the transmission/reception completion in terrupt (intcent) occurs immediately after receive data is transferred from the sion register to the cenrx0 register. (13) transmission/reception mode the transmission/reception mode is set when both the cenctl0.centxe bit = 1 and the cenctl0.cenrxe bit = 1. in this mode, transmission/reception is started by using the processing to writ e transmit data to the centx0 register as a trigger (n = 0, 1). in the single mode (c enctl0.centms bit = 0), howeve r, the condition of starting transmission/reception includes that t he receive data has been transferred from the sion register to the cenrx0 register. (if reception to the sion r egister is completed when the previously received data is held in the cenrx0 register without being read, the receive data stored in the sion register is transferred to the cenrx0 register by reading the cenrx0 register.) v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 878 of 1817 sep 19, 2011 (14) delay control of transmission/r eception completion interrupt (intcent) in the master mode (cenctl1.cencks2 to cenctl1.ce ncks0 bits = other than 111), occurrence of the transmission/reception completion interrupt (intcent) c an be delayed by half a clock (1/2 serial clock), depending on the setting (1) of the cenctl0.centms bit. the censit bit is valid only in the master mode. in the slave mode (cenctl1.cencks2 to cenctl1.cencks0 bits = 111), setting the censit bit to 1 is prohibited (even if set, the intcent interrupt is not affected). caution if the cenctl0.centms bit is set to 1 in the continuous mode (cen ctl0.centms bit = 1), the intcent interrupt is not output at the end of data other than the last data set by the cenctl3.censfn3 to cenctl3.censfn0 bits, but a delay of half a clock (1/2 serial clock) can be inserted between each data transfer. figure 18-12. delay control of transmissi on/reception completion interrupt (intcent): cenctl0.censit bit = 1, cenckp, cendap bits = 00, cenctl2.cendls3 to cenctl2 .cendls0 bits = 1000 (transfer data length: 8 bits) di7 di7 di6 di5 di4 di3 di2 di1 di0 delay do7 do6 do5 do4 do3 do2 do1 do0 do7 scken (output) sien (input) soen (output) intcent interrupt delay note note if the cenctl0.centms bit is set to 1 in the continuous mode (cenctl0. centms bits = 1), the intcent interrupt is not output at the end of data other than the la st data set by the cenctl3.censfn3 to cenctl3.censfn0 bits, but a de lay of half a clock (1/2 serial clock) can be inserted between each data transfer. remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 879 of 1817 sep 19, 2011 (15) output pins (a) scken pin the scken pin output status when the csien does not perform transmission/reception. table 18-8. scken pin output level in non-communication state cenpwr bit cenpct bit cenckp bit centxe, cenrxe bi ts cencks2 to cencks0 bits scken pin output level 111 (slave mode) high im pedance 0 ? ? ? other than 111 (master mode) high level 111 (slave mode) high im pedance 0 other than 111 (master mode) high level 111 (slave mode) high im pedance 0 1 after setting 1 ? other than 111 (master mode) low level 111 (slave mode) high im pedance changes to 00b note 1 other than 111 (master mode) high level 111 (slave mode) high im pedance 0 other than above other than 111 (master mode) note 3 111 (slave mode) high im pedance changes from 00b note 2 other than 111 (master mode) low level 111 (slave mode) high im pedance 1 ? 1 other than above other than 111 (master mode) note 3 notes 1. when the values set to the centxe and cenrxe bits change from 01 to 00, 10 to 00, or 11 to 00. 2. when the values set to the centxe and cenrxe bits change from 00 to 01, 00 to 10, or 00 to 11. 3. the previous scken pin output level is retai ned (the scken pin output level does not change). remark n = 0, 1 caution if the cenckp bit is set to 1 in the master mode (cencks2 to cencks0 bits are other than 111), the scken pin outputs a low level when it is inactive. if the cenctl0.centxe bit is cleared to 0 (disabling transmission) and cenrxe bit is clear ed to 0 (disabling reception), the scken pin outputs a high level. therefore, take the following measures to fix the scken pin to low level when csien is not used. [scke0 pin (scke1 pin)] <1> clearing the p6.p62 bit to 0 (clearing the p6.p65 bit to 0): the port output level is set to low. <2> clearing the pm6.pm62 bit to 0 (cl earing the pm6.pm65 bit register to 0): the port is set in the output mode. <3> clearing the pmc6.pmc62 to 0 (clearing the pmc6.pmc65 bit to 0): the pin is set in the port mode (fixed to low-level output). <4> clearing the ce0ctl0.ce0t xe and ce0ctl0.ce0rxe bits to 0 (clearing the ce1ctl0.ce1txe and ce1ctl0.ce1rx e bits to 0): transmission and reception are disabled. <5> setting the ce0str.ce0pct bit to 1 (setting the ce1str.ce1pct bit to 1): clearing all pointers for csibuf0 (csibuf1). v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 880 of 1817 sep 19, 2011 <6> setting the ce0ctl0.ce0t xe or ce0ctl0.ce0rxe bit to 1 (setting the ce1ctl0.ce1txe or ce1ctl0.ce1rxe bit to 1): transmission or reception is enabled (both transmission/reception can also be enabled). <7> setting the pmc6.pmc62 bit to 1 (setting the pmc6.pmc65 bit to 1): the pin is set as the alternate function (scke0 and scke1 pin outputs). because the register set values <1> and <2> are retained, control can be performed only by <3> to <7> once they have been set. (b) soen pin the soen pin output status when the csien does not perform transmission/reception. table 18-9. soen pin output level in non-communication state cenpwr bit cenpct bit cendap bit centxe bit cencks2 to cencks0 bits soen pin output level 0 ? ? ? ? low level 111 (slave mode) note 0 other than 111 (master mode) low level 0 1 after setting 1 ? ? low level 1 0 low level 1 ? ? 0 1 ? note note the previous soen pin output level is retained (the soen pin output level does not change). remark n = 0, 1 (16) csibufn overflow interrupt signal (intcentiof) in the single mode and continuous mode, the intcentiof in terrupt is output when 16 untransmitted data exist in the csibufn register and wh en the 17th data is written (to the centx0 or centx0l register) (the 17th transfer data is not written but ignored). in the single mode (cenctl0.centms bit = 0), 16 untransm itted data exist in the csib ufn register when ?write csibufn pointer value = sion load csibufn pointer va lue and censtr.cenflf bit = 1?. when transfer is completed and the sion load csibufn pointer is incremen ted, the csibufn register can write one transmission data. writing the next transmission data to the csibufn register is not availa ble even when transfer of one data has been completed in the continuous mode (cenctl0.centms bit = 1). v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 881 of 1817 sep 19, 2011 18.7 how to use (1) single mode (in master mode and transmission mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenctl0. centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable transmission by setting the centxe bit to 1. <6> confirm that the censtr.cenflf register is 0, and then write transfer data to the centx0 register. if it is clearly known that the cenflf bit is 0 because transfer data is written to that bit by the interrupt servicing routine of intcent, it is not always necessa ry to confirm that the cenflf bit is 0. <7> confirm that the intcent interrupt has occu rred and the censtr.cenemf bit is 1, and disable transmission by clearing the cenctl0.ce ntxe bit to 0 (end of transmission). caution to execute further transfer, repeat <6> before <7>. (2) single mode (in master mode and reception mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenctl0. centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable reception by setting the cenrxe bit to 1. <6> confirm that the censtr.cenflf register is 0, and then write dummy transfer data to the centx0 register (reception start trigger). if it is clearly known that the cenflf bit is 0 because dummy transfer data is written to that bit by the interrupt servic ing routine of intcent, it is not always necessary to confirm that the cenflf bit is 0. <7> confirm that the intcent interrupt has oc curred, and then read the cenrx0 register. <8> confirm that the intcent interrupt has occurred and the cenemf bit is 1, and di sable reception by clearing the cenctl0.cenrxe bit to 0 (end of reception). cautions 1. to execute further tr ansfer, repeat <6> and <7> before <8>. 2. the soen pin outputs a low level but this is invalid. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 882 of 1817 sep 19, 2011 (3) single mode (in master mode and transmission/reception mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenctl0. centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable transmission/recept ion by setting the centxe and cenrxe bits to 1. <6> confirm that the censtr.cenflf register is 0, and then write transfer data to the centx0 register. if it is clearly known that the cenflf bit is 0 because transfer data is written to that bit by the interrupt servicing routine of intcent, it is not always necessa ry to confirm that the cenflf bit is 0. <7> confirm that the intcent interrupt has oc curred, and then read the cenrx0 register. <8> confirm that the intcent interrupt has occurred and the cenemf bit is 1, and disable transmission/reception by clearing t he cenctl0.centxe bit = 0 and cenct l0.cenrxe bit = 0 register to 0 (end of transmission/reception). caution to execute further transfer , repeat <6> and <7> before <8>. (4) single mode (in slave m ode and transmission mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenctl0. centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable transmission by setting the centxe bit to 1. <6> confirm that the censtr.cenflf register is 0, and then write transfer data to the centx0 register. if it is clearly known that the cenflf bit is 0 because transfer data is written to that bit by the interrupt servicing routine of intcent, it is not always necessa ry to confirm that the cenflf bit is 0. <7> confirm that the intcent interrupt has occurred and the cenemf bit is 1, and disable transmission by clearing the cenctl0.centxe bi t to 0 (end of transmission). caution to execute further transfer, repeat <6> before <7>. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 883 of 1817 sep 19, 2011 (5) single mode (in slave mode and reception mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenctl0. centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable reception by setting the cenrxe bit to 1. <6> confirm that the censtr.cenflf register is 0, and then write dummy transfer data to the centx0 register (reception start trigger). if it is clearly known that the cenflf bit is 0 because dummy transfer data is written to that bit by the interrupt servic ing routine of intcent, it is not always necessary to confirm that the cenflf bit is 0. <7> confirm that the intcent interrupt has oc curred, and then read the cenrx0 register. <8> confirm that the intcent interrupt has occurred and the cenemf bit is 1, and di sable reception by clearing the cenctl0.cenrxe bit to 0 (end of reception). cautions 1. to execute further tr ansfer, repeat <6> and <7> before <8>. 2. the soen pin outputs a low level but this is invalid. (6) single mode (in slave mode and transmission/reception mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenctl0. centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable transmission/recept ion by setting the centxe and cenrxe bits to 1. <6> confirm that the censtr.cenflf register is 0, and then write transfer data to the centx0 register. if it is clearly known that the cenflf bit is 0 because transfer data is written to that bit by the interrupt servicing routine of intcent, it is not always necessa ry to confirm that the cenflf bit is 0. <7> confirm that the intcent interrupt has oc curred, and then read the cenrx0 register. <8> confirm that the intcent interrupt has occurred and the cenemf bit is 1, and disable transmission/reception by clearing t he cenctl0.centxe bit = 0 and cenct l0.cenrxe bit = 0 register to 0 (end of transmission/reception). caution to execute further transfer , repeat <6> and <7> before <8>. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 884 of 1817 sep 19, 2011 (7) continuous mode (in master mode and transmission mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenctl0. centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable transmission by setting the centxe bit to 1. <6> set the amount of data to be transmitted by us ing the cenctl3.censfn3 to cenctl3.censfn0 bits. <7> write the amount of data to be transmitted to the centx0 register as transfer data. writing data exceeding the set value of the cenct l3 register is prohibited. <8> confirm that the intcent interrupt has occurred and the cenemf bit is 1. then write 1 to the censtr.cenpct bit, and clear all the csibufn pointer s to 0 in preparation for the next transfer. <9> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <10> disable transmission by clearing the cenc tl0.centxe bit to 0 (end of transmission). caution to execute further transfer , repeat <6> to <9> before <10>. (8) continuous mode (in mast er mode and reception mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, censtr .cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenctl0. centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable reception by setting the cenrxe bit to 1. <6> set the amount of data to be received by us ing the cenctl3.censfn3 to cenctl3.censfn0 bits. <7> write dummy transfer data of the number of receive data to the centx0 register . the first dummy transfer data write is the trigger to start reception. writing dummy data exce eding the set value of the cenctl3 register is prohibited. <8> confirm that the intcent interrupt has occurred and t he cenemf bit is 1. then read the receive data from the cenrx0 register (sequentially read the re ceive data stored in the csibufn register). <9> write 1 to the censtr.cenpct bit, and clear all t he csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <11> disable reception by clearing the ce nctl0.cenrxe bit to 0 (end of reception). cautions 1. to execute further tran sfer, repeat <6> to <10> before <11>. 2. the soen pin outputs a low level. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 885 of 1817 sep 19, 2011 (9) continuous mode (in master m ode and transmission/reception mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenct l0.centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable transmission/recepti on by setting both the centxe and cenrxe bits to 1. <6> set the amount of data to be transmitted/receiv ed by using the cenctl3.censfn3 to cenctl3.censfn0 bits. <7> write the amount of data to be tr ansmitted to the centx0 register as transfer data. writing data exceeding the set value of the cenct l3 register is prohibited. <8> confirm that the intcent interrupt has occurred and the cenemf bit is 1. then read the receive data from the cenrx0 register (sequentially read the re ceive data stored in the csibufn register). <9> write 1 to the censtr.cenpct bit, and clear all t he csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <11> disable transmission/reception by clearing t he cenctl0.centxe bit = 0 and cenctl0.cenrxe bit = 0 register to 0 (end of transmission/reception). caution to execute further transfer, repeat <6> to <10> before <11>. (10) continuous mode (in sla ve mode and transmission mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenct l0.centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable transmission by setting the centxe bit to 1. <6> set the amount of data to be transmitted by us ing the cenctl3.censfn3 to cenctl3.censfn0 bits. <7> write the amount of data to be tr ansmitted to the centx0 register as transfer data. writing data exceeding the set value of the cenct l3 register is prohibited. <8> confirm that the intcent interrupt has occurred and the cenemf bit is 1. then write 1 to the censtr.cenpct bit, and clear all the csibufn pointer s to 0 in preparation for the next transfer. <9> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <10> disable transmission by clearing the cenc tl0.centxe bit to 0 (end of transmission). caution to execute further transfer , repeat <6> to <9> before <10>. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 886 of 1817 sep 19, 2011 (11) continuous mode (in sl ave mode and reception mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenct l0.centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable reception by setting the cenrxe bit to 1. <6> set the amount of data to be received by us ing the cenctl3.censfn3 to cenctl3.censfn0 bits. <7> write dummy transfer data of the number of receiv e data to the centx0 register . the first dummy transfer data write is the trigger to start reception. writing dummy data exce eding the set value of the cenctl3 register is prohibited. <8> confirm that the intcent interrupt has occurred an d the cenemf bit is 1. then read the receive data from the cenrx0 register (sequentially read t he receive data stored in the csibufn register). <9> write 1 to the censtr.cenpct bit, and clear all the csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <11> disable reception by clearing the ce nctl0.cenrxe bit to 0 (end of reception). cautions 1. to execute further tran sfer, repeat <6> to <10> before <11>. 2. the soen pin outputs a low level. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 887 of 1817 sep 19, 2011 (12) continuous mode (in slave m ode and transmissi on/reception mode) <1> when the cenctl0.cenpwr register is set to 1, supplying the operating clock is enabled. <2> specify the transfer mode by setti ng the cenctl1 and cenctl2 registers. <3> write 1 to the censtr.cenpct bit to clear all the csibufn pointers to 0. <4> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <5> specify the transfer mode by using the cenct l0.centms, cenctl0.cendir, and cenctl0.censit bits and, at the same time, enable transmission/recepti on by setting both the centxe and cenrxe bits to 1. <6> set the number of data to be transmitt ed/received by using the cenctl3.censfn3 to cenctl3.censfn0 bits. <7> write the amount of data to be tr ansmitted to the centx0 register as transfer data. writing data exceeding the set value of the cenct l3 register is prohibited. <8> confirm that the intcent interrupt has occurred an d the cenemf bit is 1. then read the receive data from the cenrx0 register (sequentially read t he receive data stored in the csibufn register). <9> write 1 to the censtr.cenpct bit, and clear all the csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the censtr.cenflf bit = 0, cens tr.cenemf bit = 1, and censtr.censfp3 to censfp0 bits = 0000. <11> disable transmission/reception by clearing t he cenctl0.centxe bit = 0 and cenctl0.cenrxe bit = 0 register to 0 (end of transmission/reception). caution to execute further transfer, repeat <6> to <10> before <11>. v850es/jh3-e, v850es/jj3-e chapter 18 clocked serial inte rface e with fifo (csie) r01uh0290ej0300 rev.3.00 page 888 of 1817 sep 19, 2011 18.8 cautions cautions concerning csien are shown below (n = 0, 1). (1) stopping csien the csien unit is reset and csien is stopped when the cenc tl0.cenpwr bit is cleared to 0. to operate csien, first set the cenpwr bit to 1. usually, before clearing the cenpwr bit to 0, clear both the centxe and cenrxe bits to 0 (after the end of transfer). (2) enabling transfer be sure to write 1 to the censtr.cenpct bit to clear a ll the csibufn pointers to 0 before enabling transfer by setting the cenctl0.cenpwr bits to 1. if the centxe or cenrxe bit is set to 1 without clearing the pointers, and if the previously transferred data remains in the csibufn register, transferring that data is immediately started. if transfer data is set to the csibufn register before transf er is enabled, transfer is started as soon as the centxe or cenrxe bit is set to 1. (3) caution on cenctl0 register setting be sure to set the port pins related to the csien function to the alternate-function mode before using csien. then set the cenpwr bit to 1 before setting the other bits. (4) writing data to centx0 register in single mode be sure to confirm that the censtr.cenflf register is 0 w hen writing data to the centx0 register. even if data is written to this register when the cenf lf bit is 1, the csibufn overflow in terrupt (intcentiof) is issued, and the written data is ignored. (5) censtr register stat us in continuous mode the censtr register is in the same st atus when transfer data is written (bef ore start of transfer) after the csibufn pointer is cleared (censtr.cenpct bit = 1) and when 16 data have been transferred (censtr.cenflf bit = 0, censtr.cenemf bit = 1, censtr.censf p3 to censtr.censfp0 bits = 0000). v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 889 of 1817 sep 19, 2011 chapter 19 clocked serial interface f (csif) 19.1 features { transfer rate: 8 mbps max. (f xx = 50 mhz, using internal clock) (csif0, csif4, csif5) 5 mbps max. (f xx = 50 mhz, using internal clock) (csif1 to csif3, csif6) { master mode and slave mode selectable { 8-bit to 16-bit transfer, 3-wire serial interface { interrupt request signals (intcfnt, intcfnr) { serial clock and data phase switchable { transfer data length selectable in 1-bit units between 8 and 16 bits { transfer data msb-first/lsb-first switchable { 3-wire transfer sofn: serial data output sifn: serial data input sckfn: serial clock i/o { transmission mode, reception mode, and transmission/reception mode specifiable remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 890 of 1817 sep 19, 2011 19.2 configuration the following shows the block diagram of csifn. figure 19-1. block diagram of csifn internal bus cfnctl2 cfnctl0 cfnstr controller intcfnr f cclk sofn intcfnt cfntx so latch phase control shift register cfnrx cfnctl1 phase control sifn f brgm f xx /4 f xx /6 f xx /8 f xx /12 f xx /16 f xx /32 sckfn selector remark f cclk : communication clock f xx : main clock frequency f brgm : count clock of the baud rate generator n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) m = 1 (n = 0, 1) m = 2 (n = 2, 3) m = 3 (n = 4) m = 4 (n = 5, 6) csifn includes the following hardware. table 19-1. configuration of csifn item configuration registers csifn receive data register (cfnrx) csifn transmit data register (cfntx) csifn control register 0 (cfnctl0) csifn control register 1 (cfnctl1) csifn control register 2 (cfnctl2) csifn status register (cfnstr) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 891 of 1817 sep 19, 2011 19.3 mode switching between csif and other serial interfaces 19.3.1 switching between csif0, uartc3, and i 2 c01 mode in the v850es/jh3-e and v850es/jj3-e, csif0, uartc3, and i 2 c01 share the same pin, so these functions cannot be used simultaneously. set csif0 in advance, using the pmc4, pfc4, and pfce4 registers. caution the transmit/receive operation of csif0, uartc3, and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 19-2. csif0, uartc3, and i 2 c01 mode switch settings port i/o mode sif1 (csif0) txdc3 (uartc3) sda01 (i 2 c01) pmc40 0 1 1 1 operation mode pfce40 0 0 1 pfc40 0 1 0 port i/o mode sof0 (csif0) rxdc3 (uartc3) scl01 (i 2 c01) pmc41 0 1 1 1 operation mode pfce41 0 0 1 pfc41 0 1 0 port i/o mode sckf0 (csif0) pmc42 0 1 operation mode pfce42 0 pfc42 0 pmc4 (pmc4h) (pmc4l) (pfc4l) pmc47 note pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0 note 0 note 0 note 0 note 0 note 0 note 0 note pmc48 note 8 9 10 11 12 13 14 15 pfc4 (pfc4h) pfc4 fffff468h, pfc4l fffff468h, pfc4h fffff469h after reset: 0000h r/w address: 0 note 0 note 0 note 0 note 0 note 0 note 0 note pfc48 note pfc47 note pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pmc4 fffff448h, pmc4l fffff448h, pmc4h fffff449h pfce47 note pfce46 note pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 pfce4 after reset: 00h r/w address: fffff708h note v850es/jj3-e only remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 892 of 1817 sep 19, 2011 19.3.2 mode switching between csif1, uartc1, and i 2 c00 in the v850es/jh3-e and v850es/jj3-e, csif1, uartc1, and i 2 c00 share the same pin and therefore cannot be used simultaneously. set uartc1 and i 2 c00 in advance, using the pmc2, pfc2 and pfce2 registers, before use. caution the transmit/receive operation of csif1, uartc1, and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 19-3. csif1, uartc1 and i 2 c00 mode switch settings pmc2 after reset: 00h r/w address: fffff444h pmc27 note pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 pmc20 pfc2 after reset: 00h r/w address: fffff464h pfc27 note pfc26 pfc25 pfc24 pfc23 pfc22 pfc21 pfc20 pfce27 note pfce26 pfce25 pfce24 pfce23 pfce22 pfce21 pfce20 pfce2 after reset: 00h r/w address: fffff704h port i/o mode sof1 (csif1) rxdc1 (uartc1) scl00 (i 2 c00) pmc24 0 1 1 1 operation mode pfce24 0 0 1 pfc24 0 1 0 port i/o mode sckf1 (csif1) pmc25 0 1 operation mode pfce25 0 pfc25 0 port i/o mode sif1 (csif1) txdc1 (uartc1) sda00 (i 2 c00) pmc23 0 1 1 1 operation mode pfce23 0 0 1 pfc23 0 1 0 note v850es/jj3-e only remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 893 of 1817 sep 19, 2011 19.3.3 mode switching between csif2 and uartc0 in the v850es/jh3-e and v850es/jj3-e, csif2 and uartc0 share the same pin and therefore cannot be used simultaneously. set csif2 and uartc0 in advance, usi ng the pmc3, pfc3, and pfce3 registers, before use. caution the transmit/receive operation of csif2 a nd uartc0 is not guaranteed if these functions are switched during transmission or reception. be su re to disable the one that is not used. figure 19-4. csif2 and uartc0 mode switch settings pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 pfce37 pfce36 pfce35 pfce34 pfce33 pfce32 pfce31 pfce30 pfce3 after reset: 00h r/w address: fffff706h port i/o mode asckc0 (uartc0) sckf2 (csif2) pmc32 0 1 1 operation mode pfce32 0 0 pfc32 0 1 port i/o mode rxdc0 (uartc0) sof2 (csif2) pmc31 0 1 1 operation mode pfce31 0 0 pfc31 0 1 port i/o mode txdc0 (uartc0) sif2 (csif2) pmc30 0 1 1 operation mode pfce30 0 0 pfc30 0 1 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 894 of 1817 sep 19, 2011 19.3.4 mode switching between csif3 and uartb1 in the v850es/jh3-e and v850es/jj3-e, csif3 and uartb1 share the same pin and therefore cannot be used simultaneously. set csif3 and uartb1 in advance, usi ng the pmc9, pfc9, and pfce9 registers, before use. caution the transmit/receive operation of csif3 a nd uartb1 is not guaranteed if these functions are switched during transmission or reception. be su re to disable the one that is not used. figure 19-5. csif3 and uartb1 mode switch settings pmc9 (pmc9h) (pmc9l) (pfc9l) (pfce9l) after reset: 0000h r/w address: pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h) after reset: 0000h r/w address: pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 pfce913 0 pfce911 pfce910 pfce99 pfce98 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 (pfce9h) after reset: 0000h r/w address: port i/o mode sof3 (csif3) rxdb1 (uartb1) pmc914 0 1 1 operation mode pfce914 0 0 pfc914 0 1 port i/o mode sif3 (csif3) txdb1 (uartb1) pmc913 0 1 1 operation mode pfce913 0 0 pfc913 0 1 port i/o mode sckf3 (csif3) pmc915 0 1 operation mode pfce915 0 pfc915 0 pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 895 of 1817 sep 19, 2011 19.3.5 using csif4 and uartb0 at the same time in the v850es/jh3-e and v850es/jj3-e, rxdb0 and txdb0 fo r uartb0 are assigned to two pins as shown in table 19-2 . when using csif4, use pins 32 (32) and 31 (31) or 109 (115) and 108 (114) as a set. do not use pins 32 (32) and 108 (114) or 109 (115) and 31 (31) simultaneously. table 19-2. pin assignment in uartb0 function pin number function v850es/jh3-e v850es/jj3-e alternate function 32 32 p34/sof4/tiaa20/toaa20 rxdb0 109 115 pdh4/a20/sof4 31 31 p33/sif4/tiaa11/toaa11 txdb0 108 114 pdh3/a19/sif4 in the v850es/jh3-e and v850es/jj3-e, uartb0 and csif4 s hare the same pin in the port 3 and they cannot be used at the same time. however, if either of these functi ons is used via the port dh, the other function can be used via the port 3. to switch between uart b0 and csif4, the pmc3, pfc3, and pf ce3 registers or the pmdh, pmcdh, and pmfedh registers must be set in advance. figure 19-6 show s an example of port settings when using uartb0 via port 3 and csif4 via the port dh. caution the transmit/receive operation of uartb0 or cs if4 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 896 of 1817 sep 19, 2011 figure 19-6. csif4 and uartb0 mode switch settings (1) setting of csif4 (2) setting of uartb0 pmcdh pmcdh7 pmcdh6 pmcdh5 pmcdh4 pmcdh3 11 pmcdh2 pmcdh1 pmcdh0 sckf4 sof4 sif4 sckf4 sckf4 sof4 sif4 sof4 sif4 pfcdh pfcdh5 pfcdh4 pfcdh3 00 pfcdh2 pfcdh1 pfcdh0 pfcedh pfcedh4 pfcedh3 11 pfce3 pfce37 pfce36 pfce35 pfce34 pfce33 00 pfce32 pfce31 pfce30 pfc3 pfc37 pfc36 pfc35 pfc34 pfc33 0 0 0 0 pfc32 pfc31 pfc30 pmc3 pmc37 pmc36 pmc35 1 pmc34 pmc33 11 pmc32 pmc31 pmc30 rxdb0 txdb0 rxdb0 txdb0 rxdb0 txdb0 v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 897 of 1817 sep 19, 2011 19.3.6 mode switching between csif5 and uartc6 in the v850es/jj3-e, csif5 and uartc6 share the same pin and therefore cannot be used simultaneously. set csif5 and uartc6 in advance, using the pmc4 , pfc4, and pfce4 registers, before use. caution the transmit/receive operation of csif5 a nd uartc6 is not guaranteed if these functions are switched during transmission or reception. be su re to disable the one that is not used. figure 19-7. uartc6 and csif5 mode switch settings port i/o mode sof5 (csif5) rxdc6 (uartc6) pmc47 0 1 1 operation mode pfce47 0 0 pfc47 0 1 port i/o mode sckf5 (csif5) pmc48 0 1 operation mode pfc48 0 pmc4 (pmc4h) (pmc4l) (pfc4l) pmc47 pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0000000 pmc48 8 9 10 11 12 13 14 15 pfc4 (pfc4h) pfc4 fffff468h, pfc4l fffff468h, pfc4h fffff469h after reset: 0000h r/w address: 0000000 pfc48 pfc47 pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pmc4 fffff448h, pmc4l fffff448h, pmc4h fffff449h pfce47 pfce46 pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 pfce4 after reset: 00h r/w address: fffff708h port i/o mode sif5 (csif5) txdc6 (uartc6) pmc46 0 1 1 operation mode pfce46 0 0 pfc46 0 1 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 898 of 1817 sep 19, 2011 19.3.7 mode switching between csif6 and uartc7 in the v850es/jj3-e, csif6 and uartc7 share the same pin and therefore cannot be used simultaneously. set csif6 and uartc7 in advance, using the pm c5 and pfc5 registers, before use. caution the transmit/receive operation of csif6 a nd uartc7 is not guaranteed if these functions are switched during transmission or reception. be su re to disable the one that is not used. figure 19-8. uartc7 and csif6 mode switch settings pmc5 (pmc5h) (pmc5l) pmc57 pmc56 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 000000 pmc59 pmc58 8 9 10 11 12 13 14 15 pfc5 (pfc5h) pfc5 fffff46ah, pfc5l fffff46ah, pfc5h fffff46bh after reset: 0000h r/w address: 000000 pfc59 pfc58 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pmc5 fffff44ah, pmc5l fffff44ah, pmc5h fffff44bh (pfc5l) pfc57 pfc56 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 port i/o mode sof6 (csif6) rxdc7 (uartc7) pmc58 0 1 1 operation mode pfc58 0 1 port i/o mode sckf6 (csif6) pmc59 0 1 operation mode pfc59 0 port i/o mode sif6 (csif6) txdc7 (uartc7) pmc57 0 1 1 operation mode pfc57 0 1 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 899 of 1817 sep 19, 2011 19.4 registers the following registers are used to control csifn. ? csifn receive register (cfnrx) ? csifn transmit register (cfntx) ? csifn control register 0 (cfnctl0) ? csifn control register 1 (cfnctl1) ? csifn control register 2 (cfnctl2) ? csifn status register (cfnstr) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 900 of 1817 sep 19, 2011 (1) csifn receive data register (cfnrx) the cfnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. the receive operation is started by reading the cfnrx register in the reception enabled status. if the transfer data length is 8 bits, the lower 8 bits of th is register are read-only in 8-bit units as the cfnrxl register. reset sets this register to 0000h. in addition to reset input, the cfnrx register can be initia lized by clearing (to 0) the cfnpwr bit of the cfnctl0 register. after reset: 0000h r address: cfnrx cf0rx fffffd04h, cf1rx fffffd14h, cf2rx fffffd24h, cf3rx fffffd34h, cf4rx fffffd44h, cf5rx fffffd54h, cf6rx fffffd64h remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) (2) csifn transmit data register (cfntx) the cfntx register is a 16-bit buffer regist er used to write the csifn transfer data. this register can be read or written in 16-bit units. the transmit operation is started by writing data to t he cfntx register in the transmission enabled status. if the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit uni ts as the cfntxl register. reset sets this register to 0000h. after reset 0000h r/w address: cfntx cf0tx fffffd06h, cf1tx fffffd16h, cf2tx fffffd26h, cf3tx fffffd36h, cf4tx fffffd46h, cf5tx fffffd56h, cf6tx fffffd66h remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) remark the communication start conditions are shown below. transmission mode (cfntxe bit = 1, cfnrxe bit = 0): write to cfntx register transmission/reception mode (cfntxe bit = 1, cf nrxe bit = 1): write to cfntx register reception mode (cfntxe bit = 0, cfnrxe bit = 1): read from cfnrx register (3) csifn control register 0 (cfnctl0) cfnctl0 is a register that controls the csifn serial transfer operation. v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 901 of 1817 sep 19, 2011 this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. (1/3) cfnpwr disables csifn operation and resets the cfnstr register enables csifn operation cfnpwr 0 1 specification of csifn operation disable/enable cfnctl0 cfntxe note cfnrxe note cfndir note 00 cfntms note cfnsce after reset: 01h r/w address: ? the cfnpwr bit controls the csifn operation and resets the internal circuit. disables transmit operation enables transmit operation cfntxe note 0 1 specification of transmit operation disable/enable ? the sofn output is low level when the cfntxe bit is 0. ? no reception completion interrupt is output even when the prescribed data is transferred, and the receive data (cfnrx register) is not updated, because the receive operation is disabled by clearing the cfnrxe bit to 0. disables receive operation enables receive operation cfnrxe note 0 1 specification of receive operation disable/enable < > < > < > < > < > cf0ctl0 fffffd00h, cf1ctl0 fffffd10h, cf2ctl0 fffffd20h, cf3ctl0 fffffd30h, cf4ctl0 fffffd40h, cf5ctl0 fffffd50h, cf6ctl0 fffffd60h note these bits can only be rewritten when the cfnpwr bit = 0. however, cfnpwr bit = 1 can also be set at the same time as rewriting these bits. caution to forcibly suspend transm ission/reception, clear the cfnpwr bit to 0 instead of the cfnrxe and cfntxe bits. at this time, the clock output is stopped. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 902 of 1817 sep 19, 2011 (2/3) single transfer mode continuous transfer mode cfntms note 0 1 transfer mode specification [in single transfer mode] the reception completion interrupt (intcfnr) occurs when communication is complete. even if transmission is enabled (cfntxe bit = 1), the transmission enable interrupt (intcfnt) does not occur. if the next transmit data is written during communication (cfnstr.cfntsf bit = 1), it is ignored and the next communication is not started. also, if reception-only communication is set (cfntxe bit = 0, cfnrxe bit = 1), the next communication is not started even if the receive data is read during communication (cfnstr. cfntsf bit = 1). [in continuous transfer mode] the continuous transmission is enabled by writing the next transmit data during communication (cfnstr.cfntsf bit = 1). writing the next transmission data is enabled after a transmission enable interrupt (intcfnt) occurs. if reception-only communication is set (cfntxe bit = 0, cfnrxe bit = 1) in the continuous transfer mode, the next reception is started immediately after a reception completion interrupt (intcfnr), regardless of the read operation of the cfnrx register. therefore, immediately read the receive data from the cfnrx register. if this read operation is delayed, an overrun error (cfnove bit = 1) occurs. cfndir note 0 1 specification of transfer direction mode (msb/lsb) msb-first transfer lsb-first transfer note these bits can only be rewritten when t he cfnpwr bit = 0. however, the cfnpwr can be set to 1 at the same time as these bits are rewritten. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 903 of 1817 sep 19, 2011 (3/3) communication start trigger invalid communication start trigger valid cfnsce 0 1 specification of start transfer disable/enable ? in master mode this bit enables or disables the communication start trigger. (a) in single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode a communication operation can be started by writing data to the cfntx register when the cfnsce bit is 1 . set the cfnsce bit to 1. (b) in single reception mode disable starting the next receive operation by clearing the cfnsce bit to 0 before reading the last receive data, because a receive operation is started by reading receive data (cfnrx register) note 1 . (c) in continuous reception mode clear the cfnsce bit to 0 one communication clock before reception of the last data is completed to disable the start of reception after the last data is received note 2 . ? in slave mode this bit enables or disables the communication start trigger. set the cfnsce bit to 1. [usage of cfnsce bit] ? in single reception mode <1>when reception of the last data is completed by intcfnr interrupt servicing, clear the cfnsce bit to 0 before reading the cfnrx register. <2>after confirming the cfnstr.cfntsf bit = 0, clear the cfnrxe bit to 0 to disable reception. to continue reception, set the cfnsce bit to 1 to start the next reception by dummy-reading the cfnrx register. ? in continuous reception mode <1>clear the cfnsce bit to 0 during reception of the last data by intcfnr interrupt servicing. <2>read the cfnrx register. <3>read the last reception data by reading the cfnrx register after acknowledging the cfntir interrupt. <4>after confirming the cfnstr.cfntsf bit = 0, clear the cfnrxe bit to 0 to disable reception. to continue reception, set the cfnsce bit to 1 to wait for the next reception by dummy-reading the cfnrx register. notes 1. if the cfnsce bit is read while it is 1, t he next communication operation is started. 2. the cfnsce bit is not cleared to 0 one communication clock before the completion of the last data reception, the next communication op eration is automatically started. caution be sure to clear bits 3 and 2 to ?0?. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 904 of 1817 sep 19, 2011 (4) csifn control register 1 (cfnctl1) cfnctl1 is an 8-bit register that contro ls the csifn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. caution the cfnctl1 register can be rewritten only when the cfnctl0.cfnpwr bit = 0. 0 cfnckp 0 0 1 1 specification of data transmission/ reception timing in relation to sckfn cfnctl1 0 cfndap 0 1 0 1 0 cfnckp cfndap cfncks2 cfncks1 cfncks0 after reset: 00h r/w address: cfncks2 0 0 0 0 1 1 1 1 cfncks1 0 0 1 1 0 0 1 1 cfncks0 0 1 0 1 0 1 0 1 communication clock (f cclk ) note f xx /4 f xx /6 f xx /8 f xx /12 f xx /16 f xx /32 f brgm external clock (sckfn) master mode master mode master mode master mode master mode master mode master mode slave mode mode d7 d6 d5 d4 d3 d2 d1 d0 sckfn (i/o) sifn capture sofn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckfn (i/o) sifn capture sofn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckfn (i/o) sifn capture sofn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckfn (i/o) sifn capture sofn (output) communication type 1 communication type 2 communication type 3 communication type 4 cf0ctl1 fffffd01h, cf1ctl1 fffffd11h, cf2ctl1 fffffd21h, cf3ctl1 fffffd31h, cf4ctl1 fffffd41h, cf5ctl1 fffffd51h, cf6ctl1 fffffd61h notes 1. if n is 0, 4, or 5, set the communication clock (f cclk ) to 8 mhz or lower. 2. if n is 1 to 3, or 6, set the communication clock (f cclk ) to 5 mhz or lower. remarks 1. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) 2. when n = 0 or 1, m = 1 when n = 2 or 3, m = 2 when n = 4, m = 3 when n = 5 or 6, m = 4 for details of f brgm , see 19.8 baud rate generator . v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 905 of 1817 sep 19, 2011 (5) csifn control register 2 (cfnctl2) cfnctl2 is an 8-bit register that controls the number of csifn serial transfer bits. this register can be read or written in 8-bit units. reset sets this register to 00h. caution the cfnctl2 regist er can be rewritten only when the cfnc tl0.cfnpwr bit = 0 or when both the cfntxe and cfnrxe bits = 0. after reset: 00h r/w address: 0 cfnctl2 0 0 0 cfncl3 cfncl2 cfncl1 cfncl0 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits cfncl3 0 0 0 0 0 0 0 0 1 cfncl2 0 0 0 0 1 1 1 1 cfncl1 0 0 1 1 0 0 1 1 cfncl0 0 1 0 1 0 1 0 1 serial register bit length cf0ctl2 fffffd02h, cf1ctl2 fffffd12h, cf2ctl2 fffffd22h, cf3ctl2 fffffd32h, cf4ctl2 fffffd42h, cf5ctl2 fffffd52h, cf6ctl2 fffffd62h remarks 1. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) 2. if the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the lsb of the cfntx and cfnrx registers. 3. : don?t care v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 906 of 1817 sep 19, 2011 (a) transfer data length change function the csifn transfer data length can be set in 1-bit units between 8 and 16 bits us ing the cfnctl2.cfncl3 to cfnctl2.cfncl0 bits. when the transfer bit length is set to a value other t han 16 bits, set the data to t he cfntx or cfnrx register starting from the lsb, regardless of w hether the transfer start bit is the m sb or lsb. any data can be set for the higher bits that are not us ed, but the receive data becomes 0 following serial transfer. (i) transfer bit length = 10 bits, msb first 15 10 9 0 sofn sifn insertion of 0 (ii) transfer bit length = 12 bits, lsb first 0 sofn 11 12 15 sifn insertion of 0 remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 907 of 1817 sep 19, 2011 (6) csifn status register (cfnstr) cfnstr is an 8-bit register t hat displays the csifn status. this register can be read or written in 8-bit or 1-bit units, but the cfntsf flag is read-only. reset sets this register to 00h. in addition to reset input, the cfnstr register can be in itialized by clearing (0) the cfnctl0.cfnpwr bit. cfntsf communication stopped communicating cfntsf 0 1 communication status flag cfnstr 0 0 0 00 0 cfnove after reset: 00h r/w address: ? during transmission, this register is set when data is prepared in the cfntx register, and during reception, it is set when a dummy read of the cfnrx register is performed. when transfer ends, this flag is cleared to 0 at the last edge of the clock. no overrun overrun cfnove 0 1 overrun error flag ? an overrun error occurs when the next reception is completed without the cpu reading the value of the receive buffer, upon completion of the receive operation. the cfnove flag displays the overrun error occurrence status in this case. ? the cfnove bit is valid also in the single transfer mode. therefore, when only using transmission, note the following. ? do not check the cfnove flag. ? read this bit even if reading the reception data is not required. ? the cfnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it. < > < > cf0str fffffd03h, cf1str fffffd13h, cf2str fffffd23h, cf3str fffffd33h, cf4str fffffd43h, cf5str fffffd53h, cf6str fffffd63h remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 908 of 1817 sep 19, 2011 19.5 interrupt request signals csifn can generate the following two types of interrupt request signals. ? reception completion interrupt request signal (intcfnr) ? transmission enable interrupt request signal (intcfnt) of these two interrupt request signals, the reception comple tion interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower. table 19-2. interrupts and their default priority interrupt priority reception complete high transmission enable low (1) reception completion interr upt request signal (intcfnr) when receive data is transferred to the cfnrx register while reception is enabled, the reception completion interrupt request signal is generated. this interrupt request signal can also be generated if an overrun error occurs. when the reception completion interrupt request signal is acknowledged and the data is read, read the cfnstr register to check that the result of reception is not an error. in the single transfer mode, the intcfnr interrupt req uest signal is generated upon completion of transmission, even when only transmission is executed. (2) transmission enable interr upt request sign al (intcfnt) in the continuous transmission or continuous transmissio n/reception mode, transmit data is transferred from the cfntx register and, as soon as writ ing to cfntx has been enabled, the transmission enable interrupt request signal is generated. in the single transmission and single transmission/receptio n modes, the intcfnt interrupt is not generated. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 909 of 1817 sep 19, 2011 19.6 operation 19.6.1 single transfer mode (m aster mode, transmission mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = f xx /2 or f xx /3 (cfnctl1.cfncks2 to cfnctl1.cfnc ks0 bits = 000), transfer data length = 8 bits (cfnctl2.cfncl3 to cfnctl2.cfncl0 bits = 0000) (1) operation flow start no (1), (2), (3) (4) (5) (6) (8) no (7) intcfnr interrupt generated? transmission completed? end yes yes cfnctl1 register 00h cfnctl2 register 00h cfnctl0 register c1h write cfntx register start transmission cfnctl0 00h remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 910 of 1817 sep 19, 2011 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (7) (8) sofn pin intcfnr signal (1) write 00h to the cfnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2 or f xx /3, and master mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cfnctl0 register, and select the transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) set the cfnstr.cfntsf bit to 1 by writing t he transmit data to the cfntx register, and start transmission. (5) when transmission is started, output the serial clock to the sckf n pin, and output the transmit data from the sofn pin in synchronization with the serial clock. (6) when transmission of the transfer data length se t with the cfnctl2 register is completed, stop the serial clock output and transmit data output, generate the reception completion interrupt request signal (intcfnr) at the last edge of the serial clock, and clear the cfntsf bit to 0. (7) to continue transmission, start the next transmissi on by writing the transmit dat a to the cfntx register again after the intcfnr signal is generated. (8) to end transmission, write cfnctl0.cf npwr bit = 0 and cfnctl0.cfntxe bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 911 of 1817 sep 19, 2011 19.6.2 single transfer mode (master mode, reception mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = f xx /2 or f xx /3 (cfnctl1.cfncks2 to cfnctl1.cfnc ks0 bits = 000), transfer data length = 8 bits (cfnctl2.cfncl3 to cfnctl2.cfncl0 bits = 0000) (1) operation flow start no intcfnr interrupt generated? reception completed? end yes yes no (7) cfnrx register dummy read cfnsce bit = 0 (cfnctl0) cfnctl0 register 00h read cfnrx register read cfnrx register cfnctl1 register 00h cfnctl2 register 00h cfnctl0 register a1h start reception (1), (2), (3) (4) (5) (6) (8) (9) (10) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 912 of 1817 sep 19, 2011 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sifn pin sifn pin capture timing intcfnr signal (1) write 00h to the cfnctl1 register, and se lect communication type 1, communication clock (f cclk ) = f xx /2 or f xx /3, and master mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cfnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) set the cfnstr.cfntsf bit to 1 by perfo rming a dummy read of the cfnrx register, and start reception. (5) when reception is started, output the serial clock to the sckfn pin, and capture the receive data of the sifn pin in synchronization with the serial clock. (6) when reception of the transfer data length set with the cfnctl2 regist er is completed, stop the serial clock output and data capturing, generate the reception completion interrupt request signal (intcfnr) at the last edge of the serial clo ck, and clear the cfntsf bit to 0. (7) to continue reception, read the cfnrx register while keeping th e cfnctl0.cfnsce bit = 1 after the intcfnr signal is generated. (8) to read the cfnrx register without starting the next reception, write the cfnsce bit = 0. (9) read the cfnrx register. (10) to end reception, writ e cfnctl0.cfnpwr bit = 0 and cfnctl0.cfnrxe bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 913 of 1817 sep 19, 2011 19.6.3 single transfer mode (master mode, transmission/reception mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = f xx /2 or f xx /3 (cfnctl1.cfncks2 to cfnctl1.cfnc ks0 bits = 000), transfer data length = 8 bits (cfnctl2.cfncl3 to cfnctl2.cfncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (7), (9) (5) (6) (10) no (8) transmission/reception completed? end yes cfnctl1 register 07h cfnctl2 register 00h cfnctl0 register e1h write cfntx register read cfnrx register start transmission/reception cfnctl0 00h no intcfnr interrupt generated? yes remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 914 of 1817 sep 19, 2011 (2) operation timing sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sifn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sofn pin sifn pin capture timing intcfnr signal (1) write 00h to the cfnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /2 or f xx /3, and master mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cfnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) set the cfnstr.cfntsf bit to 1 by writing t he transmit data to the cfntx register, and start transmission/reception. (5) when transmission/reception is st arted, output the serial clock to the sckfn pin, output the transmit data to the sofn pin in synchronization with the seri al clock, and capture the re ceive data of the sifn pin. (6) when transmission/reception of the transfer data length set by the cfnctl2 register is completed, stop the serial clock output, transmit data outpu t, and data capturing, generate the reception completion interrupt request signal (intcfnr) at the last edge of the serial clock, and clear the cfntsf bit to 0. (7) read the cfnrx register. (8) to continue transmission/reception, write t he transmit data to the cf ntx register again. (9) read the cfnrx register. (10) to end transmission/reception, write cfnctl0.cfnpwr bit = 0, cfnctl0.cfntxe bit = 0, and cfnctl0.cfnrxe bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 915 of 1817 sep 19, 2011 19.6.4 single transfer mode (s lave mode, transmission mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cfnc tl1.cfndap bits = 00), communication clock (f cclk ) = external clock (sckfn) (cfnctl1.cfncks2 to cfnctl1.cfncks0 bits = 111), transfer data length = 8 bits (cfnctl2.cfnc l3 to cfnctl2.cfncl0 bits = 0000) (1) operation flow start no (1), (2), (3) (4) (5) (4) (6) (8) no (7) intcfnr interrupt generated? transmission completed? end yes yes cfnctl1 register 07h cfnctl2 register 00h cfnctl0 register c1h write cfntx register start transmission cfnctl0 00h no yes sckfn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 916 of 1817 sep 19, 2011 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (7) (8) sofn pin intcfnr signal (1) write 07h to the cfnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckfn), and slave mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cfnctl0 register, and select the transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cfnstr.cfntsf bit is set to 1 by writing the transmit data to the cf ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit data from the sofn pin in synchronization with the serial clock. (6) when transmission of the transfer data length se t with the cfnctl2 register is completed, stop the serial clock input and transmit data output, generate the reception completion interrupt request signal (intcfnr) at the last edge of the serial clock, and clear the cfntsf bit to 0. (7) to continue transmission, write the transmit data to the cfntx register again after the intcfnr signal is generated, and wait for a serial clock input. (8) to end transmission, write cfnctl0.cf npwr bit = 0 and cfnctl0.cfntxe bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 917 of 1817 sep 19, 2011 19.6.5 single transfer mode (slave mode, reception mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = external clock (sckfn) (cfnctl1.cfncks 2 to cfnctl1.cfncks0 bits = 111), transfer data length = 8 bits (cfnctl2.cfnc l3 to cfnctl2.cfncl0 bits = 0000) (1) operation flow start reception completed? end yes no (7) cfnrx register dummy read cfnsce bit = 0 (cfnctl0) cfnctl0 register 00h read cfnrx register read cfnrx register cfnctl1 register 07h cfnctl2 register 00h cfnctl0 register a1h start reception no intcfnr interrupt generated? yes no yes (1), (2), (3) (4) (5) (4) (6) (6) (8) (9) (10) sckfn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 918 of 1817 sep 19, 2011 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sifn pin sifn pin capture timing intcfnr signal (1) write 07h to the cfnctl1 register, and se lect communication type 1, communication clock (f cclk ) = external clock (sckfn), and slave mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cfnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cfnstr.cfntsf bit is set to 1 by perf orming a dummy read of the cfnrx register, and the device waits for a serial clock input. (5) when a serial clock is input, capture the receive da ta of the sifn pin in synchronization with the serial clock. (6) when reception of the transfer data length set with the cfnctl2 regist er is completed, stop the serial clock input and data capturing, gener ate the reception completion in terrupt request signal (intcfnr) at the last edge of the serial clo ck, and clear the cfntsf bit to 0. (7) to continue reception, read the cfnrx register while keeping th e cfnctl0.cfnsce bit = 1 after the intcfnr signal is generated, and wait for a serial clock input. (8) to end reception, write the cfnsce bit = 0. (9) read the cfnrx register. (10) to end reception, writ e cfnctl0.cfnpwr bit = 0 and cfnctl0.cfnrxe bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 919 of 1817 sep 19, 2011 19.6.6 single transfer mode (slave mode, transmission/reception mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = external clock (sckfn) (cfnctl1.cfncks 2 to cfnctl1.cfncks0 bits = 111), transfer data length = 8 bits (cfnctl2.cfnc l3 to cfnctl2.cfncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (7), (9) (5) (4) (6) (10) no (8) transmission/reception completed? end yes cfnctl1 register 07h cfnctl2 register 00h cfnctl0 register e1h write cfntx register read cfnrx register start transmission/reception cfnctl0 00h no intcfnr interrupt generated? yes no yes sckfn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 920 of 1817 sep 19, 2011 (2) operation timing sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sifn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sofn pin sifn pin capture timing intcfnr signal (1) write 07h to the cfnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = external clock (sckfn), and slave mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cfnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cfnstr.cfntsf bit is set to 1 by writing t he transmit data to the cfnt x register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a to the sofn pin in synchronization with the serial clock, and capture the receiv e data of the sifn pin. (6) when transmission/reception of t he transfer data length set with the cfnctl2 register is completed, stop the serial clock input, transmit data output, and data capturing, generate the reception completion interrupt request signal (intcfnr) at the last edge of the serial clock, and clear the cfntsf bit to 0. (7) read the cfnrx register. (8) to continue transmission/reception, write the trans mit data to the cfntx regist er again, and wait for a serial clock input. (9) read the cfnrx register. (10) to end transmission/reception, write cfnctl0.cfnpwr bit = 0, cfnctl0.cfntxe bit = 0, and cfnctl0.cfnrxe bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 921 of 1817 sep 19, 2011 19.6.7 continuous transfer mode (master mode, transmission mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = f xx /2 or f xx /3 (cfnctl1.cfncks2 to cfnctl1.cfnc ks0 bits = 000), transfer data length = 8 bits (cfnctl2.cfncl3 to cfnctl2.cfncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4), (8) (5) (11) no (7) transmission completed? end yes cfnctl1 register 00h cfnctl2 register 00h cfnctl0 register c3h write cfntx register start transmission cfnctl0 00h no (6), (9) intcfnt interrupt generated? yes no (10) yes cfntsf bit = 0? (cfnstr register) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 922 of 1817 sep 19, 2011 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) sofn pin intcfnt signal intcfnr signal l bit 0 (1) write 00h to the cfnctl1 register, and se lect communication type 1, communication clock (f cclk ) = f xx /2 or f xx /3, and master mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cfnctl0 register, and sele ct the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) set the cfnstr.cfntsf bit to 1 by writing the transmit data to the cfntx register, and start transmission. (5) when transmission is started, output the serial clock to the sckf n pin, and output the transmit data from the sofn pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cfntx register to the shift register is completed and writing to the cfntx register is enabled, the transmission enable interr upt request signal (intcfnt) is generated. (7) to continue transmission, write the transmit data to the cfntx register again after the intcfnt signal is generated. (8) when a new transmit data is written to the cfnt x register before communication completion, the next communication is started following communication completion. (9) the transfer of the transmit data from the cfntx register to the shift regi ster is completed and the intcfnt signal is generated. to end continuous transmission with the current transmission, do not write to the cfntx register. (10) when the next transmit data is not written to t he cfntx register before tr ansfer completion, stop the serial clock output to the sckfn pin after trans fer completion, and clear the cfntsf bit to 0. (11) to release the transmission enable status, wr ite cfnctl0.cfnpwr bit = 0 and cfnctl0.cfntxe bit = 0 after checking that the cfntsf bit = 0. caution in continuous transm ission mode, the reception completi on interrupt request signal (intcfnr) is not generated. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 923 of 1817 sep 19, 2011 19.6.8 continuous transfer mode (master mode, reception mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = f xx /2 or f xx /3 (cfnctl1.cfncks2 to cfnctl1.cfnc ks0 bits = 000), transfer data length = 8 bits (cfnctl2.cfncl3 to cfnctl2.cfncl0 bits = 0000) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 924 of 1817 sep 19, 2011 (1) operation flow start no intcfnr interrupt generated? cfnove bit = 1? (cfnstr) end yes no yes cfnrx register dummy read cfnsce bit = 0 (cfnctl0) cfnove bit = 0 (cfnstr) read cfnrx register is data being received last data? yes cfnsce bit = 0 (cfnctl0) read cfnrx register cfnctl1 register 00h cfnctl2 register 00h cfnctl0 register a3h start reception (1), (2), (3) (4) (5) (6) (8) (9) (12) (13) (13) no read cfnrx register (9) (7) read cfnrx register no yes cfnctl0 register 00h no yes cfntsf bit = 0? (cfnstr) (9) (10) (11) (8) intcfnr interrupt generated? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 925 of 1817 sep 19, 2011 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckfn pin cfntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (13) (10) sifn pin intcfnr signal cfnsce bit sofn pin l sifn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cfnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /2, and master mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cfnctl0 register, and select the reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) set the cfnstr.cfntsf bit to 1 by performi ng a dummy read of the cf nrx register, and start reception. (5) when reception is started, output the serial clock to the sckfn pin, and capture the receive data of the sifn pin in synchronization with the serial clock. (6) when reception is completed, the reception co mpletion interrupt request signal (intcfnr) is generated, and reading of the cfnrx register is enabled. (7) when the cfnctl0.cfnsce bit = 1 upon commu nication completion, the next communication is started following communication completion. (8) to end continuous reception with the curr ent reception, write the cfnsce bit = 0. (9) read the cfnrx register. (10) when reception is completed, the intcfnr signal is generated, and reading of the cfnrx register is enabled. when the cfnsce bit = 0 is set before communication completion, stop the serial clock output to the sckfn pin, and clear the cfntsf bit to 0, to end the receive operation. (11) read the cfnrx register. (12) if an overrun error occurs, write the cfns tr.cfnove bit = 0, and clear the error flag. (13) to release the reception enable status, writ e cfnctl0.cfnpwr bit = 0 and cfnctl0.cfnrxe bit = 0 after checking that the cfntsf bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 926 of 1817 sep 19, 2011 19.6.9 continuous transfer mode (mast er mode, transmissi on/reception mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = f xx /2 or f xx /3 (cfnctl1.cfncks2 to cfnctl1.cfnc ks0 bits = 000), transfer data length = 8 bits (cfnctl2.cfncl3 to cfnctl2.cfncl0 bits = 0000) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 927 of 1817 sep 19, 2011 (1) operation flow start end yes no is receive data last data? yes (12) no write cfntx register cfnove bit = 0 (cfnstr) read cfnrx register read cfnrx register cfnctl1 register 00h cfnctl2 register 00h cfnctl0 register e3h no (9) yes (1), (2), (3) (4) (5) (7) (11) (7) (6), (11) (8) (13) (13) (14) (15) (15) (10) no yes intcfnt interrupt generated? no yes cfntsf bit = 0? (cfnstr) write cfntx register yes no is data being transmitted last data? start transmission/reception cfnctl0 register 00h cfnove bit = 1? (cfnstr) intcfnr interrupt generated? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 928 of 1817 sep 19, 2011 (2) operation timing (1/2) sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (15) (12) sifn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sofn pin intcfnt signal intcfnr signal sifn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cfnctl1 register, and se lect communication type 1, communication clock (f cclk ) = f xx /2 or f xx /3, and master mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cfnctl0 register, and sele ct the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) set the cfnstr.cfntsf bit to 1 by writing t he transmit data to the cfntx register, and start transmission/reception. (5) when transmission/reception is st arted, output the serial clock to the sckfn pin, output the transmit data to the sofn pin in synchronization with the seri al clock, and capture the re ceive data of the sifn pin. (6) when transfer of the transmit data from the cfntx register to the shift register is completed and writing to the cfntx register is enabled, the transmission enable interr upt request signal (intcfnt) is generated. (7) to continue transmission/receptio n, write the transmit data to t he cfntx register again after the intcfnt signal is generated. (8) when one transmission/reception is completed, the reception completion interrupt request signal (intcfnr) is generated, an d reading of the cfnrx register is enabled. (9) when a new transmit data is written to the cfntx register before communication completion, the next communication is started following communication completion. (10) read the cfnrx register. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 929 of 1817 sep 19, 2011 (2/2) (11) the transfer of the transmit data from the cfntx register to the shift register is completed and the intcfnt signal is generated. to end contin uous transmission/reception with the current transmission/reception, do not wr ite to the cfntx register. (12) when the next transmit data is not written to t he cfntx register before tr ansfer completion, stop the serial clock output to the sckfn pin after trans fer completion, and clear the cfntsf bit to 0. (13) when the reception error interrupt request si gnal (intcfnr) is generated, read the cfnrx register. (14) if an overrun error occurs, write cfnstr .cfnove bit = 0, and clear the error flag. (15) to release the transmission/reception ena ble status, write cfnc tl0.cfnpwr bit = 0, cfnctl0.cfntxe bit = 0, and cfnc tl0.cfnrxe bit = 0 after checking that the cfntsf bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 930 of 1817 sep 19, 2011 19.6.10 continuous transfer mode (slave mode, transmission mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = external clock (sckfn) (cfnctl1.cfncks 2 to cfnctl1.cfncks0 bits = 111), transfer data length = 8 bits (cfnctl2.cfnc l3 to cfnctl2.cfncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (4) (5), (8) (11) no (7) transmission completed? end yes cfnctl1 register 07h cfnctl2 register 00h cfnctl0 register c3h write cfntx register start transmission cfnctl0 00h no (10) yes cfntsf bit = 0? (cfnstr register) no (6), (9) intcfnt interrupt generated? yes no (9) yes sckfn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 931 of 1817 sep 19, 2011 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) sofn pin intcfnt signal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cfnctl1 register, and se lect communication type 1, communication clock (f cclk ) = external clock (sckfn), and slave mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cfnctl0 register, and sele ct the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cfnstr.cfntsf bit is set to 1 by writing t he transmit data to the cfnt x register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit data from the sofn pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cfntx register to the shift register is completed and writing to the cfntx register is enabled, the transmission enable interr upt request signal (intcfnt) is generated. (7) to continue transmission, write the transmit data to the cfntx register again after the intcfnt signal is generated. (8) when a serial clock is input following completion of the transmission of the transfer data length set with the cfnctl2 register, continu ous transmission is started. (9) when transfer of the transmit data from the cfntx register to the shift register is completed and writing to the cfntx register is enabled, the intcfnt signal is generated. to end continuous transmission with the current transmission, do not write to the cfntx register. (10) when the clock of the transfer data length set with the cf nctl2 register is input without writing to the cfntx register, clear the cfntsf bit to 0 to end transmission. (11) to release the transmission enable status, wr ite cfnctl0.cfnpwr bit = 0 and cfnctl0.cfntxe bit = 0 after checking that the cfntsf bit = 0. caution in continuous transmis sion mode, the reception completi on interrupt request signal (intcfnr) is not generated. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 932 of 1817 sep 19, 2011 19.6.11 continuous transfer m ode (slave mode, reception mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = external clock (sckfn) (cfnctl1.cfncks 2 to cfnctl1.cfncks0 bits = 111), transfer data length = 8 bits (cfnctl2.cfnc l3 to cfnctl2.cfncl0 bits = 0000) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 933 of 1817 sep 19, 2011 (1) operation flow start no intcfnr interrupt generated? cfnove bit = 1? (cfnstr) end no yes yes cfnrx register dummy read cfnsce bit = 0 (cfnctl0) cfnove bit = 0 (cfnstr) read cfnrx register is data being received last data? yes cfnsce bit = 0 (cfnctl0) read cfnrx register cfnctl1 register 07h cfnctl2 register 00h cfnctl0 register a3h reception start (1), (2), (3) (4) (5) (4) (6) (8) (9) (12) (13) (13) no read cfnrx register (9) (7) read cfnrx register no yes cfnctl0 register 00h intcfnr interrupt generated? (9) (10) (11) (8) no yes cfntsf bit = 0? (cfnstr) no yes sckfn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 934 of 1817 sep 19, 2011 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckfn pin cfntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (13) (10) sifn pin intcfnr signal cfnsce bit sifn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cfnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = external clock (sckfn), and slave mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cfnctl0 register, and select the reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cfnstr.cfntsf bit is set to 1 by perf orming a dummy read of the cfnrx register, and the device waits for a serial clock input. (5) when a serial clock is input, capture the receive da ta of the sifn pin in synchronization with the serial clock. (6) when reception is completed, the reception co mpletion interrupt request signal (intcfnr) is generated, and reading of the cfnrx register is enabled. (7) when a serial clock is input in the cfnctl0.cfns ce bit = 1 status, continuous reception is started. (8) to end continuous reception with the curr ent reception, write the cfnsce bit = 0. (9) read the cfnrx register. (10) when reception is completed, the intcfnr signal is generated, and reading of the cfnrx register is enabled. when cfnsce bit = 0 is set before communication completion, clear the cfntsf bit to 0 to end the receive operation. (11) read the cfnrx register. (12) if an overrun error occurs, write cfnstr .cfnove bit = 0, and clear the error flag. (13) to release the reception enable status, writ e cfnctl0.cfnpwr bit = 0 and cfnctl0.cfnrxe bit = 0 after checking that the cfntsf bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 935 of 1817 sep 19, 2011 19.6.12 continuous transfer mode (s lave mode, transmission/reception mode) msb first (cfnctl0.cfndir bit = 0), communication type 1 (cfnctl1.cfnckp and cf nctl1.cfndap bits = 00), communication clock (f cclk ) = external clock (sckfn) (cfnctl1.cfncks 2 to cfnctl1.cfncks0 bits = 111), transfer data length = 8 bits (cfnctl2.cfnc l3 to cfnctl2.cfncl0 bits = 0000) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 936 of 1817 sep 19, 2011 (1) operation flow start end yes no is receive data last data? yes no write cfntx register cfnove bit = 0 (cfnstr) read cfnrx register read cfnrx register cfnctl1 register 07h cfnctl2 register 00h cfnctl0 register e3h no yes (1), (2), (3) (4) (5) (7) (11) (9) (7) (8) (13) (12) (13) (14) (15) (15) (10) no yes cfntsf bit = 0? (cfnstr) write cfntx register yes no is data being transmitted last data? start transmission/reception cfnctl0 register 00h cfnove bit = 1? (cfnstr) intcfnr interrupt generated? (6), (11) no yes intcfnt interrupt generated? (4) no yes sckfn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 937 of 1817 sep 19, 2011 (2) operation timing (1/2) sckfn pin cfntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (15) (12) sifn pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sofn pin intcfnt signal intcfnr signal sifn pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cfnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = external clock (sckfn), and slave mode. (2) write 00h to the cfnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cfnctl0 register, and sele ct the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cfnstr.cfntsf bit is set to 1 by writing t he transmit data to the cfnt x register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a to the sofn pin in synchronization with the serial clock, and capture the receiv e data of the sifn pin. (6) when transfer of the transmit data from the cfntx register to the shift register is completed and writing to the cfntx register is enabled, the transmission enable interr upt request signal (intcfnt) is generated. (7) to continue transmission, write the transmit data to the cfntx register again after the intcfnt signal is generated. (8) when reception of the transfer dat a length set with the cfnctl2 regist er is completed, the reception completion interrupt request signal (intcfnr) is ge nerated, and reading of the cfnrx register is enabled. (9) when a serial clock is input continuously, continuous transmission/re ception is started. (10) read the cfnrx register. (11) when transfer of the transmit dat a from the cfntx register to the shift register is completed and writing to the cfntx register is enabled, the intcfnt signal is generated. to end continuous transmission/reception with the current transmission/re ception, do not write to the cfntx register. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 938 of 1817 sep 19, 2011 (2/2) (12) when the clock of the transfer data length set with the cf nctl2 register is input without writing to the cfntx register, the intcfnr signal is generat ed. clear the cfntsf bit to 0 to end transmission/reception. (13) when the intcfnr signal is gen erated, read the cfnrx register. (14) if an overrun error occurs, write cfnstr .cfnove bit = 0, and clear the error flag. (15) to release the transmission/reception ena ble status, write cfnc tl0.cfnpwr bit = 0, cfnctl0.cfntxe bit = 0, and cfnc tl0.cfnrxe bit = 0 after checking that the cfntsf bit = 0. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 939 of 1817 sep 19, 2011 19.6.13 reception error when transfer is performed with reception enabled (cfnctl0. cfnrxe bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (intcfnr) is generated again when the next receive operation is completed before the cfnrx register is read after the intcfnr signal is generated, and the overrun error flag (cfnstr.cfnove) is set to 1. even if an overrun error has occurred, the previous receive data is lost since the cfnrx regist er is updated. even if a reception error has occurred, the intcfnr signal is generat ed again upon the next reception completion if the cfnrx register is not read. to avoid an overrun error, complete reading the cfnrx regi ster by one half clock before sampling the last bit of the next receive data from the intcfnr signal generation. (1) operation timing sckfn pin cfnrx register read signal (1) (2) (4) 01h 02h 05h 0ah 15h 2ah 55h aah 00h 01h 02h 05h 0ah 15h 2ah 55h shift register aah 55h cfnrx register sifn pin intcfnr signal cfnove bit sifn pin capture timing (3) (1) start continuous transfer. (2) completion of the first transfer (3) the cfnrx register cannot be read until one hal f clock before the completion of the second transfer. (4) an overrun error occurs, and the reception co mpletion interrupt request signal (intcfnr) is generated, and then the overrun error flag (cfnst r.cfnove) is set to 1. the receive data is overwritten. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 940 of 1817 sep 19, 2011 19.6.14 clock timing (1/2) (i) communication type 1 (cfnckp and cfndap bits = 00) d6 d5 d4 d3 d2 d1 sckfn pin sifn capture reg-r/w sofn pin intcfnt interrupt note 1 intcfnr interrupt note 2 cfntsf bit d0 d7 (ii) communication type 3 (cfnckp and cfndap bits = 10) d6 d5 d4 d3 d2 d1 d0 d7 sckfn pin sifn capture reg-r/w sofn pin intcfnt interrupt note 1 intcfnr interrupt note 2 cfntsf bit notes 1. the intcfnt interrupt is set when the data writt en to the cfntx register is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. in the single transmission or single transmission/reception mode, the intcfnt interrupt request signal is not generated, but the intcfnr interrupt request signal is generated upon end of communication. 2. the intcfnr interrupt occurs if reception is co rrectly ended and receive data is ready in the cfnrx register while reception is enabled. in the si ngle mode, the intcfnr interrupt request signal is generated even in the transmission mode, upon end of communication. caution in single transfer mode, writing to the cfntx register with the cfntsf bi t set to 1 is ignored. this has no effect on the operation during transfer. for example, if the next data is written to the cfntx register wh en dma is started by generating the intcfnr signal, th e written data is not transfer red because the cfntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 941 of 1817 sep 19, 2011 (2/2) (iii) communication type 2 (c fnckp and cfndap bits = 01) d6 d5 d4 d3 d2 d1 d0 d7 sckfn pin sifn capture reg-r/w sofn pin intcfnt interrupt note 1 intcfnr interrupt note 2 cfntsf bit (iv) communication type 4 (cfnckp and cfndap bits = 11) d6 d5 d4 d3 d2 d1 d0 d7 sckfn pin sifn capture reg-r/w sofn pin intcfnt interrupt note 1 intcfnr interrupt note 2 cfntsf bit notes 1. the intcfnt interrupt is set when the data writt en to the cfntx register is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. in the single transmission or single transmission/receptio n modes, the intcfnt interrupt request signal is not generated, but the intcfnr interrupt request signal is generated upon end of communication. 2. the intcfnr interrupt occurs if reception is co rrectly ended and receive data is ready in the cfnrx register while reception is enabled. in the si ngle mode, the intcfnr interrupt request signal is generated even in the transmission mode, upon end of communication. caution in single transfer mode, writing to the cfntx register with the cfntsf bi t set to 1 is ignored. this has no effect on the operation during transfer. for example, if the next data is written to the cfntx register wh en dma is started by generating the intcfnr signal, th e written data is not transfer red because the cfntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 942 of 1817 sep 19, 2011 19.7 output pins (1) sckfn pin when csifn operation is disabled (cfnctl0.cfnpwr bit = 0), the sckfn pin output status is as follows. cfnckp cfncks2 cfncks1 cfncks0 sckfn pin output 1 1 1 high impedance 0 other than above fixed to high level 1 1 1 high impedance 1 other than above fixed to low level remarks 1. the output level of t he sckfn pin changes if any of t he cfnctl1.cfnckp or cfncks2 to cfncks0 bits is rewritten. 2. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) (2) sofn pin when csifn operation is disabled (cfnpwr bit = 0), the sofn pin output status is as follows. cfntxe cfndap cfndir sofn pin output 0 fixed to low level 0 sofn latch value (low level) 0 cfntx value (msb) 1 1 1 cfntx value (lsb) remarks 1. the sofn pin output changes when any one of the cfnctl0.cfntxe, cf nctl0.cfndir or cfnctl1.cfndap bit is rewritten. 2. : don?t care 3. n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 943 of 1817 sep 19, 2011 19.8 baud rate generator the brg1 to brg4 baud rate generators are connected to csif0 to csif6 as shown in the following block diagram. csif0 csif1 csif2 csif3 csif4 brg1 brg2 brg3 f xx f xx f xx f brg1 f brg2 f brg3 csif5 csif6 brg4 f xx f brg4 (1) prescaler mode registers 1 to 4 (prsm1 to prsm4) the prsmm registers control generation of the baud rate signal for csif. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. 0 prsmm (m = 1 to 4) 0 0 bgcem 0 0 bgcsm1 bgcsm0 disabled enabled bgcem 0 1 baud rate output f xx f xx /2 f xx /4 f xx /8 setting value (k) 0 1 2 3 bgcsm1 0 0 1 1 bgcsm0 0 1 0 1 input clock selection (f bgcsm ) after reset: 00h r/w address: prsm1 fffff320h, prsm2 fffff324h, prsm3 fffff328h, prsm4 fffff32ch < > cautions 1. do not rewrite the prsmm register during operation. 2. set the prsmm register befo re setting the bgcem bit to 1. 2. be sure to set bits 7 to 5, 3, and 2 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 944 of 1817 sep 19, 2011 (2) prescaler compare registers 1 to 4 (prscm1 to prscm4) the prscm1 to prscm4 registers are 8-bit compare registers. these registers can be read or written in 8-bit units. reset sets these registers to 00h. prscmm7 prscmm (m = 1 to 4) prscmm6 prscmm5 prscmm4 prscmm3 prscmm2 prscmm1 prscmm0 after reset: 00h r/w address: prscm1 fffff321h, prscm2 fffff325h, prscm3 fffff329h, prscm4 fffff32dh cautions 1. do not rewrite the pr scmm register during operation. 2. set the prscmm register before setting the prsmm.bgcem bit to 1. 19.8.1 baud rate generation the transmission/reception clock is generated by dividing t he main clock. the baud rate generated from the main clock is obtained by the following equation. f brgm = caution set f brgm to 8 mhz (csif0, csif4, and csif5), 5 mhz (csif1 to csif3 and csif6), or lower. remark f brgm : brgm count clock f xx : main clock oscillation frequency k: prsmm register setting value = 0 to 3 n: prscmm register setting value = 1 to 256 however, n = 256 only when the prscmm register is set to 00h. m = 1 to 4 f xx 2 k+1 n v850es/jh3-e, v850es/jj3-e chapter 19 clocked serial interface f (csif) r01uh0290ej0300 rev.3.00 page 945 of 1817 sep 19, 2011 19.9 cautions (1) when transferring transmit data and receive data using dma transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. check that the no overrun error has occurred by reading the cfnstr.cfnove bit after dma transfer has been completed. (2) if a register that is prohibited to be rewritten during op eration (cfnctl0.cfnpwr bit = 1) is rewritten by mistake during operation, set the cf nctl0.cfnpwr bit to 0 onc e, then initialize csifn. registers to which rewriting during operation is prohibited are shown below. ? cfnctl0 register: cfntxe, cfnrxe, cfndir, cfntms bits ? cfnctl1 register: cfnckp, cf ndap, cfncks2 to cfncks0 bits ? cfnctl2 register: cfncl3 to cfncl0 bits (3) in communication type 2 or 4 (cfnctl1.cfndap bit = 1) , the cfnstr.cfntsf bit is cleared half a sckfn clock after the occurrence of a reception completion interrupt (intcfnr). in the single transfer mode, writing the next transmit data is ignored during communication (cfntsf bit = 1), and the next communication is not star ted. also if reception-only co mmunication (cfnctl0.cfntxe bit = 0, cfnctl0.cfnrxe bit = 1) is set, the next communication is not started even if the receive data is read during communication (cfntsf bit = 1). therefore, when using the single transfer mode with comm unication type 2 or 4 (cfndap bit = 1), pay particular attention to the following. ? to start the next transmission, c onfirm that cfntsf bit = 0 and then wr ite the transmit data to the cfntx register. ? to perform the next reception continuously when rec eption-only communication (cfntxe bit = 0, cfnrxe bit = 1) is set, confirm that cfntsf bit = 0 and then read the cfnrx register. or, use the continuous transfer mode inst ead of the single transfer mode. us e of the continuous transfer mode is recommended especially when using dma. remark n = 0 to 4 (v850es/jh3-e) n = 0 to 6 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 946 of 1817 sep 19, 2011 chapter 20 i 2 c bus to use the i 2 c bus function, set the p24/scl00, p23/sd a00, p40/sda01, p41/ scl01, p36/sda02, p37/scl02, p99/sda03, p910/scl03, p55/sda04, and p56/scl04 pins as alternate-function pins, and set them to n-ch open-drain output. 20.1 features i 2 c00 to i 2 c04 have the following two modes. ? operation stop mode ? i 2 c (inter ic) bus mode (multimasters supported) (1) operation stop mode in this mode, serial transfer is not performed, thus enabling a reduction in power consumption. (2) i 2 c bus mode (multimaster support) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (scl0n) and a serial data bus pin (sda0n). this mode complies with the i 2 c bus format and the master device can generate ?start condition?, ?address?, ?transfer direction specification?, ?dat a?, and ?stop condition? data for the slav e device on the serial data bus. the slave device automatically detects the received statuses and data by hardware. this function can simplify the part of an application program that controls the i 2 c bus. since scl0n and sda0n pins are used for n-ch open-drain outputs, i 2 c0n requires pull-up resistors for the serial clock line and the serial data bus line. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 947 of 1817 sep 19, 2011 20.2 configuration the block diagram of the i 2 c0n is shown below. figure 20-1. block diagram of i 2 c0n internal bus iic status register n (iicsn) iic control register n (iiccn) so latch iicen dq cln1, cln0 trcn dfcn dfcn sda0n scl0n output control intiicn iic shift register n (iicn) iiccn.sttn, sptn iicsn.mstsn, excn, coin iicsn.mstsn, excn, coin lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn internal bus cldn dadn smcn dfcn cln1 cln0 clxn iic clock select register n (iiccln) stcfn iicbsyn stcenn iicrsvn iic flag register n (iicfn) iic function expansion register n (iicxn) fxx iic division clock select register m (ocksm) fxx to fxx/5 ocksthm ocksenm ocksm1 ocksm0 clear slave address register n (svan) match signal set noise eliminator iic shift register n (iicn) data retention time correction circuit n-ch open-drain output acknowledge detector acknowledge generator start condition detector stop condition detector serial clock counter serial clock controller noise eliminator n-ch open-drain output start condition generator stop condition generator wakeup controller interrupt request signal generator serial clock wait controller bus status detector prescaler prescaler remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) m = 0 to 2 v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 948 of 1817 sep 19, 2011 a serial bus configuration example is shown below. figure 20-2. serial bus c onfiguration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2 v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 949 of 1817 sep 19, 2011 i 2 c0n includes the following hardware. table 20-1. configuration of i 2 c0n item configuration registers iic shift register n (iicn) slave address register n (svan) control registers iic control register n (iiccn) iic status register n (iicsn) iic flag register n (iicf0n) iic clock select register n (iiccln) iic function expansion register n (iicxn) iic division clock select registers 0 to 2 (ocks0 to ocks2) (1) iic shift register n (iicn) the iicn register converts 8-bit serial data into 8- bit parallel data and vice versa, and can be used for both transmission and reception. write and read operations to the iicn register are used to control the actual transmit and receive operations. this register can be read or written in 8-bit units. reset sets this register to 00h. (2) slave address register n (svan) the svan register sets local addresses when in slave mode. this register can be read or written in 8-bit units. reset sets this register to 00h. (3) so latch the so latch is used to retain t he output level of the sda0n pin. (4) wakeup controller this circuit generates an interrupt request signal (int iicn) when the address value set to the svan register matches the received address or when an extension code is received. (5) prescaler this selects the samp ling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 950 of 1817 sep 19, 2011 (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated by either of the following two triggers. ? the falling edge of the eighth or ninth clock of the serial clock (set by iiccn.wtimn bit) ? interrupt occurrence due to stop conditio n detection (set by iiccn.spien bit) (8) serial clock controller in master mode, this circuit generates the clock output via the scl0n pin from the sampling clock (n = 0 to 2). (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits are used to gener ate and detect various statuses. (11) data hold time correction circuit this circuit generates the hold time for the dat a corresponding to the falling edge of the scl0n pin. (12) start condition generator this circuit generates a start condi tion when the iiccn.sttn bit is set. however, when in the communication reservation disabled status (iicfn.iicrsvn bit = 1) and when the bus is not released (iicfn.iicbsyn bit = 1), this request is ignored and the iicfn.stcfn bit is set to 1. (13) stop condition generator this circuit generates a stop condition when the iiccn.sptn bit is set. (14) bus status detector this circuit detects whether the bus is released by detecting a start condition and stop condition. however, the bus status c annot be detected immediately after operation, so set the bus status detector to the initial status by using the iicfn.stcenn bit. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 951 of 1817 sep 19, 2011 20.3 mode switching of i 2 c bus and other serial interfaces 20.3.1 mode switching between i 2 c00, csif1, and uartc1 in the v850es/jh3-e and v850es/jj3-e, i 2 c00, csif1, and uartc1 share the same pin and therefore cannot be used simultaneously. switching between csif1, uartc1, and i 2 c00 must be set in advance, using the pmc2, pfc2, and pfce2 registers. caution the transmit/receive operation of i 2 c00, csif1, and uartc1 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 20-3. i 2 c00, csif1, and uartc1 mode switch settings pmc2 after reset: 00h r/w address: fffff444h pmc27 note pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 pmc20 pfc2 after reset: 00h r/w address: fffff464h pfc27 note pfc26 pfc25 pfc24 pfc23 pfc22 pfc21 pfc20 pfce27 note pfce26 pfce25 pfce24 pfce23 pfce22 pfce21 pfce20 pfce2 after reset: 00h r/w address: fffff704h port i/o mode sof1 (csif1) rxdc1 (uartc1) scl00 (i 2 c00) pmc24 0 1 1 1 operation mode pfce24 0 0 1 pfc24 0 1 0 port i/o mode sckf1 (csif1) pmc25 0 1 operation mode pfce25 0 pfc25 0 port i/o mode sif1 (csif1) txdc1 (uartc1) sda00 (i 2 c00) pmc23 0 1 1 1 operation mode pfce23 0 0 1 pfc23 0 1 0 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 952 of 1817 sep 19, 2011 20.3.2 mode switching between i 2 c01, csif0, and uartc3 in the v850es/jh3-e and v850es/jj3-e, i 2 c01, csif0, and uartc3 share the same pin and therefore cannot be used simultaneously. switching among i 2 c01, csif0, and uartc3 must be set in advance, using the pmc4, pfc4, and pfce4 registers. caution the transmit/receive operation of i 2 c01, csif0, and uartc3 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 20-4. i 2 c01, csif0, and uartc3 mode switch settings port i/o mode sif1 (csif0) txdc3 (uartc3) sda01 (i 2 c01) pmc40 0 1 1 1 operation mode pfce40 0 0 1 pfc40 0 1 0 port i/o mode sof0 (csif0) rxdc3 (uartc3) scl01 (i 2 c01) pmc41 0 1 1 1 operation mode pfce41 0 0 1 pfc41 0 1 0 port i/o mode sckf0 (csif0) pmc42 0 1 operation mode pfce42 0 pfc42 0 pmc4 (pmc4h) (pmc4l) (pfc4l) pmc47 note pmc46 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0 note 0 note 0 note 0 note 0 note 0 note 0 note pmc48 note 8 9 10 11 12 13 14 15 pfc4 (pfc4h) pfc4 fffff468h, pfc4l fffff468h, pfc4h fffff469h after reset: 0000h r/w address: 0 note 0 note 0 note 0 note 0 note 0 note 0 note pfc48 note pfc47 note pfc46 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 8 9 10 11 12 13 14 15 after reset: 0000h r/w address: pmc4 fffff448h, pmc4l fffff448h, pmc4h fffff449h pfce47 note pfce46 note pfce45 pfce44 pfce43 pfce42 pfce41 pfce40 pfce4 after reset: 00h r/w address: fffff708h remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 953 of 1817 sep 19, 2011 20.3.3 mode switching between i 2 c02, uartc2, and can0 in the v850es/jh3-e and v850es/jj3-e, i 2 c02, uartc2, and can0 ( pd70f3783 and 70f3786 only) share the same pin and therefore cannot be us ed simultaneously. switching among i 2 c02, uartc2, and can0 must be set in advance, using the pmc3, pfc3, and pfce3 registers. caution the transmit/receive operation of i 2 c02, uartc2, and can0 ( pd70f3783 and 70f3786 only) is not guaranteed if these functions are s witched during transmission or recep tion. be sure to disable the one that is not used. figure 20-5. i 2 c02, uartc2, and can0 mode switch settings pmc3 after reset: 00h r/w address: fffff446h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pfc3 after reset: 00h r/w address: fffff466h pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 pfce37 note pfce36 note pfce35 pfce34 pfce33 pfce32 pfce31 pfce30 pfce3 after reset: 00h r/w address: fffff706h port i/o mode txdc2 (uartc2) sda02 (i 2 c02) ctxd0 (can0) note pmc36 0 1 1 1 operation mode pfce36 note 0 0 1 pfc36 0 1 0 port i/o mode rxdc2 (uartc2) scl02 (i 2 c02) crxd0 (can0) note pmc37 0 1 1 1 operation mode pfce37 note 0 0 1 pfc37 0 1 0 remark = don?t care v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 954 of 1817 sep 19, 2011 20.3.4 mode switching between i 2 c03, csie1, and uartc5 in the v850es/jh3-e and v850es/jj3-e, i 2 c03, csie1, and uartc5 share the same pin and therefore cannot be used simultaneously. switching among i 2 c03, csie1, and uartc5 must be set in advance, using the pmc9, pfc9, and pfce9 registers. caution the transmit/receive operation of i 2 c03, csie1, and uartc5 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 20-6. i 2 c03, csie1, and uartc5 mode switch settings pmc9 (pmc9h) (pmc9l) (pfc9l) (pfce9l) after reset: 0000h r/w address: pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h) after reset: 0000h r/w address: pfce9 (pfce9h) after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 pfce913 0 pfce911 pfce910 pfce99 pfce98 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 port i/o mode soe1 (csie1) rxdc5 (uartc5) scl03 (i 2 c03) pmc910 0 1 1 1 operation mode pfce910 0 0 1 pfc910 0 1 0 port i/o mode sie1 (csie1) txdc5 (uartc5) sda03 (i 2 c03) pmc99 0 1 1 1 operation mode pfce99 0 0 1 pfc99 0 1 0 port i/o mode scke1 (csie1) pmc911 0 1 operation mode pfce911 0 pfc911 0 remark x = don?t care v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 955 of 1817 sep 19, 2011 20.4 registers i 2 c0n is controlled by the following registers. ? iic control register n (iiccn) ? iic status register n (iicsn) ? iic flag register n (iicfn) ? iic clock select register n (iiccln) ? iic function expansion register n (iicxn) ? iic division clock select regi ster 0 to 2 (ocks0 to ocks2) the following registers are also used. ? iic shift registers n (iicn) ? slave address registers n (svan) remark for the alternate-function pin settings, see table 4-18 settings when port pins are used for alternate functions . (1) iic control registers n (iiccn) the iiccn registers enable/stop i 2 c0n operations, set the wait timing, and set other i 2 c operations. these registers can be read or written in 8-bit or 1-bit units. howe ver, set the spien, wtimn, and acken bits when the iicen bit is 0 or during the wait period. when chan ging the iicen bit from ?0? to ?1?, these bits can also be set at the same time. reset sets these registers to 00h. v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 956 of 1817 sep 19, 2011 (1/4) after reset: 00h r/w address: iicc0 fffffd82h, iicc1 fffffd92h, iicc2 fffffda2h, iicc3 fffffdb2h, iicc4 fffffbc2h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn iicen specification of i 2 cn operation enable/disable 0 operation stopped. iicsn register reset note 1 . internal operation stopped. 1 operation enabled. be sure to set this bit to 1 when the scl0n and sda0n lines are high level. condition for clearing (iicen bit = 0) condition for setting (iicen bit = 1) ? cleared by instruction ? after reset ? set by instruction lreln note 2 exit from communications 0 normal operation 1 this exits from the current communication operat ion and sets standby mode. this setting is automatically cleared after being executed. its us es include cases in which a locally irrelevant extension code has been received. the scl0n and sda0n lines are set to high impedance. the sttn and sptn bits and the mstsn, excn, coin, trcn, ackdn, and stdn bits of the iicsn register are cleared. the standby mode following exit from communications remains in effect until the following communication entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match occurs or an extension code is received after the start condition. condition for clearing (lreln bit = 0) condition for setting (lreln bit = 1) ? automatically cleared after execution ? after reset ? set by instruction wreln note 2 wait state cancellation control 0 wait state not canceled 1 wait state canceled. this setting is automat ically cleared after wait state is canceled. condition for clearing (wreln bit = 0) condition for setting (wreln bit = 1) ? automatically cleared after execution ? after reset ? set by instruction notes 1. the iicsn register, iicfn.stcfn and iicfn.iicbsyn bits, and iiccln.cldn and iiccln.dadn bits are reset. 2. this flag?s signal is invalid when the iicen bit = 0. caution if the i 2 cn operation is enabled (iicen bit = 1) wh en the scl0n line is high level and the sda0n line is low level, the start condition is detected immediately. to avoid this, after enabling the i 2 cn operation, immediately set the lre ln bit to 1 with a bit manipulation instruction. remarks 1. the lreln and wreln bits are 0 when read after the data has been set. 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 957 of 1817 sep 19, 2011 (2/4) spien note enabling/disabling generation of interrupt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spien bit = 0) condition for setting (spien bit = 1) ? cleared by instruction ? after reset ? set by instruction wtimn note control of wait state and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and the wait state is set. slave mode: after input of eight cl ocks, the clock is set to low level and the wait state is set for the master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and the wait state is set. slave mode: after input of nine cl ocks, the clock is set to low level and the wait state is set for the master device. during address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. this bit setting becomes valid when the address transfer is completed. in master mode, a wait state is inserted at the falling edge of the ninth clock during address transfer. for a slave device that has received a local address, a wait state is inserted at the falling edge of the ninth clock afte r ack is generated. the slave device that has received an extension code, however, enters a wait state at the falling edge of the eighth clock. condition for clearing (wtimn bit = 0) condition for setting (wtimn bit = 1) ? cleared by instruction ? after reset ? set by instruction acken note acknowledgment control 0 acknowledgment disabled. 1 acknowledgment enabled. during t he ninth clock period, the sda0n line is set to low level. the acken bit setting is invalid for address reception by the slave device. in this case, ack is generated when the addresses match. however, the acken bit setting is valid for reception of t he extension code. set the acken bit in the system that receives the extension code. condition for clearing (acken bit = 0) condition for setting (acken bit = 1) ? cleared by instruction ? after reset ? set by instruction note this flag?s signal is invalid when the iicen bit = 0. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 958 of 1817 sep 19, 2011 (3/4) sttn start condition trigger 0 start condition is not generated. 1 when bus is released (in stop mode): a start condition is generated (for starting as master). the sda0n line is changed from high level to low level while the scln line is high level and then the start condition is generated. next, after the rated amount of time has elapsed, the scl0n line is changed to low level. during communication with a third party: if the communication reservation functi on is enabled (iicfn.iicrsvn bit = 0) ? this trigger functions as a start condition reserve flag. when set to 1, it releases the bus and then automatically generates a start condition. if the communication reservation function is disabled (iicrsvn = 1) ? the iicfn.stcfn bit is set to 1 and information se t (1) to the sttn bit is cleared. this trigger does not generate a start condition. in the wait state (when master device): a restart condition is generated after the wait state is released. cautions concerning set timing for master reception: cannot be set to 1 during tran sfer. can be set to 1 only when the acken bit has been set to 0 and the slave has been no tified of final reception. for master transmission: a start condi tion may not be generated normally during the ack period. set to 1 during the wait period that follows output of the ninth clock. for slave: even when the communication reservati on function is disabled (iicrsvn bit = 1), the communication reservation status is entered. ? setting to 1 at the same time as the sptn bit is prohibited. ? when the sttn bit is set to 1, setting the sttn bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (sttn bit = 0) condition for setting (sttn bit = 1) ? when the sttn bit is set to 1 in the communication reservation disabled status ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when the lreln bit = 1 (communication save) ? when the iicen bit = 0 (operation stop) ? after reset ? set by instruction remarks 1. the sttn bit is 0 if it is read immediately after data setting. 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 959 of 1817 sep 19, 2011 (4/4) sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda0n line goes to low level, either set the scl0n line to high level or wait until the scl0n pin goes to high level. next, after the rated amount of time has elapsed, the sda0n line is changed from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acken bit has been set to 0 and during the wait period after the slave has been noti fied of final reception. for master transmission: a stop condi tion may not be generated normally during the ack reception period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the sttn bit. ? the sptn bit can be set to 1 only when in master mode note . ? when the wtimn bit has been set to 0, if the sptn bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. the wtimn bit should be changed from 0 to 1 during t he wait period following output of eight clocks, and the sptn bit should be set to 1 during the wait period that follows output of the ninth clock. ? when the sptn bit is set to 1, setting the sptn bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (sptn bit = 0) condition for setting (sptn bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? cleared when the lreln bit = 1 (communication save) ? when the iicen bit = 0 (operation stop) ? after reset ? set by instruction note set the sptn bit to 1 only in master mode. howe ver, to perform a master operation before detecting the first stop condition after operation has been enabl ed when the iicrsvn bit is 0, the sptn bit must be set to 1 and a stop condition must be set. for details, see 20.15 cautions . caution if the wreln bit is set to 1 during the ni nth clock and the wait st ate is canceled when the trcn bit is 1, the trcn bit is cleared to 0 and the sda0n line is set to high impedance. remarks 1. the sptn bit is 0 if it is r ead immediately after data setting. 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 3 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 960 of 1817 sep 19, 2011 (2) iic status registers n (iicsn) the iicsn registers indicate the status of i 2 c0n. these registers are read-only, in 8-bit or 1-bit units. however, the iicsn registers can only be read when the iiccn.sttn bit is 1 or during the wait period. reset sets these registers to 00h. caution accessing the iicsn registers is prohibited in the fo llowing statuses. for details, see 3.4.8 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates on the subclock a nd the main clock oscillation is stopped ? when the cpu operates on the internal oscillation clock (1/3) after reset: 00h r address: iics0 fffffd86h, iics1 fffffd96h, iics2 fffffda6h, iics3 fffffdb6h, iics4 fffffbc6h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn mstsn master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (mstsn bit = 0) condition for setting (mstsn bit = 1) ? when a stop condition is detected ? when the aldn bit = 1 (arbitration loss) ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a start condition is generated aldn arbitration loss detection 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the mstsn bit is cleared to 0. condition for clearing (aldn bit = 0) condition for setting (aldn bit = 1) ? automatically cleared after the iicsn register is read note ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the arbitration result is a ?loss?. excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn bit = 0) condition for setting (excn bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the higher four bits of the received address data are either ?0000? or ?1111? (set at the rising edge of the eighth clock). note this bit is also cleared when a bit manipulation in struction is executed for another bit in the iicsn register. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 961 of 1817 sep 19, 2011 (2/3) coin matching address detection 0 addresses do not match. 1 addresses match. condition for clearing (coin bit = 0) condition for setting (coin bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when the received address matches the local address (svan register) (set at the rising edge of the eighth clock). trcn transmit/receive status detection 0 receive status (other than transmit status). the sda0n line is set to high impedance. 1 transmit status. the value in the so latch is enabled for output to the sda0n line (valid starting at the falling edge of the first byte?s ninth clock). condition for clearing (trcn bit = 0) condition for setting (trcn bit = 1) ? when a stop condition is detected ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? cleared by iiccn.wreln bit = 1 note ? when the aldn bit changes from 0 to 1 (arbitration loss) ? after reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated ? when ?0? is output to the first byte?s lsb (transfer direction specification bit) slave ? when ?1? is input by the first byte?s lsb (transfer direction specification bit) ackdn ack detection 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn bit = 0) condition for setting (ackd bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? after the sda0n bit is set to low level at the rising edge of the scl0n pin?s ninth clock note the trcn bit is cleared to 0 and sda0n line becomes high impedance when the wreln bit is set to 1 and the wait state is canceled to 0 at the ninth clock by trcn bit = 1. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 962 of 1817 sep 19, 2011 (3/3) stdn start condition detection 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn bit = 0) condition for setting (stdn bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by lreln bit = 1 (communication save) ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a start condition is detected spdn stop condition detection 0 stop condition was not detected. 1 stop condition was detected. the master device ?s communication is terminated and the bus is released. condition for clearing (spdn bit = 0) condition for setting (spdn bit = 1) ? at the rising edge of the address transfer byte?s first clock following setting of th is bit and detection of a start condition ? when the iicen bit changes from 1 to 0 (operation stop) ? after reset ? when a stop condition is detected remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 963 of 1817 sep 19, 2011 (3) iic flag regi sters n (iicfn) the iicfn registers set the i 2 c0n operation mode and indicate the i 2 c bus status. these registers can be read or written in 8-bit or 1-bit units. however, the stcfn and iicbsyn bits are read-only. iicrsvn enables/disables the comm unication reservation function (see 20.14 communication reservation ). the initial value of the iicbsyn bit is set by using the stcenn bit (see 20.15 cautions ). the iicrsvn and stcenn bits can be written only when operation of i 2 c0n is disabled (iiccn.iicen bit = 0). after operation is enabled, iicfn can be read. reset sets these registers to 00h. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 964 of 1817 sep 19, 2011 after reset: 00h r/w note address: iicf0 fffffd8ah, iicf1 fffffd9ah, iicf2 fffffdaah, iicf3 fffffdbah, iicf4 fffffbcah <7> <6> 5 4 3 2 <1> <0> iicfn stcfn iicbsyn 0 0 0 0 stcenn iicrsvn stcfn sttn bit clear 0 start condition issued 1 start condition cannot be is sued, sttn bit cleared condition for clearing (stcfn bit = 0) condition for setting (stcfn bit = 1) ? cleared by iiccn.sttn bit = 1 ? when the iiccn.iicen bit = 0 ? after reset ? when start condition is not issued and sttn flag is cleared to 0 when communication reservation is disabled (iicrsvn bit = 1). iicbsyn i 2 c0n bus status 0 bus release status (default communication status when stcenn bit = 1) 1 bus communication status (default comm unication status when stcenn bit = 0) condition for clearing (iicbsyn bit = 0) condition for setting (iicbsyn bit = 1) ? when stop condition is detected ? when the iicen bit = 0 ? after reset ? when start condition is detected ? by setting the iicen bit when the stcenn bit = 0 stcenn initial start enable trigger 0 start conditions cannot be generated until a st op condition is detected following operation enable (iicen bit = 1). 1 start conditions can be generated even if a stop condition is not detected following operation enable (iicen bit = 1). condition for clearing (stcenn bit = 0) condition for setting (stcenn bit = 1) ? when start condition is detected ? after reset ? setting by instruction iicrsvn communication reservation function disable bit 0 communication reservation enabled 1 communication reservation disabled condition for clearing (iicrsvn bit = 0) condition for setting (iicrsvn bit = 1) ? clearing by instruction ? after reset ? setting by instruction note bits 6 and 7 are read-only bits. cautions 1. write the stcenn bit only wh en operation is stopped (iicen bit = 0). 2. when the stcenn bit = 1, the bus rele ased status (iicbsyn bit = 0) is recognized regardless of the actual bus status immediately after the i 2 cn bus operation is enabled. therefore, to issue the first start condition (s ttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. 3. write the iicrsvn bit only when operation is stopped (iicen bit = 0). remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 965 of 1817 sep 19, 2011 (4) iic clock select registers n (iiccln) the iiccln registers set the transfer clock for i 2 c0n. these registers can be read or written in 8-bit or 1-bit un its. however, the cldn and dadn bits are read-only. set the iiccln registers when the iiccn.iicen bit = 0. the smcn, cln1, and cln0 bits are set by combin ing the iicxn.clxn bit and the ocksthm, ocksm1, and ocksm0 bits of the ocksm register (see 20.4 (6) i 2 c0n transfer clock setting method ) (m = 0 to 2). reset sets these registers to 00h. after reset: 00h r/w note address: iiccl0 fffffd84h, iiccl1 fffffd94h, iiccl2 fffffda4h, iiccl3 fffffdb4h, iiccl4 fffffbc4h 7 6 <5> <4> 3 2 1 0 iiccln 0 0 cldn dadn smcn dfcn cln1 cln0 cldn detection of scl0n pin level (valid only when iiccn.iicen bit = 1) 0 the scl0n pin was detected at low level. 1 the scl0n pin was detected at high level. condition for clearing (cldn bit = 0) condition for setting (cldn bit = 1) ? when the scl0n pin is at low level ? when the iicen bit = 0 (operation stop) ? after reset ? when the scl0n pin is at high level dadn detection of sda0n pin level (valid only when iicen bit = 1) 0 the sda0n pin was detected at low level. 1 the sda0n pin was detected at high level. condition for clearing (dadn bit = 0) condition for setting (dad0n bit = 1) ? when the sda0n pin is at low level ? when the iicen bit = 0 (operation stop) ? after reset ? when the sda0n pin is at high level smcn operation mode switching 0 operation in standard mode. 1 operation in high-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. the digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary according to the dfcn bit setting (on/off). the digital filter is used to e liminate noise in high-speed mode. note bits 4 and 5 are read-only bits. caution be sure to clear bits 7 and 6 to ?0?. remarks 1. when the iiccn.iicen bit = 0, 0 is read when reading the cldn and dadn bits. 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 966 of 1817 sep 19, 2011 (5) iic function expansi on registers n (iicxn) the iicxn registers set i 2 c0n function expansion (valid only in the high-speed mode). these registers can be read or wri tten in 8-bit or 1-bit units. setting of the clxn bit is performed in combination with the smcn, cln1, and cln0 bits of the iiccln register and the ocksthm, ocksm1, and ocksm0 bi ts of the ocksm register (see 20.4 (6) i 2 c0n transfer clock setting method ) (m = 0 to 2). set the iicxn registers when the iiccn.iicen bit = 0. reset sets these registers to 00h. iicxn after reset: 00h r/w address: iicx0 fffffd85h, iicx1 fffffd95h, iicx2 fffffda5h, iicx3 fffffdb5h, iicx4 fffffbc5h 0 0 0 0 0 0 0 clxn < > remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) (6) i 2 c0n transfer clock setting method the i 2 c0n transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 72, 88, 96, 108, 120, 144, 192, 240, 264, 344, 352, 396, 440, 516, 688, 860 (see table 20-2 clock settings ). t: 1/f xx t r : scl0n pin rise time t f : scl0n pin fall time for example, the i 2 c0n transfer clock frequency (f scl ) when f xx = 24 mhz, m = 264, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(264 41.7 ns + 200 ns + 50 ns) ? 88.9 khz m t + t r + t f m/2 t t f t r m/2 t scl0n scl0n inversion scl0n inversion scl0n inversion the clock to be selected can be set by combining of t he smcn, cln1, and cln0 bits of the iiccln register, the clxn bit of the iicxn register, and the ocksthm, ocks m1, and ocksm0 bits of the ocksm register (m = 0 to 2). v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 967 of 1817 sep 19, 2011 table 20-2. clock settings iicxn iiccln clxn smcn cln1 cln0 selection clock transfer clock settable main clock frequency (f xx ) range transfer speed operating mode fxx/6 (ocks0 = 11h) fxx/264 24.00 mhz fxx 25.14 mhz 90.91 khz to 95.23 khz fxx/8 (ocks0 = 12h) fxx/352 24.00 mhz fxx 33.52 mhz 68.18 khz to 95.23 khz fxx/10 (ocks0 = 13h) fxx/440 30.00 mhz fxx 41.90 mhz 68.18 khz to 95.23 khz 0 0 0 0 fxx/2 (ocks0 = 18h) fxx/88 4.00 mhz fxx 6.25 mhz 45.45 khz to 71.02 khz fxx/4 (ocksm = 10h) fxx/344 24.00 mhz fxx 33.52 mhz 69.77 khz to 97.44 khz fxx/6 (ocksm = 11h) fxx/516 25.14 mhz fxx 50.00 mhz 48.72 khz to 96.90 khz fxx/8 (ocksm = 12h) fxx/688 33.52 mhz fxx 50.00 mhz 48.72 khz to 72.67 khz 0 0 0 1 fxx/10 (ocksm = 13h) fxx/860 41.90 mhz fxx 50.00 mhz 48.72 khz to 58.14 khz fxx/4 (ocksm = 10h) fxx/264 25.60 mhz 96.97 khz 0 0 1 1 fxx/6 (ocksm = 11h) fxx/396 38.40 mhz 96.97 khz standard mode (smcn = 0) fxx/4 (ocksm = 10h) fxx/96 24.00 mhz fxx 33.52 mhz 250.00 khz to 349.17 khz fxx/6 (ocksm = 11h) fxx/144 24.00 mhz fxx 50.00 mhz 166.67 khz to 347.22 khz fxx/8 (ocksm = 12h) fxx/192 32.00 mhz fxx 50.00 mhz 166.67 khz to 260.42 khz 0 1 0 x fxx/10 (ocksm = 13h) fxx/240 40.00 mhz fxx 50.00 mhz 166.67 khz to 208.33 khz fxx/4 (ocksm = 10h) fxx/72 25.60 mhz 355.56 khz 0 1 1 1 fxx/6 (ocksm = 11h) fxx/108 38.40 mhz 355.56 khz fxx/6 (ocksm = 11h) fxx/72 24.00 mhz fxx 25.14 mhz 333.33 khz to 349.17 khz fxx/8 (ocksm = 12h) fxx/96 32.00 mhz fxx 33.52 mhz 333.33 khz to 349.17 khz 1 1 0 x fxx/10 (ocksm = 13h) fxx/120 40.00 mhz fxx 41.90 mhz 333.33 khz to 349.17 khz high-speed mode (smcn = 1) other than above setting prohibited ? ? ? ? remarks 1. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) m = 0 to 2 2. : don?t care v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 968 of 1817 sep 19, 2011 (7) iic division clock select regi sters 0 to 2 (ocks0 to ocks2) the ocksm registers control the i 2 c0n division clock. these registers control the i 2 c00 division clock via the ocks0 register, the i 2 c01 and i 2 c02 division clocks via the ocks1 register, and the i 2 c03 and i 2 c04 division clocks via the ocks2 register. these registers can be read or written in 8-bit units. reset sets these registers to 00h. 0 ocksm (m = 0 to 2) 00 ocksenm ocksthm 0 ocksm1 ocksm0 after reset: 00h r/w address: ocks0 fffff340h, ocks1 fffff344h, ocks2 fffff348h stops i 2 cn division clock operation enables i 2 cn division clock operation ocksenm 0 1 operation setting of i 2 cn division clock ocksm1 0 0 1 1 0 ocksm0 0 1 0 1 0 selection of i 2 cn division clock f xx /4 f xx /6 f xx /8 f xx /10 f xx /2 ocksthm 0 0 0 0 1 remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) (8) iic shift registers n (iicn) the iicn registers are used for serial transmission/recepti on (shift operations) synchronized with the serial clock. these registers can be read or written in 8-bit units, but data should not be written to the iicn registers during a data transfer. access (read/write) the iicn registers only during the wait period. accessi ng these registers in communication states other than the wa it period is prohibited. however, for the ma ster device, the iicn registers can be written once only after the transmission trigger bit (iiccn.sttn bit) has been set to 1. a wait state is released by writing the iicn registers during the wait pe riod, and data transfer is started. reset sets these registers to 00h. after reset: 00h r/w address: iic0 fffffd80h, iic1 fffffd90h, iic2 fffffda0h, iic3 fffffdb0h, iic4 fffffbc0h 7 6 5 4 3 2 1 0 iicn remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 969 of 1817 sep 19, 2011 (9) slave address registers n (svas) the svan registers hold the i 2 c bus?s slave address. these registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. however, rewriting these registers is prohibited when the iicsn.stdn bit = 1 (start condition detection). reset sets these registers to 00h. after reset: 00h r/w address: sva0 ffff fd83h, sva1 fffffd93h , sva2 fffffda3h, sva3 fffffdb3h , sva4 fffffbc3h 7 6 5 4 3 2 1 0 svan 0 remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 970 of 1817 sep 19, 2011 20.5 i 2 c bus mode functions 20.5.1 pin configuration the serial clock pin (scl0n) and serial data bus pin (sda0n) are configured as follows. scl0n .................this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. sda0n ................this pin is used for serial data input and output. this pin is an n-ch open-drain output for both ma ster and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull-up resistor is required. figure 20-7. pin configuration diagram v dd scl0n sda0n scl0n sda0n v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 971 of 1817 sep 19, 2011 20.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ?start condition?, ?address?, ?tr ansfer direction specification? , ?data?, and ?stop condition? generated on the i 2 c bus?s serial data bus is shown below. figure 20-8. i 2 c bus serial data transfer timing 1 to 7 8 9 1 to 8 9 1 to 8 9 scl0n sda0n r/w start condition address ack data data stop condition ack ack the master device generates the start c ondition, slave address, and stop condition. ack can be generated by either the master or slave device (normally, it is gener ated by the device that receives 8-bit data). the serial clock (scl0n) is continuously output by the master devic e. however, in the sl ave device, the scl0n pin?s low-level period can be extended and a wa it state can be inserted (n = 0 to 2). remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 972 of 1817 sep 19, 2011 20.6.1 start condition a start condition is met when the scl0n pin is high level and t he sda0n pin changes from high level to low level. the start condition for the scl0n and sda0n pins is a signal that t he master device outputs to the slave device when starting a serial transfer. the slave device can detect the start condition. figure 20-9. start condition h scl0n sda0n a start condition is output when the iiccn.sttn bit is set (1) after a stop condition has been detected (iicsn.spdn bit = 1). when a start condition is detected, the iicsn.stdn bit is set (1). caution when the iiccn.iicen bit of the v850es/jh3-e and v850es/jj3-e is set to 1 while other devices are communicating, the start condition may be detected depending on the status of the communication line. be sure to set the iiccn.iicen bit to 1 when the scl0n and sda0n lines are high level. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 973 of 1817 sep 19, 2011 20.6.2 addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output so that the master device can select one of the slave devices that are connected to the bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices detect via hardware t he start condition and check whether or not the 7-bit address data matches the data values stored in the svan register. if the address data matc hes the values of the svan register, the slave device is selected and communicates with the master device until the mast er device generates a start condition or stop condition. figure 20-10. address address scl0n 1 sda0n intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (intiicn) is generate d if a local address or extension code is received during slave device operation. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) an address is output when the slave addre ss and the transfer direction described in 20.6.3 transfer direction specification are written together to the iicn r egisters as eight bits of data. rece ived addresses are written to the iicn register. the slave address is assigned to the higher 7 bits of the iicn register. v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 974 of 1817 sep 19, 2011 20.6.3 transfer direction specification in addition to the 7-bit address data, the master device send s 1 bit of data that specifie s the transfer direction. when this transfer direction specification bi t has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 20-11. transfer direction specification scl0n 1 sda0n intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the intiicn signal is generated if a local address or extension code is received during slave device operation. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 975 of 1817 sep 19, 2011 20.6.4 ack ack is used to confirm the serial data stat us of the transmitting and receiving devices. the receiving device returns ack for every 8 bits of data it receives. the transmitting device normally receives ack after transmi tting 8 bits of data. when ack is returned from the receiving device, the reception is judged as normal and proc essing continues. the detecti on of ack is confirmed using the iicsn.ackdn bit. when the master device is the receiving device, after receiv ing the final data, it does not return ack and generates a stop condition. when the slave device is the receiving device and does not return ack, the master device generates either a stop condition or a restart condi tion, and then stops the current transmission. failure to return ack may be caused by the following factors. (a) reception was not performed normally. (b) the final data was received. (c) the receiving device (slave) does not exist at the specified address. when the receiving device sets the sda0n line to low level during the ninth clock, ack is generated (normal reception). when the iiccn.acken bit is set to 1, automatic ack generati on is enabled. transmission of the eighth bit following the 7 address data bits causes the iicsn.trcn bit to be set. no rmally, set the acken bit to 1 for reception (trcn bit = 0). when the slave device is receiving (when trcn bit = 0), if the slave device cannot rece ive data or does not need the subsequent data, clear the acken bit to 0 to indica te to the master that no more data can be received. similarly, when the master device is receiving (when t rcn bit = 0) and the subsequent data is not needed, clear the acken bit to 0 to prevent ack from being generated. this not ifies the slave device (transmi tting device) of the end of the data transmission (transmission stopped). figure 20-12. ack scl0n 1 sda0n 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) when the local address is received, ack is automatically generated regardless of the value of the acken bit. no ack is generated if an address other than t he local address is received (nack). when receiving the extension code, set the ac ken bit to 1 in advance to generate ack. the ack generation method during data reception is based on the wait timing setting, as described by the following. ? when 8-clock wait is selected (iiccn.wtimn bit = 0): ack is generated in synchronization with the falling edge of the scl0n pin?s eighth clock if the acken bit is set to 1 before wait state cancellation. ? when 9-clock wait is selected (iiccn.wtimn bit = 1): ack is generated if the acken bit is set to 1 in advance. v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 976 of 1817 sep 19, 2011 20.6.5 stop condition when the scl0n pin is high level, changing the sda0n pin from low level to high level generates a stop condition. a stop condition is generated when serial transfer from the ma ster device to the slave device has been completed. when the v850es/jh3-e or v850es/jj3-e is used as t he slave device, it can detect the stop condition. figure 20-13. stop condition h scl0n sda0n remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) a stop condition is generated when the iiccn.sptn bit is set to 1. when the stop condition is detected, the iicsn.spdn bit is set to 1 and the interrupt request signal (int iicn) is generated when the iiccn.spien bit is set to 1. v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 977 of 1817 sep 19, 2011 20.6.6 wait state a wait state is used to notify the commun ication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0n pin to low level notifies the communication par tner of the wait state. when the wait state has been canceled for both the master and slave devi ces, the next data transfer can begin. figure 20-14. wait state (1/2) (a) when master device is in a nine-clock wait st ate and slave device is in an eight-clock wait state (master: transmission, slave: r eception, and iiccn.acken bit = 1) scl0n 6 sda0n 78 9 123 scl0n iicn 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iicn scl0n acken master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iicn data write (cancel wait state) slave wait after output of eighth clock. ffh is written to iicn register or iiccn.wreln bit is set to 1. transfer lines wait state from slave wait state from master remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 978 of 1817 sep 19, 2011 figure 20-14. wait state (2/2) (b) when master and slave devices are both in a nine-clock wait state (master: transmission, slave: reception, and acken bit = 1) scl0n 6 sda0n 789 123 scl0n iicn 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iicn scl0n acken master master and slave both wait after output of ninth clock. iicn data write (cancel wait state) slave ffh is written to iicn register or wreln bit is set to 1. generate according to previously set acken bit value transfer lines wait state from master/ slave wait state from slave remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) a wait state may be automatically generated depending on the setting of the iiccn.wtimn bit. normally, the receiving side cancels the wait state when the iiccn.wreln bit is se t to 1 or when ffh is written to the iicn register and the transmitting side cancels the wa it state when data is written to the iicn register. the master device can also cancel the wait state via either of the following methods. ? by setting the iiccn.sttn bit to 1 ? by setting the iiccn.sptn bit to 1 v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 979 of 1817 sep 19, 2011 20.6.7 wait state cancellation method in the case of i 2 c0n, a wait state can be canceled normally in the following ways. ? by writing data to the iicn register ? by setting the iiccn.wreln bit to 1 (wait state cancellation) ? by setting the iiccn.sttn bit to 1 (start condition generation) ? by setting the iiccn.sptn bit to 1 (stop condition generation) if any of these wait state cancellation actions is performed, i 2 c0n will cancel the wait state and restart communication. when canceling the wait state and sending data (inc luding address), write data to the iicn register. to receive data after canceling the wait state, or to complete data transmission, set the wreln bit to 1. to generate a restart condition after cancelin g the wait state, set the sttn bit to 1. to generate a stop condition after canceling the wait state, set the sptn bit to 1. execute cancellation only once for each wait state. for example, if data is written to the iicn register followin g wait state cancellation by setting the wreln bit to 1, a conflict between the sda0n line change ti ming and iicn register write timing may re sult in the data output to sda0n being an incorrect value. even in other operations, if communicati on is stopped halfway, clearing the iiccn .iicen bit to 0 will stop communication, enabling the wait state to be cancelled. if the i 2 c bus dead-locks due to noise, etc., setting the iiccn.lreln bit to 1 causes the communication operation to be exited, enabling the wait state to be cancelled. v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 980 of 1817 sep 19, 2011 20.7 i 2 c interrupt request signals (intiicn) the following shows the value of the iicsn register at the intiicn interrupt r equest signal generation timing and at the intiicn signal timing. 20.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iiccn.wtimn bit = 0 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b s 3: iicsn register = 1000x000b (wtimn bit = 1) s 4: iicsn register = 1000xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x100b s 3: iicsn register = 1000xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 981 of 1817 sep 19, 2011 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtimn bit = 0 sttn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 1000x110b (wtimn bit = 0) s 5: iicsn register = 1000x000b (wtimn bit = 1) s 6: iicsn register = 1000xx00b 7: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 sttn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 1000x110b s 4: iicsn register = 1000xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 982 of 1817 sep 19, 2011 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1010x110b s 2: iicsn register = 1010x000b s 3: iicsn register = 1010x000b (wtimn bit = 1) s 4: iicsn register = 1010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1010x110b s 2: iicsn register = 1010x100b s 3: iicsn register = 1010xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 983 of 1817 sep 19, 2011 20.7.2 slave device operation (when receiving slave address data (address match)) (1) start ~ address ~ data ~ data ~ stop <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x100b s 3: iicsn register = 0001xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 984 of 1817 sep 19, 2011 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (afte r restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 (afte r restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 985 of 1817 sep 19, 2011 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after rest art, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 (after rest art, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x110b s 5: iicsn register = 0010xx00b 6: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 986 of 1817 sep 19, 2011 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, a ddress mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001x000b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 (after restart, a ddress mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0001x110b s 2: iicsn register = 0001xx00b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 987 of 1817 sep 19, 2011 20.7.3 slave device operation (w hen receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010x100b s 4: iicsn register = 0010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 988 of 1817 sep 19, 2011 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtimn bit = 0 (afte r restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0001x110b s 4: iicsn register = 0001x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 (afte r restart, address match) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 6 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 0001x110b s 5: iicsn register = 0001xx00b 6: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 989 of 1817 sep 19, 2011 (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtimn bit = 0 (after rest art, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x010b s 4: iicsn register = 0010x000b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 (after rest art, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 s 5 s 6 7 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 0010x010b s 5: iicsn register = 0010x110b s 6: iicsn register = 0010xx00b 7: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 990 of 1817 sep 19, 2011 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, a ddress mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x000b s 3: iicsn register = 00000x10b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 (after restart, a ddress mismatch (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0010x010b s 2: iicsn register = 0010x110b s 3: iicsn register = 0010xx00b s 4: iicsn register = 00000x10b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) 20.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 1: iicsn register = 00000001b remarks 1. : generated only when spien bit = 1 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 991 of 1817 sep 19, 2011 20.7.5 arbitration loss operation (opera tion as slave after arbitration loss) (1) when arbitration loss occurs during transmission of slave address data <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0101x110b (example: when iicsn .aldn bit is read during interrupt servicing) s 2: iicsn register = 0001x000b s 3: iicsn register = 0001x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0101x110b (example: when aldn bit is read during interrupt servicing) s 2: iicsn register = 0001x100b s 3: iicsn register = 0001xx00b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 992 of 1817 sep 19, 2011 (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) s 2: iicsn register = 0010x000b s 3: iicsn register = 0010x000b 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) s 2: iicsn register = 0010x110b s 3: iicsn register = 0010x100b s 4: iicsn register = 0010xx00b 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 993 of 1817 sep 19, 2011 20.7.6 operation when arbitrat ion loss occurs (no communicat ion after arbitration loss) (1) when arbitration loss occurs durin g transmission of slave address data st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iicsn register = 01000110b (example: when iicsn .aldn bit is read during interrupt servicing) 2: iicsn register = 00000001b remarks 1. s : always generated : generated only when iiccn.spien bit = 1 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 2 s 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software 2: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 994 of 1817 sep 19, 2011 (3) when arbitration loss o ccurs during data transfer <1> when iiccn.wtimn bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 10001110b s 2: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 10001110b s 2: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 995 of 1817 sep 19, 2011 (4) when arbitration loss occurs due to restart condition during data transfer <1> not extension code (example: address mismatch) st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 01000110b (example: when aldn bit is read during interrupt servicing) 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> extension code st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn.lreln bit is set to 1 by software 3: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. dn = d6 to d0 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 996 of 1817 sep 19, 2011 (5) when arbitration loss occurs due to stop condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp s 1 2 s 1: iicsn register = 1000x110b 2: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 997 of 1817 sep 19, 2011 (6) when arbitration loss occurs due to low level of sda0n pin when attempti ng to generate a restart condition <1> when wtimn bit = 0 iiccn.sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 iiccn.sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 998 of 1817 sep 19, 2011 (7) when arbitration loss occurs due to a stop conditio n when attempting to gene rate a restart condition <1> when wtimn bit = 0 sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b 4: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 sttn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp s 1 s 2 3 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b 3: iicsn register = 01000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 999 of 1817 sep 19, 2011 (8) when arbitration loss occurs due to low level of sda0n pin when atte mpting to generate a stop condition <1> when wtimn bit = 0 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 s 4 5 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000x000b (wtimn bit = 1) s 3: iicsn register = 1000xx00b (wtimn bit = 0) s 4: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 5: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) <2> when wtimn bit = 1 iiccn.sptn bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp s 1 s 2 s 3 4 s 1: iicsn register = 1000x110b s 2: iicsn register = 1000xx00b s 3: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) 4: iicsn register = 00000001b remarks 1. s : always generated : generated only when spien bit = 1 x: don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1000 of 1817 sep 19, 2011 20.8 interrupt request signal (intiicn) generation timing and wait control the setting of the iiccn.wtimn bit det ermines the timing by which the in tiicn register is generated and the corresponding wait control, as shown below (n = 0 to 2). table 20-3. intiicn generation timing and wait control during slave device operation du ring master device operation wtimn bit address data reception data transmission a ddress data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiicn signal and wait period o ccur at the falling edge of the ninth clock only when there is a match with the addr ess set to the svan register. at this point, the ack is generated regardless of the value set to the iiccn.acken bit. for a slave device that has received an extension code, the intiicn signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the in tiicn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not ma tch the contents of the svan regist er and an extension code is not received, neither the intiicn signal nor a wait occurs. remarks 1. the numbers in the table indicate the number of t he serial clock?s clock signals. interrupt requests and wait control are both synchronized with t he falling edge of these clock signals. 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined according to the conditions described in notes 1 and 2 above, regardless of the wtimn bit. ? master device operation: interrupt and wait timing occu r at the falling edge of the ni nth clock regardless of the wtimn bit. (2) during data reception ? master/slave device operation: interrupt and wa it timing are determined according to the wtimn bit. (3) during data transmission ? master/slave device operation: interrupt and wa it timing are determined according to the wtimn bit. v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1001 of 1817 sep 19, 2011 (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting the iiccn.wreln bit to 1 ? by writing to the iicn register ? by start condition setting (iiccn.sttn bit = 1) note ? by stop condition setting (iiccn.sptn bit = 1) note note master only when an 8-clock wait has been selected (wtimn bit = 0), whether or not ack has been generated must be determined prior to wait cancellation. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) (5) stop condition detection the intiicn signal is generated wh en a stop condition is detected. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1002 of 1817 sep 19, 2011 20.9 address match detection method in i 2 c bus mode, the master device can select a particular sl ave device by transmitting the corresponding slave address. address match detection is performed automatically by hard ware. the intiicn signal occurs when a local address has been set to the svan register and when the address set to the svan register matches the slave address sent by the master device, or when an extension code has been received. 20.10 error detection in i 2 c bus mode, the status of t he serial data bus pin (sda0n) during data trans mission is captured by the iicn register of the transmitting device, so the data of the iicn register prior to transmission can be compared with the transmitted iicn data to enable detection of transmission errors. a transmissi on error is judged as having occurred when the compared data values do not match. 20.11 extension code (1) when the higher 4 bits of the rece ive address are either 0000 or 1111, the extension code flag (iicsn.excn bit) is set for extension code reception and an interrupt request signal (intiicn) is issued at the falling edge of the eighth clock. the local address stored in the svan register is not affected. (2) if 11110xx0 is set to the svan register by a 10-bit addres s transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the int iicn signal occurs at the falling edge of the eighth clock. ? higher four bits of data match: excn bit = 1 ? seven bits of data match: iicsn.coin bit = 1 (3) since the processing after the interrupt request signal occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slav e is not desired after the extension code is received, set the iiccn.lreln bit to 1 and the cpu will enter the next communication wait state. table 20-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 1111 0xx 0 10-bit slave address specif ication (when the address is authorized) 1111 0xx 1 10-bit slave address specific ation (after the address match, the read command is issued) remarks 1. for the expansion codes other than the above, see i 2 c bus specifications issued by nxp. 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1003 of 1817 sep 19, 2011 20.12 arbitration when several master devices simultaneously generate a start condition (when the iiccn.sttn bit is set to 1 before the iicsn.stdn bit is set to 1), communicati on between the master devices is perfo rmed while the number of clocks is adjusted until the data differs. this kind of operation is called arbitration (n = 0 to 2). when one of the master devices loses in arbi tration, an arbitration loss flag (iicsn.ald n bit) is set to 1 via the timing at which the arbitration loss occurred, and the scl0n and sda0n lines are both set to high impedance, which releases the bus (n = 0 to 2). arbitration loss is detected ba sed on the timing of the next interrupt request signal (intiicn) (the eighth or ninth clock, when a stop condition is detected, etc.) and the setting of the aldn bit to 1, which is made by software (n = 0 to 2). for details of interrupt request timing, see 20.7 i 2 c interrupt request signals (intiicn) . figure 20-15. arbitration timing example master 1 master 2 transfer lines scl0n sda0n scl0n sda0n scl0n sda0n master 1 loses arbitration hi-z hi-z remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1004 of 1817 sep 19, 2011 table 20-5. status during arbitration an d interrupt request signal generation timing status during arbitration inte rrupt request generation timing transmitting address transmission read/write data after address transmission transmitting extension code read/write data after extension code transmission transmitting data ack transfer period after data reception when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transfer w hen stop condition is generated (when iiccn.spien bit = 1) note 2 when sda0n pin is low level while attempting to generate restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate restart condition when stop condition is generated (when iiccn.spien bit = 1) note 2 when dsa0n pin is low level while attempting to generate stop condition when scl0n pin is low level while attempting to generate restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iiccn.wtimn bit = 1, an intiicn signal occurs at the falling edge of the ninth clock. when the wtimn bit = 0 and the extension code?s slave address is received, an intiicn signal occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spien bit to 1 for master device operation (n = 0 to 2). 20.13 wakeup function the makeup function is a function t hat generates an interrupt request signal (intiicn) when a local address or extension code has been received by using the slave function of the i 2 c bus. this function makes processing more efficient by preventing unnecessary intiicn signa ls from occurring when addresses do not match. when a start condition is detected, wakeup standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may chang e the master device (which generated the start condition) to a slave device. however, when a stop condition is detected, the iiccn.spien bit is set regardless of the wakeup function, and this determines whether intiicn signal is enabled or disabled. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1005 of 1817 sep 19, 2011 20.14 communication reservation 20.14.1 when communication reservation functi on is enabled (iicfn.iicrsvn bit = 0) to start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is releas ed. there are two modes in which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iiccn.lreln bit was set to 1) (n = 0 to 2). if the iiccn.sttn bit is set to 1 while the bus is not being us ed, a start condition is automat ically generated and a wait status is set after the bus is released (after the stop condition is detected). when the bus release is detected (when t he stop condition is detected), writing to the iicn register causes master address transfer to start. at this point, the ii ccn.spien bit should be set to 1 (n = 0 to 2). when sttn has been set to 1, the operation mode (as start c ondition or as communication reservation) is determined according to the bus status (n = 0 to 2). if the bus has been re leased .............................................a start condition is generated if the bus has not been released (stand by mode).............. communication reservation to detect which operation mode has been determined, set the s ttn bit to 1, wait for the wait period, then check the iicsn.mstsn bit (n = 0 to 2). the wait periods, which should be set via software, are listed in table 20-6. these wait periods can be set by the smcn, cln1, and cln0 bits of the iiccln register and the iicxn.clxn bit (n = 0 to 2). remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1006 of 1817 sep 19, 2011 table 20-6. wait periods clock selection clxn smcn cln1 cln0 wait period f xx /6 (ocksm = 11h) 0 0 0 0 156 clocks f xx /8 (ocksm = 12h) 0 0 0 0 208 clocks f xx /10 (ocksm = 13h) 0 0 0 0 260 clocks f xx /4 (ocksm = 10h) 0 0 0 1 188 clocks f xx /6 (ocksm = 11h) 0 0 0 1 282 clocks f xx /8 (ocksm = 12h) 0 0 0 1 376 clocks f xx /10 (ocksm = 13h) 0 0 0 1 470 clocks f xx /4 (ocksm = 10h) 0 0 1 1 148 clocks f xx /6 (ocksm = 11h) 0 0 1 1 222 clocks f xx /4 (ocksm = 10h) 0 1 0 64 clocks f xx /6 (ocksm = 11h) 0 1 0 96 clocks f xx /8 (ocksm = 12h) 0 1 0 128 clocks f xx /10 (ocksm = 13h) 0 1 0 160 clocks f xx /4 (ocksm = 10h) 0 1 1 1 52 clocks f xx /6 (ocksm = 11h) 0 1 1 1 78 clocks f xx /6 (ocksm = 11h) 1 1 0 60 clocks f xx /8 (ocksm = 12h) 1 1 0 80 clocks f xx /10 (ocksm = 13h) 1 1 0 100 clocks remarks 1. m = 0 to 2 n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) 2. = don?t care the communication reservation timing is shown below. v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1007 of 1817 sep 19, 2011 figure 20-16. communication reservation timing 2 1 3456 2 1 3456 789 scl0n sda0n program processing hardware processing write to iicn set spdn and intiicn sttn =1 communication reservation set stdn generated by master with bus access remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) sttn: bit of iiccn register stdn: bit of iicsn register spdn: bit of iicsn register communication reservations are accepted via the followin g timing. after the iicsn.stdn bit is set to 1, a communication reservation can be made by setting the iiccn.sttn bit to 1 before a stop condition is detected (n = 0 to 2). figure 20-17. timing for accep ting communication reservations scl0n sda0n stdn spdn standby mode remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1008 of 1817 sep 19, 2011 the communication reservation flowchart is illustrated below. figure 20-18. communication reservation flowchart di set1 sttn define communication reservation wait cancel communication reservation no yes iicn register xxh ei mstsn bit = 0? (communication reservation) note (generate start condition) sets sttn bit (communication reservation). secures wait period set by software (see table 20-6 ). confirmation of communication reservation clears user flag. iicn register write operation defines that communication reservation is in effect (defines and sets user flag to any ram). note the communication reservation operation execut es a write to the iic n register when a stop condition interrupt request occurs. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1009 of 1817 sep 19, 2011 20.14.2 when communication reservation functi on is disabled (iicfn.iicrsvn bit = 1) when the iiccn.sttn bit is set when the bus is not being used for communication during bus communication, this request is rejected and a start condition is not generated. there are two modes in which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iiccn.lreln bit was set to 1) (n = 0 to 2) to confirm whether the start condition was generated or the request was rejected, check the iicfn.stcfn flag. the time shown in table 20-7 is required until the stcfn flag is set after setting the sttn bit to 1. therefore, secure the time by software. table 20-7. wait periods ocksenm ocksm1 ocksm0 cln1 cln0 wait period 1 0 0 0 20 clocks 1 0 1 0 30 clocks 1 1 0 0 40 clocks 1 1 1 0 50 clocks 0 0 0 1 0 10 clocks remarks 1. : don?t care 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) m = 0 to 2 v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1010 of 1817 sep 19, 2011 20.15 cautions (1) when iicfn.stcenn bit = 0 immediately after the i 2 c0n operation is enabled, the bus communica tion status (iicfn.iicbsyn bit = 1) is recognized regardless of the actual bus status. to execute master communication in the status where a stop condition has not been detected, generat e a stop condition and then release the bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccln register. <2> set the iiccn.iicen bit. <3> set the iiccn.sptn bit. (2) when iicfn.stcenn bit = 1 immediately after i 2 c0n operation is enabled, the bus release status ( iicbsyn bit = 0) is recognized regardless of the actual bus status. to gen erate the first start condition (iiccn.sttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) when the iiccn.iicen bit of the v850es/jh3-e and v850es/jj3-e is set to 1 while other devices are communicating, the start condition may be detected depending on the status of the communication line. be sure to set the iiccn.iicen bit to 1 when the scl0n and sda0n lines are high level. (4) determine the operation clock frequency by using the iiccln, iicxn, and ocksm regi sters before enabling the operation (iiccn.iicen bit = 1). to change the operation clock frequency, first clear the iiccn.iicen bit to 0. (5) after the iiccn.sttn and iiccn.sptn bits have been set to 1, they must not be re-set without being cleared to 0 first. (6) if transmission has been reserved, set the iiccn.spien bit to 1 so that an interrupt request is generated by the detection of a stop condition. after an interrupt reques t has been generated, the wait status will be released by writing communication data to i 2 cn, then transfer will begin. if an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait status because an interrupt request was not generated. however, it is not necessary to set the spien bit to 1 for the software to detect the iicsn.mstsn bit. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1011 of 1817 sep 19, 2011 20.16 communication operations the following shows three operation procedures together with flowcharts. (1) master operation in single master system the flowchart when using the v850es/jh3-e and v850es/jj3-e as the master in a singl e master system is shown below. this flowchart is broadly divided into initial settings and communication processing. execute the initial settings at startup. if communication with a slave is required, prepare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c0n bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a communication. here, when data and the clock are at a high level for a certain period (1 frame), the v850es/jh3-e or v850es/jj3-e takes part in communication in a bus release state. this flowchart is broadly divided into initial settings, communication waiting, and communication processing. the processing when the v850es/jh3-e or v850es/jj3-e loses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. execute the initia l settings at startup to take part in communication. then, wait for the communication request as t he master or wait for the s pecification as the slave. the actual communication is performed in the communica tion processing, and includes arbitration with other masters data as well as transmi ssion/reception with the slave. (3) slave operation an example of when the v850es/jh3-e or v 850es/jj3-e is used as the slave of the i 2 c0n bus is shown below. when used as the slave, operation is started by an interrup t. execute the initial setting s at startup, then wait for intiicn interrupt occurrence (communication waiting). when the intiicn interrupt occurs, the communication status is judged and its result is pa ssed as a flag to the main processing. by checking the flags, the necessary communication processing can be performed. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1012 of 1817 sep 19, 2011 20.16.1 master operation in single master system figure 20-19. master operation in single master system iicxn 0xh iiccln xxh ocksm xxh iicfn 0xh set stcenn, iicrsvn = 0 iiccn xxh acken = wtimn = spien = 1 iicen = 1 set ports initialize i 2 c bus note sptn = 1 svan xxh write iicn write iicn sptn = 1 wreln = 1 start end read iicn acken = 0 wtimn = wreln = 1 no no yes no no no yes yes yes yes stcenn = 1? acken = 1 wtimn = 0 intiicn interrupt occurred? transfer completed? transfer completed? restarted? trcn = 1? ackdn = 1? ackdn = 1? refer to table 4-18 using port pin as alternate-function pin to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting communication start preparation (start condition generation) communication start (address, transfer direction specification) waiting for ack detection waiting for data transmission transmission start communication processing initial settings reception start waiting for data reception no yes intiicn interrupt occurred? waiting for ack detection communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiicn interrupt occurred? yes no intiicn interrupt occurred? yes no yes no yes no intiicn interrupt occurred? sttn = 1 note release the i 2 c0n bus (scl0n, sda0n pins = high level) in compliance with the specifications of the communicating product. for example, when the eeprom tm outputs a low level to the sda0n pin, set the scl0n pin to the output port and output clock pulses from that output port until the sda0n pin becomes constantly high level. remarks 1. for the transmission and reception formats, comply with the specifications of the communicating product. 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) m = 0 to 2 v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1013 of 1817 sep 19, 2011 20.16.2 master operation in multimaster system figure 20-20. master operation in multimaster system (1/3) iicxn 0xh iiccln xxh ocksm xxh iicfn 0xh set stcenn, iicrsvn iiccn xxh acken = wtimn = spien = 1 iicen = 1 set ports sptn = 1 svan xxh spien = 1 start slave operation slave operation bus release status for a certain period confirmation of bus status is in progress yes confirm bus status note master operation started? communication reservation enable communication reservation disable spdn = 1? stcenn = 1? iicrsvn = 0? a refer to table 4-18 using port pin as alternate-function pin to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting (communication start request issued) (no communication start request) ? waiting for slave specification from another master ? waiting for communication start request (depending on user program) communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiicn interrupt occurred? intiicn interrupt occurred? yes no yes no spdn = 1? yes no slave operation no intiicn interrupt occurred? yes no 1 b spien = 0 yes no waiting for communication request communication waiting initial settings note confirm that the bus release status (iiccln.cldn bit = 1, iiccln.dadn bit = 1) has been maintained for a certain period (1 frame, for example). when the sda0 n pin is constantly low level, determine whether to release the i 2 c0n bus (scl0n, sda0n pins = high level) by referring to the specifications of the communicating product. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) m = 0 to 2 v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1014 of 1817 sep 19, 2011 figure 20-20. master operation in multimaster system (2/3) sttn = 1 wait slave operation yes mstsn = 1? excn = 1 or coin =1? communication start preparation (start condition generation) securing wait time by software (refer to table 20-6 ) waiting for bus release (communication being reserved) wait status after stop condition detection and start condition generation by communication reservation function no intiicn interrupt occurred? yes yes no no a c sttn = 1 wait slave operation yes iicbsyn = 0? excn = 1 or coin =1? communication start preparation (start condition generation) communication reservation disabled communication reservation enabled securing wait time by software (refer to table 20-7 ) waiting for bus release stop condition detection no no intiicn interrupt occurred? yes yes no yes stcfn = 0? no b d c d communication processing communication processing remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1015 of 1817 sep 19, 2011 figure 20-20. master operation in multimaster system (3/3) write iicn wtimn = 1 wreln = 1 read iicn acken = 1 wtimn = 0 wtimn = wreln = 1 acken = 0 write iicn yes trcn = 1? restarted? mstsn = 1? communication start (address, transfer direction specification) transmission start no yes waiting for data transmission reception start yes no intiicn interrupt occurred? yes no transfer completed? waiting for ack detection yes no intiicn interrupt occurred? waiting for data transmission not in communication yes no intiicn interrupt occurred? no yes ackdn = 1? no yes no c 2 yes mstsn = 1? no yes transfer completed? no yes ackdn = 1? no 2 yes mstsn = 1? no 2 waiting for ack detection yes no intiicn interrupt occurred? yes mstsn = 1? no c 2 yes excn = 1 or coin = 1? no 1 2 sptn = 1 sttn = 1 slave operation end communication processing communication processing remarks 1. for the transmission and reception formats, comply with the specifications of the communicating product. 2. when using the v850es/jh3-e or v850es/jj3-e as the master in a multimaster system, read the iicsn.mstsn bit for each intiicn interrupt o ccurrence to confirm the arbitration result. 3. when using the v850es/jh3-e or v850es/jj3-e as the slave in a multimaster system, confirm the status using the iicsn and iicfn registers for each intiicn interrupt occurrence to determine the next processing. 4. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1016 of 1817 sep 19, 2011 20.16.3 slave operation the following shows the processing procedure of slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiicn interrupt (processing requiring a significant change of the oper ation status, such as stop condition detecti on during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiicn interrupt servicing performs only status change processing and that the actual data communication is performed during the main processing. figure 20-21. overview of so ftware during slave operation i 2 c intiicn signal setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags ar e prepared so that the data transfer processing can be performed by passing these flags to the main processing instead of the intiicn signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progress (valid address detection stop condition detection, ack from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. this is the same status as an intiicn interrupt during normal data transfer. this flag is set in the interrupt processing bl ock and cleared in the main processing block. the ready flag for the first data for transmission is not set in the inte rrupt processing block, so t he first data is transmitted without clear processing (the address match is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of iicsn.trcn bit. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1017 of 1817 sep 19, 2011 the following shows the operation of the ma in processing block during slave operation. i 2 c0n starts and waits for the communication enab le status. when communication is enabled, i 2 c0n performs transfer using the communication mode flag and ready flag (the processi ng of the stop condition and st art condition is performed by interrupts, conditions are confirmed by flags). for transmission, the transmission operation is repeated until the master device stops returning ack. when the master device stops returning ack, transfer is complete. for reception, the required nu mber of data is received and ack is not returned for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart conditi on. this causes exit from communications. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1018 of 1817 sep 19, 2011 figure 20-22. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 0? read iicn clear ready flag clear ready flag communication direction flag = 1? wreln = 1 ackdn = 1? clear communication mode flag wreln = 1 write iicn iiccn xxh acken = wtimn = 1 spien = 0, iicen = 1 svan xxh local address setting iicxn 0xh iiccln xxh ocksm xxh set ports transfer clock selection iicfn 0xh set iicrsvn start condition setting transmission start reception start no yes no communication mode flag = 1? yes no ready flag = 1? refer to table 4-18 using port pin as alternate-function pin to set the i 2 c mode before this function is used. start initial settings communication processing remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) m = 0 to 2 v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1019 of 1817 sep 19, 2011 the following shows an example of the proc essing of the slave device by an int iicn interrupt (it is assumed that no extension codes are used here). during intiicn interrupt serv icing, the status is confirm ed and the following steps are executed. <1> when a stop condition is detected, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the addr ess does not match, communication is terminated. if the address matches, the communication mode is set, the wait state is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, w hen the ready flag is set, operation retu rns from the interrupt while the i 2 c0n bus remains in the wait status. remarks 1. <1> to <3> above correspond to <1> to <3> in figure 20-23 slave operation flowchart (2) . 2. n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) figure 20-23. slave operation flowchart (2) yes yes yes no no no intiicn occurred set ready flag interrupt servicing completed spdn = 1? stdn = 1? coin = 1? clear communication direction flag, ready flag, and communication mode flag <1> <2> <3> communication direction flag trcn set communication mode flag clear ready flag v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1020 of 1817 sep 19, 2011 20.17 timing of data communication when using i 2 c bus mode, the master dev ice outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits t he iicsn.trcn bit, which s pecifies the data transfer direction, and then starts serial communication with the slave device. the shift operation of the iicn register is synchronized wit h the falling edge of the serial clock pin (scl0n). the transmit data is transferred to the so latch an d is output (msb first) via the sda0n pin. data input via the sda0n pin is captured by the iic n register at the rising edge of the scl0n pin. the data communication timing is shown below. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1021 of 1817 sep 19, 2011 figure 20-24. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l l h h l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data note 1 iicn ffh note 2 transmit start condition receive note 2 notes 1. cancel the wait during a master transmission by writing data to iicn, not by setting wreln. 2. to cancel the slave wait state, write ffh to iicn or set wreln. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1022 of 1817 sep 19, 2011 figure 20-24. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h l l l l l l h h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data note 1 iicn ffh note 2 iicn ffh note 2 iicn data note 1 note 2 note 2 ack ack processing by master device transfer lines transmit processing by slave device receive notes 1. cancel the wait during a master transmission by writing data to iicn, not by setting wreln. 2. to cancel the slave wait state, write ffh to iicn or set wreln. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1023 of 1817 sep 19, 2011 figure 20-24. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l l h h l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data note 1 iicn address iicn ffh note2 iicn ffh note2 note 2 note 2 (when spien = 1) ack processing by master device transmit (when spien = 1) transfer lines processing by slave device stop condition start condition receive notes 1. cancel the wait during a master transmission by writing data to iicn, not by setting wreln. 2. to cancel the slave wait state, write ffh to iicn or set wreln. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1024 of 1817 sep 19, 2011 figure 20-25. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l h l acken mstsn sttn l l sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 d4 d3 d2 d5 d6 d7 iicn address iicn ffh note 1 note 1 iicn data note 2 ack r processing by master device receive transmit receive transmit transfer lines processing by slave device notes 1. to cancel the master wait state, write ffh to iicn or set wreln. 2. cancel the wait during a slave transmission by writing to iicn, not by setting wreln. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1025 of 1817 sep 19, 2011 figure 20-25. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (2/3) (b) data iicn ackdn stdn spdn wtimn h h h l l l l l l l h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n 1 89 2345678 9 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note 1 note 1 iicn data note 2 iicn data note 2 iicn ffh note 1 iicn ffh note 1 processing by master device receive transfer lines processing by slave device transmit notes 1. to cancel the master wait state, write ffh to iicn or set wreln. 2. cancel the wait during a slave transmission by writing to iicn, not by setting wreln. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapter 20 i 2 c bus r01uh0290ej0300 rev.3.00 page 1026 of 1817 sep 19, 2011 figure 20-25. example of sl ave to master communication (when 8-clock wait for master and 9-cl ock wait for slave are selected) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iicn address iicn ffh note 1 note 1 note 1, 3 iicn data note 2 nack (when spien = 1) iicn ffh note 1 note 3 processing by master device receive transfer lines processing by slave device stop condition start condition transmit (when spien = 1) receive notes 1. to cancel the wait state, write ffh to iicn or set wreln. 2. cancel the wait during a slave transmission by writing to iicn, not by setting wreln. 3. when the wait during a slave transmission is canceled by setting wreln, trcn is cleared. remark n = 0 to 3 (v850es/jh3-e) n = 0 to 4 (v850es/jj3-e) v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1027 of 1817 sep 19, 2011 chapter 21 can controller caution 1. the can controller is allocated in the programmable peripheral i/o area. before using the can controller, enable use of the programmable peripheral i/o area by using the bpc register. for details, refer to 3.4.7 pr ogrammable peripheral i/o registers. 2. when using the can cont roller, make sure that f xx = 32 to 50 mhz. 21.1 overview the v850es/jh3-e and v850es/jj3-e featur e an on-chip 1-channel can (controller area network) controller that complies with the can protocol as standardized in iso 11898. the v850es/jh3-e and v850es/jj3-e products wit h an on-chip can controller are as follows. ? pd70f3783, 70f3786 21.1.1 features ? compliant with iso 11898 and tested according to iso/dis 16845 (can conformance test) ? standard frame and extended fram e transmission/reception enabled ? transfer rate: 1 mbps max. (can clock input 8 mhz) ? 32 message buffers/channels ? receive/transmit history list function ? automatic block transmission function ? multi-buffer receive block function ? mask setting of four patterns is possible for each channel v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1028 of 1817 sep 19, 2011 21.1.2 overview of functions table 21-1 presents an overview of the can controller functions. table 21-1. overview of functions function details protocol can protocol iso 11898 (standard and extended frame transmission/reception) baud rate maximum 1 mbps (can clock input 8 mhz) data storage storing messages in the can ram number of messages ? 32 message buffers/channels ? each message buffer can be set to be either a transmit message buffer or a receive message buffer. message reception ? unique id can be set to each message buffer. ? mask setting of four patterns is possible for each channel. ? a receive completion interrupt is generated each time a message is received and stored in a message buffer. ? two or more receive message buffers can be used as a fifo receive buffer (multi-buffer receive block function). ? receive history list function message transmission ? unique id can be set to each message buffer. ? transmit completion interrupt for each message buffer ? message buffer numbers 0 to 7 specified as transmit message buffers can be used for automatic block transfer. message transmis sion interval is programmable (automatic block transmission function (herea fter referred to as ?abt?)). ? transmission history list function remote frame processing remote frame processing by transmit message buffer time stamp function ? the time stamp function can be set for a re ceive message when a 16-bit timer is used in combination. ? the time stamp capture trigger can be se lected (sof or eof in a can message frame can be detected). diagnostic function ? readable error counters ? ?valid protocol operation flag? for verification of bus connections ? receive-only mode ? single-shot mode ? can protocol error type decoding ? self-test mode release from bus-off state ? can be forcibly released from bus-off by so ftware (timing restrictions are ignored). ? cannot be automatically released from bus-o ff (release request by software is required). power save mode ? can sleep mode (can be woken up by can bus) ? can stop mode (cannot be woken up by can bus) v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1029 of 1817 sep 19, 2011 21.1.3 configuration the can controller is composed of the following four blocks. (1) internal bus interface this functional block provides an internal bus interfac e and means of transmitting and receiving signals between the can module and the host cpu. (2) mcm (memory control module) this functional block controls access to the can prot ocol layer and to the can ram within the can module. (3) can protocol layer this functional block is involved in the oper ation of the can protocol and its related settings. (4) can ram this is the can memory functional block, which is used to store message ids, message data, etc. figure 21-1. block diagram of can module ctxd0 crxd0 cpu can module can ram internal bus mcm (memory control module) npb interface interrupt request intc0trx intc0rec intc0err intc0wup can protocol layer can transceiver message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer 31 c0mask1 c0mask2 c0mask3 c0mask4 ... can_h0 can_l0 can bus tsout v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1030 of 1817 sep 19, 2011 21.2 can protocol can (controller area network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class c). can is prescribed by iso 11898. for details, refer to the iso 11898 specifications. the can specification is generally divided into two layers: a ph ysical layer and a data link layer. in turn, the data link layer includes logical link and medium access control. the composition of these la yers is illustrated below. figure 21-2. composition of layers physical layer prescription of signal level and bit description data link layer note logical link control (llc) medium access control (mac) acceptance filtering overload report recovery management data capsuled/not capsuled frame coding (stuffing/no stuffing) medium access management error detection error report acknowledgment seriated/not seriated higher lower note can controller specification 21.2.1 frame format (1) standard format frame ? the standard format frame uses 11-bit identifiers, wh ich means that it can handle up to 2,048 messages. (2) extended format frame ? the extended format frame uses 29-bit (11 bits + 18 bi ts) identifiers, which increases the number of messages that can be handled to 2,048 2 18 messages. ? an extended format frame is set when ?recessive level? (c mos level of ?1?) is set for both the srr and ide bits in the arbitration field. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1031 of 1817 sep 19, 2011 21.2.2 frame types the following four types of frames are used in the can protocol. table 21-2. frame types frame type description data frame frame used to transmit data remote frame frame used to request a data frame error frame frame used to report error detection overload frame frame used to delay the next data frame or remote frame (1) bus value the bus values are divided into dominant and recessive. ? dominant level is indicated by logical 0. ? recessive level is indicated by logical 1. ? when a dominant level and a recessive level are transmi tted simultaneously, the bus value becomes dominant level. 21.2.3 data frame and remote frame (1) data frame a data frame is composed of seven fields. figure 21-3. data frame r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8> remark d: dominant = 0 r: recessive = 1 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1032 of 1817 sep 19, 2011 (2) remote frame a remote frame is composed of six fields. figure 21-4. remote frame r d interframe space end of frame (eof) ack field crc field control field arbitration field start of frame (sof) remote frame <1> <2> <3> <5> <6> <7> <8> remarks 1. the data field is not transferred even if the cont rol field?s data length code is not ?0000b?. 2. d: dominant = 0 r: recessive = 1 (3) description of fields <1> start of frame (sof) the start of frame field is located at t he start of a data frame or remote frame. figure 21-5. start of frame (sof) r d 1 bit start of frame (interframe space or bus idle) (arbitration field) remark d: dominant = 0 r: recessive = 1 ? if a dominant level is detected in the bus idle stat e, a hardware synchronization is performed (the current tq is assigned to be the sync segment). ? if a dominant level is sampled at the sample point fo llowing such a hardware synchronization, the bit is assigned to be a sof. if a recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a noise on ly. in this case an error frame is not generated. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1033 of 1817 sep 19, 2011 <2> arbitration field the arbitration field is used to set the priori ty, data frame/remote frame, and frame format. figure 21-6. arbitration field (in standard format mode) r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) id28 . . . . . . . . . . . . . . . . . . . . id18 (1 bit) (1 bit) cautions 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. remark d: dominant = 0 r: recessive = 1 figure 21-7. arbitration field (in extended format mode) r d r1 r0 rtr ide srr identifier identifier arbitration field (control field) (11 bits) (18 bits) id28 id18 id17 id0 (1 bit) (1 bit) (1 bit) cautions 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. remark d: dominant = 0 r: recessive = 1 table 21-3. rtr frame settings frame type rtr bit data frame 0 (d) remote frame 1 (r) table 21-4. frame format setting (ide bit) and number of identifier (id) bits frame format srr bit ide bit number of bits standard format mode none 0 (d) 11 bits extended format mode 1 (r) 1 (r) 29 bits v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1034 of 1817 sep 19, 2011 <3> control field the control field sets ?dlc? as the number of dat a bytes in the data field (dlc = 0 to 8). figure 21-8. control field r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) remark d: dominant = 0 r: recessive = 1 in a standard format frame, the control fiel d?s ide bit is the same as the r1 bit. table 21-5. data length setting data length code dlc3 dlc2 dlc1 dlc0 data byte count 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0 caution in the remote frame, there is no da ta field even if the data length code is not 0000b. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1035 of 1817 sep 19, 2011 <4> data field the data field contains the am ount of data (byte units) set by the control field. up to 8 units of data can be set. figure 21-9. data field r d data 0 (8 bits) msb lsb data 7 (8 bits) msb lsb data field (crc field) (control field) remark d: dominant = 0 r: recessive = 1 <5> crc field the crc field is a 16-bit field that is used to check for errors in transmit data. figure 21-10. crc field r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field or control field) remark d: dominant = 0 r: recessive = 1 ? the polynomial p(x) used to generate the 15-bi t crc sequence is expressed as follows. p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 ? transmitting node: transmits the crc sequence calculat ed from the data (before bit stuffing) in the start of frame, arbitration fiel d, control field, and data field. ? receiving node: compares the crc sequence calc ulated using data bits that exclude the stuffing bits in the receive data with the crc sequence in the crc field. if the two crc sequences do not match, the node issues an error frame. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1036 of 1817 sep 19, 2011 <6> ack field the ack field is used to acknowledge normal reception. figure 21-11. ack field r d ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field) remark d: dominant = 0 r: recessive = 1 ? if no crc error is detected, the receiving node sets the ack slot to the dominant level. ? the transmitting node outputs two recessive-level bits. <7> end of frame (eof) the end of frame field indicates the end of data frame/remote frame. figure 21-12. end of frame (eof) r d end of frame (7 bits) (interframe space or overload frame) (ack field) remark d: dominant = 0 r: recessive = 1 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1037 of 1817 sep 19, 2011 <8> interframe space the interframe space is inserted after a data frame, remo te frame, error frame, or overload frame to separate one frame from the next. ? the bus state differs dep ending on the error status. (a) error active node the interframe space consists of a 3-bit intermission field and a bus idle field. figure 21-13. interframe space (error active node) r d interframe space intermission (3 bits) bus idle (0 to bits) (frame) (frame) remarks 1. bus idle: state in which the bus is not used by any node. 2. d: dominant = 0 r: recessive = 1 (b) error passive node the interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. figure 21-14. interframe space (error passive node) r d interframe space intermission (3 bits) suspend transmission (8 bits) bus idle (0 to bits) (frame) (frame) remarks 1. bus idle: state in which the bus is not used by any node. suspend transmission: sequence of 8 re cessive-level bits transmitted from the node in the error passive status. 2. d: dominant = 0 r: recessive = 1 usually, the intermission field is 3 bits. if the transmi tting node detects a dominant level at the third bit of the intermission field, however, it executes transmission. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1038 of 1817 sep 19, 2011 ? operation in error status table 21-6. operation in error status error status operation error active a node in this status can transmit immediately after a 3-bit intermission. error passive a node in this status can transmit 8 bits after the intermission. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1039 of 1817 sep 19, 2011 21.2.4 error frame an error frame is output by a node that has detected an error. figure 21-15. error frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag 2 error flag 1 error bit error frame remark d: dominant = 0 r: recessive = 1 table 21-7. definition of error frame fields no. name bit count definition <1> error flag 1 6 error active node: outputs 6 domin ant-level bits consecutively. error passive node: outputs 6 rece ssive-level bits consecutively. if another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> error flag 2 0 to 6 nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> error delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> error bit ? the bit at which the error was detected. the error flag is output from the bit next to the error bit. in the case of a crc error, this bit is output following the ack delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1040 of 1817 sep 19, 2011 21.2.5 overload frame an overload frame is transmitted under the following conditions. ? when the receiving node has not co mpleted the reception operation note ? if a dominant level is detected at the first two bits during intermission ? if a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter note in this can controller, all reception frames can be l oaded without outputting an overload frame because of the enough high-speed internal processing. figure 21-16. overload frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag (node n) overload flag (node m) frame overload frame remark d: dominant = 0 r: recessive = 1 node n node m table 21-8. definition of overload frame fields no name bit count definition <1> overload flag 6 outputs 6 domin ant-level bits consecutively. <2> overload flag from other node 0 to 6 the node that received an overload flag in the interframe space outputs an overload flag. <3> overload delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1041 of 1817 sep 19, 2011 21.3 functions 21.3.1 determining bus priority (1) when a node starts transmission: ? during bus idle, the node that out put data first transmits the data. (2) when more than one n ode starts transmission: ? the node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive leve l are simultaneously transmitted, the dominant level is taken as the bus value). ? the transmitting node compares its output arbi tration field and the data level on the bus. table 21-9. determining bus priority level match continuous transmission level mismatch continuous transmission (3) priority of data frame and remote frame ? when a data frame and a remote frame are on the bus, the data frame has priority because its rtr bit, the last bit in the arbitration field, carries a dominant level. remark if the extended-format data frame and the standard-form at remote frame conflict on the bus (if id28 to id18 of both of them are the sa me), the standard-format remote frame takes priority. 21.3.2 bit stuffing bit stuffing is used to establish synchronization by appending 1 bit of inverted-level data if the same level continues for 5 bits, in order to prevent a burst error. table 21-10. bit stuffing transmission during the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 inverted-level bit of data is inserted before the following bit. reception during the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, re ception is continued after deleting the next bit. 21.3.3 multi masters as the bus priority (a node which acquires transmission righ ts) is determined by the identifier, any node can be the bus master. 21.3.4 multi cast although there is one transmitting node, two or more nodes c an receive the same data at the same time because the same identifier can be set to two or more nodes. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1042 of 1817 sep 19, 2011 21.3.5 can sleep mode/can stop mode function the can sleep mode/can stop mode function puts the can c ontroller in waiting mode to achieve low power consumption. the controller is woken up from the can sleep mode by bus operation but it is not wo ken up from the can stop mode by bus operation (the can stop mode is controlled by cpu access). 21.3.6 error control function (1) error types table 21-11. error types description of error detection state type detection method detection condition transmission/ reception field/frame bit error comparison of the output level and level on the bus mismatch of levels transmitting/ receiving node bit that is outputting data on the bus at the start of frame to end of frame, error frame and overload frame. stuff error check of the receive data at the stuff bit 6 consecutive bits of the same output level receiving node start of frame to crc sequence crc error comparison of the crc sequence generated from the receive data and the received crc sequence mismatch of crc receiving node crc field form error field/frame check of the fixed format detection of fixed format violation receiving node crc delimiter ack field end of frame error frame overload frame ack error check of the ack slot by the transmitting node detection of recessive level in ack slot transmitting node ack slot (2) output timing of error frame table 21-12. output timing of error frame type output timing bit error, stuff error, form error, ack error error frame output is started at the timing of the bit following the detected error. crc error error frame output is started at the timing of the bit following the ack delimiter. (3) processing in case of error the transmission node re-transmits the data frame or remote frame after the error frame. (however, it does not re- transmit the frame in the single-shot mode.) v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1043 of 1817 sep 19, 2011 (4) error state (a) types of error states the following three types of error states are defined by the can specification. ? error active ? error passive ? bus-off these types of error states are classified by the values of the c0erc.tec7 to c0erc.tec0 bits (transmission error counter bits) and the c0erc.rec6 to c0erc.rec0 bits (reception error counter bits) as shown in table 21-13. the present error state is indi cated by the c0info register. when each error counter value becomes equal to or greater than the error warning level (96), the c0info.tecs0 or c0info.recs0 bit is set to 1. in this case, the bus state must be tested because it is considered that the bus has a serious fault. an error counter value of 128 or more indicates an error passive state and the tecs1 or recs1 bit is set to 1. ? if the value of the transmission error counter is great er than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the c0info.boff bit is set to 1. ? if only one node is active on the bus at startup (i.e., when the bus is connected only to the local station), ack is not returned even if data is transmitted. co nsequently, re-transmission of the error frame and data is repeated. in the error passive state, however, t he transmission error counter is not incremented and the bus-off state is not reached. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1044 of 1817 sep 19, 2011 table 21-13. types of error states type operation value of error counter indication of c0info register operation specific to error state transmission 0 to 95 tecs1, tecs0 = 00 reception 0 to 95 recs1, recs0 = 00 transmission 96 to 127 tecs1, tecs0 = 01 error active reception 96 to 127 recs1, recs0 = 01 ? outputs an active error flag (6 consecutive dominant- level bits) on detection of the error. transmission 128 to 255 tecs1, tecs0 = 11 error passive reception 128 or more recs1, recs0 = 11 ? outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. ? transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). bus-off transmission 256 or more (not indicated) note boff = 1, tecs1, tecs0 = 11 ? communication is not possible. however, when the frame is received, no messages are stored and the following operations are performed. <1> tsout toggles. <2> rec is incremented/decremented. <3> valid bit is set. ? if the initialization mode is set, after request to transit to an operation mode other than the initialization mode, 11 consecutive rece ssive-level bits are generated 128 times, and then the error counter is reset to 0 and the error active state can be restored. note the value of the transmit error counter (tec) does not carry any meaning if boff has been set. if an error that increments the value of the transmission error counter by 8 while the counter value is in a range of 248 to 255 occurs, the counter is not incremented and the bus-off state is assumed. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1045 of 1817 sep 19, 2011 (b) error counter the error counter counts up when an error has occurre d, and counts down upon successful transmission and reception. the error counter counts up immediately after error detection. table 21-14. error counter state transmission error counter (tec7 to tec0 bits) reception error counter (rec6 to rec0 bits) receiving node detects an error (except bit error in the active error flag or overload flag). no change +1 (reps bit = 0) receiving node detects dominant level following error flag of error frame. no change +8 (reps bit = 0) transmitting node transmits an error flag. [as exceptions, the error counter does not change in the following cases.] <1> ack error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> a stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. +8 no change bit error detection while active error flag or overload flag is being output (error-active transmitting node) +8 no change bit error detection while active error flag or overload flag is being output (error-active receiving node) no change +8 (reps bit = 0) when the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant-level bits. when the node detects 8 consecutive dominant levels after a passive error flag +8 (transmitting) +8 (receiving, reps bit = 0) when the transmitting node has co mpleted transmission without error ( 0 if error counter = 0) ?1 no change when the receiving node has completed reception without error no change ? ?1 (1 rec6 to rec0 127, reps bit = 0) ? 0 (rec6 to rec0 = 0, reps bit = 0) ? any value of 119 to 127 is set (reps bit = 1) (c) occurrence of bit error in intermission an overload frame is generated. caution if an error occurs, it is controlled accordin g to the contents of the transmission error counter and reception error counter before the error o ccurred. the value of the error counter is incremented after the erro r flag has been output. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1046 of 1817 sep 19, 2011 (5) recovery from bus-off state when the can module is in the bus-off state, the transmission pins (ctxd0) cut off from the can bus always output the recessive level. the can module recovers from the bus-off stat e in the following bus-off recovery sequence. <1> request to enter the can initialization mode <2> request to enter a can operation mode (a) recovery operation through normal recovery sequence (b) forced recovery operation that skips recovery sequence (a) recovery from bus-off state through normal recovery sequence the can module first issues a request to enter the init ialization mode (refer to timing <1> in figure 21-17). this request will be immediately acknowledged, and t he c0ctrl.opmode2 to opmode0 bits are cleared to 000b. processing such as analyzing the fault that has caused the bus-off state, re-defining the can module and message buffer using application software, or st opping the operation of the can module can be performed by clearing the c0gmctrl.gom bit to 0. next, the module requests to change the mode from the initialization mode to an operation mode (refer to timing <2> in figure 21-17). this starts an operation to recover the can module from the bus-off state. the conditions under which the module can recover from t he bus-off state are defined by the can protocol iso 11898, and it is necessary to detect 11 consecutive recessive-level bits more than 128 times. at this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. when the recovery conditions are satisfied (refer to timing <3> in figure 21-17), the can module can enter the operation mode it has r equested. until the can module enters this operation mode, it stays in the initialization mode. whether the can module has comp leted transition to any ot her operation mode can be confirmed by reading the opmode2 to opmode0 bits. before transition to any other operation mode is completed, opmode2 to opmode0 bits = 000b is read. during the bus-off period and bus-off recovery sequence, the c0info.boff bit stays set (to 1). in the bus-off recovery sequence, the reception error counter (c0e rc.rec0 to c0erc.rec6) counts the number of times 11 consecutive recessive-level bits have been detected on the bus. therefore, the recovery state can be checked by reading the rec0 to rec6 bits. cautions 1. if a request to cha nge the mode from the initializati on mode to any operation mode to execute the bus-off recovery sequence agai n during a bus-off recovery sequence, the bus-off recovery sequence starts from the beginning and 11 cont iguous recessive bits are counted 128 times again on the bus. 2. in the bus-off recovery seque nce, the rec0 to rec6 bits counts up (+1) each time 11 consecutive recessive-level bits have been detected. even during the bus-off period, the can module can enter the can sleep mode or can stop mode. to be released from the bus-off state, the module must en ter the initialization mode once. if the module is in the can sleep mode or can stop mode, however, it cannot directly enter the initialization mode. in this case, the bus off recovery sequence is started at the same time as the can sleep mode is released even wit hout shifting to the initialization m ode. in addition to clearing the c0ctrl.psmode1 and c0ctrl .psmode0 bits by software, the bus off recovery sequence is also started due to wakeup by dominant edge detection on the can bus (while the can clock is supplied, the c0ctrl.psmode0 bit must be cleared by software after a dominant edge is detected.) . v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1047 of 1817 sep 19, 2011 figure 21-17. recovery from bus-o ff state through normal recovery sequence ?error-passive? 00h 00h 00h 00h 80h tec[7:0] ffh boff bit in c0info register opmode[2:0] in c0ctrl register (written by user) opmode[2:0] in c0ctrl register (read by user) tec[7:0] in c0erc register rec[7:0] in c0erc register tec > ffh 00h 00h 00h ffh < tec [7:0] ?bus-off? ?bus-off-recovery-sequence? ?error-active? 00h tec[7:0] < 80h 00h rec[7:0] < 80h 00h rec[7:0] 80h <1> <2> <3> undefined (b) forced recovery operation that skips bus-off recovery sequence the can module can be forcibly released from the bus-o ff state, regardless of the bus state, by skipping the bus-off recovery sequence. here is the procedure. first, the can module requests to ent er the initialization mode. for t he operation and points to be noted at this time, see 21.3.6 (5) (a) recovery from bus-off state through normal recovery sequence . next, the module requests to enter an operation mode. at the same time, the c0ctrl.ccerc bit must be set to 1. as a result, the bus-off recovery sequence defined by the can protocol iso 11898 is skipped, and the module immediately enters the operation mode. in this case , the module is connected to the can bus after it has monitored 11 consecutive recessive-level bits. for details, refer to the processing in figure 21-54. caution this function is not defi ned by the can protocol iso 11898. when using this function, thoroughly evaluate its effe ct on the network system. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1048 of 1817 sep 19, 2011 (6) initializing can module error counter re gister (c0erc) in initialization mode if it is necessary to initialize the c0erc and c0info r egisters for debugging or evaluating a program, they can be initialized to the default value by setting the c0ctrl.ccerc bit in the initialization mode. when initialization has been completed, the ccerc bit is automatically cleared to 0. cautions 1. this function is enabled on ly in the initialization mode. even if the ccerc bit is set to 1 in a can operation mode, the c0erc and c0info registers are not initialized. 2. the ccerc bit can be set at the same time as the request to enter a can operation mode. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1049 of 1817 sep 19, 2011 21.3.7 baud rate control function (1) prescaler the can controller has a presca ler that divides the clock (f can ) supplied to can. this prescaler generates a can protocol layer base clock (f tq ) that is the can module system clock (f canmod ) divided by 1 to 256 (see 21.6 (12) can0 module bit rate presc aler register (c0brp) ). (2) data bit time (8 to 25 time quanta) one data bit time is defined as shown in figure 21-18. 1 time quanta = 1/f tq the can controller sets the data bit time by replacing it with the bit timing parameters such as time segment 1, time segment 2, and resynchronization jump width (sjw ), as shown in figure 21-18. time segment 1 is equivalent to the total of the pr opagation (prop) segment and phase segm ent 1 that are defined by the can protocol specification. time segment 2 is equivalent to phase segment 2. figure 21-18. segment setting data bit time (dbt) phase segment 1 prop segment sync segment phase segment 2 time segment 1 (tseg1) time segment 2 (tseg2) sample point (spt) segment name settable range notes on setting to conform to can specification time segment 1 (tseg1) 2tq to 16tq ? time segment 2 (tseg2) 1tq to 8tq ipt of the can controller is 0tq. to conform to the can protocol specification, theref ore, a length equal or less to phase segment 1 must be set here. this means that the length of time segment 1 minus 1tq is the settable upper limit of time segment 2. resynchronization jump width (sjw) 1tq to 4tq the length of time segment 1 minus 1tq or 4tq, whichever smaller. remark ipt: information processing time tq: time quanta v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1050 of 1817 sep 19, 2011 remark the can protocol specificat ion defines the segments constituting the data bit time as shown in figure 21-19. figure 21-19. configuration of data bit time defined by can specification phase segment 1 prop segment sync segment phase segment 2 sample point (spt) sjw data bit time (dbt) segment name segment length description sync segment (synchronization segment) 1 this segment starts at the edge where the level changes from recessive to dominant when hardware synchronization is established. prop segment (propagation segment) programmable to 1 to 8, or greater this segment absorbs the delay of the output buffer, can bus, and input buffer. the length of this segment is set so that ack is returned before the start of phase segment 1. time of prop segment (delay of output buffer) + 2 (delay of can bus) + (delay of input buffer) phase segment 1 (phase buffer segment 1) programmable to 1 to 8 phase segment 2 (phase buffer segment 2) phase segment 1 or ipt, whichever greater this segment compensates for an error in the data bit time. the longer this segment, the wider the permissible range but the slower the communication speed. sjw (resynchronization jump width) programmable from 1tq to segment 1tq to 4tq, whichever is smaller this width sets the upper limit of expansion or contraction of the phase segment during resynchronization. remark ipt: information processing time tq: time quanta v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1051 of 1817 sep 19, 2011 (3) synchronizing data bit ? the receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. ? the transmitting node transmits data in synchroniza tion with the bit timing of the transmitting node. (a) hardware synchronization this synchronization is established when the receiving node detects the start of frame in the interframe space. ? when a falling edge is detected on the bus, that tq means the sync segment an d the next segment is the prop segment. in this case, synchroniza tion is established regardless of sjw. figure 21-20. hardware synchronization due to dominant level detect ion during bus idle start of frame interframe space can bus bit timing phase segment 1 prop segment sync segment phase segment 2 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1052 of 1817 sep 19, 2011 (b) resynchronization synchronization is established again if a level change is detected on t he bus during reception (only if a recessive level was sampled previously). ? the phase error of the edge is given by the relati ve position of the detected edge and sync segment. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1053 of 1817 sep 19, 2011 21.4 connection with target system the microcontroller with on-chip can controller has to be connected to the can bus using an external transceiver. figure 21-22. connection to can bus microcontroller with on-chip can controller transceiver ctxd0 crxd0 canl canh v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1054 of 1817 sep 19, 2011 21.5 internal registers of can controller 21.5.1 can controller configuration table 21-15. list of can controller registers item register name can0 global control register (c0gmctrl) can0 global clock select ion register (c0gmcs) can0 global automatic bl ock transmission contro l register (c0gmabt) can global registers can0 global automatic bloc k transmission delay setti ng register (c0gmabtd) can0 module mask 1 register (c0mask1l, c0mask1h) can0 module mask 2 register (c0mask2l, c0mask2h) can0 module mask 3 register (c0mask3l, c0mask3h) can0 module mask 4 registers (c0mask4l, c0mask4h) can0 module control register (c0ctrl) can0 module last error information register (c0lec) can0 module information register (c0info) can0 module error counter register (c0erc) can0 module interrupt enable register (c0ie) can0 module interrupt status register (c0ints) can0 module bit rate pres caler register (c0brp) can0 module bit rate register (c0btr) can0 module last in-pointer register (c0lipt) can0 module receive histor y list register (c0rgpt) can0 module last out-pointer register (c0lopt) can0 module transmit histor y list register (c0tgpt) can module registers can0 module time stamp register (c0ts) can0 message data byte 01 register m (c0mdata01m) can0 message data byte 0 register m (c0mdata0m) can0 message data byte 1 register m (c0mdata1m) can0 message data byte 23 register m (c0mdata23m) can0 message data byte 2 register m (c0mdata2m) can0 message data byte 3 register m (c0mdata3m) can0 message data byte 45 register m (c0mdata45m) can0 message data byte 4 register m (c0mdata4m) can0 message data byte 5 register m (c0mdata5m) can0 message data byte 67 register m (c0mdata67m) can0 message data byte 6 register m (c0mdata6m) can0 message data byte 7 register m (c0mdata7m) can0 message data length register m (c0mdlcm) can0 message configurati on register m (c0mconfm) can0 message id register m (c0midlm, c0midhm) message buffer registers can0 message control register m (c0mctrlm) remarks 1. the can global register is defined as c0gm v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1055 of 1817 sep 19, 2011 21.5.2 register access type table 21-16. register access types (1/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec000h can0 global control register c0gmctrl 0000h 03fec002h can0 global clock se lection register c0gmcs 0fh 03fec006h can0 global autom atic block transmission register c0gmabt 0000h 03fec008h can0 global automat ic block transmission del a register c0gmabtd 00h 03fec040h c0mask1l undefined 03fec042h can0 module mask 1 register c0mask1h undefined 03fec044h c0mask2l undefined 03fec046h can0 module mask 2 register c0mask2h undefined 03fec048h c0mask3l undefined 03fec04ah can0 module mask 3 register c0mask3h undefined 03fec04ch c0mask4l undefined 03fec04eh can0 module mask 4 register c0mask4h undefined 03fec050h can0 module control register c0ctrl 0000h 03fec052h can0 module last error code register c0lec r/w 00h 03fec053h can0 module information register c0info 00h 03fec054h can0 module error counter register c0erc r 0000h 03fec056h can0 module interrupt enable register c0ie 0000h 03fec058h can0 module interrupt status register c0ints 0000h 03fec05ah can0 module bit-rate prescaler register c0brp ffh 03fec05ch can0 module bit-rate register c0btr r/w 370fh 03fec05eh can0 module last in-pointer register c0lipt r undefined 03fec060h can0 module receive histor y list register c0rgpt r/w xx02h 03fec062h can0 module last out-pointer register c0lopt r undefined 03fec064h can0 module transmit history list register c0tgpt xx02h 03fec066h can0 module time stamp register c0ts r/w 0000h v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1056 of 1817 sep 19, 2011 table 21-16. register access types (2/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec100h can0 message data byte 01 register 00 c0mdata0100 undefined 03fec100h can0 message data byte 0 register 00 c0mdata000 undefined 03fec101h can0 message data byte 1 register 00 c0mdata100 undefined 03fec102h can0 message data byte 23 register 00 c0mdata2300 undefined 03fec102h can0 message data byte 2 register 00 c0mdata200 undefined 03fec103h can0 message data byte 3 register 00 c0mdata300 undefined 03fec104h can0 message data byte 45 register 00 c0mdata4500 undefined 03fec104h can0 message data byte 4 register 00 c0mdata400 undefined 03fec105h can0 message data byte 5 register 00 c0mdata500 undefined 03fec106h can0 message data byte 67 register 00 c0mdata6700 undefined 03fec106h can0 message data byte 6 register 00 c0mdata600 undefined 03fec107h can0 message data byte 7 register 00 c0mdata700 undefined 03fec108h can0 message data length register 00 c0mdlc00 0000xxxxb 03fec109h can0 message configurat ion register 00 c0mconf00 undefined 03fec10ah c0midl00 undefined 03fec10ch can0 message identifier register 00 c0midh00 undefined 03fec10eh can0 message control register 00 c0mctrl00 00x00000 000xx000b 03fec120h can0 message data byte 01 register 01 c0mdata0101 undefined 03fec120h can0 message data byte 0 register 01 c0mdata001 undefined 03fec121h can0 message data byte 1 register 01 c0mdata101 undefined 03fec122h can0 message data byte 23 register 01 c0mdata2301 undefined 03fec122h can0 message data byte 2 register 01 c0mdata201 undefined 03fec123h can0 message data byte 3 register 01 c0mdata301 undefined 03fec124h can0 message data byte 45 register 01 c0mdata4501 undefined 03fec124h can0 message data byte 4 register 01 c0mdata401 undefined 03fec125h can0 message data byte 5 register 01 c0mdata501 undefined 03fec126h can0 message data byte 67 register 01 c0mdata6701 undefined 03fec126h can0 message data byte 6 register 01 c0mdata601 undefined 03fec127h can0 message data byte 7 register 01 c0mdata701 undefined 03fec128h can0 message data length register 01 c0mdlc01 0000xxxxb 03fec129h can0 message configurat ion register 01 c0mconf01 undefined 03fec12ah c0midl01 undefined 03fec12ch can0 message identifier register 01 c0midh01 undefined 03fec12eh can0 message control register 01 c0mctrl01 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1057 of 1817 sep 19, 2011 table 21-16. register access types (3/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec140h can0 message data byte 01 register 02 c0mdata0102 undefined 03fec140h can0 message data byte 0 register 02 c0mdata002 undefined 03fec141h can0 message data byte 1 register 02 c0mdata102 undefined 03fec142h can0 message data byte 23 register 02 c0mdata2302 undefined 03fec142h can0 message data byte 2 register 02 c0mdata202 undefined 03fec143h can0 message data byte 3 register 02 c0mdata302 undefined 03fec144h can0 message data byte 45 register 02 c0mdata4502 undefined 03fec144h can0 message data byte 4 register 02 c0mdata402 undefined 03fec145h can0 message data byte 5 register 02 c0mdata502 undefined 03fec146h can0 message data byte 67 register 02 c0mdata6702 undefined 03fec146h can0 message data byte 6 register 02 c0mdata602 undefined 03fec147h can0 message data byte 7 register 02 c0mdata702 undefined 03fec148h can0 message data length register 02 c0mdlc02 0000xxxxb 03fec149h can0 message configurat ion register 02 c0mconf02 undefined 03fec14ah c0midl02 undefined 03fec14ch can0 message identifier register 02 c0midh02 undefined 03fec14eh can0 message control register 02 c0mctrl02 00x00000 000xx000b 03fec160h can0 message data byte 01 register 03 c0mdata0103 undefined 03fec160h can0 message data byte 0 register 03 c0mdata003 undefined 03fec161h can0 message data byte 1 register 03 c0mdata103 undefined 03fec162h can0 message data byte 23 register 03 c0mdata2303 undefined 03fec162h can0 message data byte 2 register 03 c0mdata203 undefined 03fec163h can0 message data byte 3 register 03 c0mdata303 undefined 03fec164h can0 message data byte 45 register 03 c0mdata4503 undefined 03fec164h can0 message data byte 4 register 03 c0mdata403 undefined 03fec165h can0 message data byte 5 register 03 c0mdata503 undefined 03fec166h can0 message data byte 67 register 03 c0mdata6703 undefined 03fec166h can0 message data byte 6 register 03 c0mdata603 undefined 03fec167h can0 message data byte 7 register 03 c0mdata703 undefined 03fec168h can0 message data length register 03 c0mdlc03 0000xxxxb 03fec169h can0 message configuration register 03 c0mconf03 undefined 03fec16ah c0midl03 undefined 03fec16ch can0 message identifier register 03 c0midh03 undefined 03fec16eh can0 message control register 03 c0mctrl03 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1058 of 1817 sep 19, 2011 table 21-16. register access types (4/17) bit manipulation units after reset address register name symbol r/w 1 bit 8 bits 16 bits 03fec180h can0 message data byte 01 register 04 c0mdata0104 undefined 03fec180h can0 message data byte 0 register 04 c0mdata004 undefined 03fec181h can0 message data byte 1 register 04 c0mdata104 undefined 03fec182h can0 message data byte 23 register 04 c0mdata2304 undefined 03fec182h can0 message data byte 2 register 04 c0mdata204 undefined 03fec183h can0 message data byte 3 register 04 c0mdata304 undefined 03fec184h can0 message data byte 45 register 04 c0mdata4504 undefined 03fec184h can0 message data byte 4 register 04 c0mdata404 undefined 03fec185h can0 message data byte 5 register 04 c0mdata504 undefined 03fec186h can0 message data byte 67 register 04 c0mdata6704 undefined 03fec186h can0 message data byte 6 register 04 c0mdata604 undefined 03fec187h can0 message data byte 7 register 04 c0mdata704 undefined 03fec188h can0 message data length register 04 c0mdlc04 0000xxxxb 03fec189h can0 message configur ation register 04 c0mconf04 undefined 03fec18ah c0midl04 undefined 03fec18ch can0 message identifier register 04 c0midh04 undefined 03fec18eh can0 message control register 04 c0mctrl04 00x00000 000xx000b 03fec1a0h can0 message data byte 01 register 05 c0mdata0105 undefined 03fec1a0h can0 message data byte 0 register 05 c0mdata005 undefined 03fec1a1h can0 message data byte 1 register 05 c0mdata105 undefined 03fec1a2h can0 message data byte 23 register 05 c0mdata2305 undefined 03fec1a2h can0 message data byte 2 register 05 c0mdata205 undefined 03fec1a3h can0 message data byte 3 register 05 c0mdata305 undefined 03fec1a4h can0 message data byte 45 register 05 c0mdata4505 undefined 03fec1a4h can0 message data byte 4 register 05 c0mdata405 undefined 03fec1a5h can0 message data byte 5 register 05 c0mdata505 undefined 03fec1a6h can0 message data byte 67 register 05 c0mdata6705 undefined 03fec1a6h can0 message data byte 6 register 05 c0mdata605 undefined 03fec1a7h can0 message data byte 7 register 05 c0mdata705 undefined 03fec1a8h can0 message data length register 05 c0mdlc05 0000xxxxb 03fec1a9h can0 message configuration register 05 c0mconf05 undefined 03fec1aah c0midl05 undefined 03fec1ach can0 message identifier register 05 c0midh05 undefined 03fec1aeh can0 message control register 05 c0mctrl05 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1059 of 1817 sep 19, 2011 table 21-16. register access types (5/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec1c0h can0 message data byte 01 register 06 c0mdata0106 undefined 03fec1c0h can0 message data byte 0 register 06 c0mdata006 undefined 03fec1c1h can0 message data byte 1 register 06 c0mdata106 undefined 03fec1c2h can0 message data byte 23 register 06 c0mdata2306 undefined 03fec1c2h can0 message data byte 2 register 06 c0mdata206 undefined 03fec1c3h can0 message data byte 3 register 06 c0mdata306 undefined 03fec1c4h can0 message data byte 45 register 06 c0mdata4506 undefined 03fec1c4h can0 message data byte 4 register 06 c0mdata406 undefined 03fec1c5h can0 message data byte 5 register 06 c0mdata506 undefined 03fec1c6h can0 message data byte 67 register 06 c0mdata6706 undefined 03fec1c6h can0 message data byte 6 register 06 c0mdata606 undefined 03fec1c7h can0 message data byte 7 register 06 c0mdata706 undefined 03fec1c8h can0 message data length register 06 c0mdlc06 0000xxxxb 03fec1c9h can0 message configur ation register 06 c0mconf06 undefined 03fec1cah c0midl06 undefined 03fec1cch can0 message identifier register 06 c0midh06 undefined 03fec1ceh can0 message control register 06 c0mctrl06 00x00000 000xx000b 03fec1e0h can0 message data byte 01 register 07 c0mdata0107 undefined 03fec1e0h can0 message data byte 0 register 07 c0mdata007 undefined 03fec1e1h can0 message data byte 1 register 07 c0mdata107 undefined 03fec1e2h can0 message data byte 23 register 07 c0mdata2307 undefined 03fec1e2h can0 message data byte 2 register 07 c0mdata207 undefined 03fec1e3h can0 message data byte 3 register 07 c0mdata307 undefined 03fec1e4h can0 message data byte 45 register 07 c0mdata4507 undefined 03fec1e4h can0 message data byte 4 register 07 c0mdata407 undefined 03fec1e5h can0 message data byte 5 register 07 c0mdata507 undefined 03fec1e6h can0 message data byte 67 register 07 c0mdata6707 undefined 03fec1e6h can0 message data byte 6 register 07 c0mdata607 undefined 03fec1e7h can0 message data byte 7 register 07 c0mdata707 undefined 03fec1e8h can0 message data length register 07 c0mdlc07 0000xxxxb 03fec1e9h can0 message configuration register 07 c0mconf07 undefined 03fec1eah c0midl07 undefined 03fec1ech can0 message identifier register 07 c0midh07 undefined 03fec1eeh can0 message control register 07 c0mctrl07 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1060 of 1817 sep 19, 2011 table 21-16. register access types (6/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec200h can0 message data byte 01 register 08 c0mdata0108 undefined 03fec200h can0 message data byte 0 register 08 c0mdata008 undefined 03fec201h can0 message data byte 1 register 08 c0mdata108 undefined 03fec202h can0 message data byte 23 register 08 c0mdata2308 undefined 03fec202h can0 message data byte 2 register 08 c0mdata208 undefined 03fec203h can0 message data byte 3 register 08 c0mdata308 undefined 03fec204h can0 message data byte 45 register 08 c0mdata4508 undefined 03fec204h can0 message data byte 4 register 08 c0mdata408 undefined 03fec205h can0 message data byte 5 register 08 c0mdata508 undefined 03fec206h can0 message data byte 67 register 08 c0mdata6708 undefined 03fec206h can0 message data byte 6 register 08 c0mdata608 undefined 03fec207h can0 message data byte 7 register 08 c0mdata708 undefined 03fec208h can0 message data length register 08 c0mdlc08 0000xxxxb 03fec209h can0 message configur ation register 08 c0mconf08 undefined 03fec20ah c0midl08 undefined 03fec20ch can0 message identifier register 08 c0midh08 undefined 03fec20eh can0 message control register 08 c0mctrl08 00x00000 000xx000b 03fec220h can0 message data byte 01 register 09 c0mdata0109 undefined 03fec220h can0 message data byte 0 register 09 c0mdata009 undefined 03fec221h can0 message data byte 1 register 09 c0mdata109 undefined 03fec222h can0 message data byte 23 register 09 c0mdata2309 undefined 03fec222h can0 message data byte 2 register 09 c0mdata209 undefined 03fec223h can0 message data byte 3 register 09 c0mdata309 undefined 03fec224h can0 message data byte 45 register 09 c0mdata4509 undefined 03fec224h can0 message data byte 4 register 09 c0mdata409 undefined 03fec225h can0 message data byte 5 register 09 c0mdata509 undefined 03fec226h can0 message data byte 67 register 09 c0mdata6709 undefined 03fec226h can0 message data byte 6 register 09 c0mdata609 undefined 03fec227h can0 message data byte 7 register 09 c0mdata709 undefined 03fec228h can0 message data length register 09 c0mdlc09 0000xxxxb 03fec229h can0 message configuration register 09 c0mconf09 undefined 03fec22ah c0midl09 undefined 03fec22ch can0 message identifier register 09 c0midh09 undefined 03fec22eh can0 message control register 09 c0mctrl09 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1061 of 1817 sep 19, 2011 table 21-16. register access types (7/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec240h can0 message data byte 01 register 10 c0mdata0110 undefined 03fec240h can0 message data byte 0 register 10 c0mdata010 undefined 03fec241h can0 message data byte 1 register 10 c0mdata110 undefined 03fec242h can0 message data byte 23 register 10 c0mdata2310 undefined 03fec242h can0 message data byte 2 register 10 c0mdata210 undefined 03fec243h can0 message data byte 3 register 10 c0mdata310 undefined 03fec244h can0 message data byte 45 register 10 c0mdata4510 undefined 03fec244h can0 message data byte 4 register 10 c0mdata410 undefined 03fec245h can0 message data byte 5 register 10 c0mdata510 undefined 03fec246h can0 message data byte 67 register 10 c0mdata6710 undefined 03fec246h can0 message data byte 6 register 10 c0mdata610 undefined 03fec247h can0 message data byte 7 register 10 c0mdata710 undefined 03fec248h can0 message data length register 10 c0mdlc10 0000xxxxb 03fec249h can0 message configur ation register 10 c0mconf10 undefined 03fec24ah c0midl10 undefined 03fec24ch can0 message identifier register 10 c0midh10 undefined 03fec24eh can0 message control register 10 c0mctrl10 00x00000 000xx000b 03fec260h can0 message data byte 01 register 11 c0mdata0111 undefined 03fec260h can0 message data byte 0 register 11 c0mdata011 undefined 03fec261h can0 message data byte 1 register 11 c0mdata111 undefined 03fec262h can0 message data byte 23 register 11 c0mdata2311 undefined 03fec262h can0 message data byte 2 register 11 c0mdata211 undefined 03fec263h can0 message data byte 3 register 11 c0mdata311 undefined 03fec264h can0 message data byte 45 register 11 c0mdata4511 undefined 03fec264h can0 message data byte 4 register 11 c0mdata411 undefined 03fec265h can0 message data byte 5 register 11 c0mdata511 undefined 03fec266h can0 message data byte 67 register 11 c0mdata6711 undefined 03fec266h can0 message data byte 6 register 11 c0mdata611 undefined 03fec267h can0 message data byte 7 register 11 c0mdata711 undefined 03fec268h can0 message data length register 11 c0mdlc11 0000xxxxb 03fec269h can0 message configuration register 11 c0mconf11 undefined 03fec26ah c0midl11 undefined 03fec26ch can0 message identifier register 11 c0midh11 undefined 03fec26eh can0 message control register 11 c0mctrl11 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1062 of 1817 sep 19, 2011 table 21-16. register access types (8/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec280h can0 message data byte 01 register 12 c0mdata0112 undefined 03fec280h can0 message data byte 0 register 12 c0mdata012 undefined 03fec281h can0 message data byte 1 register 12 c0mdata112 undefined 03fec282h can0 message data byte 23 register 12 c0mdata2312 undefined 03fec282h can0 message data byte 2 register 12 c0mdata212 undefined 03fec283h can0 message data byte 3 register 12 c0mdata312 undefined 03fec284h can0 message data byte 45 register 12 c0mdata4512 undefined 03fec284h can0 message data byte 4 register 12 c0mdata412 undefined 03fec285h can0 message data byte 5 register 12 c0mdata512 undefined 03fec286h can0 message data byte 67 register 12 c0mdata6712 undefined 03fec286h can0 message data byte 6 register 12 c0mdata612 undefined 03fec287h can0 message data byte 7 register 12 c0mdata712 undefined 03fec288h can0 message data length register 12 c0mdlc12 0000xxxxb 03fec289h can0 message configur ation register 12 c0mconf12 undefined 03fec28ah c0midl12 undefined 03fec28ch can0 message identifier register 12 c0midh12 undefined 03fec28eh can0 message control register 12 c0mctrl12 00x00000 000xx000b 03fec2a0h can0 message data byte 01 register 13 c0mdata0113 undefined 03fec2a0h can0 message data byte 0 register 13 c0mdata013 undefined 03fec2a1h can0 message data byte 1 register 13 c0mdata113 undefined 03fec2a2h can0 message data byte 23 register 13 c0mdata2313 undefined 03fec2a2h can0 message data byte 2 register 13 c0mdata213 undefined 03fec2a3h can0 message data byte 3 register 13 c0mdata313 undefined 03fec2a4h can0 message data byte 45 register 13 c0mdata4513 undefined 03fec2a4h can0 message data byte 4 register 13 c0mdata413 undefined 03fec2a5h can0 message data byte 5 register 13 c0mdata513 undefined 03fec2a6h can0 message data byte 67 register 13 c0mdata6713 undefined 03fec2a6h can0 message data byte 6 register 13 c0mdata613 undefined 03fec2a7h can0 message data byte 7 register 13 c0mdata713 undefined 03fec2a8h can0 message data length register 13 c0mdlc13 0000xxxxb 03fec2a9h can0 message configuration register 13 c0mconf13 undefined 03fec2aah c0midl13 undefined 03fec2ach can0 message identifier register 13 c0midh13 undefined 03fec2aeh can0 message control register 13 c0mctrl13 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1063 of 1817 sep 19, 2011 table 21-16. register access types (9/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec2c0h can0 message data byte 01 register 14 c0mdata0114 undefined 03fec2c0h can0 message data byte 0 register 14 c0mdata014 undefined 03fec2c1h can0 message data byte 1 register 14 c0mdata114 undefined 03fec2c2h can0 message data byte 23 register 14 c0mdata2314 undefined 03fec2c2h can0 message data byte 2 register 14 c0mdata214 undefined 03fec2c3h can0 message data byte 3 register 14 c0mdata314 undefined 03fec2c4h can0 message data byte 45 register 14 c0mdata4514 undefined 03fec2c4h can0 message data byte 4 register 14 c0mdata414 undefined 03fec2c5h can0 message data byte 5 register 14 c0mdata514 undefined 03fec2c6h can0 message data byte 67 register 14 c0mdata6714 undefined 03fec2c6h can0 message data byte 6 register 14 c0mdata614 undefined 03fec2c7h can0 message data byte 7 register 14 c0mdata714 undefined 03fec2c8h can0 message data length register 14 c0mdlc14 0000xxxxb 03fec2c9h can0 message configur ation register 14 c0mconf14 undefined 03fec2cah c0midl14 undefined 03fec2cch can0 message identifier register 14 c0midh14 undefined 03fec2ceh can0 message control register 14 c0mctrl14 00x00000 000xx000b 03fec2e0h can0 message data byte 01 register 15 c0mdata0115 undefined 03fec2e0h can0 message data byte 0 register 15 c0mdata015 undefined 03fec2e1h can0 message data byte 1 register 15 c0mdata115 undefined 03fec2e2h can0 message data byte 23 register 15 c0mdata2315 undefined 03fec2e2h can0 message data byte 2 register 15 c0mdata215 undefined 03fec2e3h can0 message data byte 3 register 15 c0mdata315 undefined 03fec2e4h can0 message data byte 45 register 15 c0mdata4515 undefined 03fec2e4h can0 message data byte 4 register 15 c0mdata415 undefined 03fec2e5h can0 message data byte 5 register 15 c0mdata515 undefined 03fec2e6h can0 message data byte 67 register 15 c0mdata6715 undefined 03fec2e6h can0 message data byte 6 register 15 c0mdata615 undefined 03fec2e7h can0 message data byte 7 register 15 c0mdata715 undefined 03fec2e8h can0 message data length register 15 c0mdlc15 0000xxxxb 03fec2e9h can0 message configuration register 15 c0mconf15 undefined 03fec2eah c0midl15 undefined 03fec2ech can0 message identifier register 15 c0midh15 undefined 03fec2eeh can0 message control register 15 c0mctrl15 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1064 of 1817 sep 19, 2011 table 21-16. register access types (10/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec300h can0 message data byte 01 register 16 c0mdata0116 undefined 03fec300h can0 message data byte 0 register 16 c0mdata016 undefined 03fec301h can0 message data byte 1 register 16 c0mdata116 undefined 03fec302h can0 message data byte 23 register 16 c0mdata2316 undefined 03fec302h can0 message data byte 2 register 16 c0mdata216 undefined 03fec303h can0 message data byte 3 register 16 c0mdata316 undefined 03fec304h can0 message data byte 45 register 16 c0mdata4516 undefined 03fec304h can0 message data byte 4 register 16 c0mdata416 undefined 03fec305h can0 message data byte 5 register 16 c0mdata516 undefined 03fec306h can0 message data byte 67 register 16 c0mdata6716 undefined 03fec306h can0 message data byte 6 register 16 c0mdata616 undefined 03fec307h can0 message data byte 7 register 16 c0mdata716 undefined 03fec308h can0 message data length register 16 c0mdlc16 0000xxxxb 03fec309h can0 message configurat ion register 16 c0mconf16 undefined 03fec30ah c0midl16 undefined 03fec30ch can0 message identifier register 16 c0midh16 undefined 03fec30eh can0 message control register 16 c0mctrl16 00x00000 000xx000b 03fec320h can0 message data byte 01 register 17 c0mdata0117 undefined 03fec320h can0 message data byte 0 register 17 c0mdata017 undefined 03fec321h can0 message data byte 1 register 17 c0mdata117 undefined 03fec322h can0 message data byte 23 register 17 c0mdata2317 undefined 03fec322h can0 message data byte 2 register 17 c0mdata217 undefined 03fec323h can0 message data byte 3 register 17 c0mdata317 undefined 03fec324h can0 message data byte 45 register 17 c0mdata4517 undefined 03fec324h can0 message data byte 4 register 17 c0mdata417 undefined 03fec325h can0 message data byte 5 register 17 c0mdata517 undefined 03fec326h can0 message data byte 67 register 17 c0mdata6717 undefined 03fec326h can0 message data byte 6 register 17 c0mdata617 undefined 03fec327h can0 message data byte 7 register 17 c0mdata717 undefined 03fec328h can0 message data length register 17 c0mdlc17 0000xxxxb 03fec329h can0 message configuration register 17 c0mconf17 undefined 03fec32ah c0midl17 undefined 03fec32ch can0 message identifier register 17 c0midh17 undefined 03fec32eh can0 message control register 17 c0mctrl17 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1065 of 1817 sep 19, 2011 table 21-16. register access types (11/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec340h can0 message data byte 01 register 18 c0mdata0118 undefined 03fec340h can0 message data byte 0 register 18 c0mdata018 undefined 03fec341h can0 message data byte 1 register 18 c0mdata118 undefined 03fec342h can0 message data byte 23 register 18 c0mdata2318 undefined 03fec342h can0 message data byte 2 register 18 c0mdata218 undefined 03fec343h can0 message data byte 3 register 18 c0mdata318 undefined 03fec344h can0 message data byte 45 register 18 c0mdata4518 undefined 03fec344h can0 message data byte 4 register 18 c0mdata418 undefined 03fec345h can0 message data byte 5 register 18 c0mdata518 undefined 03fec346h can0 message data byte 67 register 18 c0mdata6718 undefined 03fec346h can0 message data byte 6 register 18 c0mdata618 undefined 03fec347h can0 message data byte 7 register 18 c0mdata718 undefined 03fec348h can0 message data length register 18 c0mdlc18 0000xxxxb 03fec349h can0 message configurat ion register 18 c0mconf18 undefined 03fec34ah c0midl18 undefined 03fec34ch can0 message identifier register 18 c0midh18 undefined 03fec34eh can0 message control register 18 c0mctrl18 00x00000 000xx000b 03fec360h can0 message data byte 01 register 19 c0mdata0119 undefined 03fec360h can0 message data byte 0 register 19 c0mdata019 undefined 03fec361h can0 message data byte 1 register 19 c0mdata119 undefined 03fec362h can0 message data byte 23 register 19 c0mdata2319 undefined 03fec362h can0 message data byte 2 register 19 c0mdata219 undefined 03fec363h can0 message data byte 3 register 19 c0mdata319 undefined 03fec364h can0 message data byte 45 register 19 c0mdata4519 undefined 03fec364h can0 message data byte 4 register 19 c0mdata419 undefined 03fec365h can0 message data byte 5 register 19 c0mdata519 undefined 03fec366h can0 message data byte 67 register 19 c0mdata6719 undefined 03fec366h can0 message data byte 6 register 19 c0mdata619 undefined 03fec367h can0 message data byte 7 register 19 c0mdata719 undefined 03fec368h can0 message data length register 19 c0mdlc19 0000xxxxb 03fec369h can0 message configuration register 19 c0mconf19 undefined 03fec36ah c0midl19 undefined 03fec36ch can0 message identifier register 19 c0midh19 undefined 03fec36eh can0 message control register 19 c0mctrl19 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1066 of 1817 sep 19, 2011 table 21-16. register access types (12/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec380h can0 message data byte 01 register 20 c0mdata0120 undefined 03fec380h can0 message data byte 0 register 20 c0mdata020 undefined 03fec381h can0 message data byte 1 register 20 c0mdata120 undefined 03fec382h can0 message data byte 23 register 20 c0mdata2320 undefined 03fec382h can0 message data byte 2 register 20 c0mdata220 undefined 03fec383h can0 message data byte 3 register 20 c0mdata320 undefined 03fec384h can0 message data byte 45 register 20 c0mdata4520 undefined 03fec384h can0 message data byte 4 register 20 c0mdata420 undefined 03fec385h can0 message data byte 5 register 20 c0mdata520 undefined 03fec386h can0 message data byte 67 register 20 c0mdata6720 undefined 03fec386h can0 message data byte 6 register 20 c0mdata620 undefined 03fec387h can0 message data byte 7 register 20 c0mdata720 undefined 03fec388h can0 message data length register 20 c0mdlc20 0000xxxxb 03fec389h can0 message configurat ion register 20 c0mconf20 undefined 03fec38ah c0midl20 undefined 03fec38ch can0 message identifier register 20 c0midh20 undefined 03fec38eh can0 message control register 20 c0mctrl20 00x00000 000xx000b 03fec3a0h can0 message data byte 01 register 21 c0mdata0121 undefined 03fec3a0h can0 message data byte 0 register 21 c0mdata021 undefined 03fec3a1h can0 message data byte 1 register 21 c0mdata121 undefined 03fec3a2h can0 message data byte 23 register 21 c0mdata2321 undefined 03fec3a2h can0 message data byte 2 register 21 c0mdata221 undefined 03fec3a3h can0 message data byte 3 register 21 c0mdata321 undefined 03fec3a4h can0 message data byte 45 register 21 c0mdata4521 undefined 03fec3a4h can0 message data byte 4 register 21 c0mdata421 undefined 03fec3a5h can0 message data byte 5 register 21 c0mdata521 undefined 03fec3a6h can0 message data byte 67 register 21 c0mdata6721 undefined 03fec3a6h can0 message data byte 6 register 21 c0mdata621 undefined 03fec3a7h can0 message data byte 7 register 21 c0mdata721 undefined 03fec3a8h can0 message data length register 21 c0mdlc21 0000xxxxb 03fec3a9h can0 message configuration register 21 c0mconf21 undefined 03fec3aah c0midl21 undefined 03fec3ach can0 message identifier register 21 c0midh21 undefined 03fec3aeh can0 message control register 21 c0mctrl21 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1067 of 1817 sep 19, 2011 table 21-16. register access types (13/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec3c0h can0 message data byte 01 register 22 c0mdata0122 undefined 03fec3c0h can0 message data byte 0 register 22 c0mdata022 undefined 03fec3c1h can0 message data byte 1 register 22 c0mdata122 undefined 03fec3c2h can0 message data byte 23 register 22 c0mdata2322 undefined 03fec3c2h can0 message data byte 2 register 22 c0mdata222 undefined 03fec3c3h can0 message data byte 3 register 22 c0mdata322 undefined 03fec3c4h can0 message data byte 45 register 22 c0mdata4522 undefined 03fec3c4h can0 message data byte 4 register 22 c0mdata422 undefined 03fec3c5h can0 message data byte 5 register 22 c0mdata522 undefined 03fec3c6h can0 message data byte 67 register 22 c0mdata6722 undefined 03fec3c6h can0 message data byte 6 register 22 c0mdata622 undefined 03fec3c7h can0 message data byte 7 register 22 c0mdata722 undefined 03fec3c8h can0 message data length register 22 c0mdlc22 0000xxxxb 03fec3c9h can0 message configur ation register 22 c0mconf22 undefined 03fec3cah c0midl22 undefined 03fec3cch can0 message identifier register 22 c0midh22 undefined 03fec3ceh can0 message control register 22 c0mctrl22 00x00000 000xx000b 03fec3e0h can0 message data byte 01 register 23 c0mdata0123 undefined 03fec3e0h can0 message data byte 0 register 23 c0mdata023 undefined 03fec3e1h can0 message data byte 1 register 23 c0mdata123 undefined 03fec3e2h can0 message data byte 23 register 23 c0mdata2323 undefined 03fec3e2h can0 message data byte 2 register 23 c0mdata223 undefined 03fec3e3h can0 message data byte 3 register 23 c0mdata323 undefined 03fec3e4h can0 message data byte 45 register 23 c0mdata4523 undefined 03fec3e4h can0 message data byte 4 register 23 c0mdata423 undefined 03fec3e5h can0 message data byte 5 register 23 c0mdata523 undefined 03fec3e6h can0 message data byte 67 register 23 c0mdata6723 undefined 03fec3e6h can0 message data byte 6 register 23 c0mdata623 undefined 03fec3e7h can0 message data byte 7 register 23 c0mdata723 undefined 03fec3e8h can0 message data length register 23 c0mdlc23 0000xxxxb 03fec3e9h can0 message configuration register 23 c0mconf23 undefined 03fec3eah c0midl23 undefined 03fec3ech can0 message identifier register 23 c0midh23 undefined 03fec3eeh can0 message control register 23 c0mctrl23 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1068 of 1817 sep 19, 2011 table 21-16. register access types (14/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec400h can0 message data byte 01 register 24 c0mdata0124 undefined 03fec400h can0 message data byte 0 register 24 c0mdata024 undefined 03fec401h can0 message data byte 1 register 24 c0mdata124 undefined 03fec402h can0 message data byte 23 register 24 c0mdata2324 undefined 03fec402h can0 message data byte 2 register 24 c0mdata224 undefined 03fec403h can0 message data byte 3 register 24 c0mdata324 undefined 03fec404h can0 message data byte 45 register 24 c0mdata4524 undefined 03fec404h can0 message data byte 4 register 24 c0mdata424 undefined 03fec405h can0 message data byte 5 register 24 c0mdata524 undefined 03fec406h can0 message data byte 67 register 24 c0mdata6724 undefined 03fec406h can0 message data byte 6 register 24 c0mdata624 undefined 03fec407h can0 message data byte 7 register 24 c0mdata724 undefined 03fec408h can0 message data length register 24 c0mdlc24 0000xxxxb 03fec409h can0 message configurat ion register 24 c0mconf24 undefined 03fec40ah c0midl24 undefined 03fec40ch can0 message identifier register 24 c0midh24 undefined 03fec40eh can0 message control register 24 c0mctrl24 00x00000 000xx000b 03fec420h can0 message data byte 01 register 25 c0mdata0125 undefined 03fec420h can0 message data byte 0 register 25 c0mdata025 undefined 03fec421h can0 message data byte 1 register 25 c0mdata125 undefined 03fec422h can0 message data byte 23 register 25 c0mdata2325 undefined 03fec422h can0 message data byte 2 register 25 c0mdata225 undefined 03fec423h can0 message data byte 3 register 25 c0mdata325 undefined 03fec424h can0 message data byte 45 register 25 c0mdata4525 undefined 03fec424h can0 message data byte 4 register 25 c0mdata425 undefined 03fec425h can0 message data byte 5 register 25 c0mdata525 undefined 03fec426h can0 message data byte 67 register 25 c0mdata6725 undefined 03fec426h can0 message data byte 6 register 25 c0mdata625 undefined 03fec427h can0 message data byte 7 register 25 c0mdata725 undefined 03fec428h can0 message data length register 25 c0mdlc25 0000xxxxb 03fec429h can0 message configuration register 25 c0mconf25 undefined 03fec42ah c0midl25 undefined 03fec42ch can0 message identifier register 25 c0midh25 undefined 03fec42eh can0 message control register 25 c0mctrl25 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1069 of 1817 sep 19, 2011 table 21-16. register access types (15/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec440h can0 message data byte 01 register 26 c0mdata0126 undefined 03fec440h can0 message data byte 0 register 26 c0mdata026 undefined 03fec441h can0 message data byte 1 register 26 c0mdata126 undefined 03fec442h can0 message data byte 23 register 26 c0mdata2326 undefined 03fec442h can0 message data byte 2 register 26 c0mdata226 undefined 03fec443h can0 message data byte 3 register 26 c0mdata326 undefined 03fec444h can0 message data byte 45 register 26 c0mdata4526 undefined 03fec444h can0 message data byte 4 register 26 c0mdata426 undefined 03fec445h can0 message data byte 5 register 26 c0mdata526 undefined 03fec446h can0 message data byte 67 register 26 c0mdata6726 undefined 03fec446h can0 message data byte 6 register 26 c0mdata626 undefined 03fec447h can0 message data byte 7 register 26 c0mdata726 undefined 03fec448h can0 message data length register 26 c0mdlc26 0000xxxxb 03fec449h can0 message configurat ion register 26 c0mconf26 undefined 03fec44ah c0midl26 undefined 03fec44ch can0 message identifier register 26 c0midh26 undefined 03fec44eh can0 message control register 26 c0mctrl26 00x00000 000xx000b 03fec460h can0 message data byte 01 register 27 c0mdata0127 undefined 03fec460h can0 message data byte 0 register 27 c0mdata027 undefined 03fec461h can0 message data byte 1 register 27 c0mdata127 undefined 03fec462h can0 message data byte 23 register 27 c0mdata2327 undefined 03fec462h can0 message data byte 2 register 27 c0mdata227 undefined 03fec463h can0 message data byte 3 register 27 c0mdata327 undefined 03fec464h can0 message data byte 45 register 27 c0mdata4527 undefined 03fec464h can0 message data byte 4 register 27 c0mdata427 undefined 03fec465h can0 message data byte 5 register 27 c0mdata527 undefined 03fec466h can0 message data byte 67 register 27 c0mdata6727 undefined 03fec466h can0 message data byte 6 register 27 c0mdata627 undefined 03fec467h can0 message data byte 7 register 27 c0mdata727 undefined 03fec468h can0 message data length register 27 c0mdlc27 0000xxxxb 03fec469h can0 message configuration register 27 c0mconf27 undefined 03fec46ah c0midl27 undefined 03fec46ch can0 message identifier register 27 c0midh27 undefined 03fec46eh can0 message control register 27 c0mctrl27 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1070 of 1817 sep 19, 2011 table 21-16. register access types (16/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec480h can0 message data byte 01 register 28 c0mdata0128 undefined 03fec480h can0 message data byte 0 register 28 c0mdata028 undefined 03fec481h can0 message data byte 1 register 28 c0mdata128 undefined 03fec482h can0 message data byte 23 register 28 c0mdata2328 undefined 03fec482h can0 message data byte 2 register 28 c0mdata228 undefined 03fec483h can0 message data byte 3 register 28 c0mdata328 undefined 03fec484h can0 message data byte 45 register 28 c0mdata4528 undefined 03fec484h can0 message data byte 4 register 28 c0mdata428 undefined 03fec485h can0 message data byte 5 register 28 c0mdata528 undefined 03fec486h can0 message data byte 67 register 28 c0mdata6728 undefined 03fec486h can0 message data byte 6 register 28 c0mdata628 undefined 03fec487h can0 message data byte 7 register 28 c0mdata728 undefined 03fec488h can0 message data length register 28 c0mdlc28 0000xxxxb 03fec489h can0 message configurat ion register 28 c0mconf28 undefined 03fec48ah c0midl28 undefined 03fec48ch can0 message identifier register 28 c0midh28 undefined 03fec48eh can0 message control register 28 c0mctrl28 00x00000 000xx000b 03fec4a0h can0 message data byte 01 register 29 c0mdata0129 undefined 03fec4a0h can0 message data byte 0 register 29 c0mdata029 undefined 03fec4a1h can0 message data byte 1 register 29 c0mdata129 undefined 03fec4a2h can0 message data byte 23 register 29 c0mdata2329 undefined 03fec4a2h can0 message data byte 2 register 29 c0mdata229 undefined 03fec4a3h can0 message data byte 3 register 29 c0mdata329 undefined 03fec4a4h can0 message data byte 45 register 29 c0mdata4529 undefined 03fec4a4h can0 message data byte 4 register 29 c0mdata429 undefined 03fec4a5h can0 message data byte 5 register 29 c0mdata529 undefined 03fec4a6h can0 message data byte 67 register 29 c0mdata6729 undefined 03fec4a6h can0 message data byte 6 register 29 c0mdata629 undefined 03fec4a7h can0 message data byte 7 register 29 c0mdata729 undefined 03fec4a8h can0 message data length register 29 c0mdlc29 0000xxxxb 03fec4a9h can0 message configuration register 29 c0mconf29 undefined 03fec4aah c0midl29 undefined 03fec4ach can0 message identifier register 29 c0midh29 undefined 03fec4aeh can0 message control register 29 c0mctrl29 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1071 of 1817 sep 19, 2011 table 21-16. register access types (17/17) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset 03fec4c0h can0 message data byte 01 register 30 c0mdata0130 undefined 03fec4c0h can0 message data byte 0 register 30 c0mdata030 undefined 03fec4c1h can0 message data byte 1 register 30 c0mdata130 undefined 03fec4c2h can0 message data byte 23 register 30 c0mdata2330 undefined 03fec4c2h can0 message data byte 2 register 30 c0mdata230 undefined 03fec4c3h can0 message data byte 3 register 30 c0mdata330 undefined 03fec4c4h can0 message data byte 45 register 30 c0mdata4530 undefined 03fec4c4h can0 message data byte 4 register 30 c0mdata430 undefined 03fec4c5h can0 message data byte 5 register 30 c0mdata530 undefined 03fec4c6h can0 message data byte 67 register 30 c0mdata6730 undefined 03fec4c6h can0 message data byte 6 register 30 c0mdata630 undefined 03fec4c7h can0 message data byte 7 register 30 c0mdata730 undefined 03fec4c8h can0 message data length register 30 c0mdlc30 0000xxxxb 03fec4c9h can0 message configur ation register 30 c0mconf30 undefined 03fec4cah c0midl30 undefined 03fec4cch can0 message identifier register 30 c0midh30 undefined 03fec4ceh can0 message control register 30 c0mctrl30 00x00000 000xx000b 03fec4e0h can0 message data byte 01 register 31 c0mdata0131 undefined 03fec4e0h can0 message data byte 0 register 31 c0mdata031 undefined 03fec4e1h can0 message data byte 1 register 31 c0mdata131 undefined 03fec4e2h can0 message data byte 23 register 31 c0mdata2331 undefined 03fec4e2h can0 message data byte 2 register 31 c0mdata231 undefined 03fec4e3h can0 message data byte 3 register 31 c0mdata331 undefined 03fec4e4h can0 message data byte 45 register 31 c0mdata4531 undefined 03fec4e4h can0 message data byte 4 register 31 c0mdata431 undefined 03fec4e5h can0 message data byte 5 register 31 c0mdata531 undefined 03fec4e6h can0 message data byte 67 register 31 c0mdata6731 undefined 03fec4e6h can0 message data byte 6 register 31 c0mdata631 undefined 03fec4e7h can0 message data byte 7 register 31 c0mdata731 undefined 03fec4e8h can0 message data length register 31 c0mdlc31 0000xxxxb 03fec4e9h can0 message configuration register 31 c0mconf31 undefined 03fec4eah c0midl31 undefined 03fec4ech can0 message identifier register 31 c0midh31 undefined 03fec4eeh can0 message control register 31 c0mctrl31 r/w 00x00000 000xx000b v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1072 of 1817 sep 19, 2011 21.5.3 register bit configuration table 21-17. can global register bit configuration address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 03fec000h 0 0 0 0 0 0 0 clear gom 03fec001h c0gmctrl (w) 0 0 0 0 0 0 set efsd set gom 03fec000h 0 0 0 0 0 0 efsd gom 03fec001h c0gmctrl (r) mbon 0 0 0 0 0 0 0 03fec002h c0gmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 03fec006h 0 0 0 0 0 0 0 clear abttrg 03fec007h c0gmabt (w) 0 0 0 0 0 0 set abtclr set abttrg 03fec006h 0 0 0 0 0 0 abtclr abttrg 03fec007h c0gmabt (r) 0 0 0 0 0 0 0 0 03fec008h c0gmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1073 of 1817 sep 19, 2011 table 21-18. can module register bit configuration (1/2) address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 03fec040h cmid7 to cmid0 03fec041h c0mask1l cmid15 to cmid8 03fec042h cmid23 to cmid16 03fec043h c0mask1h 0 0 0 cmid28 to cmid24 03fec044h cmid7 to cmid0 03fec045h c0mask2l cmid15 to cmid8 03fec046h cmid23 to cmid16 03fec047h c0mask2h 0 0 0 cmid28 to cmid24 03fec048h cmid7 to cmid0 03fec049h c0mask3l cmid15 to cmid8 03fec04ah cmid23 to cmid16 03fec04bh c0mask3h 0 0 0 cmid28 to cmid24 03fec04ch cmid7 to cmid0 03fec04dh c0mask4l cmid15 to cmid8 03fec04eh cmid23 to cmid16 03fec04fh c0mask4h 0 0 0 cmid28 to cmid24 03fec050h 0 clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 03fec051h c0ctrl (w) set ccerc set al 0 set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 03fec050h ccerc al valid ps mode1 ps mode0 op mode2 op mode1 op mode0 03fec051h c0ctrl (r) 0 0 0 0 0 0 rstat tstat 03fec052h c0lec (w) 0 0 0 0 0 0 0 0 03fec052h c0lec (r) 0 0 0 0 0 lec2 lec1 lec0 03fec053h c0info 0 0 0 boff tecs1 tecs0 recs1 recs0 03fec054h tec7 to tec0 03fec055h c0erc rec7 to rec0 03fec056h 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 03fec057h c0ie (w) 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 03fec056h 0 0 cie5 cie4 cie3 cie2 cie1 cie0 03fec057h c0ie (r) 0 0 0 0 0 0 0 0 03fec058h 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 03fec059h c0ints (w) 0 0 0 0 0 0 0 0 03fec058h 0 0 cints5 cints4 cints3 cints2 cints1 cints0 03fec059h c0ints (r) 0 0 0 0 0 0 0 0 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1074 of 1817 sep 19, 2011 table 21-18. can module register bit configuration (2/2) address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 03fec05ah c0brp tqprs7 to tqprs0 03fec05ch 0 0 0 0 tseg13 to tseg10 03fec05dh c0btr 0 0 sjw1, sjw0 0 tseg22 to tseg20 03fec05eh c0lipt lipt7 to lipt0 03fec060h 0 0 0 0 0 0 0 clear rovf 03fec061h c0rgpt (w) 0 0 0 0 0 0 0 0 03fec060h 0 0 0 0 0 0 rhpm rovf 03fec061h c0rgpt (r) rgpt7 to rgpt0 03fec062h c0lopt lopt7 to lopt0 03fec064h 0 0 0 0 0 0 0 clear tovf 03fec065h c0tgpt (w) 0 0 0 0 0 0 0 0 03fec064h 0 0 0 0 0 0 thpm tovf 03fec065h c0tgpt (r) tgpt7 to tgpt0 03fec066h 0 0 0 0 0 clear tslock clear tssel clear tsen 03fec067h c0ts (w) 0 0 0 0 0 set tslock set tssel set tsen 03fec066h 0 0 0 0 0 tslock tssel tsen 03fec067h c0ts (r) 0 0 0 0 0 0 0 0 03fec068h to 03fec0ffh ? access prohibited (reserved for future use) v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1075 of 1817 sep 19, 2011 table 21-19. message buffer register bit configuration address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 03fecxx0h message data (byte 0) 03fecxx1h c0mdata01m message data (byte 1) 03fecxx0h c0mdata0m message data (byte 0) 03fecxx1h c0mdata1m message data (byte 1) 03fecxx2h message data (byte 2) 03fecxx3h c0mdata23m message data (byte 3) 03fecxx2h c0mdata2m message data (byte 2) 03fecxx3h c0mdata3m message data (byte 3) 03fecxx4h message data (byte 4) 03fecxx5h c0mdata45m message data (byte 5) 03fecxx4h c0mdata4m message data (byte 4) 03fecxx5h c0mdata5m message data (byte 5) 03fecxx6h message data (byte 6) 03fecxx7h c0mdata67m message data (byte 7) 03fecxx6h c0mdata6m message data (byte 6) 03fecxx7h c0mdata7m message data (byte 7) 03fecxx8h c0mdlcm 0 mdlc3 mdlc2 mdlc1 mdlc0 03fecxx9h c0mconfm ows rtr mt2 mt1 mt0 0 0 ma0 03fecxxah id7 id6 id5 id4 id3 id2 id1 id0 03fecxxbh c0midlm id15 id14 id13 id12 id11 id10 id9 id8 03fecxxch id23 id22 id21 id20 id19 id18 id17 id16 03fecxxdh c0midhm ide 0 0 id28 id27 id26 id25 id24 03fecxxeh 0 0 0 clear mow clear ie clear dn clear trq clear rdy 03fecxxfh c0mctrlm (w) 0 0 0 0 set ie 0 set trq set rdy 03fecxxeh 0 0 0 mow ie dn trq rdy 03fecxxfh c0mctrlm (r) 0 0 muc 0 0 0 0 0 03fecxx0 to 03fecxxfh ? access prohibited (reserved for future use) remark m = 00 to 31 xx = 10, 12, 14, 16, 18, 1a, 1c, 1e, 20, 22, 24, 26, 28, 2a, 2c, 2e, 30, 32, 34, 36, 38, 3a, 3c, 3e, 40, 42, 44, 46, 48, 4a, 4c, 4e v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1076 of 1817 sep 19, 2011 21.6 registers caution accessing the can controller registers is prohibite d in the following statuses. for details, refer to 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock remark m = 00 to 31 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1077 of 1817 sep 19, 2011 (1) can0 global control register (c0gmctrl) the c0gmctrl register is used to cont rol the operation of the can module. (1/2) after reset: 0000h r/w address: 03fec000h (a) read 15 14 13 12 11 10 9 8 c0gmctrl mbon 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 efsd gom (b) write 15 14 13 12 11 10 9 8 c0gmctrl 0 0 0 0 0 0 set efsd set gom 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear gom (a) read mbon bit enabling access to message buffer regi ster, transmit/receive history registers 0 write access and read access to the message buffer register and the transm it/receive history list registers is disabled. 1 write access and read access to the message buffer register and the transm it/receive history list registers is enabled. cautions 1. while the mbon bit is cleared (to 0), software access to the message buffers (c0mdata0m, c0mdata1m, c0mdata01m, c0mdata2m, c0mdata3m, c0mdata23m, c0mdata4m, c0mdata5m, c0mdata45m, c0mdata6m, c0mdata7m, c0mdata67m, c0mdlcm, c0mconfm, c0midlm, c0midhm, a nd c0mctrlm), or registers related to transmit history or receive history (c0lopt, c0tgpt, c0lipt, and c0rgpt) is disabled. 2. this bit is read-only. even if 1 is written to the mbon bit while it is 0, the value of the mbon bit does not change, and access to th e message buffer registers, or registers related to transmit history or receive history remains disabled. remark when the can sleep mode/can stop mode is entered , or when the gom bit is cleared to 0, the mbon bit is cleared to 0. when the can sleep mode/can stop mode is released, or when the gom bit is set to 1, the mbon bit is set to 1. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1078 of 1817 sep 19, 2011 (2/2) efsd bit enabling forced shut down 0 forced shut down by gom bit = 0 disabled. 1 forced shut down by gom bit = 0 enabled. caution to request forced shut down, clear the gom bit to 0 immediately afte r the efsd bit has been set to 1. if access to another register (incl uding reading the c0gmct rl register) is executed without clearing the gom bit immedi ately after the efsd bit has been set to 1, the efsd bit is forcibly cleared to 0, and the for ced shut down request is invalid. gom global operation mode bit 0 can module is disabled from operating. 1 can module is enabled to operate. caution the gom bit is clear ed to 0 only in the initia lization mode or immediatel y after the efsd bit is set to 1. (b) write set efsd efsd bit setting 0 no change in efsd bit. 1 efsd bit set to 1. set gom clear gom gom bit setting 0 1 gom bit cleared to 0. 1 0 gom bit set to 1. other than above no change in gom bit. caution be sure to set the gom bit and efsd bit separately. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1079 of 1817 sep 19, 2011 (2) can0 global clock selection register (c0gmcs) the c0gmcs register is used to select the can module system clock. after reset: 0fh r/w address: 03fec002h 7 6 5 4 3 2 1 0 c0gmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 ccp3 ccp2 ccp1 ccp0 can module system clock (f canmod ) 0 0 0 0 f can /1 0 0 0 1 f can /2 0 0 1 0 f can /3 0 0 1 1 f can /4 0 1 0 0 f can /5 0 1 0 1 f can /6 0 1 1 0 f can /7 0 1 1 1 f can /8 1 0 0 0 f can /9 1 0 0 1 f can /10 1 0 1 0 f can /11 1 0 1 1 f can /12 1 1 0 0 f can /13 1 1 0 1 f can /14 1 1 1 0 f can /15 1 1 1 1 f can /16 (default value) caution make sure that f xx = 32 to 50 mhz. remark f can = f xx /2 f can : can clock frequency f xx : main clock frequency f xmpll : pll output clock frequency for peripheral clocks v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1080 of 1817 sep 19, 2011 (3) can0 global automatic block transm ission control register (c0gmabt) the c0gmabt register is used to control the automatic block transmission (abt) operation. (1/2) after reset: 0000h r/w address: 03fec006h (a) read 15 14 13 12 11 10 9 8 c0gmabt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 abtclr abttrg (b) write 15 14 13 12 11 10 9 8 c0gmabt 0 0 0 0 0 0 set abtclr set abttrg 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear abttrg caution before changing the normal operation mode with abt to the init ialization mode, be sure to set the c0gmabt register to the de fault value (0000h). after se tting, confirm that the c0gmabt register is initialized to 0000h. (a) read abtclr automatic block transmi ssion engine clear status bit 0 clearing the automatic transmission engine is completed. 1 the automatic transmissi on engine is being cleared. remarks 1. set the abtclr bit to 1 while t he abttrg bit is cleared to 0. the operation is not guaranteed if the abtclr bit is set to 1 while the abttrg bit is set to 1. 2. when the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared to 0 as so on as the requested clearing processing is complete. abttrg automatic block transmission status bit 0 automatic block transmission is stopped. 1 automatic block transmissi on is under execution. cautions 1. do not set the abttrg bit to 1 in the in itialization mode. if the abttrg bit is set to 1 in the initialization mode, the ope ration is not guaranteed afte r the can module has entered the normal operation mode with abt. 2. do not set the abttrg bit to 1 while the c0ct rl.tstat bit is set to 1. directly confirm that the tstat bit = 0 before setting the abttrg bit to 1. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1081 of 1817 sep 19, 2011 (2/2) (b) write set abtclr automatic block trans mission engine clear request bit 0 the automatic block transmission engine is in idle status or under operation. 1 request to clear the automatic block transmissi on engine. after the automatic block transmission engine has been cleared, automatic block transmission is started from message buffer 0 by setting the abttrg bit to 1. set abttrg clear abttrg automatic block tr ansmission start bit 0 1 request to stop automatic block transmission. 1 0 request to start automatic block transmission. other than above no change in abttrg bit. caution even if the abttrg bit is set (1), transm ission is not immediately executed, depending on the situation such as when a mes sage is received from another node or when a message other than the abt message (message buffers 8 to 31) is transmitted. even if the abttrg bit is cleared (0), transmi ssion is not terminated mi dway. if transmission is under execution, it is continued until comp leted (regardless of whether transmission is successful or fails). v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1082 of 1817 sep 19, 2011 (4) can0 global automatic block transm ission delay register (c0gmabtd) the c0gmabtd register is used to set the interval at wh ich the data of the message buffer assigned to abt is to be transmitted in the normal operation mode with abt. after reset: 00h r/w address: 03fec008h 7 6 5 4 3 2 1 0 c0gmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0 abtd3 abtd2 abtd1 abtd0 data frame interval during aut omatic block transmission (unit: data bit time (dbt)) 0 0 0 0 0 dbt (default value) 0 0 0 1 2 5 dbt 0 0 1 0 2 6 dbt 0 0 1 1 2 7 dbt 0 1 0 0 2 8 dbt 0 1 0 1 2 9 dbt 0 1 1 0 2 10 dbt 0 1 1 1 2 11 dbt 1 0 0 0 2 12 dbt other than above setting prohibited cautions 1. do not change the contents of the c0 gmabtd register while the abttrg bit is set to 1. 2. the timing at which the abt message is actually transmitted onto the can bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an abt mess age (message buffers 8 to 31) is made. 3. be sure to set bits 4 to 7 to ?0?. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1083 of 1817 sep 19, 2011 (5) can0 module mask control register (c0mas kal, c0maskah) (a = 1, 2, 3, or 4) the c0maskal and c0maskah registers are used to ext end the number of receivable messages in the same message buffer by masking part of the identifier (id) of a message and invalidating the id comparison of the masked part. (1/2) ? can0 module mask 1 register (c0mask1l, c0mask1h) after reset: undefined r/w address: c0mask1l 03fec040h, c0mask1h 03fec042h 15 14 13 12 11 10 9 8 c0mask1l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 c0mask1h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 ? can0 module mask 2 register (c0mask2l, c0mask2h) after reset: undefined r/w address: c0mask2l 03fec044h, c0mask2h 03fec046h 15 14 13 12 11 10 9 8 c0mask2l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 c0mask2h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1084 of 1817 sep 19, 2011 (2/2) ? can0 module mask 3 register (c0mask3l, c0mask3h) after reset: undefined r/w address: c0mask3l 03fec048h, c0mask3h 03fec04ah 15 14 13 12 11 10 9 8 c0mask3l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 c0mask3h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 ? can0 module mask 4 register (c0mask4l, c0mask4h) after reset: undefined r/w address: c0mask4l 03fec04ch, c0mask4h 03fec04eh 15 14 13 12 11 10 9 8 c0mask4l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 7 6 5 4 3 2 1 0 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 15 14 13 12 11 10 9 8 c0mask4h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 7 6 5 4 3 2 1 0 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmid28 to cmid0 mask pattern setting of id bit 0 the id bits of the message buffer set by the cmid28 to cmid0 bits are compared with the id bits of the received message frame. 1 the id bits of the message buffer set by the cmid28 to cmid0 bits are not compared with the id bits of the received message frame (they are masked). caution be sure to set bits 13 to 15 of the c0maskah register to 0. remark masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, the cmid17 to cmid0 bits are ignored. therefore, only the cm id28 to cmid18 bits of the received id are masked. the same mask c an be used for both the standard and extended ids. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1085 of 1817 sep 19, 2011 (6) can0 module control register (c0ctrl) the c0ctrl register is used to control the operation mode of the can module. (1/4) after reset: 0000h r/w address: 03fec050h (a) read 15 14 13 12 11 10 9 8 c0ctrl 0 0 0 0 0 0 rstat tstat 7 6 5 4 3 2 1 0 ccerc al valid psmode 1 psmode 0 opmode 2 opmode 1 opmode 0 (b) write 15 14 13 12 11 10 9 8 c0ctrl set ccerc set al 0 set psmode 1 set psmode 0 set opmode 2 set opmode 1 set opmode 0 7 6 5 4 3 2 1 0 0 clear al clear valid clear psmode 1 clear psmode 0 clear opmode 2 clear opmode 1 clear opmode 0 (a) read rstat reception status bit 0 reception is stopped. 1 reception is in progress. remark ? the rstat bit is set to 1 under the following conditions (timing) ? the sof bit of a receive frame is detected ? on occurrence of arbitration loss during a transmit frame ? the rstat bit is cleared to 0 under the following conditions (timing) ? when a recessive level is detected at the second bit of the interframe space ? on transition to the initialization mode at the first bit of the interframe space tstat transmission status bit 0 transmission is stopped. 1 transmission is in progress. remark ? the tstat bit is set to 1 under the following conditions (timing) ? the sof bit of a transmit frame is detected ? the tstat bit is cleared to 0 under the following conditions (timing) ? during transition to bus-off status ? on occurrence of arbitration loss in transmit frame ? on detection of recessive level at t he second bit of the interframe space ? on transition to the initialization mode at the first bit of the interframe space v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1086 of 1817 sep 19, 2011 (2/4) ccerc error counter clear bit 0 the c0erc and c0info registers are not cleared in the initialization mode. 1 the c0erc and c0info registers are cleared in the initialization mode. remarks 1. the ccerc bit is used to clear the c0erc and c0 info registers for re-initialization or forced recovery from the bus-off status. this bit c an be set to 1 only in the initialization mode. 2. when the c0erc and c0info registers have been cleared, the ccerc bit is also cleared to 0 automatically. 3. the ccerc bit can be set to 1 at the same time as a request to change the initialization mode to an operation mode is made. 4. if the ccerc bit is set to 1 immediately after the init mode is entered in t he self test mode, the receive data may be corrupted. al bit to set operation in case of arbitration loss 0 re-transmission is not executed in case of an arbitration loss in the single-shot mode. 1 re-transmission is executed in case of an arbitration loss in the single-shot mode. remark the al bit is valid only in the single-shot mode. valid valid receive message frame detection bit 0 a valid message frame has not been received since the valid bit was last cleared to 0. 1 a valid message frame has been received since the valid bit was last cleared to 0. remarks 1. detection of a valid receive message fram e is not dependent upon the existence or non- existence of the storage in the receive message buffer (data frame) or transmit message buffer (remote frame). 2. clear the valid bit (0) before changing the initialization mode to an operation mode. 3. if only two can nodes are connected to the can bus with one transmitting a message frame in the normal mode and the other in the receive- only mode, since no ack is generated in the receive-only mode, the valid bit is not set to 1 before the transmitting node enters the error passive status. 4. to clear the valid bit, set the clear valid bit to 1 first and confirm that the valid bit is cleared. if it is not cleared, perform clearing processing again. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1087 of 1817 sep 19, 2011 (3/4) psmode1 psmode0 power save mode 0 0 no power save mode is selected. 0 1 can sleep mode 1 0 setting prohibited 1 1 can stop mode cautions 1. transition to and from the can stop mode must be made via can sleep mode. a request for direct transition to and fr om the can stop mode is ignored. 2. after releasing the power save mode, the c0 gmctrl.mbon flag must be checked before accessing the messag e buffer again. 3. a request for transition to the can sleep mode is held pe nding until it is canceled by software or until the can bus enters the bus idle state. the software can check transition to the can sleep mode by readi ng the psmode0 and psmode1 bits. opmode2 opmode1 opmode0 operation mode 0 0 0 no operation mode is selected (can module is in the initialization mode). 0 0 1 normal operation mode 0 1 0 normal operation mode with automat ic block transmission function (normal operation mode with abt) 0 1 1 receive-only mode 1 0 0 single-shot mode 1 0 1 self-test mode other than above setting prohibited caution it may take time to change the mode to the initialization m ode or power save mode. therefore, be sure to check if the mode has been successfully changed, by reading the register value before executing the processing. remark the opmode0 to opmode2 bits are read- only in the can sleep mode or can stop mode. (b) write set ccerc setting of ccerc bit 1 ccerc bit is set to 1. other than above ccerc bit is not changed. set al clear al setting of al bit 0 1 al bit is cleared to 0. 1 0 al bit is set to 1. other than above al bit is not changed. clear valid setting of valid bit 0 valid bit is not changed. 1 valid bit is cleared to 0. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1088 of 1817 sep 19, 2011 (4/4) set psmode0 clear psmode0 setting of psmode0 bit 0 1 psmode0 bit is cleared to 0. 1 0 psmode bit is set to 1. other than above psmode0 bit is not changed. set psmode1 clear psmode1 setting of psmode1 bit 0 1 psmode1 bit is cleared to 0. 1 0 psmode1 bit is set to 1. other than above psmode1 bit is not changed. set opmode0 clear opmode0 setting of opmode0 bit 0 1 opmode0 bit is cleared to 0. 1 0 opmode0 bit is set to 1. other than above opmode0 bit is not changed. set opmode1 clear opmode1 setting of opmode1 bit 0 1 opmode1 bit is cleared to 0. 1 0 opmode1 bit is set to 1. other than above opmode1 bit is not changed. set opmode2 clear opmode2 setting of opmode2 bit 0 1 opmode2 bit is cleared to 0. 1 0 opmode2 bit is set to 1. other than above opmode2 bit is not changed. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1089 of 1817 sep 19, 2011 (7) can0 module last error in formation register (c0lec) the c0lec register provides the erro r information of the can protocol. after reset: 00h r/w address: 03fec052h 7 6 5 4 3 2 1 0 c0lec 0 0 0 0 0 lec2 lec1 lec0 lec2 lec1 lec0 last can protocol error information 0 0 0 no error 0 0 1 stuff error 0 1 0 form error 0 1 1 ack error 1 0 0 bit error. (the can module tried to transm it a recessive-level bit as part of a transmit message (except the arbitration fi eld), but the value on the can bus is a dominant-level bit.) 1 0 1 bit error. (the can module tried to tran smit a dominant-level bit as part of a transmit message, ack bit, error frame, or overload frame, but the value on the can bus is a recessive-level bit.) 1 1 0 crc error 1 1 1 undefined caution be sure to set bits 3 to 7 to ?0?. remarks 1. the contents of the c0lec r egister are not cleared when t he can module changes from an operation mode to the initialization mode. 2. if an attempt is made to write a value other than 00h to the c0lec register by software, the access is ignored. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1090 of 1817 sep 19, 2011 (8) can0 module information register (c0info) the c0info register indicates the status of the can module. after reset: 00h r address: 03fec053h 7 6 5 4 3 2 1 0 c0info 0 0 0 boff tecs1 tecs0 recs1 recs0 boff bus-off status bit 0 not bus-off status (transmit error counter 255). (the value of the transmi t counter is less than 256.) 1 bus-off status (transmit error counter > 255). (the value of the transmit error counter is 256 or more.) tecs1 tecs0 transmission e rror counter status bit 0 0 the value of the transmission error counter is less than that of the warning level ( < 96). 0 1 the value of the transmission error counter is in the range of the warning level (96 to 127). 1 0 undefined 1 1 the value of the transmission error counter is in the range of the error passive or bus-off status ( 128). recs1 recs0 reception error counter status bit 0 0 the value of the reception error counter is less than that of the warning level ( < 96). 0 1 the value of the reception error counter is in the range of the warning level (96 to 127). 1 0 undefined 1 1 the value of the reception error c ounter is in the error passive range ( 128). caution be sure to set bits 5 to 7 to ?0?. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1091 of 1817 sep 19, 2011 (9) can0 module error counter register (c0erc) the c0erc register indicates the count value of the transmission/reception error counter. after reset: 0000h r address: 03fec054h 15 14 13 12 11 10 9 8 c0erc reps rec6 rec5 rec4 rec3 rec2 rec1 rec0 7 6 5 4 3 2 1 0 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 reps reception error passive status bit 0 the value of the reception error c ounter is not error passive (< 128) 1 the value of the reception error count er is in the error passive range ( 128) rec6 to rec0 reception error counter bit 0 to 127 number of reception errors. these bits reflect the status of the reception error counter. the number of errors is defined by the can protocol. remark the rec6 to rec0 bits of the reception error count er are invalid in the reception error passive status (c0info.recs1, c0inf o.recs0 bit = 11b). tec7 to tec0 transmission error counter bit 0 to 255 number of transmission errors. these bits reflect the status of the transmission error counter. the number of errors is defined by the can protocol. remark the tec7 to tec0 bits of the transmission e rror counter are invalid in the bus-off status (c0info.boff bit = 1). v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1092 of 1817 sep 19, 2011 (10) can0 module interrupt enable register (c0ie) the c0ie register is used to enable or disable the interrupts of the can module. (1/2) after reset: 0000h r/w address: 03fec056h (a) read 15 14 13 12 11 10 9 8 c0ie 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 cie5 cie4 cie3 cie2 cie1 cie0 (b) write 15 14 13 12 11 10 9 8 c0ie 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 7 6 5 4 3 2 1 0 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 (a) read cie5 to cie0 can module interrupt enable bit 0 output of the interrupt corresponding to inte rrupt status register cintsx is disabled. 1 output of the interrupt corresponding to interrupt status register cintsx is enabled. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1093 of 1817 sep 19, 2011 (2/2) (b) write set cie5 clear cie5 setting of cie5 bit 0 1 cie5 bit is cleared to 0. 1 0 cie5 bit is set to 1. other than above cie5 bit is not changed. set cie4 clear cie4 setting of cie4 bit 0 1 cie4 bit is cleared to 0. 1 0 cie4 bit is set to 1. other than above cie4 bit is not changed. set cie3 clear cie3 setting of cie3 bit 0 1 cie3 bit is cleared to 0. 1 0 cie3 bit is set to 1. other than above cie3 bit is not changed. set cie2 clear cie2 setting of cie2 bit 0 1 cie2 bit is cleared to 0. 1 0 cie2 bit is set to 1. other than above cie2 bit is not changed. set cie1 clear cie1 setting of cie1 bit 0 1 cie1 bit is cleared to 0. 1 0 cie1 bit is set to 1. other than above cie1 bit is not changed. set cie0 clear cie0 setting of cie0 bit 0 1 cie0 bit is cleared to 0. 1 0 cie0 bit is set to 1. other than above cie0 bit is not changed. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1094 of 1817 sep 19, 2011 (11) can0 module interrupt st atus register (c0ints) the c0ints register indicates the in terrupt status of the can module. after reset: 0000h r/w address: 03fec058h (a) read 15 14 13 12 11 10 9 8 c0ints 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 cints5 cints4 cints3 cints2 cints1 cints0 (b) write 15 14 13 12 11 10 9 8 c0ints 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 (a) read cints5 to cints0 can interrupt status bit 0 no related interrupt source event is generated. 1 a related interrupt source event is generated. interrupt status bit related interrupt source event cints5 wakeup interrupt from can sleep mode note cints4 arbitration loss interrupt cints3 can protocol error interrupt cints2 can error status interrupt cints1 interrupt on completion of reception of valid message frame to message buffer m cints0 interrupt on normal completion of tr ansmission of message frame from message buffer m note the cints5 bit is set (1) only when the can modul e is woken up from the can sleep mode by a can bus operation. the cints5 bit is not set (1) when the can sleep mode has been released by software. (b) write clear cints5 to cints0 setting of cints5 to cints0 bits 0 cints5 to cints0 bits are not changed. 1 cints5 to cints0 bits are cleared to 0. caution the status bit of this register is not auto matically cleared. clear it (0) by software if each status must be checked in the interrupt servicing. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1095 of 1817 sep 19, 2011 (12) can0 module bit rate prescaler register (c0brp) the c0brp register is used to select the can protocol layer base clock (f tq ). the communication baud rate is set to the c0btr register. after reset: ffh r/w address: 03fec05ah 7 6 5 4 3 2 1 0 c0brp tqprs7 tqprs6 tqprs5 tqprs4 tqprs3 tqprs2 tqprs1 tqprs0 tqprs7 to tqprs0 can protocol layer base system clock (f tq ) 0 f canmod /1 1 f canmod /2 n f canmod /(n + 1) : : 255 f canmod /256 (default value) figure 21-23. can module clock ccp 3 ccp2 prescaler can0 module bit-rate prescaler register (c0brp) can0 global clock selection register (c0gmcs) baud rate generator can0 bit-rate register (c0btr) ccp1 ccp0 tqprs0 f can f canmod f tq 0 0 0 0 tqprs1 tqprs2 tqprs3 tqprs4 tqprs5 tqprs6 tqprs7 remark f can : can clock frequency f canmod : can module system clock frequency f tq : can protocol layer base system clock frequency caution the c0brp register can be write- accessed only in the initialization mode. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1096 of 1817 sep 19, 2011 (13) can0 module bit rate register (c0btr) the c0btr register is used to control the data bit time of the communication baud rate. figure 21-24. data bit time data bit time (dbt) time segment 1 (tseg1) phase segment 2 phase segment 1 sample point (spt) prop segment sync segment time segment 2 (tseg2) v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1097 of 1817 sep 19, 2011 after reset: 370fh r/w address: 03fec05ch 15 14 13 12 11 10 9 8 c0btr 0 0 sjw1 sjw0 0 tseg22 tseg21 tseg20 7 6 5 4 3 2 1 0 0 0 0 0 tseg13 t seg12 tseg11 tseg10 sjw1 sjw0 length of synchronization jump width 0 0 1tq 0 1 2tq 1 0 3tq 1 1 4tq (default value) tseg22 tseg21 tseg20 length of time segment 2 0 0 0 1tq 0 0 1 2tq 0 1 0 3tq 0 1 1 4tq 1 0 0 5tq 1 0 1 6tq 1 1 0 7tq 1 1 1 8tq (default value) tseg13 tseg12 tseg 11 tseg10 length of time segment 1 0 0 0 0 setting prohibited 0 0 0 1 2tq note 0 0 1 0 3tq note 0 0 1 1 4tq 0 1 0 0 5tq 0 1 0 1 6tq 0 1 1 0 7tq 0 1 1 1 8tq 1 0 0 0 9tq 1 0 0 1 10tq 1 0 1 0 11tq 1 0 1 1 12tq 1 1 0 0 13tq 1 1 0 1 14tq 1 1 1 0 15tq 1 1 1 1 16tq (default value) note this setting must not be made when the c0brp register = 00h. remark tq = 1/f tq (f tq : can protocol layer base system clock) v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1098 of 1817 sep 19, 2011 (14) can0 module last in-pointer register (c0lipt) the c0lipt register indicates the num ber of the message buffer in which a data frame or a remote frame was last stored. after reset: undefined r address: 03fec05eh 7 6 5 4 3 2 1 0 c0lipt lipt7 lipt6 lipt5 li pt4 lipt3 lipt2 lipt1 lipt0 lipt7 to lipt0 last in-pointer register (c0lipt) 0 to 31 when the c0lipt register is read, the contents of the element indexed by the last in-pointer (lipt) of the receive history list are read. these contents indicate the number of the message buffer in which a data frame or a remote frame was last stored. remark the read value of the c0li pt register is undefined if a data fr ame or a remote frame has never been stored in the message buffer. if the c0rgpt.rhpm bit is set to 1 after the can module has changed from the initialization mode to an operation mode, therefore, the r ead value of the c0lipt register is undefined. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1099 of 1817 sep 19, 2011 (15) can0 module receive history list register (c0rgpt) the c0rgpt register is used to read the receive history list. (1/2) after reset: xx02h r/w address: 03fec060h (a) read 15 14 13 12 11 10 9 8 c0rgpt rgpt7 rgpt6 rgpt5 rg pt4 rgpt3 rgpt2 rgpt1 rgpt0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 rhpm rovf (b) write 15 14 13 12 11 10 9 8 c0rgpt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear rovf (a) read rgpt7 to rgpt0 receive history list read pointer 0 to 31 when the c0rgpt register is read, the contents of the element indexed by the receive history list get pointer (rgpt) of the receive history list are re ad. these contents indicate the number of the message buffer in which a data frame or a remote frame has been stored. rhpm note 1 receive history list pointer match 0 the receive history list has at least one message buffer number that has not been read. 1 the receive history list has no message buffer numbers that have not been read. rovf note 2 receive history list overflow bit 0 all the message buffer numbers that have not bee n read are preserved. all the numbers of the message buffers in which a new data frame or remo te frame has been received and stored are recorded to the receive history list (the receive history list has a vacant element). 1 at least 23 entries have been stored since the host processor serviced the rhl last time (i.e. read c0rgpt). the first 22 entries are sequentially stored whereas the last entry might have been overwritten by newly received messages a number of times because all buffer numbers are stored at position lipt-1 when the rovf bit is set to 1. as a consequence receptions cannot be completely recovered in the order that they were received. notes 1. the read value of the rgpt 0 to rgpt7 bits is invalid when the rhpm bit = 1. 2. if all the receive history is read by the c0rgpt r egister while the rovf bit is set (1), the rhpm bit is not cleared (0) but kept set (1) ev en if newly received data is stored. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1100 of 1817 sep 19, 2011 (2/2) (b) write clear rovf setting of rovf bit 0 rovf bit is not changed. 1 rovf bit is cleared to 0. (16) can0 module last out-pointer register (c0lopt) the c0lopt register indicates the num ber of the message buffer to which a data frame or a remote frame was transmitted last. after reset: undefined r address: c0lopt 03fec062h, c1lopt 03fec662h 7 6 5 4 3 2 1 0 c0lopt lopt7 lopt6 lopt5 lo pt4 lopt3 lopt 2 lopt1 lopt0 lopt7 to lopt0 last out-pointer of transmit history list (lopt) 0 to 31 when the c0lopt register is read, the contents of the element indexed by the last out-pointer (lopt) of the receive history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. remark the value read from the c0lopt register is undefined if a data frame or remote frame has never been transmitted from a message buffer. if the c0tg pt.thpm bit is set to 1 after the can module has changed from the initialization mode to an oper ation mode, therefore, the read value of the c0lopt register is undefined. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1101 of 1817 sep 19, 2011 (17) can0 module transmit history list register (c0tgpt) the c0tgpt register is used to read the transmit history list. (1/2) after reset: xx02h r/w address: 03fec064h (a) read 15 14 13 12 11 10 9 8 c0tgpt tgpt7 tgpt6 tgpt5 tg pt4 tgpt3 tgpt2 tgpt1 tgpt0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 thpm tovf (b) write 15 14 13 12 11 10 9 8 c0tgpt 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 clear tovf (a) read tgpt7 to tgpt0 transmit history list read pointer 0 to 31 when the c0tgpt register is read, the content s of the element indexed by the read pointer (tgpt) of the transmit history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. thpm note 1 transmit history pointer match 0 the transmit history list has at least one message buffer number that has not been read. 1 the transmit history list has no message buffer numbers that have not been read. tovf note 2 transmit history list overflow bit 0 all the message buffer numbers that have not bee n read are preserved. all the numbers of the message buffers to which a new data frame or remote frame has been transmitted are recorded to the transmit history list (the transm it history list has a vacant element). 1 at least 7 entries have been stored since the host processor serviced the thl last time (i.e. read c0tgpt). the first 6 entries are sequentially stored whereas the last entry might have been overwritten by newly transmitted messages a number of times because all buffer numbers are stored at position lopt-1 when tovf bit is se t to 1. as a consequence receptions cannot be completely recovered in the order that they were received. notes 1. the read value of the tgpt 0 to tgpt7 bits is invalid when the thpm bit = 1. 2. if all the transmit history is read by the c0tgpt regi ster while the tovf bit is set (1), the thpm bit is not cleared (0) but kept set (1), even if transmission of new data has been completed. remark transmission from message buffers 0 to 7 is not re corded to the transmit history list in the normal operation mode with abt. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1102 of 1817 sep 19, 2011 (2/2) (b) write clear tovf setting of tovf bit 0 tovf bit is not changed. 1 tovf bit is cleared to 0. (18) can0 module time stamp register (c0ts) the c0ts register is used to c ontrol the time stamp function. (1/2) after reset: 0000h r/ w address: 03fec066h (a) read 15 14 13 12 11 10 9 8 c0ts 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 tslock tssel tsen (b) write 15 14 13 12 11 10 9 8 c0ts 0 0 0 0 0 set tslock set tssel set tsen 7 6 5 4 3 2 1 0 0 0 0 0 0 clear tslock clear tssel clear tsen remark the lock function of the time stamp functions must not be used when the can module is in the normal operation mode with abt. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1103 of 1817 sep 19, 2011 (2/2) (a) read tslock time stamp lock function enable bit 0 time stamp lock function stopped. the tsout signal toggles each time the selected time stamp capture event occurs. 1 time stamp lock function enabled. the tsout signal toggled each time the selected time stamp capture event occurred. however, the tsout output signal is locked when a data frame has been correctly received to message buffer 0 note . note the tsen bit is automatically cleared to 0. tssel time stamp capture event selection bit 0 the time stamp capture event is sof. 1 the time stamp capture event is the last bit of eof. tsen tsout operation setting bit 0 tsout toggle operation is disabled. 1 tsout toggle operation is enabled. remark the tsout signal is output from the can cont roller to a timer. for details, refer to chapter 7 16- bit timer/event counter a (taa) . (b) write set tslock clear tslock setting of tslock bit 0 1 tslock bit is cleared to 0. 1 0 tslock bit is set to 1. other than above tslock bit is not changed. set tssel clear tssel setting of tssel bit 0 1 tssel bit is cleared to 0. 1 0 tssel bit is set to 1. other than above tssel bit is not changed. set tsen clear tsen setting of tsen bit 0 1 tsen bit is cleared to 0. 1 0 tsen bit is set to 1. other than above tsen bit is not changed . v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1104 of 1817 sep 19, 2011 (19) can0 message data byte register (c0mdataxm , c0mdataym) (x = 0 to 7, y = 01, 23, 45, 67) the c0mdataxm register is used to st ore the data of a transmit/receive message, and can be accessed in 8-bit unit. the c0mdataxm register can be accessed in 16-bit units by the c0mdataym register. (1/2) after reset: undefined r/w address: see table 21-16 . 15 14 13 12 11 10 9 8 c0mdata01m mdata01 15 mdata01 14 mdata01 13 mdata01 12 mdata01 11 mdata01 10 mdata01 9 mdata01 8 7 6 5 4 3 2 1 0 mdata01 7 mdata01 6 mdata01 5 mdata01 4 mdata01 3 mdata01 2 mdata01 1 mdata01 0 7 6 5 4 3 2 1 0 c0mdata0m mdata0 7 mdata0 6 mdata0 5 mdata0 4 mdata0 3 mdata0 2 mdata0 1 mdata0 0 7 6 5 4 3 2 1 0 c0mdata1m mdata1 7 mdata1 6 mdata1 5 mdata1 4 mdata1 3 mdata1 2 mdata1 1 mdata1 0 15 14 13 12 11 10 9 8 c0mdata23m mdata23 15 mdata23 14 mdata23 13 mdata23 12 mdata23 11 mdata23 10 mdata23 9 mdata23 8 7 6 5 4 3 2 1 0 mdata23 7 mdata23 6 mdata23 5 mdata23 4 mdata23 3 mdata23 2 mdata23 1 mdata23 0 7 6 5 4 3 2 1 0 c0mdata2m mdata2 7 mdata2 6 mdata2 5 mdata2 4 mdata2 3 mdata2 2 mdata2 1 mdata2 0 7 6 5 4 3 2 1 0 c0mdata3m mdata3 7 mdata3 6 mdata3 5 mdata3 4 mdata3 3 mdata3 2 mdata3 1 mdata3 0 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1105 of 1817 sep 19, 2011 (2/2) 15 14 13 12 11 10 9 8 c0mdata45m mdata45 15 mdata45 14 mdata45 13 mdata45 12 mdata45 11 mdata45 10 mdata45 9 mdata45 8 7 6 5 4 3 2 1 0 mdata45 7 mdata45 6 mdata45 5 mdata45 4 mdata45 3 mdata45 2 mdata45 1 mdata45 0 7 6 5 4 3 2 1 0 c0mdata4m mdata4 7 mdata4 6 mdata4 5 mdata4 4 mdata4 3 mdata4 2 mdata4 1 mdata4 0 7 6 5 4 3 2 1 0 c0mdata5m mdata5 7 mdata5 6 mdata5 5 mdata5 4 mdata5 3 mdata5 2 mdata5 1 mdata5 0 15 14 13 12 11 10 9 8 c0mdata67m mdata67 15 mdata67 14 mdata67 13 mdata67 12 mdata67 11 mdata67 10 mdata67 9 mdata67 8 7 6 5 4 3 2 1 0 mdata67 7 mdata67 6 mdata67 5 mdata67 4 mdata67 3 mdata67 2 mdata67 1 mdata67 0 7 6 5 4 3 2 1 0 c0mdata6m mdata6 7 mdata6 6 mdata6 5 mdata6 4 mdata6 3 mdata6 2 mdata6 1 mdata6 0 7 6 5 4 3 2 1 0 c0mdata7m mdata7 7 mdata7 6 mdata7 5 mdata7 4 mdata7 3 mdata7 2 mdata7 1 mdata7 0 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1106 of 1817 sep 19, 2011 (20) can0 message data length register m (c0mdlcm) the c0mdlcm register is used to set the number of bytes of the data field of a message buffer. after reset: 0000xxxxb r/w address: see table 21-16 . 7 6 5 4 3 2 1 0 c0mdlcm 0 0 0 0 mdlc3 mdlc2 mdlc1 mdlc0 mdlc3 mdlc2 mdlc1 mdlc0 data length of transmit/receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 setting prohibited (if these bits are set during transmi ssion, 8-byte data is transmitted regardless of the set dlc value when a data frame is transmitted. however, the dlc actually transmitted to the can bus is the dlc value set to this register.) note note the data and dlc value actually transmitted to can bus are as follows. type of transmit frame length of transmit data dlc transmitted data frame number of bytes specified by dlc (however, 8 bytes if dlc 8) remote frame 0 bytes mdlc3 to mdlc0 bits cautions 1. be sure to set bits 7 to 4 to 0000b. 2. receive data is stored in as many c0m dataxm register as the number of bytes (however, the upper limit is 8) corresponding to dlc of receive frame. the c0 mdataxm register in which no data is stor ed is undefined. 3. be sure to set bits 4 to 7 to ?0?. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1107 of 1817 sep 19, 2011 (21) can0 message configuration register m (c0mconfm) the c0mconfm register is used to specify t he type of the message buffer and to set a mask. (1/2) after reset: undefined r/w address: see table 21-16 . 7 6 5 4 3 2 1 0 c0mconfm ows rtr mt2 mt1 mt0 0 0 ma0 ows overwrite control bit 0 the message buffer note that has already received a data frame is not overwritten by a newly received data frame. the newly received data frame is discarded. 1 the message buffer that has already received a data frame is overwritten by a newly received data frame. note the ?message buffer that has already received a data frame? is a receive message buffer whose the c0mctrlm.dn bit has been set to 1. remark a remote frame is received and stored, regardle ss of the setting of the ows and dn bits. a remote frame that satisfies the other condi tions (id matches, the rtr bit = 0, the c0mctrlm.trq bit = 0) is always received and stored in the corresponding message buffer (interrupt generated, dn flag set, the c0mdlcm.mdlc0 to c0mdlcm.mdlc3 bits updat ed, and recorded to the receive history list). rtr remote frame request bit note 0 transmit a data frame. 1 transmit a remote frame. note the rtr bit specifies the type of message frame that is transmitted fr om a message buffer defined as a transmit message buffer. even if a valid remote frame has been receiv ed, the rtr bit of the transmit message buffer that has received the frame remains cl eared to 0. even if a remote frame whose id matches has been received from the can bus with the rtr bit of the transmit message buffer set to 1 to transmit a remote frame, that remote frame is not re ceived or stored (interrupt generated, dn flag set, the mdlc0 to mdlc3 bits updated, and recorded to the receive history list). mt2 mt1 mt0 message buffer type setting bit 0 0 0 transmit message buffer 0 0 1 receive message buffer (no mask setting) 0 1 0 receive message buffer (mask 1 set) 0 1 1 receive message buffer (mask 2 set) 1 0 0 receive message buffer (mask 3 set) 1 0 1 receive message buffer (mask 4 set) other than above setting prohibited v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1108 of 1817 sep 19, 2011 (2/2) ma0 message buffer assignment bit 0 message buffer not used. 1 message buffer used. caution be sure to set bits 2 and 1 to ?0?. (22) can0 message id register m (c0midlm, c0midhm) the c0midlm and c0midhm registers ar e used to set an identifier (id). after reset: undefined r/w address: see table 21-16 . 15 14 13 12 11 10 9 8 c0midlm id15 id14 id13 id12 id11 id10 id9 id8 7 6 5 4 3 2 1 0 id7 id6 id5 id4 id3 id2 id1 id0 15 14 13 12 11 10 9 8 c0midhm ide 0 0 id28 id27 id26 id25 id24 7 6 5 4 3 2 1 0 id23 id22 id21 id20 id19 id18 id17 id16 ide format mode specification bit 0 standard format mode (id28 to id18: 11 bits) note 1 extended format mode (id28 to id0: 29 bits) note the id17 to id0 bits are not used. id28 to id0 message id id28 to id18 standard id value of 11 bits (when ide = 0) id28 to id0 extended id value of 29 bits (when ide = 1) cautions 1. be sure to write 0 to bits 14 and 13 of the c0midhm register. 2. be sure to arrange the id values to be registered in accordance wit h the bit positions of this register. for the standard id, shift the bit positions of id28 to id18 of the id value. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1109 of 1817 sep 19, 2011 (23) can0 message control register m (c0mctrlm) the c0mctrlm register is used to cont rol the operation of the message buffer. (1/3) after reset: 00x000000 000xx000b r/w address: see table 21-16 . (a) read 15 14 13 12 11 10 9 8 c0mctrlm 0 0 muc 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 mow ie dn trq rdy (b) write 15 14 13 12 11 10 9 8 c0mctrlm 0 0 0 0 set ie 0 set trq set rdy 7 6 5 4 3 2 1 0 0 0 0 clear mow clear ie clear dn clear trq clear rdy (a) read muc note bit indicating that message buffer data is being updated 0 the can module is not updating the me ssage buffer (reception and storage). 1 the can module is updating the message buffer (reception and storage). note the muc bit is undefined until the firs t reception and storage is performed. mow message buffer overwrite status bit 0 the message buffer is not overwritt en by a newly received data frame. 1 the message buffer is overwritten by a newly received data frame. remark the mow bit is not set to 1 even if a remote fr ame is received and stored in the transmit message buffer with the dn bit = 1. ie message buffer interrupt request enable bit 0 receive message buffer: valid message re ception completion interrupt disabled. transmit message buffer: normal message tr ansmission completion interrupt disabled. 1 receive message buffer: valid message reception completion interrupt enabled. transmit message buffer: normal message transmission completion interrupt enabled. dn message buffer data update bit 0 a data frame or remote frame is not stored in the message buffer. 1 a data frame or remote frame is stored in the message buffer. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1110 of 1817 sep 19, 2011 (2/3) trq message buffer transmission request bit 0 no message frame transmitting request that is pe nding or being transmitted is in the message buffer. 1 the message buffer is holding transmission of a me ssage frame pending or is transmitting a message frame. caution do not set the trq bit and rdy bit to 1 at the same time. be sure to set the rdy bit to 1 before setting the trq bit to 1. rdy message buffer ready bit 0 the message buffer can be written by software. the can module cannot write to the message buffer. 1 writing the message buffer by software is ignored (e xcept a write access to the rdy, trq, dn, and mow bits). the can module can write to the message buffer. cautions 1. do not clear the rdy bit (0) during message transmission. fo llow transmission abort procedures in order to clear the rdy bit for redefinition. 2. if the rdy bit is not clear ed (0) even when the processing to clear it is executed, execute the clearing processing again. 3. confirm, by reading the rdy bit again, that the rdy bit has b een cleared (0) before writing data to the message buffer. however, it is unnecessary to confirm that th e trq or rdy bit has been set (1) or that the dn or mow bit has b een cleared (0). (b) write clear mow setting of mow bit 0 mow bit is not changed. 1 mow bit is cleared to 0. set ie clear ie setting of ie bit 0 1 ie bit is cleared to 0. 1 0 ie bit is set to 1. other than above ie bit is not changed. caution be sure to set the ie and rdy bits separately. clear dn setting of dn bit 1 dn bit is cleared to 0. 0 dn bit is not changed. caution do not set the dn bit to 1 by softw are. be sure to write 0 to bit 10. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1111 of 1817 sep 19, 2011 (3/3) set trq clear trq setting of trq bit 0 1 trq bit is cleared to 0. 1 0 trq bit is set to 1. other than above trq bit is not changed. caution even if the trq bit is set (1), transm ission may not be immediately executed depending on the situation such as wh en a message is received from anot her node or when a message is transmitted from the message buffer. transmission under execution is not terminated midway even if the trq bit is cleared. transmission is continued until it is completed (regardless of whether it is executed successfully or fails). set rdy clear rdy setting of rdy bit 0 1 rdy bit is cleared to 0. 1 0 rdy bit is set to 1. other than above rdy bit is not changed. caution be sure to set the trq and rdy bits separately. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1112 of 1817 sep 19, 2011 21.7 bit set/clear function the can control registers include register s whose bits can be set or cleared vi a the cpu and via the can interface. an operation error occurs if the following r egisters are written directly. do not writ e any values directly via bit manipulati on, read/modify/write, or direct writing of target values. ? can0 global control register (c0gmctrl) ? can0 global automatic block transmission control register (c0gmabt) ? can0 module control register (c0ctrl) ? can0 module interrupt enable register (c0ie) ? can0 module interrupt status register (c0ints) ? can0 module receive history list register (c0rgpt) ? can0 module transmit history list register (c0tgpt) ? can0 module time stamp register (c0ts) ? can0 message control register (c0mctrlm) remark m = 00 to 31 all the 16 bits in the above registers can be read via the usual method. use the procedure described in figure 21-25 below to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the bit status after set/clear operation is specified in figure 21-26) . figure 21-25 shows how the values of set bits or clear bit s relate to set/clear/no change operations in the corresponding register. figure 21-25. example of bi t setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set no change clear bit status register?s current value write value register?s value after write operation clear clear no change no change set v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1113 of 1817 sep 19, 2011 figure 21-26. bit status after bit setting/clearing operations 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 c lear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n status of bit n after bit set/clear operation 0 0 no change 0 1 0 1 0 1 1 1 no change remark n = 0 to 7 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1114 of 1817 sep 19, 2011 21.8 can controller initialization 21.8.1 initialization of can module before can module operation is enabled, the can module system clock needs to be determined by setting the c0gmcs.ccp0 to c0gmcs.ccp3 bits by software. do not change the setting of the can module system clock after can module operation is enabled. the can module is enabled by setting the c0gmctrl.gom bit. for the procedure of initia lizing the can module, see 21.16 operation of can controller. 21.8.2 initialization of message buffer after the can module is enabled, the me ssage buffers contain undefined values. a minimum initialization for all the message buffers, even for those not used in the application, is necessary before switch ing the can module from the initialization mode to one of the operation modes. ? clear the c0mctrlm.rdy, c0mctrlm.trq, and c0mctrlm.dn bits to 0. ? clear the c0mconfm.ma0 bit to 0. remark m = 00 to 31 21.8.3 redefinition of message buffer redefining a message buffer means changing the id and control information of the message buffer while a message is being received or transmitted, without affect ing other transmission/reception operations. (1) to redefine message buffe r in initialization mode place the can module in the initializ ation mode once and then change the id and control information of the message buffer in the initialization mode. after changing the id and control information, set the can module to an operation mode. (2) to redefine message buffer during reception perform redefinition as shown in figure 21-39. (3) to redefine message buffer during transmission to rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (see 21.10.4 (1) transmission abort pro cess other than in normal operation mode with automatic block transmi ssion (abt), 21.10.4 (2) transmi ssion abort process except for abt transmission in normal operation mode wit h automatic block transmission (abt)) . confirm that transmission has been aborted or completed, and then r edefine the message buffer. after redefining the transmit message buffer, set a transmission request using the procedure described below. when setting a transmission request to a message buffer that has been redefined withou t aborting the transmission in progress, however, the 1- bit wait time is not necessary. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1115 of 1817 sep 19, 2011 figure 21-27. setting transmission request (trq) to transmit message buffer after redefinition execute transmission? wait for 1 bit of can data. set trq bit set trq bit = 1 clear trq bit = 0 yes no redefinition completed end cautions 1. when a message is received, reception filt ering is performed in accordance with the id and mask set to each receive message buffer. if the proce dure in figure 21-39 is not observed, the contents of the message buffer after it has been redefined may contradict the result of reception (result of reception filtering). if this happens, check that the id and ide received first and stored in the message buffer following redefinition are tho se stored after the message buffer has been redefined. if no id and ide ar e stored after redefinition, rede fine the message buffer again. 2. when a message is transmitted, the transmi ssion priority is checked in accordance with the id, ide, and rtr bits set to each transmit message buffer to which a transmission request was set. the transmit message buffer having the highest pr iority is selected for transmission. if the procedure in figure 21-27 is not observed, a mess age with an id not having the highest priority may be transmitted after redefinition. 21.8.4 transition from initializat ion mode to operation mode the can module can be switched to the following operation modes. ? normal operation mode ? normal operation mode with abt ? receive-only mode ? single-shot mode ? self-test mode v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1116 of 1817 sep 19, 2011 figure 21-28. transiti on to operation modes can module channel invalid [receive-only mode] opmode[2:0]=03h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 03h [single-shot mode] opmode[2:0]=04h opmode[2:0] = 04h opmode[2:0] = 05h init mode opmode[2:0] = 00h efsd = 1 and gom = 0 all can modules are in init mode and gom = 0 gom = 1 reset reset released [normal operation mode with abt] opmode[2:0]=02h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 02h opmode[2:0] = 01h opmode[2:0] = 00h and can bus is busy. [normal operation mode] opmode[2:0]=01h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and can bus is busy. [self-test mode] opmode[2:0]=05h the transition from the initializati on mode to an operation mode is c ontrolled by the c0ctrl.opmode2 to c0ctrl.opmode0 bits. changing from one operation mode into another requires shifting to the initialization mode in between. do not change one operation mode to another directly; othe rwise the operation will not be guaranteed. requests for transition from an operation mode to the initialization mode are hel d pending when the can bus is not in the interframe space (i.e., frame reception or transmission is in progress), and the can m odule enters the initialization mode at the first bit in the interframe space (the values of the opmode2 to opmode0 bits are changed to 000b). after issuing a request to change the mode to the initialization mode, read the opmo de2 to opmode0 bits until their values become 000b to confirm that the module has entered the initialization mode (see figure 21-37 ). 21.8.5 resetting error counter c0erc of can module if it is necessary to reset the c0erc and c0info registers when re-initialization or forced recovery from the bus-off status is made, set the c0ctrl.ccerc bit to 1 in the initialization mode. when this bit is set to 1, the c0erc and c0info registers are cleared to their default values. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1117 of 1817 sep 19, 2011 21.9 message reception 21.9.1 message reception all buffers satisfying the following conditions are searched in all the message buffer areas in all the operation modes in order to store newly receive messages. ? used as a message buffer (c0mconfm.ma0 bit is set to 1.) ? set as a receive message buffer (c0mconfm.mt2 to c0mconfm.mt0 bits ar e set to 001b, 010b, 011b, 100b, or 101b.) ? ready for reception (c0mctrlm.rdy bit is set to 1.) remark m = 00 to 31 when two or more message buffers of the can module re ceive a message, the message is stored according to the priority explained below. the message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. for example, when an unmaske d receive message buffer and a receive message buffer linked to mask 1 have the same id, the received message is not stored in the message buffer linked to mask 1 that has not received a message, even if a message has already been re ceived in the unmasked receive message buffer. in other words, when a condition has been set to store a message in tw o or more message buffers with different priorities, the message buffer with the highest priority always stores the me ssage; the message is not stored in message buffers with a lower priority. this also applies when the message buffer wit h the highest priority is unable to receive and store a message (i.e., when the dn bit = 1 indicating that a message has already been received, but rewriting is disabled because the ows bit = 0). in this case, the message is not actually received and stored in the candidate message buffer with the highest priority, but neither is it stored in a message buffer with a lower priority. priority storing condition if same id is set dn bit = 0 1 (high) unmasked message buffer dn bit = 1 and ows bit = 1 dn bit = 0 2 message buffer linked to mask 1 dn bit = 1 and ows bit = 1 dn bit = 0 3 message buffer linked to mask 2 dn bit = 1 and ows bit = 1 dn bit = 0 4 message buffer linked to mask 3 dn bit = 1 and ows bit = 1 dn bit = 0 5 (low) message buffer linked to mask 4 dn bit = 1 and ows bit = 1 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1118 of 1817 sep 19, 2011 21.9.2 reading reception data if it is necessary to consistently read data from t he can message buffer by software, follow the recommended procedures shown in figures 21-49 and 21-50. while receiving a message, the can module sets the c0mctrlm .dn bit two times, at the beginning of the processing to store data in the message buffer and at the end of this storing processing. during this storing processing, the c0mctrlm.muc bit of the message buffer is set (1) (refer to figure 21-29 ). before the data is completely stored, the re ceive history list is written. during th is data storing period (muc bit = 1), the cpu is prohibited from rewriting the c0 mctrlm.rdy bit of the message buffer in which the data is to be stored. completion of this data storing processing may be delayed by a cpu?s access to any message buffer. remark m = 0 to 31 figure 21-29. dn and muc bit setting period (in standard id format) sof (1) id ide rtr r0 dlc data0-data7 crc ack eof can standard id format (11) (1) (1) (1) (4) (0-64) (16) (2) recessive dominant dn bit muc bit message stored data, dlc, id message buffer (7) the dn bit is set (1) and the muc bit is cleared (0) at the same time. c0ints.cints1 bit the dn and muc bits are set (1) at the same time. ifs intc0rec signal operation of can controller v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1119 of 1817 sep 19, 2011 21.9.3 receive history list function the receive history list (rhl) function records in the rece ive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. the rhl consists of stor age elements equivalent to up to 23 messages, the last in-message pointer (lipt) with the corresponding c0lipt register and the receive history list get pointer (rgpt) with the corresponding c0rgpt register. the rhl is undefined immediately after th e transition of the can module from the initialization mode to one of the operation modes. the c0lipt register holds the contents of the rhl element indicated by the value of the lipt pointer minus 1. by reading the c0lipt register, t herefore, the number of the message buffer that received and stored a data frame or remote frame first can be checked. the lipt point er is utilized as a write pointer that indicates to what part of the rhl a message buffer number is recorded. any time a data frame or remote frame is received and stored, the corresponding message buffer number is recorded to the rhl element indicat ed by the lipt pointer. each time recording to the rhl has been completed, the lipt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be recorded chronologically. the rgpt pointer is utilized as a read pointer that reads a recorded message buffer number from the rhl. this pointer indicates the first rhl element t hat the cpu has not read yet. by reading the c0rgpt register by software, the number of a message buffer that has received and stored a data frame or remote frame can be read. each time a message buffer number is read from the c0rgpt regist er, the rgpt pointer is automatically incremented. if the value of the rgpt pointer matc hes the value of the lipt pointer, the c0rgpt.rhpm bit (receive history list pointer match) is set to 1. this indicates that no message buffer number that has not been r ead remains in the rhl. if a new message buffer number is recorded, the lipt pointer is incremented and because its value no longer matches the value of the rgpt pointer, the rhpm bit is cleared. in other words, the numbers of the unread message buffers exist in the rhl. if the lipt pointer is increm ented and matches the value of the rgpt point er minus 1, the c0rgpt.rovf bit (receive history list overflow) is set to 1. this indicates that t he rhl is full of numbers of me ssage buffers that have not been read. when further message reception and stori ng occur, the last recorded message buffer number is overwritten by the number of the message buffer that received and stored the new message . after the rovf bit has been set to 1, the recorded message buffer numbers in the rhl do not completely reflect chronological order. however the messages themselves are not lost and can be located by a cpu search in the message buffer memory with the help of the dn bit. caution even if the receive hi story list overflows (c0rgpt.rovf bit = 1) , the receive history can be read until no more history is left unread and the c0rgpt.rhpm bit is set (1). however, the rovf bit is kept set (1) (= overflow occurs) until cleared (0) by software. in this status, the rhpm bit is not cleared (0), unless the rovf bit is cleared (0), even if a new recei ve history is stored and written to the list. if rovf bit = 1 and rhpm bit = 1 and the receive hi story list overflows, therefore, the rhpm bit indicates that no more history is left unread e ven if new history is received and stored. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1120 of 1817 sep 19, 2011 as long as the rhl contains 23 or less entries the sequence of occurrence is maintained. if more receptions occur without the rhl being read by the host processor, a comp lete sequence of receptions can not be recovered. figure 21-30. receive history list last in- message pointer (lipt) receive history list get pointer (rgpt) - message buffer 6, 9, 2, and 7 are read by host processor. - newly received messages are stored in message buffer 3, 4, and 8. event: receive history list get pointer (rgpt) last in- message pointer (lipt) - 20 other messages are received. message buffer 6 carries last received message. - upon reception in message buffer 6, rhl is full. - rovf bit is set to 1. event: last in- message pointer (lipt) last in- message pointer (lipt) receive history list get pointer (rgpt) receive history list get pointer (rgpt) receive history list (rhl) message buffer 6 message buffer 9 message buffer 2 message buffer 7 0 1 2 3 4 5 6 7 22 23 : : : receive history list (rhl) message buffer 3 message buffer 4 message buffer 8 0 1 2 3 4 5 6 7 22 23 : : : receive history list (rhl) message buffer 10 message buffer 11 message buffer 6 message buffer 3 message buffer 4 message buffer 8 message buffer 5 message buffer 9 message buffer 1 0 1 2 3 4 5 6 7 22 23 : : : - reception in message buffer 13, 14, and 15 occurs. - overflow situation occurs. event: receive history list (rhl) message buffer 10 message buffer 11 message buffer 15 message buffer 3 message buffer 4 message buffer 8 message buffer 5 message buffer 9 message buffer 1 0 1 2 3 4 5 6 7 22 23 : : : rovf bit = 1 lipt is blocked rovf bit = 1 lipt is blocked rovf bit = 1 denotes that lipt equals rgpt ? 1 while message buffer number stored to element indicated by lipt ? 1. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1121 of 1817 sep 19, 2011 21.9.4 mask function for some message buffers that are used for reception, whet her one of four global reception masks is applied can be selected. load resulting from comparing message identifiers is reduc ed by masking some bits, and, as a result, some different identifiers can be received in a buffer. by using the mask function, the identifier of a message rece ived from the can bus can be compared with the identifier set to a message buffer in advance. regardless of whether the masked id is set to 0 or 1, the received message can be stored in the defined message buffer. while the mask function is in effect, an identifier bit that is defined to be 1 by a mask in the received message is not compared with the corresponding ident ifier bit in the message buffer. however, this comparison is performed for any bi t whose value is defined as 0 by the mask. for example, let us assume that all me ssages that have a standard-format id, in which bits id27 to id25 are 0 and bits id24 and id22 are 1, are to be stored in message buffer 14. the procedure for this example is shown below. <1> identifier to be stored in message buffer id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x 0 0 0 1 x 1 x x x x remark x = don?t care <2> identifier to be configured in message buffer 14 (example) (using c0midl14 and c0midh14 registers) id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x 0 0 0 1 x 1 x x x x id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 x x x x x x x x x x x id6 id5 id4 id3 id2 id1 id0 x x x x x x x id with the id27 to id25 bits cleared to 0 and the id24 and id22 bits set to 1 is registered (initialized) to message buffer 14. remark x = don?t care remark message buffer 14 is set as a standard format i dentifier that is linked to mask 1 (c0mconf14.mt2 to c0mconf14.mt0 bits are set to 010b). v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1122 of 1817 sep 19, 2011 <3> mask setting for can module 1 (mask 1) (example) (using can1 address mask 1 registers l and h (c1mask1l and c1mask1h)) cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 1 0 0 0 0 1 0 1 1 1 1 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 1 1 1 1 1 1 1 1 1 1 1 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1 1 1 1 1 1 1 1: not compared (masked) 0: compared the cmid27 to cmid24 and cmid22 bits are clear ed to 0, and the cmid28, cmid23, and cmid21 to cmid0 bits are set to 1. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1123 of 1817 sep 19, 2011 21.9.5 multi buffer receive block function the multi buffer receive block (mbrb) function is used to store a block of data in two or more message buffers sequentially with no cpu interaction, by setting the same id to two or more message buffers with the same message buffer type. these message buffers can be allocated in any area in the message buffer memory, and they are not necessarily to be allocated adjacent to each other. suppose, for example, the same message buffer type is se t to 10 message buffers, message buffers 10 to 19, and the same id is set to each message buffer. if the first message w hose id matches an id of the message buffers is received, it is stored in message buffer 10. at this point, the dn bit of message buffer 10 is set, prohibiting overwriting the message buffer. when the next message with a matching id is received, it is received and stored in message buffer 11. each time a message with a matching id is received, it is sequentially (i n the ascending order) stored in message buffers 12, 13, and so on. even when a data block consisting of multiple messages is received, the messages can be stored and received without overwriting the previous ly received matching-id data. whether a data block has been received and stored can be checked by setting the c0mctrlm.ie bit of each message buffer. for example, if a data block consists of k messages , k message buffers are initialized for reception of the data block. the ie bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the ie bit in message buffer k-1 is set to 1 (interrupts enabled). in this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating t hat mbrb has become full. alternativel y, by clearing the ie bit of message buffers 0 to (k-3) and setting the ie bit of message buffer k-2, a warning that mbrb is about to overflow can be issued. the basic conditions of storing receiv e data in each message buffer for the mbrb are the same as the conditions of storing data in a single message buffer. cautions 1. mbrb can be configured for each of the same message buffer types. therefore, even if a message buffer of another mbrb whose id match es but whose message buffer type is different has a vacancy, the received message is not stored in that message buffer, but instead discarded. 2. mbrb does not have a ring buffer structure. the refore, after a message is stored in the message buffer having the highest number in the mbrb configuration, a newly received message will no longer be stored in the message buffer in th e order from the lowest message buffer number. 3. mbrb operates based on the reception and stor age conditions; there are no settings dedicated to mbrb, such as function enable bits. by setting th e same message buffer type and id to two or more message buffers, mbrb is automatically configured. 4. with mbrb, ?matching id? means ?matching id a fter mask?. even if the id set to each message buffer is not the same, if the id that is masked by the mask register matches, it is considered a matching id and the buffer that has this id is treated as the storage destination of a message. 5. priority among each mbrb conforms to the priority shown in 21.9. 1 message reception. remark m = 00 to 31 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1124 of 1817 sep 19, 2011 21.9.6 remote frame reception in all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. ? used as a message buffer (c0mconfm.ma0 bit set to 1.) ? set as a transmit message buffer (c0mconfm.mt2 to c0mconfm.mt0 bits set to 000b) ? ready for reception (c0mctrlm.rdy bit set to 1.) ? set to transmit message (c0mconfm.rtr bit is cleared to 0.) ? transmission request is not set. (c0mctrlm.trq bit is set to 0.) upon acceptance of a remote frame, the following actions ar e executed if the id of the received remote frame matches the id of a message buffer that satisfies the above conditions. ? the c0mdlcm.dlc3 to c0mdlcm.dlc0 bits store the received dlc value. ? the c0mdata0m to c0mdata7m registers in the data ar ea are not updated (data before reception is saved). ? the c0mctrlm.dn bit is set to 1. ? the c0ints.cints1 bit is set to 1 (if the c0mctrlm.ie bit of the message buffer that receives and stores the frame is set to 1). ? the receive completion interrupt (intc0rec) is output (i f the ie bit of the message buffer that receives and stores the frame is set to 1 and if the c0ie.cie1 bit is set to 1). ? the message buffer number is recorded in the receive history list. caution when a message buffer is searched for receivi ng and storing a remote frame, overwrite control by the c0mconfm.ows bit of the message buffer and the dn bit are not affected. the setting of the ows bit is ignored and the dn bit is set to 1 in every case. if more than one transmit message buffer has th e same id and the id of the received remote frame matches that id, the remote frame is stored in th e transmit message buffer with the lowest message buffer number. remark m = 00 to 31 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1125 of 1817 sep 19, 2011 21.10 message transmission 21.10.1 message transmission in all the operation modes, if the c0mctrlm.trq bit is se t to 1 in a message buffer that satisfies the following conditions, the message buffer that is to transmit a message is searched. ? used as a message buffer (c0mconfm.ma0 bit set to 1.) ? set as a transmit message buffer (c0mconfm.mt2 to c0mconfm.mt0 bits set to 000b.) ? ready for transmission (c0mctrlm.rdy bit is set to 1.) remark m = 00 to 31 the can system is a multi-master comm unication system. in a system like this, the priority of message transmission is determined based on message identifiers (i ds). to facilitate transmission processi ng by software when there are several messages awaiting transmission, the can module uses hardware to check the id of the message with the highest priority and automatically identifies that message. this elim inates the need for software-based priority control. transmission priority is controlled by the identifier (id). figure 21-31. message processing example message no. the can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1126 of 1817 sep 19, 2011 after the transmit message search, the transmit message with t he highest priority of the transmit message buffers that have a pending transmission request (message buffers with the trq bit set to 1 in advance) is transmitted. if a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. if the new transmission request has a higher priority, it is transmitted, unless transmission of a message with a low priority has already started. to solve this reversal of priorities , software can request that transmission of a message of lo w priority be stopped. the highest priority is determined according to the following rules. priority conditions description 1 (high) value of first 11 bits of id [id28 to id18]: the message frame with the lowest value represented by the first 11 bits of the id is transmitted first. if the value of an 11- bit standard id is equal to or smaller than the first 11 bits of a 29-bit extended id, the 11-bit standard id has a higher priority than a message frame with a 29-bit extended id. 2 frame type a data frame with an 11-bit standard id (c0mconfm.rtr bit is cleared to 0) has a higher priority than a remote frame with a standard id and a message frame with an extended id. 3 id type a message frame with a standard id (c0mi dhm.ide bit is cleared to 0) has a higher priority than a message frame with an extended id. 4 value of lower 18 bits of id [id17 to id0]: if one or more transmission-pending ex tended id message frame has equal values in the first 11 bits of the id and the same frame type (equal rtr bit values), the message frame with the lowest value in the lower 18 bits of its extended id is transmitted first. 5 (low) message buffer number if two or more message buffers request tr ansmission of message frames with the same id, the message from the message buffer with the lowest message buffer number is transmitted first. remarks 1. if the automatic block transmission request bit c0gmabt .abttrg bit is set to 1 in the normal operation mode with abt, the trq bit is set to 1 only for one message buffer in the abt message buffer group. if the abt mode was triggered by the abttrg bit (1), one trq bit is set to 1 in the abt area (buffers 0 to 7). in addition to this trq bit, the application can request transmissions (set trq bit to 1) for other tx- message buffers that do not belong to the abt area. in that case an internal arbitration process (tx- search) evaluates all of the tx-message buffers with the trq bit set to 1 and chooses the message buffer that contains the highest prioritized identifier for the next transmission. if there are 2 or more identifiers that have the highest priority (i.e. ident ical identifiers), the message located at the lowest message buffer number is transmitted first. upon successful transmission of a message frame, the following operations are performed. - the trq bit of the corresponding transmit me ssage buffer is automatically cleared to 0. - the transmission completion status bit cints0 of the c0ints register is set to 1 (if the interrupt enable bit (ie) of the corresponding tr ansmit message buffer is set to 1). - an interrupt request signal intc0trx is output (i f the c0ie.cie0 bit is set to 1 and if the interrupt enable bit (ie) of the corresponding tr ansmit message buffer is set to 1). 2. before changing the contents of the transmit message buffer, the rdy flag of this buffer must be cleared. since the rdy flag may be temporarily locked while the internal processing is changed, it is necessary to check the status of the rdy flag by softw are after changing the buffer contents. 3. m = 00 to 31 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1127 of 1817 sep 19, 2011 21.10.2 transmit history list function the transmit history list (thl) function re cords in the transmit history list the number of the transmit message buffer in which each data frame or remote frame was received and stored. the thl consists of storage elements equivalent to up to seven messages, the last out-message pointer (lopt) with the corresponding c0lopt register, and the transmit history list get pointer (tgpt) with the corresponding c0tgpt register. the thl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the c0lopt register holds the contents of the thl element i ndicated by the value of the lopt pointer minus 1. by reading the c0lopt register, t herefore, the number of the message buffer t hat transmitted a data frame or remote frame first can be checked. the lopt pointer is utilized as a write pointer that indicates to what part of the thl a message buffer number is recorded. any time a data frame or re mote frame is transmitted, the corresponding message buffer number is recorded to the thl element indicated by the lopt pointer. each time recording to the thl has been completed, the lopt pointer is automatically incremented. in this wa y, the number of the message buffer that has received and stored a frame will be recorded chronologically. the tgpt pointer is utilized as a r ead pointer that reads a recorded message buffer number from the thl. this pointer indicates the first thl element that the cpu has not yet read. by reading the c0tgpt register by software, the number of a message buffer that has completed transmission can be read. each time a message buffer number is read from the c0tgpt register, the tgpt poi nter is automatically incremented. if the value of the tgpt pointer matches the value of the lopt pointer, the c0tgpt.thpm bit (transmit history list pointer match) is set to 1. this indicates that no message buffer numbers that have not been read remain in the thl. if a new message buffer number is recorded, the lopt pointer is incremented and because its value no longer matches the value of the tgpt pointer, the thpm bit is cleared. in other words, the numbe rs of the unread message buffers exist in the thl. if the lopt pointer is incremented and matc hes the value of the tgpt pointer minus 1, the tovf bit (transmit history list overflow) of the c0tgpt register is set to 1. this indicates that the thl is full of message buffer numbers that have not been read. if a new message is received and stored, the message buffer number recorded last is overwritten by the number of the message buffer that receiv ed and stored the new message. after the tovf bit has been set (1), therefore, the recorded message buffer numbers in the thl do not comp letely reflect chronological order. however the transmitted messages can be found by a cpu search applied to all transmi t message buffers unless the cpu has not overwritten a transmit object in one of these buffers beforehand. in to tal up to six transmission completions can occur without overflowing the thl. caution even if the transmit histor y list overflows (c0tgpt.tovf bit = 1) , the transmit history can be read until no more history is left unread and the c0tgpt.thp m bit is set (1). however, the tovf bit is kept set (1) (= overflow occurs) until clear ed (0) by software. in this status , the thpm bit is not cleared (0), unless the tovf bit is cleared (0), even if a new transmit history is stored and writ ten to the list. if the tovf bit = 1 and the thpm bit = 1 and the receive history list overflows, therefore, the thpm bit indicates that no more history is left unread e ven if new history is received and stored. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1128 of 1817 sep 19, 2011 figure 21-32. transmit history list last out- message pointer (lopt) - cpu confirms tx completion of message buffer 6, 9, and 2. - tx completion of message buffer 3, and 4. event: transmit history list get pointer (tgpt) - message buffer 8, 5, 6, and 10 completes transmission. - thl is full. - tovf bit is set to 1. event: transmit history list (thl) message buffer 6 message buffer 9 message buffer 2 message buffer 7 0 1 2 3 4 5 6 7 - message buffer 11, 13, and 14 completes transmission. - overflow situation occurs. event: tovf bit = 1 lopt is blocked tovf bit = 1 lopt is blocked tovf bit = 1 denotes that lopt equals tgpt ? 1 while message buffer number stored to element indicated by lopt ? 1. last out- message pointer (lopt) transmit history list get pointer (tgpt) transmit history list (thl) message buffer 7 message buffer 3 message buffer 4 0 1 2 3 4 5 6 7 transmit history list (thl) message buffer 6 message buffer 10 message buffer 7 message buffer 3 message buffer 4 message buffer 8 message buffer 5 0 1 2 3 4 5 6 7 last out- message pointer (lopt) transmit history list get pointer (tgpt) transmit history list (thl) message buffer 6 message buffer 14 message buffer 7 message buffer 3 message buffer 4 message buffer 8 message buffer 5 0 1 2 3 4 5 6 7 last out- message pointer (lopt) transmit history list get pointer (tgpt) v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1129 of 1817 sep 19, 2011 21.10.3 automatic block transmission (abt) the automatic block transmission (abt) f unction is used to transmit two or more data frames successively with no cpu interaction. the maximum number of transmit message buffe rs assigned to the abt function is eight (message buffer numbers 0 to 7). by setting the c0ctrl.opmode2 to c0ctrl.opmode0 bits to 010b, ?normal operation mode with automatic block transmission function? (hereafter referred to as abt mode) can be selected. to issue an abt transmission request, define the message buffe rs by software first. set the c0mconfm.ma0 bit (1) in all the message buffers used for abt, and define all th e buffers as transmit message buffers by setting the c0mconfm.mt2 to c0mconfm.m t0 bits to 000b. be sure to set the id for the message buffers for atb for each message buffer, even when that id is being used for all the me ssage buffers. to use two or more ids, set the id of each message buffer by using the c0midlm and c0midhm regist ers. set the c0mdlcm an d c0mdata0m to c0mdata7m registers before issuing a transmission request for the abt function. after initialization of message buffers for abt is finished, the c0 mctrlm.rdy bit needs to be set (1). in the abt mode, the c0mctrlm.trq bit does not have to be manipulated by software. after the data for the abt message buffers has been prepared, set the c0gmabt. abttrg bit to 1. automatic block transmission is then started. when abt is started, the trq bit in the fi rst message buffer (message buffer 0) is automatically set to 1. after transmi ssion of the data of message buffer 0 is finished, the trq bit of the next message buffer, message buffer 1, is set aut omatically. in this way, transmission is executed successively. a delay time can be inserted by program in the interval in which the transmission request (trq bit) is automatically set while successive transmission is being executed. the delay time to be inserted is defi ned by the c0gmabtd register. the unit of the delay time is dbt (data bit time). db t depends on the setting of t he c0brp and c0btr registers. during abt, the priority of the transmission id is not se arched in the abt transmit message buffer. the data of message buffers 0 to 7 is sequentially transmitted. when tr ansmission of the data frame fr om message buffer 7 has been completed, the abttrg bit is automatically cl eared to 0 and the abt operation is finished. if the rdy bit of an abt message buffer is cleared during abt , no data frame is transmitted from that buffer, abt is stopped, and the abttrg bit is cleared. after that, transmi ssion can be resumed from the message buffer where abt stopped, by setting the rdy and abttrg bits to 1 by softwar e. to not resume transmission from the message buffer where abt stopped, the internal abt engine can be rese t by setting the c0gmabt.abtclr bit to 1 while abt mode is stopped and the abttrg bit is cleared to 0. in this case, transmission is started from me ssage buffer 0 if the abtclr bit is cleared to 0 and then the abttrg bit is set to 1. an interrupt can be used to check if data frames have been transmitted from all the message buffers for abt. to do so, the c0mctrlm.ie bit of each message buffer except the last message buffer needs to be cleared (0). if a transmit message buffer other than those used by the abt function (message buffers 8 to 31) is assigned to a transmit message buffer, the priority of the message to be transmitted is determined by the priority of the transmission message buffer of the abt message buffer whose transmissi on is currently held pending and the transmission message buffer of the message buffers other than those used by the abt function. transmission of a data frame from an abt message buffer is not recorded in the transmit history list (thl). v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1130 of 1817 sep 19, 2011 cautions 1. to resume the normal operation mode with abt from the message buffer 0, set the abtclr bit to 1 while the abttrg bit is cleared to 0. if the abtc lr bit is set to 1 while the abttrg bit is set to 1, the subsequent operati on is not guaranteed. 2. whether the automatic block transmission engine is cleared by setting the abtclr bit to 1 can be confirmed if the abtclr bit is automatically cleared to 0 immediately after the processing of the clearing request is completed. 3. do not set the abttrg bit in the initialization mode. if the abttrg bit is set in the initialization mode, the proper operation is not guaranteed afte r the mode is changed from the initialization mode to the abt mode. 4. do not set the trq bit of the abt message bu ffers to 1 by software in the normal operation mode with abt. otherwise, the operation is not guaranteed. 5. the c0gmabtd register is u sed to set the delay time that is inserted in the period from completion of the preceding abt m essage to setting of the trq bit for the next abt message when the transmission re quests are set in the order of message numbers for each message for abt that is successively transmi tted in the abt mode. the timing at which the messages are actually transmitted onto the can bus varies depending on the status of transmission from other stations and the status of the setting of the tr ansmission request for messages other than the abt messages (message buffers 8 to 31). 6. if a transmission request is made for a messag e other than an abt message and if no delay time is inserted in the interval in which transm ission requests for abt are automatically set (c0gmabtd register = 00h), messages other than abt messages may be transmitted regardless of their priority in regards to the abt message. 7. do not clear the rdy bit to 0 when the abttrg bit = 1. 8. if a message is received from another node in the normal operation mode with abt, the message may be transmitted after the time of one frame has elapsed even when c0 gmabtd register = 00h. remark m = 00 to 31 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1131 of 1817 sep 19, 2011 21.10.4 transmission abort process remark m = 00 to 31 (1) transmission abort process other than in normal operation mode with automati c block transmission (abt) the user can clear the c0mctrlm.trq bit to 0 to abort a transmission request. the trq bit will be cleared immediately if the abort was successful. whether t he transmission was successfully aborted or not can be checked using the c0ctrl.tstat bit and the c0tgpt register, which indi cate the transmission status on the can bus (for details, refer to the processing in figure 21-46 ). (2) transmission abort process except for abt transmission in normal ope ration mode with automatic block transmission (abt) the user can clear the c0gmabt.abttrg bit to 0 to a bort a transmission request. after checking the abttrg bit of the c0gmabt register = 0, clear the c0mctrlm.trq bit to 0. the trq bit will be cleared immediately if the abort was successful. whether the transmission was succe ssfully aborted or not can be checked by using the c0ctrl.tstat bit and the c0tg pt register, which indicate the transmiss ion status on the ca n bus (for details, refer to the process in figure 21-47 ). (3) transmission abort in no rmal operation mode with automa tic block transmission (abt) to abort abt that is already started, clear the c0gmabt.abttrg bit to 0. in this case, the abttrg bit remains 1 if an abt message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. this aborts abt. if the last transmission (before abt) was successful, the no rmal operation mode with abt is left with the internal abt pointer pointing to the next message buffer to be transmitted. in the case of an erroneous transmission, the position of the internal abt poi nter depends on the status of the trq bit in the last transmitted message buffer. if t he trq bit is set to 1 when clearing the abttrg bit is requested, the internal abt poi nter points to the last transmitted message buffer (for details, refer to the process in figure 21-48 (a) ). if the trq bit is cleared to 0 when clearin g the abttrg bit is requested, the internal abt pointer is increased in increments of 1 and indicates the next message buffer in the abt area (for details, refer to the process in figure 21-48 (b) ). caution be sure to abort abt by clearing the abttrg bi t to 0. the operation is not guaranteed if aborting transmission is requested by clearing rdy. when the normal operation mode with abt is resumed afte r abt has been aborted and the abttrg bit is set to 1, the next abt message buffer to be transmitted c an be determined from the following table. status of trq of abt message buffer abort after succe ssful transmission abort a fter erroneous transmission set (1) next message buffer in the abt area note same message buffer in the abt area cleared (0) next message buffer in the abt area note next message buffer in the abt area note note the above resumption operation can be performed only if a message buffer ready for abt exists in the abt area. for example, an abort request that is issued while abt of message buffer 7 is in progress is regarded as completion of abt, rather than abort, if transmission of me ssage buffer 7 has been successfully completed, even if the abttrg bit is cleared to 0. if the c0mctrlm.rdy bit in the next message buffer in the abt area is cleared to 0, the internal abt pointer is retained, but the resumption operation is not performed even if the abttrg bit is set to 1, and abt ends immediately. remark m = 00 to 31 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1132 of 1817 sep 19, 2011 21.10.5 remote frame transmission remote frames can be transmitted only from transmit message buffers. set whether a data frame or remote frame is transmitted via the c0mconfm.rtr bit. setting (1 ) the rtr bit sets remote frame transmission. remark m = 00 to 31 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1133 of 1817 sep 19, 2011 21.11 power saving modes 21.11.1 can sleep mode the can sleep mode can be used to set the can controller to standby mode in order to reduce power consumption. the can module can enter the can sleep mode from all operat ion modes. release of the can sleep mode returns the can module to exactly the same operation mode from which the can sleep mode was entered. in the can sleep mode, the can module does not transm it messages, even when transmission requests are issued or pending. (1) entering can sleep mode the cpu issues a can sleep mode transition reques t by writing 01b to the c0ctrl.psmode1 and c0ctrl.psmode0 bits. this transition request is only acknowledged only under the following conditions. (i) the can module is already in one of the following operation modes ? normal operation mode ? normal operation mode with abt ? receive-only mode ? single-shot mode ? self-test mode ? can stop mode in all the above operation modes (ii) the can bus state is bus idle (the 4th bit in the interframe space is recessive) note note if the can bus is fixed to dominant, the request fo r transition to the can sleep mode is held pending. also the transition from can stop mode to can slee p mode is independent of the can bus state. (iii) no transmission request is pending if any one of the conditions mentioned above is not met, the can module will operate as follows. ? if the can sleep mode is requested from the initializ ation mode, the can sleep m ode transition request is ignored and the can module remains in the initialization mode. ? if the can bus state is not bus idle (i.e., the can bus state is either transmitting or receiving) when the can sleep mode is requested in one of t he operation modes, immediate transi tion to the can sleep mode is not possible. in this case, the can sleep mode trans ition request has to be held pending until the can bus state becomes bus idle (the 4th bit in the interframe space is recessive). in the time from the can sleep mode request to successful transition, the psmode1 and psmode0 bits remain 00b. when the module has entered the can sleep mode, the psmode1 and psmode0 bits are set to 01b. ? if a request for transition to the initialization mode a nd a request for transition to the can sleep mode are made at the same time while the can module is in one of the operation modes, the request for the initialization mode is enabled. the can module enters the initialization m ode at a predetermined timing. at this time, the can sleep mode request is not held pending and is ignored. ? even when the initialization mode and sleep mode are not requested simultaneously (i.e the first request was not granted when a second request was made), the r equest for initialization has priority over the can sleep mode request. the can sleep mode request is canc elled when the initialization mode is requested. when a pending request for the initialization mode is pr esent, a subsequent request for the can sleep mode request is cancelled right at the point in time when it was submitted. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1134 of 1817 sep 19, 2011 (2) status in can sleep mode the can module is in one of the following states after it enters the can sleep mode. ? the internal operating clock is stopped a nd the power consumption is minimized. ? the function to detect the falling edge of the can reception pin (crxd0) rema ins in effect to wake up the can module from the can bus. ? to wake up the can module from the cpu, data can be written to t he psmode1 and psmode0 bits, but nothing can be written to other cann module registers or bits. ? the can0 module registers can be read, except for the c0lipt, c0rgpt, c0lopt , and c0tgpt registers. ? the can0 message buffer register s cannot be written or read. ? c0gmctrl.mbon bit is cleared to 0. ? a request for transition to the initializati on mode is not acknowledged and is ignored. (3) releasing can sleep mode the can sleep mode is releas ed by the following events. ? when the cpu writes 00b to the psmode1 and psmode0 bits ? a falling edge at the can reception pin (crxd0) (i.e. the can bus level shifts from recessive to dominant) cautions1. even if the falling edge belongs to the sof of a receive message, this message will not be received and stored. if the cpu has turned off the cl ock to the can while the can was in sleep mode, later on the can sleep mode will not be re leased and psmode[1:0] bi ts will continue to be 01b unless the clock for the can is provided again. in addi tion to this, the receive message will not be received afterwards. caution 2. if a falling edge is detected at the can recep tion pin (crxd0) while th e can clock is supplied, the psmode0 bit must be cleared by software. (for details, refer to the processing in figure 21- 53.) after releasing the sleep mode, the can module returns to the operation mode from wh ich the can sleep mode was requested and the psmode1 and psmode0 bits are reset to 00b . if the can sleep mode is released by a change in the can bus state, the c0ints.cints5 bit is set to 1, regardless of the c0ie.cie bit. after the can module is released from the can sleep mode, it participates in the can bus again by automat ically detecting 11 consecutive recessive-level bits on the can bus. after releasing the sleep mode and before accessing the message buffer by application again, confirm that c0gmctrl.mbon bit = 1. when a request for transition to the initialization mode is made while the can module is in the can sleep mode, that request is ignored; the cpu has to be released from sleep mode by software first before ent ering the initialization mode. caution when the can sleep mode is released by an event of the can bus, a wakeup interrupt occurs even if the event of the can bu s occurs immediately after the mode has been changed to the sleep mode. note that the in terrupt can occur at any time. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1135 of 1817 sep 19, 2011 21.11.2 can stop mode the can stop mode can be used to set the can controller to standby mode to reduce power consumption. the can module can enter the can stop mode only from the can sl eep mode. release of the can stop mode puts the can module in the can sleep mode. the can stop mode can only be released (shifting to can sl eep mode) by writing 01b to the c0ctrl.psmode1 and c0ctrl.psmode0 bits and not by a change in the can bus state. no message is transmitted even when transmission requests are issued or pending. (1) entering can stop mode a can stop mode transition request is issued by writing 11b to the psmode1 and psmode0 bits. a can stop mode request is only acknowledged when the ca n module is in the can sleep mode. in all other modes, the request is ignored. caution to set the can module to the can stop mode, the module must be in the can sleep mode. to confirm that the module is in the sleep mode, check that the psm ode1 and psmode0 bits = 01b, and then request the can stop mode. if a bus change occurs at the can reception pin (crxd0) while this process is being performed, the can sl eep mode is automatically released. in this case, the can stop mode transi tion request cannot be acknowle dged (while the can clock is supplied, however, the psmode0 must be cleared by software after the bus level of the can reception pin (crxd0) is changed). (2) status in can stop mode the can module is in one of the following states after it enters the can stop mode. ? the internal operating clock is stopped a nd the power consumption is minimized. ? to wake up the can module from the cpu, data can be written to t he psmode1 and psmode0 bits, but nothing can be written to other can0 module registers or bits. ? the can0 module registers can be read, except for the c0lipt, c0rgpt, c0lopt , and c0tgpt registers. ? the can0 message buffer register s cannot be written or read. ? the c0gmctrl.mbon bit is cleared to 0. ? an initialization mode transition reques t is not acknowledged and is ignored. (3) releasing can stop mode the can stop mode can only be released by writing 01b to the psmode1 and psmode0 bits. after releasing the can stop mode, the can modul e enters the can sleep mode. when the initialization mode is requested while the can m odule is in the can stop mode, that request is ignored; the cpu has to release the stop mode an d subsequently the can sleep mode before entering into initialization mode. it is impossible to enter another operation mode di rectly from the can stop m ode without entering the can sleep mode, the request will be ignored. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1136 of 1817 sep 19, 2011 21.11.3 example of using power saving modes in some application systems, it may be necessary to plac e the cpu in a power saving mode to reduce the power consumption. by using the power savi ng mode specific to the can module and the power saving mode specific to the cpu in combination, the cpu can be woken up fr om the power saving status by the can bus. here is an example of using the power saving modes. first, put the can module in the can sleep mode (psmode1, psmode0 bits = 01b). next, put the cpu in the power saving mode. if an edge transition from recessive to dominant is detected at the crxd0 signal in this status, the cints5 bit in the can module is set to 1. if the c0ctrl.cie5 bit is set to 1, a wakeup interrupt (intc0wup) is generated. the can module is automatically released from the can sleep mode (psmode1, psmode0 bits = 00b) and returns to normal operation mode (while the can clock is supplied, howe ver, the psmode0 must be cleared by software after a bus level change is detected at the can re ception pin (crxd0).). the cpu, in re sponse to intc0wup, can release its own power saving mode and return to normal operation mode. to further reduce the power consumption of the cpu, the internal clocks, in cluding that of the can module, may be tuned off. in this case, the operating clo ck supplied to the can module is turned off after the can module is put in the can sleep mode. then t he cpu enters a power saving mode in which the clock supplied to the cpu is turned off. if an edge transition from recessive to dominant is detected at the crxd0 signal in this status, the can module can set the cints5 bit to 1 and generate a wakeup inte rrupt (intc0wup) even if it is not s upplied with a clock. the other functions, however, do not operate because the clock supply to the can mo dule is shut off, and the module remains in the can sleep mode. the cpu, in response to intc0wup, releases its power saving mode, resumes supply of the internal clocks, including the clock to the can module, after oscillation stabi lization time has elapsed, and star ts instruction execution. the can module is immediately released from the can sleep mode when the clock supply is resumed, and returns to normal operation mode (psmode1, psmode0 bits = 00b). v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1137 of 1817 sep 19, 2011 21.12 interrupt function the can module provides 6 different interrupt sources. the occurrence of these interrupt sources is stored in interrupt status registers. four separat e interrupt request signals are generated from the six interr upt sources. when an interrupt request signal that corresponds to two or more interrupt sources is generated, the interr upt sources can be identified by using an interrupt status register. after an interrupt source has occurred, the corresponding interrupt stat us bit must be cleared to 0 by software. table 21-20. list of can module interrupt sources interrupt status bit interrupt enable bit no. name register name register interrupt request signal interrupt source description 1 cints0 note 1 c0ints cie0 note 1 c0ie intc0trx message frame successfu lly transmitted from message buffer m 2 cints1 note 1 c0ints cie1 note 1 c0ie intc0rec valid message frame reception in message buffer m 3 cints2 c0ints cie2 c0ie can module error state interrupt note 2 4 cints3 c0ints cie3 c0ie can module protocol error interrupt note 3 5 cints4 c0ints cie4 c0ie intc0err can module arbitration loss interrupt 6 cints5 c0ints cie5 c0ie intc0wup can module wakeup interrupt from can sleep mode note 4 notes 1. the c0mctrl.ie bit (message buffer interrupt enable bit) of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process. 2. this interrupt is generated when the transmission/reception error counter is at the warning level, or in the error passive or bus-off state. 3. this interrupt is generated when a stuff error, form error, ack error, bit error, or crc error occurs. 4. this interrupt is generated when the can module is woken up from the can sleep mode because a falling edge is detected at the can reception pin (can bus transition from recessive to dominant). remark m = 00 to 31 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1138 of 1817 sep 19, 2011 21.13 diagnosis functions and special operational modes the can module provides a receive-only mode, single-s hot mode, and self-test mode to support can bus diagnosis functions or the operation of s pecial can communication methods. 21.13.1 receive-only mode the receive-only mode is used to monitor receive message s without causing any interference on the can bus and can be used for can bus analysis nodes. for example, this mode can be used for automatic baud-rate detection. the bau d rate in the can module is changed until ?valid reception? is detected, so that the baud rates in the module match (?valid reception? means a message frame has been received in the can protocol layer without o ccurrence of an error and with an appropriate ack between nodes connected to the can bus). a valid re ception does not require message frames to be stored in a receive message buffer (data frames) or transmit message buffer (remote frames). the event of valid reception is indicated by setting the c0ctrl.valid bit (1). figure 21-33. can module terminal co nnection in receive-only mode can macro tx rx crxd0 ctxd0 fixed to the recessive level v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1139 of 1817 sep 19, 2011 in the receive-only mode, no message frames can be trans mitted from the can module to the can bus. transmit requests issued for message buffers defined as transmit message buffers are held pending. in the receive-only mode, the can transmission pin (ctxd0) in the can module is fixed to the recessive level. therefore, no active error flag can be transmitted from the can module to the can bus even when a can bus error is detected while receiving a message frame. since no transmi ssion can be issued from the can module, the transmission error counter the c0erc.tec7 to c0erc.tec0 bits are never updated. therefore, a ca n module in the receive-only mode does not enter the bus-off state. furthermore, ack is not returned to the can bus in this mode upon the valid reception of a message frame. internally, the local node recognizes that it has transmitted ack. an overload frame cannot be transmitted to the can bus. caution if only two can nodes are connected to the can bus and one of them is operating in the receive-only mode, there is no ack on the can bu s. due to the missing ack, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. the transmitting node becomes error passive after transmitting the mess age frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred). wh en the message frame is transmitted for the 17th time, the transmitting node gene rates a passive error flag. the receiving node in the receive-only mode detects the first valid message frame at this poi nt, and the valid bit is set to 1 for the first time. 21.13.2 single-shot mode in the single-shot mode, automatic re-t ransmission as defined in the can protoc ol is switched off. (according to the can protocol, a message frame transmission that has been aborted by ei ther arbitration loss or error occurrence has to be repeated without control by software.) all other behavior of single-shot mode is identical to normal operation mode. features of single-shot mode can not be us ed in combination with normal mode with abt. the single-shot mode disables the re-t ransmission of an aborted message frame transmission according to the setting of the c0ctrl.al bit. when the al bit is cleared to 0, re-transmission upon arbitration loss and upon error occurrence is disabled. if the al bit is set to 1, re-transmission upon er ror occurrence is disabled, but re-transmission upon arbitration loss is enabled. as a consequence, t he c0mctrlm.trq bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events. ? successful transmission of the message frame ? arbitration loss while sending the message frame (al bit = 0) ? error occurrence while sending the message frame the events arbitration loss and error occurrence can be distinguished by checking the c0ints.cints4 and c0ints.cints3 bits, and the type of the error can be identifi ed by reading the c0lec.lec2 to c0lec.lec0 bits of the register. upon successful transmission of the message frame, the trans mit completion interrupt the cints0 bit of the c0ints register is set to 1. if the c0ie.cie0 bit is set to 1 at this time, an interrupt request signal is output. the single-shot mode can be used when emulating time-t riggered communication methods (e.g., ttcan level 1). caution the al bit is only valid in single-shot mode. it does not affect the oper ation of re-transmission upon arbitration loss in other operation modes. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1140 of 1817 sep 19, 2011 21.13.3 self-test mode in the self-test mode, message frame transmission and mess age frame reception can be tested without connecting the can node to the can bus or without affecting the can bus. in the self-test mode, the can module is completely disconnected from the ca n bus, but transmission and reception are internally looped back. the can transmission pin (ctxd0) is fixed to the recessive level. if the falling edge on the can reception pin (crxd0) is det ected after the can module has entered the can sleep mode from the self-test mode, however, the module is rel eased from the can sleep mode in the same manner as the other operation modes (when t he sleep mode is released while the can clo ck is supplied, however, the psmode0 bit must be cleared by software after a falling edge is detected at the can reception pin (crxd0).). to keep the module in the can sleep mode, use the can rec eption pin (crxd0) as a port pin. figure 21-34. can module terminal connection in self-test mode can macro tx rx crxd0 ctxd0 fixed to the recessive level v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1141 of 1817 sep 19, 2011 21.13.4 transmission/reception ope ration in each operation mode table 21-21 shows the transmission/recept ion operation in each operation mode. table 21-21. overview of transmission/r eception operation in each operation mode operation mode data frame/ remote frame transmission ack transmission error frame/ overload frame transmission retransmission automatic block transmission (abt) setting of valid bit storing data in message buffer initialization mode ? ? ? ? ? ? ? normal operation mode ? normal operation mode with abt receive-only mode ? ? ? ? ? single-shot mode ? note 1 ? self test mode note 2 note 2 note 2 note 2 ? note 2 note 2 notes 1. if arbitration is lost, retransmission can be selected by the c0ctrl.al bit. 2. each signal is not output to the external circuit but is internally generated by the can module. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1142 of 1817 sep 19, 2011 21.14 time stamp function can is an asynchronous, serial protocol. all nodes connect ed to the can bus have a local, autonomous clock. as a consequence, the clocks of the nodes have no relation (i.e ., the clocks are asynchronous and may even have different frequencies). in some applications, however, a common time base over the net work (= global time base) is needed. in order to build up a global time base, a time stamp functi on is used. the essential mechanism of a time stamp function is the capture of timer values triggered by signals on the can bus. 21.14.1 time stamp function the can controller supports the capturing of timer values tri ggered by a specific frame. an on-chip 16-bit capture timer unit in a microcontroller system is used in addition to the can controller. the 16-bit capture timer unit captures the timer value according to a trigger signal (tsout) for capturing t hat is output when a data frame is received from the can controller. the cpu can retrieve the time of occurrence of the capture event, i.e., the time stamp of the message received from the can bus, by reading the captured value. the tsout signal c an be selected from the following two event sources and is specifie d by the c0ts.tssel bit. ? sof event (start of frame) (tssel bit = 0) ? eof event (last bit of end of frame) (tssel bit = 1) the tsout signal is enabled by setting the c0ts.tsen bit to 1. figure 21-35. timing diagram of capture signal tsout t tsout sof sof sof sof the tsout signal toggles its level upon occurrence of the se lected event during data fram e reception (in figure 21-34, the sof is used as the trigger event sour ce). to capture a timer value by using the tsout signal, the capture timer unit must detect the capture signal at both the rising edge and falling edge. this time stamp function is controlled by the c0ts.tsloc k bit. when the tslock bit is cleared to 0, the tsout signal toggles upon occurrence of the selected event. if t he tslock bit is set to 1, the tsout signal toggles upon occurrence of the selected event, but t he toggle is stopped as the tsen bit is automatically cleared to 0 when a data frame starts to be received and stored in message buffer 0. this suppresses the subsequent toggle occurrence by the tsout signal, so that the time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data frame was received in message buffer 0. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1143 of 1817 sep 19, 2011 caution the time stamp function usi ng the tslock bit stops toggle of th e tsout signal by receiving a data frame in message buffer 0. therefore, message buffer 0 must be set as a receive message buffer. since a receive message buffer ca nnot receive a remote frame, toggle of the tsout signal cannot be stopped by reception of a remote frame. toggle of the tsout signal does not stop when a data frame is received in a message buffer other than message buffer 0. for these reasons, a data frame ca nnot be received in message buff er 0 when the can module is in the normal operation mode with abt, because message buffer 0 must be set as a transmit message buffer. in this operation mode, therefore, the f unction to stop toggle of the tsout signal by the tslock bit cannot be used. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1144 of 1817 sep 19, 2011 21.15 baud rate settings 21.15.1 bit rate setting conditions make sure that the settings are within t he range of limit values for ensuring corre ct operation of the can controller, as follows. (a) 5tq spt (sampling point) 17 tq spt = tseg1 + 1tq (b) 8 tq dbt (data bit time) 25 tq dbt = tseg1 + tseg2 + 1tq = tseg2 + spt (c) 1 tq sjw (synchronization jump width) 4tq sjw dbt ? spt (d) 4tq tseg1 16tq [3 setting value of tseg1[3:0] 15] (e) 1tq tseg2 8tq [0 setting value of tseg2[2:0] 7] remark tq = 1/f tq (f tq : can protocol layer base system clock) tseg1[3:0] (c0btr.tseg 13 to c0btr.tseg10 bits) tseg2[2:0] (c0btr.tseg 22 to c0btr.tseg20 bits) table 21-22 shows the combinations of bi t rates that satisfy the above conditions. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1145 of 1817 sep 19, 2011 table 21-22. settable bit rate combinations (1/3) valid bit rate setting c0btr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg13 to tseg10 tseg22 to tseg20 sampling point (unit: %) 25 1 8 8 8 1111 111 68.0 24 1 7 8 8 1110 111 66.7 24 1 9 7 7 1111 110 70.8 23 1 6 8 8 1101 111 65.2 23 1 8 7 7 1110 110 69.6 23 1 10 6 6 1111 101 73.9 22 1 5 8 8 1100 111 63.6 22 1 7 7 7 1101 110 68.2 22 1 9 6 6 1110 101 72.7 22 1 11 5 5 1111 100 77.3 21 1 4 8 8 1011 111 61.9 21 1 6 7 7 1100 110 66.7 21 1 8 6 6 1101 101 71.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 20 1 3 8 8 1010 111 60.0 20 1 5 7 7 1011 110 65.0 20 1 7 6 6 1100 101 70.0 20 1 9 5 5 1101 100 75.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 19 1 2 8 8 1001 111 57.9 19 1 4 7 7 1010 110 63.2 19 1 6 6 6 1011 101 68.4 19 1 8 5 5 1100 100 73.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 18 1 1 8 8 1000 111 55.6 18 1 3 7 7 1001 110 61.1 18 1 5 6 6 1010 101 66.7 18 1 7 5 5 1011 100 72.2 18 1 9 4 4 1100 011 77.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1146 of 1817 sep 19, 2011 table 21-22. settable bit rate combinations (2/3) valid bit rate setting c0btr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg13 to tseg10 tseg22 to tseg20 sampling point (unit: %) 17 1 2 7 7 1000 110 58.8 17 1 4 6 6 1001 101 64.7 17 1 6 5 5 1010 100 70.6 17 1 8 4 4 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 16 1 1 7 7 0111 110 56.3 16 1 3 6 6 1000 101 62.5 16 1 5 5 5 1001 100 68.8 16 1 7 4 4 1010 011 75.0 16 1 9 3 3 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 15 1 2 6 6 0111 101 60.0 15 1 4 5 5 1000 100 66.7 15 1 6 4 4 1001 011 73.3 15 1 8 3 3 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 14 1 1 6 6 0110 101 57.1 14 1 3 5 5 0111 100 64.3 14 1 5 4 4 1000 011 71.4 14 1 7 3 3 1001 010 78.6 14 1 9 2 2 1010 001 85.7 14 1 11 1 1 1011 000 92.9 13 1 2 5 5 0110 100 61.5 13 1 4 4 4 0111 011 69.2 13 1 6 3 3 1000 010 76.9 13 1 8 2 2 1001 001 84.6 13 1 10 1 1 1010 000 92.3 12 1 1 5 5 0101 100 58.3 12 1 3 4 4 0110 011 66.7 12 1 5 3 3 0111 010 75.0 12 1 7 2 2 1000 001 83.3 12 1 9 1 1 1001 000 91.7 v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1147 of 1817 sep 19, 2011 table 21-22. settable bit rate combinations (3/3) valid bit rate setting c0btr register setting value dbt length sync segment prop segment phase segment1 phase segment2 tseg13 to tseg10 tseg22 to tseg20 sampling point (unit: %) 11 1 2 4 4 0101 011 63.6 11 1 4 3 3 0110 010 72.7 11 1 6 2 2 0111 001 81.8 11 1 8 1 1 1000 000 90.9 10 1 1 4 4 0100 011 60.0 10 1 3 3 3 0101 010 70.0 10 1 5 2 2 0110 001 80.0 10 1 7 1 1 0111 000 90.0 9 1 2 3 3 0100 010 66.7 9 1 4 2 2 0101 001 77.8 9 1 6 1 1 0110 000 88.9 8 1 1 3 3 0011 010 62.5 8 1 3 2 2 0100 001 75.0 8 1 5 1 1 0101 000 87.5 7 note 1 2 2 2 0011 001 71.4 7 note 1 4 1 1 0100 000 85.7 6 note 1 1 2 2 0010 001 66.7 6 note 1 3 1 1 0011 000 83.3 5 note 1 2 1 1 0010 000 80.0 4 note 1 1 1 1 0001 000 75.0 note setting with a dbt value of 7 or less is valid only wh en the value of the c0brp r egister is other than 00h. caution the values in table 21-22 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consid eration oscillation errors and delays of the can bus and can transceiver. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1148 of 1817 sep 19, 2011 21.15.2 representative exampl es of baud rate settings tables 21-23 and 21-24 show representative examples of baud rate settings. table 21-23. representative e xamples of baud rate settings (f canmod = 8 mhz) (1/2) valid bit rate setting (unit: kbps) c0btr register setting value set baud rate value (unit: kbps) division ratio of c0brp register c0brp register set value length of dbt sync segment prop segment phase segment1 phase segment2 tseg13 to tseg10 tseg22 to tseg20 sampling point (unit: %) 1000 1 00000000 8 1 1 3 3 0011 010 62.5 1000 1 00000000 8 1 3 2 2 0100 001 75.0 1000 1 00000000 8 1 5 1 1 0101 000 87.5 500 1 00000000 16 1 1 7 7 0111 110 56.3 500 1 00000000 16 1 3 6 6 1000 101 62.5 500 1 00000000 16 1 5 5 5 1001 100 68.8 500 1 00000000 16 1 7 4 4 1010 011 75.0 500 1 00000000 16 1 9 3 3 1011 010 81.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 500 2 00000001 8 1 1 3 3 0011 010 62.5 500 2 00000001 8 1 3 2 2 0100 001 75.0 500 2 00000001 8 1 5 1 1 0101 000 87.5 250 2 00000001 16 1 1 7 7 0111 110 56.3 250 2 00000001 16 1 3 6 6 1000 101 62.5 250 2 00000001 16 1 5 5 5 1001 100 68.8 250 2 00000001 16 1 7 4 4 1010 011 75.0 250 2 00000001 16 1 9 3 3 1011 010 81.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 250 4 00000011 8 1 3 2 2 0100 001 75.0 250 4 00000011 8 1 5 1 1 0101 000 87.5 125 4 00000011 16 1 1 7 7 0111 110 56.3 125 4 00000011 16 1 3 6 6 1000 101 62.5 125 4 00000011 16 1 5 5 5 1001 100 68.8 125 4 00000011 16 1 7 4 4 1010 011 75.0 125 4 00000011 16 1 9 3 3 1011 010 81.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 125 8 00000111 8 1 3 2 2 0100 001 75.0 125 8 00000111 8 1 5 1 1 0101 000 87.5 caution the values in table 21-23 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consid eration oscillation errors and delays of the can bus and can transceiver. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1149 of 1817 sep 19, 2011 table 21-23. representative e xamples of baud rate settings (f canmod = 8 mhz) (2/2) valid bit rate setting (unit: kbps) c0btr register setting value set baud rate value (unit: kbps) division ratio of c0brp register c0brp register set value length of dbt sync segment prop segment phase segment1 phase segment2 tseg13 to tseg10 tseg22 to tseg20 sampling point (unit: %) 100 4 00000011 20 1 7 6 6 1100 101 70.0 100 4 00000011 20 1 9 5 5 1101 100 75.0 100 5 00000100 16 1 7 4 4 1010 011 75.0 100 5 00000100 16 1 9 3 3 1011 010 81.3 100 8 00000111 10 1 3 3 3 0101 010 70.0 100 8 00000111 10 1 5 2 2 0110 001 80.0 100 10 00001001 8 1 3 2 2 0100 001 75.0 100 10 00001001 8 1 5 1 1 0101 000 87.5 83.3 4 00000011 24 1 7 8 8 1110 111 66.7 83.3 4 00000011 24 1 9 7 7 1111 110 70.8 83.3 6 00000101 16 1 5 5 5 1001 100 68.8 83.3 6 00000101 16 1 7 4 4 1010 011 75.0 83.3 6 00000101 16 1 9 3 3 1011 010 81.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3 8 00000111 12 1 5 3 3 0111 010 75.0 83.3 8 00000111 12 1 7 2 2 1000 001 83.3 83.3 12 00001011 8 1 3 2 2 0100 001 75.0 83.3 12 00001011 8 1 5 1 1 0101 000 87.5 33.3 10 00001001 24 1 7 8 8 1110 111 66.7 33.3 10 00001001 24 1 9 7 7 1111 110 70.8 33.3 12 00001011 20 1 7 6 6 1100 101 70.0 33.3 12 00001011 20 1 9 5 5 1101 100 75.0 33.3 15 00001110 16 1 7 4 4 1010 011 75.0 33.3 15 00001110 16 1 9 3 3 1011 010 81.3 33.3 16 00001111 15 1 6 4 4 1001 011 73.3 33.3 16 00001111 15 1 8 3 3 1010 010 80.0 33.3 20 00010011 12 1 5 3 3 0111 010 75.0 33.3 20 00010011 12 1 7 2 2 1000 001 83.3 33.3 24 00010111 10 1 3 3 3 0101 010 70.0 33.3 24 00010111 10 1 5 2 2 0110 001 80.0 33.3 30 00011101 8 1 3 2 2 0100 001 75.0 33.3 30 00011101 8 1 5 1 1 0101 000 87.5 caution the values in table 21-23 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consid eration oscillation errors and delays of the can bus and can transceiver. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1150 of 1817 sep 19, 2011 table 21-24. representative e xamples of baud rate settings (f canmod = 16 mhz) (1/2) valid bit rate setting (unit: kbps) c0btr register setting value set baud rate value (unit: kbps) division ratio of c0brp register c0brp register set value length of dbt sync segment prop segment phase segment1 phase segment2 tseg13 to tseg10 tseg22 to tseg20 sampling point (unit: %) 1000 1 00000000 16 1 1 7 7 0111 110 56.3 1000 1 00000000 16 1 3 6 6 1000 101 62.5 1000 1 00000000 16 1 5 5 5 1001 100 68.8 1000 1 00000000 16 1 7 4 4 1010 011 75.0 1000 1 00000000 16 1 9 3 3 1011 010 81.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 1000 2 00000001 8 1 3 2 2 0100 001 75.0 1000 2 00000001 8 1 5 1 1 0101 000 87.5 500 2 00000001 16 1 1 7 7 0111 110 56.3 500 2 00000001 16 1 3 6 6 1000 101 62.5 500 2 00000001 16 1 5 5 5 1001 100 68.8 500 2 00000001 16 1 7 4 4 1010 011 75.0 500 2 00000001 16 1 9 3 3 1011 010 81.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 500 4 00000011 8 1 3 2 2 0100 001 75.0 500 4 00000011 8 1 5 1 1 0101 000 87.5 250 4 00000011 16 1 3 6 6 1000 101 62.5 250 4 00000011 16 1 5 5 5 1001 100 68.8 250 4 00000011 16 1 7 4 4 1010 011 75.0 250 4 00000011 16 1 9 3 3 1011 010 81.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 250 8 00000111 8 1 3 2 2 0100 001 75.0 250 8 00000111 8 1 5 1 1 0101 000 87.5 125 8 00000111 16 1 3 6 6 1000 101 62.5 125 8 00000111 16 1 7 4 4 1010 011 75.0 125 8 00000111 16 1 9 3 3 1011 010 81.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125 16 00001111 8 1 3 2 2 0100 001 75.0 125 16 00001111 8 1 5 1 1 0101 000 87.5 caution the values in table 21-24 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consid eration oscillation errors and delays of the can bus and can transceiver. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1151 of 1817 sep 19, 2011 table 21-24. representative e xamples of baud rate settings (f canmod = 16 mhz) (2/2) valid bit rate setting (unit: kbps) c0btr register setting value set baud rate value (unit: kbps) division ratio of c0brp register c0brp register set value length of dbt sync segment prop segment phase segment1 phase segment2 tseg13 to tseg10 tseg22 to tseg20 sampling point (unit: %) 100 8 00000111 20 1 9 5 5 1101 100 75.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 100 10 00001001 16 1 7 4 4 1010 011 75.0 100 10 00001001 16 1 9 3 3 1011 010 81.3 100 16 00001111 10 1 3 3 3 0101 010 70.0 100 16 00001111 10 1 5 2 2 0110 001 80.0 100 20 00010011 8 1 3 2 2 0100 001 75.0 83.3 8 00000111 24 1 7 8 8 1110 111 66.7 83.3 8 00000111 24 1 9 7 7 1111 110 70.8 83.3 12 00001011 16 1 7 4 4 1010 011 75.0 83.3 12 00001011 16 1 9 3 3 1011 010 81.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.3 16 00001111 12 1 5 3 3 0111 010 75.0 83.3 16 00001111 12 1 7 2 2 1000 001 83.3 83.3 24 00010111 8 1 3 2 2 0100 001 75.0 83.3 24 00010111 8 1 5 1 1 0101 000 87.5 33.3 30 00011101 24 1 7 8 8 1110 111 66.7 33.3 30 00011101 24 1 9 7 7 1111 110 70.8 33.3 24 00010111 20 1 9 5 5 1101 100 75.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.3 30 00011101 16 1 7 4 4 1010 011 75.0 33.3 30 00011101 16 1 9 3 3 1011 010 81.3 33.3 32 00011111 15 1 8 3 3 1010 010 80.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.3 37 00100100 13 1 6 3 3 1000 010 76.9 33.3 37 00100100 13 1 8 2 2 1001 001 84.6 33.3 40 00100111 12 1 5 3 3 0111 010 75.0 33.3 40 00100111 12 1 7 2 2 1000 001 83.3 33.3 48 00101111 10 1 3 3 3 0101 010 70.0 33.3 48 00101111 10 1 5 2 2 0110 001 80.0 33.3 60 00111011 8 1 3 2 2 0100 001 75.0 33.3 60 00111011 8 1 5 1 1 0101 000 87.5 caution the values in table 21-24 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consid eration oscillation errors and delays of the can bus and can transceiver. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1152 of 1817 sep 19, 2011 21.16 operation of can controller the processing procedure shown below is recommended to operate the can controller. develop your program by referring to this recommended processing procedure. remark m = 00 to 31 figure 21-36. initialization start set c0gmcs register. set c0brp register, c0btr register. set c0ie register. set c0mask register. initialize message buffers. set c0ctrl register (set opmode bit). end set c0gmctrl register (set gom bit = 1) remark opmode: normal operation mode, normal operation mode with abt, receive-only mode, single- shot mode, self-test mode v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1153 of 1817 sep 19, 2011 figure 21-37. re-initialization start set c0brp register, c0btr register. set c0ie register. set c0mask register. set c0ctrl register. (set opmode bit) end clear opmode. init mode? no yes no c0erc and c0info register clear? initialize message buffers. yes set ccerc bit. set ccerc bit = 1 caution after setting the can module to the initializ ation mode, avoid setting the module to another operation mode immediately after. if it is n ecessary to immediately set the module to another operation mode, be sure to access registers othe r than the c0ctrl and c0gmctrl registers (e.g., set a message buffer). remark opmode: normal operation mode, normal operation mode with abt, receive-only mode, single- shot mode, self-test mode v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1154 of 1817 sep 19, 2011 figure 21-38. message buffer initialization start set c0mconfm register. set c0midhm register, c0midlm register. set c0mdlcm register. clear c0mdatam register. set c0mctrlm register. end transmit message buffer? yes no clear rdy bit. set rdy bit = 0 clear rdy bit = 1 rdy bit = 1? rdy bit = 0? no yes yes set rdy bit. set rdy bit = 1 clear rdy bit = 0 no cautions 1. before a message buffer is initialized, the rdy bit must be cleared. 2. make the following settings for message buffers not used by the application. ? clear the c0mctrlm.rdy, c0mctrlm .trq, and c0mctrlm.dn bits to 0. ? clear the c0mconfm.ma0 bit to 0. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1155 of 1817 sep 19, 2011 figure 21-39 shows the processing for a receive message buffer (c0mconfm.mt2 to c0mconfm.mt0 bits = 001b to 101b). figure 21-39. message buffer redefinition start end no ye s no ye s ye s no start set message buffers. end rdy = 1? no ye s clear rdy bit. c0mctrlm.set_rdy = 0 c0mctrlm.clear_rdy = 1 rdy = 0? rstat = 0 or valid = 1? note 1 no clear valid bit. c0ctrlclear_valid =1 set rdy bit. c0mctrlm.set_rdy = 1 c0mctrlm.clear_rdy = 0 ye s ye s no wait for a period of 4 can data bits note 2 . notes 1. if redefinition is performed during a message re ception, confirm that a message is being received because the rdy bit must be set a fter a message is co mpletely received. 2. this 4-bit period may redefine the message buffer while a message is received and stored. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1156 of 1817 sep 19, 2011 figure 21-40 shows the processing for a transmit message bu ffer during transmission (mt2 to mt0 bits of c0mconfm register = 000b). figure 21-40. message buffer re definition during transmission start end rdy = 0? no ye s remote frame data frame transmit abort process transmit? = 1 ye s wait for 1can data bits no start end rdy bit = 0? no ye s data frame or remote frame? set rdy bit. set_rdy bit = 1 clear_rdy bit = 0 set c0mdataxm, c0mdlcm registers. clear rtr bit of c0mconfm register. set c0midlm and c0midhm registers. set c0mdlcm register. set rtr bit of c0mconfm register. set c0midlm and c0midhm registers. remote frame data frame transmit abort process clear rdy bit. set_rdy bit = 0 clear_rdy bit = 1 transmit? set trq bit. set_trq bit = 1 clear_trq bit = 0 ye s wait for a 1-bit period of can data. no v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1157 of 1817 sep 19, 2011 figure 21-41 shows the processing for a transmit message buffer (c0mconfm.mt2 to c0mconfm.mt0 bits = 000b). figure 21-41. message transmit processing start set trq bit. set trq bit = 1 clear trq bit = 0 end trq bit = 0? yes no clear rdy bit. set rdy bit = 0 clear rdy bit = 1 set rdy bit. set rdy bit = 1 clear rdy bit = 0 rdy bit = 0? yes no data frame or remote frame? remote frame data frame set rtr bit of c0mdlcm register and c0mconfm register. set c0midlm and c0midhm registers. set c0mdataxm, c0mdlcm registers. clear rtr bit of c0mconfm register. set c0midlm and c0midhm registers. cautions 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1158 of 1817 sep 19, 2011 figure 21-42 shows the processing for a transmit message buffer (c0mconfm.mt2 to c0mconfm.mt0 bits = 000b). figure 21-42. abt message transmit processing start end abttrg = 0? no ye s rdy = 0? set rdy bit ye s no set abttrg bit set all abt transmit messages? tstat = 0? ye s no ye s no start end abttrg bit = 0? no ye s clear rdy bit set_rdy bit = 0 clear_rdy bit = 1 rdy bit = 0? set rdy bit. ye s no set abttrg bit. set all abt transmit messages? tstat bit = 0? ye s no ye s no set_abttrg = 1 clear_abttrg = 0 set_rdy bit = 1 clear_rdy bit = 0 set c0mdataxm register. set c0mdlcm register. clear rtr bit of c0mconfm register. set c0midlm and c0midhm registers. caution the abttrg bit should be set to 1 after the tstat bit is cleared to 0. the checking of the tstat bit and the setting for the abttrg bit to 1 must be continuous. remark this processing (message transmit processing wit h abs) can only be applied to message buffers 0 to 7. for message buffers other than the abt message buffers, refer to figure 21-41 . v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1159 of 1817 sep 19, 2011 figure 21-43. transmission via in terrupt (using c0lopt register) start end transmit completion interrupt servicing read c0lopt register. clear rdy bit. set rdy bit = 0 clear rdy bit = 1 rdy bit = 0? no yes set rdy bit. set rdy bit = 1 clear rdy bit = 0 set trq bit. set trq bit = 1 clear trq bit = 0 data frame or remote frame? remote frame data frame set c0mdlcm register. set rtr bit of c0mconfm register. set c0midlm and c0midhm registers. set c0mdataxm, c0mdlcm registers. clear rtr bit of c0mconfm register. set c0midlm and c0midhm registers. cautions 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. remark check the mbon bit at the start and end of the in terrupt routine to see if the message buffer and transmit history register can be accessed, because a can sleep mode transition request which has been held pending may be under execution. if the mbon bit is cleared (0), stop the processing under execution. re-execute the processing after the mbon bit is set (1) again. it is therefore recommended to cancel the can sleep mode tr ansition request before executing transmission interrupt servicing. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1160 of 1817 sep 19, 2011 figure 21-44. transmission via in terrupt (using c0tgpt register) start end clear rdy bit. set rdy bit = 0 clear rdy bit = 1 tovf bit = 1? clear tovf bit. clear tovf bit = 1 thpm bit = 1? yes no yes no transmit completion interrupt servicing set rdy bit. set rdy bit = 1 clear rdy bit = 0 set trq bit. set rdy bit = 1 clear rdy bit = 0 read c0tgpt register. rdy bit = 0? yes no data frame or remote frame? remote frame data frame set c0mdlcm register. set rtr bit of c0mconfm register. set c0midlm and c0midhm registers. set c0mdataxm, c0mdlcm registers. clear rtr bit of c0mconfm register. set c0midlm and c0midhm registers. cautions 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. remarks 1. check the mbon bit at the start and end of the interrupt routine to see if the message buffer and transmit history register can be accessed, becau se a can sleep mode transition request which has been held pending may be under execution. if the mbon bit is cleared (0), stop the processing under execution. re-execute the processing after the mbon bit is set (1) again. it is therefore recommended to cancel the can sl eep mode transition request before executing transmission interrupt servicing. 2. if the tovf bit is set (1) again, the transmit history list contradi cts. therefore, scan all the transmit message buffers that have completed transmission. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1161 of 1817 sep 19, 2011 figure 21-45. transmi ssion via software polling start end read c0tgpt register. cints0 bit = 1? tovf bit = 1? clear tovf bit. clear tovf bit = 1 thpm bit = 1? yes no yes no yes no clear cints0 bit. clear cints0 bit = 1 clear rdy bit. set rdy bit = 0 clear rdy bit = 1 set rdy bit. set rdy bit = 1 clear rdy bit = 0 set trq bit. set trq bit = 1 clear trq bit = 0 rdy bit = 0? no yes data frame or remote frame? set c0mdlcm register. set rtr bit of c0mconfm register. set c0midlm and c0midhm registers. set c0mdataxm, c0mdlcm registers. clear rtr bit of c0mconfm register. set c0midlm and c0midhm registers. remote frame data frame cautions 1. the trq bit should be set after the rdy bit is set. 2. the rdy bit and trq bit should not be set at the same time. remarks 1. check the mbon bit at the start and end of the polling routine to see if the message buffer and transmit history register can be accessed, becau se a can sleep mode transition request which has been held pending may be under execution. if the mbon bit is cleared (0), stop the processing under execution. re-execute the processing after the mbon bit is set (1) again. 2. if the tovf bit is set (1) again, the transmit history list contradi cts. therefore, scan all the transmit message buffers that have completed transmission. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1162 of 1817 sep 19, 2011 figure 21-46. transmission abort processing (oth er than in normal operation mode with abt) start no yes end clear trq bit. set trq bit = 0 clear trq bit = 1 tstat bit = 0? no wait for a period of 11 can data bits note . yes read c0lopt register. message buffer to be aborted matches c0lopt register? transmission successful transmit abort request was successful. note during a period of a total of 11 bits, 3 bits of in terframe space and 8 bits of suspend transmission, the transmission request may have already been acknowledged by the protocol layer. consequently, transmission may not be aborted but started even if the trq bit is cleared. cautions 1. execute transmission abort processi ng by clearing the trq bit, not the rdy bit. 2. before making a sleep mode transition re quest, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. do not execute a new tr ansmission request that includ es other message buffers while transmission abort processing is in progress. 5. if data of the same message buffer are successively transmitted or if only one message buffer is used, judgments whether transmi ssion has been successfully executed or failed may contradict. in such a case, make a judgm ent by using the history information of the c0tgpt register. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1163 of 1817 sep 19, 2011 figure 21-47. transmission abort pr ocessing except for abt transmission (normal operation mode with abt) end no ye s no transmission successful transmit abort request was successful. ye s no ye s start read c0lopt register. end no ye s clear trq bit. set_trq bit = 0 clear_trq bit = 1 tstat bit = 0? message buffer to be aborted matches c0lopt register? no wait for a period of 11 can data bits. note ye s no abttrg bit = 0? clear abttrg bit. set_abttrg bit = 0 clear_abttrg bit = 1 ye s note during a period of a total of 11 bits, 3 bits of in terframe space and 8 bits of suspend transmission, the transmission request may have already been acknow ledged by the protocol layer. consequently, transmission may not be aborted but started even if the trq bit is cleared. cautions 1. execute transmission abort processi ng by clearing the trq bit, not the rdy bit. 2. before making a sleep mode transition request, confirm th at there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. do not execute a new tran smission request including in th e other message buffers while transmission abort processing is in progress. 5. if data of the same message buffer are successively transmitted or if only one message buffer is used, judgments whether transmi ssion has been successfully executed or failed may contradict. in such a case, make a judgm ent by using the history information of the c0tgpt register. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1164 of 1817 sep 19, 2011 figure 21-48 (a) shows processing that does not skip resu ming the transmission of a message that was interrupted when the transmission of an abt message buffer was aborted. figure 21-48 (a). abt transmission abort pr ocessing (normal operation mode with abt) end abttrg bit = 0? yes no start no yes clear abttrg bit. set abttrg bit = 0 clear abttrg bit = 1 set abtclr bit. set abtclr bit = 1. clear trq bit of message buffer whose transmission was aborted. transmit abort transmission start pointer clear? tstat bit = 0? yes no cautions 1. do not set any transmission request s while abt transmission abort processing is in progress. 2. make a can sleep mode/can stop mode transi tion request after the abttrg bit is cleared (after abt mode is stopped) following the pr ocedure shown in figure 21-48 (a) or (b). when clearing a transmission request in an area other than the abt area, follow the procedure shown in figure 21-46. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1165 of 1817 sep 19, 2011 figure 21-48 (b) shows the processing that does not skip re suming the transmission of a message that was interrupted when the transmission of an abt message buffer was aborted. figure 21-48 (b). abt transm ission abort processing (norma l operation mode with abt) end abttrg bit = 0? yes no start no yes clear abttrg bit. set abttrg bit = 0 clear abttrg bit = 1 set abtclr bit. set abtclr bit = 1 transmit abort transmission start pointer clear? clear trq bit of message buffer undergoing transmission. cautions 1. do not set any transmission request s while abt transmission abort processing is in progress. 2. make a can sleep mode/can stop mode requ est after the abttrg bit is cleared (after abt mode is stopped) following the procedure sh own in figure 21-48 (a) or (b). when clearing a transmission request in an area ot her than the abt area, follow the procedure shown in figure 21-46. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1166 of 1817 sep 19, 2011 figure 21-49. reception via inte rrupt (using c0lipt register) start end read c0lipt register. dn bit = 0 and muc bit = 0 note yes no clear dn bit. clear dn bit = 1 clear cints1 bit. clear cints1 bit = 1 receive completion interrupt read c0mdataxm, c0mdlcm, c0midlm, and c0midhm registers. note check the muc and dn bits using one read access. remark check the mbon bit at the start and end of the interrupt routine to see if the message buffer and receive history register can be accessed, bec ause a can sleep mode transition request which has been held pending may be under execution. if the mbon bit is cleared (0), stop the processing under execution. re-execute the processing after the mbon bit is set (1) again. it is therefore recommended to cancel the can sleep mode transition request before executing reception interrupt servicing. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1167 of 1817 sep 19, 2011 figure 21-50. reception via inte rrupt (using c0rgpt register) end rovf bit = 1? yes no clear rovf bit. clear rovf bit = 1 rhpm bit = 1? yes start no clear dn bit. clear dn bit = 1 dn bit = 0 and muc bit = 0 note read c0mdataxm, c0mdlcm, c0midlm, and c0midhm registers. yes no receive completion interrupt read c0rgpt register. read normal data. read illegal data. note check the muc and dn bits using one read access. remarks 1. check the mbon bit at the start and end of the in terrupt routine to see if the message buffer and receive history register can be accessed, be cause a can sleep mode transition request which has been held pending may be under execution. if the mbon bit is cleared (0), stop the processing under execution. re-execute the processing after the mbon bit is set (1) again. it is therefore recommended to cancel the can sl eep mode transition request before executing reception interrupt servicing. 2. if the rovf bit has been once set (1), the receive hi story list contradicts. therefore, scan all the receive message buffers that have completed reception. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1168 of 1817 sep 19, 2011 figure 21-51. reception via software polling start end read c0rgpt register yes no rovf bit = 1? yes no clear rovf bit. clear rovf bit = 1 clear dn bit. clear dn bit = 1 rhpm bit = 1? no yes cints1 bit = 1? no yes clear cints1 bit. clear cints1 bit = 1 read c0mdataxm, c0mdlcm, c0midlm, and c0midhm registers. dn bit = 0 and muc bit = 0 note read normal data. read illegal data. note check the muc and dn bits using one read access. remarks 1. check the mbon bit at the start and end of the polling routine to see if the message buffer and receive history register can be accessed, be cause a can sleep mode transition request which has been held pending may be under execution. if the mbon bit is cleared (0), stop the processing under execution. re-execute the processing after the mbon bit is set (1) again. 2. if the rovf bit has been once set (1), the receive hi story list contradicts. therefore, scan all the receive message buffers that have completed reception. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1169 of 1817 sep 19, 2011 figure 21-52. setting can sleep mode/stop mode start (when psmode[1:0] = 00b) psmode0 = 1? set psmode0 bit set_psmode1 = 1 clear_psmode1 = 0 can sleep mode can sleep mode end ye s no set psmode1 bit. set_psmode1 = 1 clear_psmode1 = 0 psmode1 = 1? can stop mode request can sleep mode again? set c0ctrl register. (set opmode) ye s no ye s no access to registers other than the c0ctrl and c0gmctrl registers. init mode? ye s no clear cints5 bit. clear_cints5 = 1 clear opmode. caution to abort transmission before making a re quest for the can sleep m ode, perform processing according to figures 21-46 to 21-48. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1170 of 1817 sep 19, 2011 figure 21-53. clear can sleep/stop mode start end clear psmode1 bit. set psmode1 bit = 0 clear psmode1 bit = 1 can stop mode can sleep mode after dominant edge detection, psmode0 bit = 0 cints5 bit = 1 clear cints5 bit. clear cints5 bit = 1 (when can clock is not supplied) can sleep mode release when can bus becomes active (when can clock is supplied note ) can sleep mode release when can bus becomes active clear cints5 bit. clear cints5 bit = 1 clear psmode0 bit. set psmode0 bit = 0 clear psmode0 bit = 1 clear psmode0 bit. set psmode0 bit = 0 clear psmode0 bit = 1 after dominant edge detection, psmode0 bit = 0/1 cints5 bit = 1 can sleep mode release by user note the state in which the can clock is supplied means the state in which the can sleep mode is set without setting any of the following cpu standby modes. ? stop mode ? idle1 and idle2 modes ? the main clock has been stopped in subclock operation mode or sub-idle mode v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1171 of 1817 sep 19, 2011 figure 21-54. bus-off recovery (other than in normal operation mode with abt) start boff bit = 1? no yes set ccerc bit. set ccerc bit = 1 end no yes set c0ctrl register. (clear opmode bit) access to register other than c0ctrl and c0gmctrl registers. forced recovery from bus off? set c0ctrl register. (set opmode bit) set c0ctrl register. (set opmode bit) wait for recovery from bus off. clear all trq bits note . note to initialize the message buffer by clearing the rdy bit before starting the bus-off recovery sequence, clear all the trq bits. caution if a request to change the mode from the in itialization mode to any op eration mode is made to execute the bus-off recovery sequence again dur ing a bus-off recovery sequence, the receive error counter (c0erc.rec0 to rec6 bits) is cl eared. it is therefor e necessary to detect 11 contiguous recessive bits 128 times on the bus again. remark opmode: normal operation mode, normal operation mode with abt, receive-only mode, single- shot mode, self-test mode v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1172 of 1817 sep 19, 2011 figure 21-55. bus-off recovery (normal operation mode with abt) start no yes set ccerc bit. set ccerc bit = 1 end no yes access to register other than c0ctrl and c0gmctrl registers. set c0ctrl register. (set opmode bit.) set c0ctrl register. (set opmode.) clear all trq bit note boff bit = 1? set c0ctrl register. (clear opmode bit.) clear abttrg bit. set abttrg bit = 0 clear abttrg bit = 1 forced recovery from bus off? wait for recovery from bus off. note to initialize the message buffer by clearing the rdy bit before starting the bus-off recovery sequence, clear all the trq bits. caution if a request to change the mode from the in itialization mode to any op eration mode is made to execute the bus-off recovery sequence again dur ing a bus-off recovery sequence, the receive error counter (c0erc.rec0 to rec6 bits) is cl eared. it is therefor e necessary to detect 11 contiguous recessive bits 128 times on the bus again. remark opmode: normal operation mode, normal operation mode with abt, receive-only mode, single- shot mode, self-test mode v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1173 of 1817 sep 19, 2011 figure 21-56. normal shutdown process start clear gom bit. set gom bit = 0 clear gom bit = 1 shutdown successful gom bit = 0, efsd bit = 0 end init mode v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1174 of 1817 sep 19, 2011 figure 21-57. forced shutdown process start set efsd bit. set efsd bit = 1 clear gom bit. set gom bit = 0 clear gom bit = 1 shutdown successful gom bit = 0, efsd bit = 0 end must be a continuous write. gom bit = 0? yes no caution do not read- or write-access any register s by software between setting the efsd bit and clearing the gom bit. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1175 of 1817 sep 19, 2011 figure 21-58. error handling start cints2 bit = 1? cints3 bit = 1? cints4 bit = 1? clear cints2 bit. clear cints2 bit = 1 end yes no no yes no yes check can module state. (read c0info register) check can protocol error state. (read c0lec register) clear cints3 bit. clear cints3 bit = 1 clear cints4 bit. clear cints4 bit = 1 error interrupt v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1176 of 1817 sep 19, 2011 figure 21-59. setting cpu standby (from can sleep mode) start set psmode0 bit. set psmode0 bit = 1 clear psmode0 bit = 0 yes no psmode0 bit = 1? can sleep mode set cpu standby mode. end clear cints5 bit. clear cints5 bit = 1 clear psmode0 bit. set psmode0 bit = 0 clear psmode0 bit = 1 yes no mbon bit = 0? yes no cints5 bit 1? note check if the cpu is in the can sleep mode before setting it to the standby mode. the can sleep mode may be released by wakeup after it is checked if the cpu is in the can sleep mode and before the cpu is set in the standby mode. v850es/jh3-e, v850es/jj3-e chapt er 21 can controller r01uh0290ej0300 rev.3.00 page 1177 of 1817 sep 19, 2011 figure 21-60. setting cpu st andby (from can stop mode) start end set psmode0 bit. set psmode0 bit = 1 clear psmode0 bit = 0 psmode0 bit = 1? psmode1 bit = 1? no yes no set psmode1 bit. set psmode1 bit = 1 clear psmode1 bit = 0 clear psmode0 bit. set psmode0 bit = 0 clear psmode0 bit = 1 clear cints5 bit note clear cints5 bit = 1 yes mbon bit = 1? yes no can stop mode set cpu standby mode. can sleep mode note during wakeup interrupts caution the can stop mode can only be released by writing 01 to the c0ctrl.psmode1 and c0ctrl.psmode0 bits. the can stop mode cannot be released by changing the can bus. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1178 of 1817 sep 19, 2011 chapter 22 usb function controller (usbf) the v850es/jh3-e and v850es/jj3-e have an internal usb f unction controller (usbf) conforming to the universal serial bus specification. data communication using the polling method is performed between the usb function controller and external host device by using a token-based protocol. 22.1 overview ? conforms to the universal serial bus specification ? supports 12 mbps (full-speed) transfer ? endpoint for transfer incorporated endpoint name fifo size (bytes) transfer type remark endpoint0 read 64 control transfer ? endpoint0 write 64 control transfer ? endpoint1 64 2 bulk 1 transfer (in) 2-buffer configuration endpoint2 64 2 bulk 1 transfer (out) 2-buffer configuration endpoint3 64 2 bulk 2 transfer (in) 2-buffer configuration endpoint4 64 2 bulk 2 transfer (out) 2-buffer configuration endpoint7 8 interrupt transfer ? ? bulk transfer (in/out) can be executed as dma transfer (2-cycle single-transfer mode) ? usb clock: internal clock (6 mhz external clock internal clock multiplied by 8 = 48 mhz internal clock) or external clock (external clock input to exclk pin (f usb = 48 mhz)) selectable caution the registers listed in 22.6.2 usb function cont roller register list must be accessed after specifying that the internal clock or the external clock is to be used as the usb clock and enabling clock supply to the usb function controller. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1179 of 1817 sep 19, 2011 22.2 configuration 22.2.1 block diagram figure 22-1. block diagram of usb function controller usbf controller sie i/o buffer endpoint endpoint0 read (64 bytes) endpoint0 write (64 bytes) endpoint1 (64 bytes 2) endpoint2 (64 bytes 2) endpoint3 (64 bytes 2) endpoint4 (64 bytes 2) endpoint7 (8 bytes) usbf interrupt (intusbf0) internal cpu usb resume interrupt (intusbf1) usb clock udmf udpf bridge circuit bridge interrupt enable register (brginte) remarks 1. inside broken lines: these functions are included in the usb function controller. 2. n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1180 of 1817 sep 19, 2011 22.2.2 usb memory map the usb function controller seen from the cpu is assigned to the cs1 space in the microcontroller. the memory space is divided for use as follows. table 22-1. division of cpu memory space address area 00200000h to 00200092h epc control register area 00200100h to 00200114h epc data hold register area 00200144h to 002003c4h epc request data register area 00200400h to 00200408h bridge register area 00200500h to 0020050eh dma register area 00201000h ep1 (bulk-in1) 00202000h bulk-in register area ep3 (bulk-in2) 00210000h ep2 (bulk-out1) 00220000h bulk-out register area ep4 (bulk-out2) 00240000h peripheral control register area v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1181 of 1817 sep 19, 2011 22.3 external circuit configuration 22.3.1 outline in usb transmission, when communication is performed with the host controller and function controller facing each other, pull-up/pull-down resistors must be connected to the usb signal (d+/d ? ) to identify the communication partner. moreover in the v850es/jh3-e and v850es/jj3-e, series resistors must also be connected. because the v850es/jh3-e and v850es/jj3-e do not include t hese pull-up/pull-down resistors and series resistors, be sure to connect them externally. the following shows the outline configurati on of the usb transmission line. for deta ils of the external configuration, see the description provided in each section. figure 22-2. outline configuration of pull-up, pu ll-down, series resistors in usb transmission line function device host device (usb function controller in the v850es/jh3-e and v850es/jj3-e is fixed to full speed) connect series resistors when using the v850es/jh3-e and v850es/jj3-e full speed low speed 15 k 5% 15 k 5% function side mount either one in accordance with operation speed. host side v dd d+ d- v dd v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1182 of 1817 sep 19, 2011 22.3.2 connection configuration figure 22-3. example of usb function controller connection vbus d+ d ? p42/intp10 udpf udmf v850es/jh3-e, v850es/jj3-e p41 uv dd ic1 uv dd r2 ic2 r1 vbus is resistance- divided at a ratio of r1:r2. insert a series resistor adjacent to the v850es/jh3-e or v850es/jj3-e. make the length of the wiring between resistors and d+/d ? of the usb connector the same. usb connector schmitt buffer recommended 50 k or more (floating protection) connect a pull-up resistor to d+. 1.5 k 5%. determine the pull-up resistor value in accordance with the buffer type (pull-down/pull-up) of the port pin to be used. 30 5% 30 5% (1) series resistor connection to d+/d ? connect series resistors of 30 5% to the d+/d ? pins (ufdp, ufdm) of the usb function controller in the v850es/jh3-e and v850es/jj3-e. if they are not connect ed, the impedance rating cannot be satisfied and the output waveform may be disturbed. allocate the series resistors adjacent to the v850es/ jh3-e or v850es/jj3-e, and ma ke the length of the wiring between the series resistors and the usb connectors the same, to make the impedance of d+ and d ? equal (a differential with 90 5% is recommended). (2) pull-up control of d+ because the function controller of the v850es/jh3-e and v850es/jj3-e is fixed to full speed (fs), be sure to pull up the d+ pin (ufdp) by 1.5 k 5% to uv dd . to disable a connection report (d+ pull up) to the us b host/hub (such as during high priority servicing or initialization), control the pull-up resist or of d+ via a general-purpose port in the system. for a circuit such as the one shown in figure 22-3, control the pull-up control signal and the vbus input signal of the d+ pin by using a general-purpose port and the usb cable vbus (and circuit) . in figure 22-3, if the general-purpose port is row level, pulling up of d+ is prohibited. for the ic2 in figure 22-3, use an ic to which volt age can be applied when the system power is off. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1183 of 1817 sep 19, 2011 (3) detection of usb cable connection/disconnection the usb function controller (usbf) requires a vbus input si gnal to recognize whether the usb cable is connected or disconnected, because the state of t he usbf is controlled by hardware. the voltage from the usb host or hub (5 v) is applied as the vbus input signal when the usb cable vbus is connected to the usb host or hub while the usbf power is off. therefore, for ic1 in figure 22-3, use an ic to which voltage can be applied when the system power is off. when disconnecting the usb cable in the circuit in figure 22-3, the input signal to intp10 may be unstable while the vbus voltage is dropping. it is therefore recommended to use a schmitt buffer for ic1 in figure 22-3. (4) floating protection during initialization or when usbf is unused when the usb function controller is initialized or unused, to avoi d a floating status, pull the d+/d ? pins down using a resistor of 50 k or higher. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1184 of 1817 sep 19, 2011 22.4 cautions (1) clock accuracy to operate the usb function controller, the internal clock (6 mhz external clock internal clock multiplied by 8 = 48 mhz internal clock) or external clock (external clock input to exclk pin (f usb = 48 mhz)) must be used as the usb clock. when the internal clock is used as the usb clock, use a resonator with an accuracy of 6 mhz 500 ppm (max.). when the external clock is used, apply a clock with an accuracy of 48 mhz 500 ppm (max.) to the exclk pin. if the usb clock accuracy drops, the transmission data cannot satisfy the usb rating. (2) stopping the usb clock when the main clock (f xx ) has been selected as the usb function contro ller clock and it is necessary to stop the usb function controller, be sure to stop the usb functi on controller (by setting bits 1 and 0 of the ufckmsk register to 1) first before stopping the main clock (f xx ). if the main clock (f xx ) is stopped without first stopping the usb function controller, a malfunction might occur due to noise in the clock pulse when the main clock (f xx ) is restarted. similarly, when an external clock whose signal is input from the exclk pin is selected as the usb function controller clock, measures must be ta ken to prevent noise from being generated in the clock pulse by the external circuit. if this is not feasible, then the usb function c ontroller must be stopped first before stopping the main clock (f xx ). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1185 of 1817 sep 19, 2011 22.5 requests the usb standard has a request command that reports requests from the host device to the function device to execute response processing. the requests are received in the setup stage of control transfer, and most can be automatically processed via the hardware of the usb functi on controller (usbf). 22.5.1 automatic requests (1) decode the following tables show the request format and the correspondence between requests and decoded values. table 22-2. request format offset field name 0 bmrequesttype 1 brequest 2 lower side 3 wvalue higher side 4 lower side 5 windex higher side 6 lower side 7 wlength higher side v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1186 of 1817 sep 19, 2011 table 22-3. correspondence between requests and decoded values decoded value response bmrequesttype brequest wvalue windex wlength offset request 0 1 3 2 5 4 7 6 df ad cf data stage get_interface 81h 0ah 00h 00h 00h 0nh 00h 01h stall stall ack nak get_configuration 80h 08h 00h 00h 00h 00h 00h 01h ack nak ack nak ack nak get_descriptor device 80h 06h 01h 00h 00h 00h xxh xxh note 1 ack nak ack nak ack nak get_descriptor configuration 80h 06h 02h 00h 00h 00h xxh xxh note 1 ack nak ack nak ack nak get_status device 80h 00h 00h 00h 00h 00h 00h 02h ack nak ack nak ack nak get_status endpoint 0 82h 00h 00h 00h 00h 00h 80h 00h 02h ack nak ack nak ack nak get_status endpoint x 82h 00h 00h 00h 00h $$h 00h 02h stall stall ack nak clear_feature device note 2 00h 01h 00h 01h 00h 00h 00h 00h ack nak ack nak ack nak clear_feature endpoint 0 note 2 02h 01h 00h 00h 00h 00h 80h 00h 00h ack nak ack nak ack nak clear_feature endpoint x note 2 02h 01h 00h 00h 00h $$h 00h 00h stall stall ack nak set_feature device note 3 00h 03h 00h 01h 00h 00h 00h 00h ack nak ack nak ack nak set_feature endpoint 0 note 3 02h 03h 00h 00h 00h 00h 80h 00h 00h ack nak ack nak ack nak set_feature endpoint x note 3 02h 03h 00h 00h 00h $$h 00h 00h stall stall ack nak set_interface 01h 0bh 00h 0#h 00h 0?h 00h 00h stall stall ack nak set_configuration note 4 00h 09h 00h 00h 01h 00h 00h 00h 00h ack nak ack nak ack nak set_address 00h 05h xxh xxh 00h 00h 00h 00h ack nak ack nak ack nak remark : data stage : no data stage notes 1. if the wlength value is lower than the prepared value, the wlength value is retur ned; if the wlength value is the prepared value or higher, the prepared value is returned. 2. the clear_feature request clears uf0 device status register l (uf0 dstl) and uf0 epn status register l (uf0ensl) (n = 0 to 4, 7) when ack is received in the status stage. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1187 of 1817 sep 19, 2011 notes 3. the set_feature request sets the uf0 device status register l (uf0 dstl) and uf0 epn status register l (uf0ensl) (n = 0 to 4, 7) when ack is received in the status stage. if the e0halt bit of the uf0e0sl register is set, a stall response is made in the stat us stage or data stage of c ontrol transfer for a request other than the get_status endpoint0 request, set_feature endpoint0 request, and a request generated by the cpudec interrupt request, until the clear_feature endpoint0 request is received. a stall response to an unsupported request does not set t he e0halt bit of the uf0e0sl register to 1, and the stall response is cleared as soon as the next setup token has been received. 4. if the wvalue is not the default value, an automatic stall response is made. cautions 1. the sequence of contro l transfer defined by the universal se rial bus specification is not satisfied under the following conditions. the operation is not guar anteed under these conditions. ? if an in/out token is sudden ly received without a setup stage ? if data pid1 is sent in th e data phase of the setup stage ? if a token of 128 addresses or more is received ? if the request data transmitted in th e setup stage is of less than 8 bytes 2. an ack response is made even when the host transmits data other than a null packet in the status stage. 3. if the wlength value is 00h during control transfer (read) of fw processing, a null packet is automatically transmitted for control transfer (without data). the fw request does not automatically transmit a null packet. remarks 1. df: default state, ad: addre ssed state, cf: configured state 2. n = 0 to 4 it is determined by the setting of the uf0 active in terface number register (uf0aifn) whether a request with interface number 1 to 4 is correctly responded to , depending on whether the interface number of the target is valid or not. 3. $$: valid endpoint number including transfer direction the valid endpoint is determined by the currently set alternate setting number (see 22.6.3 (36) uf0 active alternative setting register (uf0aas) , (38) uf0 endpoint 1 in terface mapping register (uf0e1im) to (42) uf0 endpoint 7 interf ace mapping register (uf0e7im) ). 4. ? and #: value transmitted from host (information on interface numbers 0 to 4) it is determined by the uf0 active interface number register (uf0aifn) and uf0 active alternative setting register (uf0aas) whether an alternate setting request corresponding to each interface number is correctly responded to or not, depending on whether t he interface number and alternate setting of the target are valid or not. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1188 of 1817 sep 19, 2011 (2) processing the processing of an automatic request in the default state, addressed state, and configured state is described below. remark default state: state in which an opera tion is performed with the default address addressed state: state afte r an address has been allocated configured state: state a fter set_configuration wvalue = 1 has been correctly received (a) clear_feature() request a stall response is made in t he status stage if the clear_feature() request cannot be cleared, if feature does not exist, or if the target is an interface or an endpoint that does not exist. a stall response is also made if the wlength value is other than 0. ? default state: the correct response is made when the clear_feature() request has been received only if the target is a device or a reques t for endpoint0; otherwise a stall response is made in the status stage. ? addressed state: the correct response is made when the clear_feature() request has been received only if the target is a device or a reques t for endpoint0; otherwise a stall response is made in the status stage. ? configured state: the correct response is ma de when the clear_feature() request has been received only if the target is a device or a request for an endpoint that exists; otherwise a stall response is made in the status stage. when the clear_feature() request has been correctly processed, the corresponding bit of the uf0 clr request register (uf0clr) is set to 1, the enhalt bit of the uf0 epn status register l (uf0ensl) is cleared to 0, and an interrupt is issued (n = 0 to 4, 7). if t he clear_feature() request is received when the subject is an endpoint, the toggle bit (that controls switching be tween data0 and data1) of the corresponding endpoint is always re-set to data0. (b) get_configuration() request a stall response is made in the data stage if any of wvalue, windex, or wlength is other than the values shown in table 22-3. ? default state: the value stored in the uf0 c onfiguration register (uf0cnf) is returned when the get_configuration() request has been received. ? addressed state: the value stor ed in the uf0cnf register is retu rned when the get_configuration() request has been received. ? configured state: the value stor ed in the uf0cnf register is retu rned when the get_configuration() request has been received. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1189 of 1817 sep 19, 2011 (c) get_descriptor() request if the subject descriptor has a length that is a multiple of wmaxpacketsize, a null packet is returned to indicate the end of the data stage. if the length of the descriptor at this time is less than the wlength value, the entire descriptor is returned; if the length of the descriptor is greater than the wlength value, the descriptor up to the wlength value is returned. ? default state: the value stored in uf0 de vice descriptor register n (uf0ddn) and uf0 configuration/interface/endpoint descriptor regi ster m (uf0ciem) is returned (n = 0 to 17, m = 0 to 255) when the get_descriptor() request has been received. ? addressed state: the value stor ed in the uf0ddn register and uf0c iem register is returned when the get_descriptor() request has been received. ? configured state: the value st ored in the uf0ddn register and uf0c iem register is returned when the get_descriptor() request has been received. a descriptor of up to 256 bytes can be stored in the uf0c iem register. to return a descriptor of more than 256 bytes, set the cdcgdst bit of the uf0modc register to 1 and process the get_descriptor() request by fw. store the value of the total number of bytes of the descriptor set by the uf0ciem register ? 1 in the uf0 descriptor length register (uf0dscl). the transfer data is controlled by the value of this data + 1 and wlength. (d) get_interface() request if either of wvalue and wlength is other than that shown in table 22-3, or if windex is other than that set by the uf0 active interface number register (uf0aifn), a stall response is made in the data stage. ? default state: a stall response is made in the data stage when the get_interface() request has been received. ? addressed state: a stall response is made in the data stage when the get_interface() request has been received. ? configured state: the value stor ed in the uf0 interface n register (u f0ifn) corresponding to the windex value is returned (n = 0 to 4) when the get_interface() request has been received. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1190 of 1817 sep 19, 2011 (e) get_status() request a stall response is made in the data stage if any of wvalue, windex, or wlength is other than the values shown in table 22-3. a stall response is also made in the data stage if the target is an interface or an endpoint that does not exist. ? default state: the value stor ed in the target status register note is returned only when the get_status() request has been received and when the request is for a device or endpoint0; otherwise a stall response is made in the data stage. ? addressed state: the value stor ed in the target status register note is returned only when the get_status() request has been received and when the request is for a device or endpoint0; otherwise a stall response is made in the data stage. ? configured state: the value st ored in the target status register note is returned only when the get_status() request has been received and when the request is for a device or an endpoint that exists; otherwise a stall response is made in the data stage. note the target status register is as follows. ? if the target is a device: uf0 de vice status register l (uf0dstl) ? if the target is endpoint 0: uf0 ep0 status register l (uf0e0sl) ? if the target is endpoint n: uf0 epn status register l (uf0ensl) (n = 1 to 4, 7) (f) set_address() request a stall response is made in the status stage if either of windex or wlengt h is other than the values shown in table 22-3. a stall response is also made if t he specified device address is greater than 127. ? default state: the device enters the addressed st ate and changes the usb address value to be input to sie into a specified address value if the s pecified address is other than 0 when the set_address() request has been received. if the specified address is 0, the device remains in the default state. ? addressed state: the device enter s the default state and returns the us b address value to be input to sie to the default address if the specified a ddress is 0 when the set_address() request has been received. if the specified address is other than 0, the device remains in the addressed state, and changes the usb address va lue to be input to sie into a specified new address value. ? configured state: the device remains in the conf igured state and returns the usb address value to be input to sie to the default address if the spec ified address is 0 when the set_address() request has been received. in this case, the endpoints other than endpoint 0 remain valid, and control transfer (in), control transfer (out), bulk transfer and interrupt transfer for an endpoint other than endpoint 0 are also acknowl edged. if the specif ied address is other than 0, the device remains in the configured state and changes the usb address value to be input to sie into a specified new address value. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1191 of 1817 sep 19, 2011 (g) set_configuration() request if any of wvalue, windex, or wlength is other than the values shown in table 22-3, a stall response is made in the status stage. ? default state: the conf bit of the uf0 mode status register (u f0mods) and the uf0 configuration register (uf0cnf) are set to 1 if the s pecified configuration value is 1 when the set_configuration() request has been received. if the specified configuration value is 0, the conf bit of the uf 0mods register and uf0cnf regist er are cleared to 0. in other words, the device skips the address ed state and moves to t he configured state in which it responds to the default address. ? addressed state: the conf bit of the uf0mods register and uf0cnf re gister are set to 1 and the device enters the configured state if the specified configur ation value is 1 when the set_configuration() request has been received. if the specified configuration value is 0, the device remains in the addressed state. ? configured state: the conf bit of the uf0mods register and uf0cnf re gister are set to 1 and the device returns to the addressed state if the s pecified configuration value is 0 when the set_configuration() request has been received. if the specified configuration value is 1, the device remains in the configured state. if the set_configuration() request has been correctly pr ocessed, the target bi t of the uf0 set request register (uf0set) is set to 1, and an interrupt is issued. all halt features are cleared after the set_configuration() request has been completed even if the specified configurati on value is the same as the current configuration value. if the set_co nfiguration() request has been co rrectly processed, the data toggle of all endpoints is always in itialized to data0 again (it is defined that the default st atus, alternative setting 0, is set from when the set_configuration request is received to when the set_interface request is received). (h) set_feature() request a stall response is made in the stat us stage if the set_feature() request is for a feature that cannot be set or does not exist, or if the target is an interface or an endpoint that does not exist. a stall response is also made if the wlength value is other than 0. ? default state: the correct response is made w hen the set_feature() request has been received, only if the request is for a device or endpoint0 ; otherwise a stall response is made in the status stage. ? addressed state: the correct response is made w hen the set_feature() request has been received, only if the request is for a device or endpoint0 ; otherwise a stall response is made in the status stage. ? configured state: the correct response is made when the set_feature() request has been received, only if the request is for a device or an endpoin t that exists; otherwise a stall response is made in the status stage. when the set_feature() request has bee n correctly processed, the tar get bit of the uf0 set request register (uf0set) and the enhalt bit of the uf0 epn status register l (uf0ensl) are set to 1, and an interrupt is issued (n = 0 to 4, 7). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1192 of 1817 sep 19, 2011 (i) set_interface() request if wlength is other than the values shown in table 22-3, if windex is other than the va lue set to the uf0 active interface number register (uf0aifn), or if wvalue is other than the value set to the uf0 active alternative setting register (uf0aas), a stall response is made in the status stage. ? default state: a stall response is made in the status stage when the set_interface() request has been received. ? addressed state: a stall response is made in t he status stage when the set_interface() request has been received. ? configured state: null packet is transmitted in the status stage when the set_interface() request has been received. when the set_interface() request has been correctly proc essed, an interrupt is issued. all the halt features of the endpoint linked to the target interface are cleared a fter the set_interface() request has been cleared. the data toggle of al l the endpoints related to the target interface number is always initialized again to data0. when the currently selected alternat ive setting is to be changed by correctly processing the set_interface() request, the fifo of t he endpoint that is affected is comple tely cleared, and all the related interrupt sources are also initialized. when the set_interface() request has been completed, t he fifo of all the endpoints linked to the target interface are cleared. at the same time, halt feature and data pid are initialized, and the related uf0 int status n register (uf0isn) is cleared to 0 (n = 0 to 4). (only halt feature and data pid are cleared when the set_configuration request has been completed.) if the target endpoint is not s upported by the set_interface() req uest during dma transfer, the dma request signal is immediately deasserted, and the fi fo of the endpoint that has been linked when the set_interface() request has been completed is completely cl eared. as a result of this clearing of the fifo, data transferred by dma is not correctly processed. 22.5.2 other requests (1) response and processing the following table shows how other req uests are responded to and processed. table 22-4. response and processing of other requests request response and processing get_descriptor string generation of cpudec interrupt request get_status interface automatic stall response clear_feature interface automatic stall response set_feature interface automatic stall response all set_descriptor generation of cpudec interrupt request all other requests generation of cpudec interrupt request v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1193 of 1817 sep 19, 2011 22.6 register configuration 22.6.1 usb control registers (1) usb clock select register (ucksel) the ucksel register selects the operat ion clock of the usb controller. the ucksel register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 ucksel 0 0 0 0 0 uusel1 0 after reset: 00h r/w address: ffffff40h uusel1 0 1 external clock input from exclk pin (f usb = 48 mhz) main clock (f xx = 48 mhz) selection of usb controller operation clock 7 6 543210 caution be sure to set bits 7 to 2, and 0 to ??0??. (2) usb function control register (ufckmsk) the ufckmsk register contro ls enable/disable of usb function controller operation. the ufckmsk register can be read or written in 8-bit or 1-bit units. reset sets this register to 03h. 0 ufckmsk other than above 0000 0 ufbufmsk ufmsk after reset: 03h r/w address: ffffff41h ufbufmsk 0 0 1 ufmsk 0 1 1 operation enabled operation stopped (set while usb is suspend) operation stopped setting prohibited usb function controller operation enable/disable 7 6 543210 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1194 of 1817 sep 19, 2011 22.6.2 usb function controller register list (1) epc control register (1/2) manipulatable bits address function register name symbol r/w 1 8 16 default value 00200000h uf0 ep0nak register uf0e0n r/w 00h 00200002h uf0 ep0nakall register uf0e0na r/w 00h 00200004h uf0 epnak register uf0en r/w 00h 00200006h uf0 epnak mask register uf0enm r/w 00h 00200008h uf0 sndsie register uf0sds r/w 00h 0020000ah uf0 clr request register uf0clr r 00h 0020000ch uf0 set request register uf0set r 00h 0020000eh uf0 ep status 0 register uf0eps0 r 00h 00200010h uf0 ep status 1 register uf0eps1 r 00h 00200012h uf0 ep status 2 register uf0eps2 r 00h 00200020h uf0 int status 0 register uf0is0 r 00h 00200022h uf0 int status 1 register uf0is1 r 00h 00200024h uf0 int status 2 register uf0is2 r 00h 00200026h uf0 int status 3 register uf0is3 r 00h 00200028h uf0 int status 4 register uf0is4 r 00h 0020002eh uf0 int mask 0 register uf0im0 r/w 00h 00200030h uf0 int mask 1 register uf0im1 r/w 00h 00200032h uf0 int mask 2 register uf0im2 r/w 00h 00200034h uf0 int mask 3 register uf0im3 r/w 00h 00200036h uf0 int mask 4 register uf0im4 r/w 00h 0020003ch uf0 int clear 0 register uf0ic0 w ffh 0020003eh uf0 int clear 1 register uf0ic1 w ffh 00200040h uf0 int clear 2 register uf0ic2 w ffh 00200042h uf0 int clear 3 register uf0ic3 w ffh 00200044h uf0 int clear 4 register uf0ic4 w ffh 0020004ch uf0 int & dmarq register uf0idr r/w 00h 0020004eh uf0 dma status 0 register uf0dms0 r 00h 00200050h uf0 dma status 1 register uf0dms1 r 00h 00200060h uf0 fifo clear 0 register uf0fic0 w 00h 00200062h uf0 fifo clear 1 register uf0fic1 w 00h 0020006ah uf0 data end register uf0dend r/w 00h 0020006eh uf0 gpr register uf0gpr w 00h 00200074h uf0 mode control register uf0modc r/w 00h 00200078h uf0 mode status register uf0mods r 00h v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1195 of 1817 sep 19, 2011 (2/2) manipulatable bits address function register name symbol r/w 1 8 16 default value 00200080h uf0 active interface number register uf0aifn r/w 00h 00200082h uf0 active alternative setting register uf0aas r/w 00h 00200084h uf0 alternative setting status register uf0ass r 00h 00200086h uf0 endpoint 1 interface mapping register uf0e1im r/w 00h 00200088h uf0 endpoint 2 interface mapping register uf0e2im r/w 00h 0020008ah uf0 endpoint 3 interface mapping register uf0e3im r/w 00h 0020008ch uf0 endpoint 4 interface mapping register uf0e4im r/w 00h 00200092h uf0 endpoint 7 interface mapping register uf0e7im r/w 00h (2) epc data hold register manipulatable bits address function register name symbol r/w 1 8 16 default value 00200100 h uf0 ep0 read register uf0e0r r undefined 00200102h uf0 ep0 length register uf0e0l r 00h 00200104h uf0 ep0 setup register uf0e0st r 00h 00200106h uf0 ep0 write register uf0e0w w undefined 00200108h uf0 bulk-out 1 register uf0bo1 r undefined 0020010ah uf0 bulk-out 1 length register uf0bo1l r 00h 0020010ch uf0 bulk-out 2 register uf0bo2 r undefined 0020010eh uf0 bulk-out 2 length register uf0bo2l r 00h 00200110h uf0 bulk-in 1 register uf0bi1 w undefined 00200112h uf0 bulk-in 2 register uf0bi2 w undefined 00200114h uf0 interrupt 1 register uf0int1 w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1196 of 1817 sep 19, 2011 (3) epc request data register (1/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 00200144h uf0 device status register l uf0dstl r/w 00h 0020014ch uf0 ep0 status register l uf0e0sl r/w 00h 00200150h uf0 ep1 status register l uf0e1sl r/w 00h 00200154h uf0 ep2 status register l uf0e2sl r/w 00h 00200158h uf0 ep3 status register l uf0e3sl r/w 00h 0020015ch uf0 ep4 status register l uf0e4sl r/w 00h 00200168h uf0 ep7 status register l uf0e7sl r/w 00h 00200180h uf0 address register uf0adrs r 00h 00200182h uf0 configuration register uf0cnf r 00h 00200184h uf0 interface 0 register uf0if0 r 00h 00200186h uf0 interface 1 register uf0if1 r 00h 00200188h uf0 interface 2 register uf0if2 r 00h 0020018ah uf0 interface 3 register uf0if3 r 00h 0020018ch uf0 interface 4 register uf0if4 r 00h 002001a0h uf0 descriptor length register uf0dscl r/w 00h 002001a2h uf0 device descriptor register 0 uf0dd0 r/w undefined 002001a4h uf0 device descriptor register 1 uf0dd1 r/w undefined 002001a6h uf0 device descriptor register 2 uf0dd2 r/w undefined 002001a8h uf0 device descriptor register 3 uf0dd3 r/w undefined 002001aah uf0 device descriptor register 4 uf0dd4 r/w undefined 002001ach uf0 device descriptor register 5 uf0dd5 r/w undefined 002001aeh uf0 device descriptor register 6 uf0dd6 r/w undefined 002001b0h uf0 device descriptor register 7 uf0dd7 r/w undefined 002001b2h uf0 device descriptor register 8 uf0dd8 r/w undefined 002001b4h uf0 device descriptor register 9 uf0dd9 r/w undefined 002001b6h uf0 device descriptor register 10 uf0dd10 r/w undefined 002001b8h uf0 device descriptor register 11 uf0dd11 r/w undefined 002001bah uf0 device descriptor register 12 uf0dd12 r/w undefined 002001bch uf0 device descriptor register 13 uf0dd13 r/w undefined 002001beh uf0 device descriptor register 14 uf0dd14 r/w undefined 002001c0h uf0 device descriptor register 15 uf0dd15 r/w undefined 002001c2h uf0 device descriptor register 16 uf0dd16 r/w undefined 002001c4h uf0 device descriptor register 17 uf0dd17 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1197 of 1817 sep 19, 2011 (2/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 002001c6h uf0 configuration/interface/endpoint descriptor register 0 uf0cie0 r/w undefined 002001c8h uf0 configuration/interface/endpoint descriptor register 1 uf0cie1 r/w undefined 002001cah uf0 configuration/interface/endpoint descriptor register 2 uf0cie2 r/w undefined 002001cch uf0 configuration/interface/endpoint descriptor register 3 uf0cie3 r/w undefined 002001ceh uf0 configuration/interface/endpoint descriptor register 4 uf0cie4 r/w undefined 002001d0h uf0 configuration/interface/endpoint descriptor register 5 uf0cie5 r/w undefined 002001d2h uf0 configuration/interface/endpoint descriptor register 6 uf0cie6 r/w undefined 002001d4h uf0 configuration/interface/endpoint descriptor register 7 uf0cie7 r/w undefined 002001d6h uf0 configuration/interface/endpoint descriptor register 8 uf0cie8 r/w undefined 002001d8h uf0 configuration/interface/endpoint descriptor register 9 uf0cie9 r/w undefined 002001dah uf0 configuration/interface/endpoint descriptor register 10 uf0cie10 r/w undefined 002001dch uf0 configuration/interface/endpoint descriptor register 11 uf0cie11 r/w undefined 002001deh uf0 configuration/interface/endpoint descriptor register 12 uf0cie12 r/w undefined 002001e0h uf0 configuration/interface/endpoint descriptor register 13 uf0cie13 r/w undefined 002001e2h uf0 configuration/interface/endpoint descriptor register 14 uf0cie14 r/w undefined 002001e4h uf0 configuration/interface/endpoint descriptor register 15 uf0cie15 r/w undefined 002001e6h uf0 configuration/interface/endpoint descriptor register 16 uf0cie16 r/w undefined 002001e8h uf0 configuration/interface/endpoint descriptor register 17 uf0cie17 r/w undefined 002001eah uf0 configuration/interface/endpoint descriptor register 18 uf0cie18 r/w undefined 002001ech uf0 configuration/interface/endpoint descriptor register 19 uf0cie19 r/w undefined 002001eeh uf0 configuration/interface/endpoint descriptor register 20 uf0cie20 r/w undefined 002001f0h uf0 configuration/interface/endpoint descriptor register 21 uf0cie21 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1198 of 1817 sep 19, 2011 (3/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 002001f2h uf0 configuration/interface/endpoint descriptor register 22 uf0cie22 r/w undefined 002001f4h uf0 configuration/interface/endpoint descriptor register 23 uf0cie23 r/w undefined 002001f6h uf0 configuration/interface/endpoint descriptor register 24 uf0cie24 r/w undefined 002001f8h uf0 configuration/interface/endpoint descriptor register 25 uf0cie25 r/w undefined 002001fah uf0 configuration/interface/endpoint descriptor register 26 uf0cie26 r/w undefined 002001fch uf0 configuration/interface/endpoint descriptor register 27 uf0cie27 r/w undefined 002001feh uf0 configuration/interface/endpoint descriptor register 28 uf0cie28 r/w undefined 00200200h uf0 configuration/interface/endpoint descriptor register 29 uf0cie29 r/w undefined 00200202h uf0 configuration/interface/endpoint descriptor register 30 uf0cie30 r/w undefined 00200204h uf0 configuration/interface/endpoint descriptor register 31 uf0cie31 r/w undefined 00200206h uf0 configuration/interface/endpoint descriptor register 32 uf0cie32 r/w undefined 00200208h uf0 configuration/interface/endpoint descriptor register 33 uf0cie33 r/w undefined 0020020ah uf0 configuration/interface/endpoint descriptor register 34 uf0cie34 r/w undefined 0020020ch uf0 configuration/interface/endpoint descriptor register 35 uf0cie35 r/w undefined 0020020eh uf0 configuration/interface/endpoint descriptor register 36 uf0cie36 r/w undefined 00200210h uf0 configuration/interface/endpoint descriptor register 37 uf0cie37 r/w undefined 00200212h uf0 configuration/interface/endpoint descriptor register 38 uf0cie38 r/w undefined 00200214h uf0 configuration/interface/endpoint descriptor register 39 uf0cie39 r/w undefined 00200216h uf0 configuration/interface/endpoint descriptor register 40 uf0cie40 r/w undefined 00200218h uf0 configuration/interface/endpoint descriptor register 41 uf0cie41 r/w undefined 0020021ah uf0 configuration/interface/endpoint descriptor register 42 uf0cie42 r/w undefined 0020021ch uf0 configuration/interface/endpoint descriptor register 43 uf0cie43 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1199 of 1817 sep 19, 2011 (4/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 0020021eh uf0 configuration/interface/endpoint descriptor register 44 uf0cie44 r/w undefined 00200220h uf0 configuration/interface/endpoint descriptor register 45 uf0cie45 r/w undefined 00200222h uf0 configuration/interface/endpoint descriptor register 46 uf0cie46 r/w undefined 00200224h uf0 configuration/interface/endpoint descriptor register 47 uf0cie47 r/w undefined 00200226h uf0 configuration/interface/endpoint descriptor register 48 uf0cie48 r/w undefined 00200228h uf0 configuration/interface/endpoint descriptor register 49 uf0cie49 r/w undefined 0020022ah uf0 configuration/interface/endpoint descriptor register 50 uf0cie50 r/w undefined 0020022ch uf0 configuration/interface/endpoint descriptor register 51 uf0cie51 r/w undefined 0020022eh uf0 configuration/interface/endpoint descriptor register 52 uf0cie52 r/w undefined 00200230h uf0 configuration/interface/endpoint descriptor register 53 uf0cie53 r/w undefined 00200232h uf0 configuration/interface/endpoint descriptor register 54 uf0cie54 r/w undefined 00200234h uf0 configuration/interface/endpoint descriptor register 55 uf0cie55 r/w undefined 00200236h uf0 configuration/interface/endpoint descriptor register 56 uf0cie56 r/w undefined 00200238h uf0 configuration/interface/endpoint descriptor register 57 uf0cie57 r/w undefined 0020023ah uf0 configuration/interface/endpoint descriptor register 58 uf0cie58 r/w undefined 0020023ch uf0 configuration/interface/endpoint descriptor register 59 uf0cie59 r/w undefined 0020023eh uf0 configuration/interface/endpoint descriptor register 60 uf0cie60 r/w undefined 00200240h uf0 configuration/interface/endpoint descriptor register 61 uf0cie61 r/w undefined 00200242h uf0 configuration/interface/endpoint descriptor register 62 uf0cie62 r/w undefined 00200244h uf0 configuration/interface/endpoint descriptor register 63 uf0cie63 r/w undefined 00200246h uf0 configuration/interface/endpoint descriptor register 64 uf0cie64 r/w undefined 00200248h uf0 configuration/interface/endpoint descriptor register 65 uf0cie65 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1200 of 1817 sep 19, 2011 (5/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 0020024ah uf0 configuration/interface/endpoint descriptor register 66 uf0cie66 r/w undefined 0020024ch uf0 configuration/interface/endpoint descriptor register 67 uf0cie67 r/w undefined 0020024eh uf0 configuration/interface/endpoint descriptor register 68 uf0cie68 r/w undefined 00200250h uf0 configuration/interface/endpoint descriptor register 69 uf0cie69 r/w undefined 00200252h uf0 configuration/interface/endpoint descriptor register 70 uf0cie70 r/w undefined 00200254h uf0 configuration/interface/endpoint descriptor register 71 uf0cie71 r/w undefined 00200256h uf0 configuration/interface/endpoint descriptor register 72 uf0cie72 r/w undefined 00200258h uf0 configuration/interface/endpoint descriptor register 73 uf0cie73 r/w undefined 0020025ah uf0 configuration/interface/endpoint descriptor register 74 uf0cie74 r/w undefined 0020025ch uf0 configuration/interface/endpoint descriptor register 75 uf0cie75 r/w undefined 0020025eh uf0 configuration/interface/endpoint descriptor register 76 uf0cie76 r/w undefined 00200260h uf0 configuration/interface/endpoint descriptor register 77 uf0cie77 r/w undefined 00200262h uf0 configuration/interface/endpoint descriptor register 78 uf0cie78 r/w undefined 00200264h uf0 configuration/interface/endpoint descriptor register 79 uf0cie79 r/w undefined 00200266h uf0 configuration/interface/endpoint descriptor register 80 uf0cie80 r/w undefined 00200268h uf0 configuration/interface/endpoint descriptor register 81 uf0cie81 r/w undefined 0020026ah uf0 configuration/interface/endpoint descriptor register 82 uf0cie82 r/w undefined 0020026ch uf0 configuration/interface/endpoint descriptor register 83 uf0cie83 r/w undefined 0020026eh uf0 configuration/interface/endpoint descriptor register 84 uf0cie84 r/w undefined 00200270h uf0 configuration/interface/endpoint descriptor register 85 uf0cie85 r/w undefined 00200272h uf0 configuration/interface/endpoint descriptor register 86 uf0cie86 r/w undefined 00200274h uf0 configuration/interface/endpoint descriptor register 87 uf0cie87 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1201 of 1817 sep 19, 2011 (6/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 00200276h uf0 configuration/interface/endpoint descriptor register 88 uf0cie88 r/w undefined 00200278h uf0 configuration/interface/endpoint descriptor register 89 uf0cie89 r/w undefined 0020027ah uf0 configuration/interface/endpoint descriptor register 90 uf0cie90 r/w undefined 0020027ch uf0 configuration/interface/endpoint descriptor register 91 uf0cie91 r/w undefined 0020027eh uf0 configuration/interface/endpoint descriptor register 92 uf0cie92 r/w undefined 00200280h uf0 configuration/interface/endpoint descriptor register 93 uf0cie93 r/w undefined 00200282h uf0 configuration/interface/endpoint descriptor register 94 uf0cie94 r/w undefined 00200284h uf0 configuration/interface/endpoint descriptor register 95 uf0cie95 r/w undefined 00200286h uf0 configuration/interface/endpoint descriptor register 96 uf0cie96 r/w undefined 00200288h uf0 configuration/interface/endpoint descriptor register 97 uf0cie97 r/w undefined 0020028ah uf0 configuration/interface/endpoint descriptor register 98 uf0cie98 r/w undefined 0020028ch uf0 configuration/interface/endpoint descriptor register 99 uf0cie99 r/w undefined 0020028eh uf0 configuration/interface/endpoint descriptor register 100 uf0cie100 r/w undefined 00200290h uf0 configuration/interface/endpoint descriptor register 101 uf0cie101 r/w undefined 00200292h uf0 configuration/interface/endpoint descriptor register 102 uf0cie102 r/w undefined 00200294h uf0 configuration/interface/endpoint descriptor register 103 uf0cie103 r/w undefined 00200296h uf0 configuration/interface/endpoint descriptor register 104 uf0cie104 r/w undefined 00200298h uf0 configuration/interface/endpoint descriptor register 105 uf0cie105 r/w undefined 0020029ah uf0 configuration/interface/endpoint descriptor register 106 uf0cie106 r/w undefined 0020029ch uf0 configuration/interface/endpoint descriptor register 107 uf0cie107 r/w undefined 0020029eh uf0 configuration/interface/endpoint descriptor register 108 uf0cie108 r/w undefined 002002a0h uf0 configuration/interface/endpoint descriptor register 109 uf0cie109 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1202 of 1817 sep 19, 2011 (7/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 002002a2h uf0 configuration/interface/endpoint descriptor register 110 uf0cie110 r/w undefined 002002a4h uf0 configuration/interface/endpoint descriptor register 111 uf0cie111 r/w undefined 002002a6h uf0 configuration/interface/endpoint descriptor register 112 uf0cie112 r/w undefined 002002a8h uf0 configuration/interface/endpoint descriptor register 113 uf0cie113 r/w undefined 002002aah uf0 configuration/interface/endpoint descriptor register 114 uf0cie114 r/w undefined 002002ach uf0 configuration/interface/endpoint descriptor register 115 uf0cie115 r/w undefined 002002aeh uf0 configuration/interface/endpoint descriptor register 116 uf0cie116 r/w undefined 002002b0h uf0 configuration/interface/endpoint descriptor register 117 uf0cie117 r/w undefined 002002b2h uf0 configuration/interface/endpoint descriptor register 118 uf0cie118 r/w undefined 002002b4h uf0 configuration/interface/endpoint descriptor register 119 uf0cie119 r/w undefined 002002b6h uf0 configuration/interface/endpoint descriptor register 120 uf0cie120 r/w undefined 002002b8h uf0 configuration/interface/endpoint descriptor register 121 uf0cie121 r/w undefined 002002bah uf0 configuration/interface/endpoint descriptor register 122 uf0cie122 r/w undefined 002002bch uf0 configuration/interface/endpoint descriptor register 123 uf0cie123 r/w undefined 002002beh uf0 configuration/interface/endpoint descriptor register 124 uf0cie124 r/w undefined 002002c0h uf0 configuration/interface/endpoint descriptor register 125 uf0cie125 r/w undefined 002002c2h uf0 configuration/interface/endpoint descriptor register 126 uf0cie126 r/w undefined 002002c4h uf0 configuration/interface/endpoint descriptor register 127 uf0cie127 r/w undefined 002002c6h uf0 configuration/interface/endpoint descriptor register 128 uf0cie128 r/w undefined 002002c8h uf0 configuration/interface/endpoint descriptor register 129 uf0cie129 r/w undefined 002002cah uf0 configuration/interface/endpoint descriptor register 130 uf0cie130 r/w undefined 002002cch uf0 configuration/interface/endpoint descriptor register 131 uf0cie131 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1203 of 1817 sep 19, 2011 (8/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 002002ceh uf0 configuration/interface/endpoint descriptor register 132 uf0cie132 r/w undefined 002002d0h uf0 configuration/interface/endpoint descriptor register 133 uf0cie133 r/w undefined 002002d2h uf0 configuration/interface/endpoint descriptor register 134 uf0cie134 r/w undefined 002002d4h uf0 configuration/interface/endpoint descriptor register 135 uf0cie135 r/w undefined 002002d6h uf0 configuration/interface/endpoint descriptor register 136 uf0cie136 r/w undefined 002002d8h uf0 configuration/interface/endpoint descriptor register 137 uf0cie137 r/w undefined 002002dah uf0 configuration/interface/endpoint descriptor register 138 uf0cie138 r/w undefined 002002dch uf0 configuration/interface/endpoint descriptor register 139 uf0cie139 r/w undefined 002002deh uf0 configuration/interface/endpoint descriptor register 140 uf0cie140 r/w undefined 002002e0h uf0 configuration/interface/endpoint descriptor register 141 uf0cie141 r/w undefined 002002e2h uf0 configuration/interface/endpoint descriptor register 142 uf0cie142 r/w undefined 002002e4h uf0 configuration/interface/endpoint descriptor register 143 uf0cie143 r/w undefined 002002e6h uf0 configuration/interface/endpoint descriptor register 144 uf0cie144 r/w undefined 002002e8h uf0 configuration/interface/endpoint descriptor register 145 uf0cie145 r/w undefined 002002eah uf0 configuration/interface/endpoint descriptor register 146 uf0cie146 r/w undefined 002002ech uf0 configuration/interface/endpoint descriptor register 147 uf0cie147 r/w undefined 002002eeh uf0 configuration/interface/endpoint descriptor register 148 uf0cie148 r/w undefined 002002f0h uf0 configuration/interface/endpoint descriptor register 149 uf0cie149 r/w undefined 002002f2h uf0 configuration/interface/endpoint descriptor register 150 uf0cie150 r/w undefined 002002f4h uf0 configuration/interface/endpoint descriptor register 151 uf0cie151 r/w undefined 002002f6h uf0 configuration/interface/endpoint descriptor register 152 uf0cie152 r/w undefined 002002f8h uf0 configuration/interface/endpoint descriptor register 153 uf0cie153 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1204 of 1817 sep 19, 2011 (9/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 002002fah uf0 configuration/interface/endpoint descriptor register 154 uf0cie154 r/w undefined 002002fch uf0 configuration/interface/endpoint descriptor register 155 uf0cie155 r/w undefined 002002feh uf0 configuration/interface/endpoint descriptor register 156 uf0cie156 r/w undefined 00200300h uf0 configuration/interface/endpoint descriptor register 157 uf0cie157 r/w undefined 00200302h uf0 configuration/interface/endpoint descriptor register 158 uf0cie158 r/w undefined 00200304h uf0 configuration/interface/endpoint descriptor register 159 uf0cie159 r/w undefined 00200306h uf0 configuration/interface/endpoint descriptor register 160 uf0cie160 r/w undefined 00200308h uf0 configuration/interface/endpoint descriptor register 161 uf0cie161 r/w undefined 0020030ah uf0 configuration/interface/endpoint descriptor register 162 uf0cie162 r/w undefined 0020030ch uf0 configuration/interface/endpoint descriptor register 163 uf0cie163 r/w undefined 0020030eh uf0 configuration/interface/endpoint descriptor register 164 uf0cie164 r/w undefined 00200310h uf0 configuration/interface/endpoint descriptor register 165 uf0cie165 r/w undefined 00200312h uf0 configuration/interface/endpoint descriptor register 166 uf0cie166 r/w undefined 00200314h uf0 configuration/interface/endpoint descriptor register 167 uf0cie167 r/w undefined 00200316h uf0 configuration/interface/endpoint descriptor register 168 uf0cie168 r/w undefined 00200318h uf0 configuration/interface/endpoint descriptor register 169 uf0cie169 r/w undefined 0020031ah uf0 configuration/interface/endpoint descriptor register 170 uf0cie170 r/w undefined 0020031ch uf0 configuration/interface/endpoint descriptor register 171 uf0cie171 r/w undefined 0020031eh uf0 configuration/interface/endpoint descriptor register 172 uf0cie172 r/w undefined 00200320h uf0 configuration/interface/endpoint descriptor register 173 uf0cie173 r/w undefined 00200322h uf0 configuration/interface/endpoint descriptor register 174 uf0cie174 r/w undefined 00200324h uf0 configuration/interface/endpoint descriptor register 175 uf0cie175 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1205 of 1817 sep 19, 2011 (10/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 00200326h uf0 configuration/interface/endpoint descriptor register 176 uf0cie176 r/w undefined 00200328h uf0 configuration/interface/endpoint descriptor register 177 uf0cie177 r/w undefined 0020032ah uf0 configuration/interface/endpoint descriptor register 178 uf0cie178 r/w undefined 0020032ch uf0 configuration/interface/endpoint descriptor register 179 uf0cie179 r/w undefined 0020032eh uf0 configuration/interface/endpoint descriptor register 180 uf0cie180 r/w undefined 00200330h uf0 configuration/interface/endpoint descriptor register 181 uf0cie181 r/w undefined 00200332h uf0 configuration/interface/endpoint descriptor register 182 uf0cie182 r/w undefined 00200334h uf0 configuration/interface/endpoint descriptor register 183 uf0cie183 r/w undefined 00200336h uf0 configuration/interface/endpoint descriptor register 184 uf0cie184 r/w undefined 00200338h uf0 configuration/interface/endpoint descriptor register 185 uf0cie185 r/w undefined 0020033ah uf0 configuration/interface/endpoint descriptor register 186 uf0cie186 r/w undefined 0020033ch uf0 configuration/interface/endpoint descriptor register 187 uf0cie187 r/w undefined 0020033eh uf0 configuration/interface/endpoint descriptor register 188 uf0cie188 r/w undefined 00200340h uf0 configuration/interface/endpoint descriptor register 189 uf0cie189 r/w undefined 00200342h uf0 configuration/interface/endpoint descriptor register 190 uf0cie190 r/w undefined 00200344h uf0 configuration/interface/endpoint descriptor register 191 uf0cie191 r/w undefined 00200346h uf0 configuration/interface/endpoint descriptor register 192 uf0cie192 r/w undefined 00200348h uf0 configuration/interface/endpoint descriptor register 193 uf0cie193 r/w undefined 0020034ah uf0 configuration/interface/endpoint descriptor register 194 uf0cie194 r/w undefined 0020034ch uf0 configuration/interface/endpoint descriptor register 195 uf0cie195 r/w undefined 0020034eh uf0 configuration/interface/endpoint descriptor register 196 uf0cie196 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1206 of 1817 sep 19, 2011 (11/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 00200350h uf0 configuration/interface/endpoint descriptor register 197 uf0cie197 r/w undefined 00200352h uf0 configuration/interface/endpoint descriptor register 198 uf0cie198 r/w undefined 00200354h uf0 configuration/interface/endpoint descriptor register 199 uf0cie199 r/w undefined 00200356h uf0 configuration/interface/endpoint descriptor register 200 uf0cie200 r/w undefined 00200358h uf0 configuration/interface/endpoint descriptor register 201 uf0cie201 r/w undefined 0020035ah uf0 configuration/interface/endpoint descriptor register 202 uf0cie202 r/w undefined 0020035ch uf0 configuration/interface/endpoint descriptor register 203 uf0cie203 r/w undefined 0020035eh uf0 configuration/interface/endpoint descriptor register 204 uf0cie204 r/w undefined 00200360h uf0 configuration/interface/endpoint descriptor register 205 uf0cie205 r/w undefined 00200362h uf0 configuration/interface/endpoint descriptor register 206 uf0cie206 r/w undefined 00200364h uf0 configuration/interface/endpoint descriptor register 207 uf0cie207 r/w undefined 00200366h uf0 configuration/interface/endpoint descriptor register 208 uf0cie208 r/w undefined 00200368h uf0 configuration/interface/endpoint descriptor register 209 uf0cie209 r/w undefined 0020036ah uf0 configuration/interface/endpoint descriptor register 210 uf0cie210 r/w undefined 0020036ch uf0 configuration/interface/endpoint descriptor register 211 uf0cie211 r/w undefined 0020036eh uf0 configuration/interface/endpoint descriptor register 212 uf0cie212 r/w undefined 00200370h uf0 configuration/interface/endpoint descriptor register 213 uf0cie213 r/w undefined 00200372h uf0 configuration/interface/endpoint descriptor register 214 uf0cie214 r/w undefined 00200374h uf0 configuration/interface/endpoint descriptor register 215 uf0cie215 r/w undefined 00200376h uf0 configuration/interface/endpoint descriptor register 216 uf0cie216 r/w undefined 00200378h uf0 configuration/interface/endpoint descriptor register 217 uf0cie217 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1207 of 1817 sep 19, 2011 (12/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 0020037ah uf0 configuration/interface/endpoint descriptor register 218 uf0cie218 r/w undefined 0020037ch uf0 configuration/interface/endpoint descriptor register 219 uf0cie219 r/w undefined 0020037eh uf0 configuration/interface/endpoint descriptor register 220 uf0cie220 r/w undefined 00200380h uf0 configuration/interface/endpoint descriptor register 221 uf0cie221 r/w undefined 00200382h uf0 configuration/interface/endpoint descriptor register 222 uf0cie222 r/w undefined 00200384h uf0 configuration/interface/endpoint descriptor register 223 uf0cie223 r/w undefined 00200386h uf0 configuration/interface/endpoint descriptor register 224 uf0cie224 r/w undefined 00200388h uf0 configuration/interface/endpoint descriptor register 225 uf0cie225 r/w undefined 0020038ah uf0 configuration/interface/endpoint descriptor register 226 uf0cie226 r/w undefined 0020038ch uf0 configuration/interface/endpoint descriptor register 227 uf0cie227 r/w undefined 0020038eh uf0 configuration/interface/endpoint descriptor register 228 uf0cie228 r/w undefined 00200390h uf0 configuration/interface/endpoint descriptor register 229 uf0cie229 r/w undefined 00200392h uf0 configuration/interface/endpoint descriptor register 230 uf0cie230 r/w undefined 00200394h uf0 configuration/interface/endpoint descriptor register 231 uf0cie231 r/w undefined 00200396h uf0 configuration/interface/endpoint descriptor register 232 uf0cie232 r/w undefined 00200398h uf0 configuration/interface/endpoint descriptor register 233 uf0cie233 r/w undefined 0020039ah uf0 configuration/interface/endpoint descriptor register 234 uf0cie234 r/w undefined 0020039ch uf0 configuration/interface/endpoint descriptor register 235 uf0cie235 r/w undefined 0020039eh uf0 configuration/interface/endpoint descriptor register 236 uf0cie236 r/w undefined 002003a0h uf0 configuration/interface/endpoint descriptor register 237 uf0cie237 r/w undefined 002003a2h uf0 configuration/interface/endpoint descriptor register 238 uf0cie238 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1208 of 1817 sep 19, 2011 (13/13) manipulatable bits address function register name symbol r/w 1 8 16 default value 002003a4h uf0 configuration/interface/endpoint descriptor register 239 uf0cie239 r/w undefined 002003a6h uf0 configuration/interface/endpoint descriptor register 240 uf0cie240 r/w undefined 002003a8h uf0 configuration/interface/endpoint descriptor register 241 uf0cie241 r/w undefined 002003aah uf0 configuration/interface/endpoint descriptor register 242 uf0cie242 r/w undefined 002003ach uf0 configuration/interface/endpoint descriptor register 243 uf0cie243 r/w undefined 002003aeh uf0 configuration/interface/endpoint descriptor register 244 uf0cie244 r/w undefined 002003b0h uf0 configuration/interface/endpoint descriptor register 245 uf0cie245 r/w undefined 002003b2h uf0 configuration/interface/endpoint descriptor register 246 uf0cie246 r/w undefined 002003b4h uf0 configuration/interface/endpoint descriptor register 247 uf0cie247 r/w undefined 002003b6h uf0 configuration/interface/endpoint descriptor register 248 uf0cie248 r/w undefined 002003b8h uf0 configuration/interface/endpoint descriptor register 249 uf0cie249 r/w undefined 002003bah uf0 configuration/interface/endpoint descriptor register 250 uf0cie250 r/w undefined 002003bch uf0 configuration/interface/endpoint descriptor register 251 uf0cie251 r/w undefined 002003beh uf0 configuration/interface/endpoint descriptor register 252 uf0cie252 r/w undefined 002003c0h uf0 configuration/interface/endpoint descriptor register 253 uf0cie253 r/w undefined 002003c2h uf0 configuration/interface/endpoint descriptor register 254 uf0cie254 r/w undefined 002003c4h uf0 configuration/interface/endpoint descriptor register 255 uf0cie255 r/w undefined v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1209 of 1817 sep 19, 2011 (4) bridge register manipulatable bits address function register name symbol r/w 1 8 16 default value 00200400h bridge interrupt control register brgintt r/w 0000h 00200402h bridge interrupt enable register brginte r/w 0000h 00200404h epc macro control register epcclt r/w 0000h 00200408h cpu i/f bus control register cpubctl r/w 0000h (5) dma register manipulatable bits address function register name symbol r/w 1 8 16 default value 00200500h ep1 dma control register 1 uf0e1dc1 r/w 0000h 00200502h ep1 dma control register 2 uf0e1dc2 r/w 0000h 00200504h ep2 dma control register 1 uf0e2dc1 r/w 0000h 00200506h ep2 dma control register 2 uf0e2dc2 r/w 0000h 00200508h ep3 dma control register 1 uf0e3dc1 r/w 0000h 0020050ah ep3 dma control register 2 uf0e3dc2 r/w 0000h 0020050ch ep4 dma control register 1 uf0e4dc1 r/w 0000h 0020050eh ep4 dma control register 2 uf0e4dc2 r/w 0000h (6) bulk-in register manipulatable bits address function register name symbol r/w 1 8 16 default value 00201000h uf0 ep1 bulk-in transfer data register uf0ep1bi w 0000h 00202000h uf0 ep3 bulk-in transfer data register uf0ep3bi w 0000h (7) bulk-out register manipulatable bits address function register name symbol r/w 1 8 16 default value 00210000h uf0 ep2 bulk-out transfer data register uf0ep2bo r 0000h 00220000h uf0 ep4 bulk-out transfer data register uf0ep4bo r 0000h (8) peripheral control register manipulatable bits address function register name symbol r/w 1 8 16 default value 00240000h usbf dma request enable register ufdrqen r/w 0000h v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1210 of 1817 sep 19, 2011 22.6.3 epc control registers (1) uf0 ep0nak register (uf0e0n) this register controls nak of endpoint0 (except an automatically executed request). this register can be read or written in 8-bit units (however, bit 0 can only be read). it takes five usb clocks to reflect the status on this re gister after the uf0fic0 and uf0fic1 registers have been set. if it is necessary to read the status correctly, t herefore, separate a write signa l that accesses the uf0fic0 and uf0fic1 registers from a read signal that acce sses the uf0eps0, uf0eps1, uf0eps2, uf0e0n, and uf0en registers by at least four usb clocks. while nak is being transmitted to endpoint0 read, endpoi nt2, and endpoint4, a write access to the ep0nkr bit is ignored. 0 uf0e0n 0 5 00 3 0 2 0 1 ep0nkr ep0nkw address 00200000h after reset 00h 0 4 6 7 bit position bit name function 1 ep0nkr this bit controls nak to the out token to endpoint0 (except an automatically executed request). it is automatically set to 1 by hardware when endpoint0 has correctly received data. it is also cleared to 0 by hardware when the data of the uf0e0r register has been read by fw (counter value = 0). 1: transmit nak. 0: do not transmit nak (default value). set this bit to 1 by fw when data should not be received from the usb bus for some reason even when usbf is ready for receiv ing data. in this case, usbf continues transmitting nak until this bit is cleared to 0 by fw. this bit is also cleared to 0 as soon as the uf0e0r register has been cleared. 0 ep0nkw this bit indicates how nak to the in token to endpoint0 is controlled (except an automatically executed request). this bit is automatically cleared to 0 by hardware when the data of endpoint0 is transmitted and the host correctly receives the transmitted data. the data of the uf0e0w register is retained until this bit is cleared. therefore, it is not necessary to rewrite this bit even in the case of a retransmission re quest that is made if the host could not receive data correctly. to send a short packet, be sure to set the e0ded bit of the uf0dend register to 1. this bit is automatically set to 1 when the fifo is full. as soon as the e0ded bit of the uf0d end register is set to 1, the ep0nkw bit is automatically set to 1 at the same time. 1: do not transmit nak. 0: transmit nak (default value). if control transfer enters the status stage while ack cannot be correctly received in the data stage, this bit is cleared to 0 as soon as t he uf0e0w register is cleared. this bit is also cleared to 0 when uf0e0w is cleared by fw. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1211 of 1817 sep 19, 2011 next, the procedure of a setup transaction t hat uses in/out tokens is explained below. (a) when in token is used (except a re quest automatically executed by hardware) fw should be used to clear the prot bit of the uf0is1 register to 0 after receiving the cpudec interrupt and before reading data from the uf0e0st register. next, perform proce ssing in accordance with the request and, if it is necessary to return data by an in token, write dat a to the uf0e0w register. c onfirm that the prot bit of the uf0is1 register is 0 after writing has been completed, and set the e0ded bit of the uf0dend register to 1. the hardware sends out data at the first in token after the ep0nkw bit has been set to 1. if the prot bit of the uf0is1 register is 1, it indica tes that a setup transaction has occurred again before completion of control transfer. in this case, clear the prot bit of the uf0is1 register to 0 by clearing the protc bit of the uf0ic1 register to 0, and then read data from the uf0e0st register again. a request received later can be read. (b) when out token is used (except a re quest automatically executed by hardware) fw should be used to clear the prot bit of the uf0i s1 register after receiving the cpudec interrupt and before reading data from the uf0e0st register. confirm t hat the prot bit of the uf 0is1 register is 0 before reading data from the uf0e0r register. if the prot bit is 1, it means that invalid da ta is retained. clear the fifo by fw (the ep0nkr bit is automatically cleared to 0) . if the prot bit of the uf0is1 register is 0, read the data of the uf0e0l regi ster and read as many data from the uf0e 0r register as set. when reading data from the uf0e0r register has been co mpleted (when the counter of the uf0e0r register has been cleared to 0), the hardware automatically clears the ep0nkr bit to 0. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1212 of 1817 sep 19, 2011 (2) uf0 ep0nakall register (uf0e0na) this register controls nak to all the requests of endpoint 0. it is also valid for automatically executed requests. this register can be read or written in 8-bit units. 0 uf0e0na 0 5 00 3 0 2 0 1 0 ep0nka address 00200002h after reset 00h 0 4 6 7 bit position bit name function 0 ep0nka this bit controls nak to a transaction other than a setup transaction to endpoint0 (including an automatically executed request ). this bit is manipulated by fw. 1: transmit nak. 0: do not transmit nak (default value). this register is used to prevent a conflict between a write access by fw and a read access from sie when the data used for an automatically executed request is to be changed. it postpones reflecting a write access on this bit from fw while an access from sie is being made. before rewriting the reques t data register from fw, confirm that this bit has been correctly set to 1. setting this bit to 1 is reflected only in the following cases. ? immediately after usbf has been reset and a setup token has never been received ? immediately after reception of bus reset and a setup token has never been received ? pid of a setup token has been detected ? the stage has been changed to the status stage clearing this bit to 0 is reflected immediatel y, except while an in token is being received and a nak response is being made. setting the ep0nka bit to 1 is reflected in the above four cases during endpoint0 transfer, but it is reflected immediately after data has been written to the bit while endpoint0 is transferring no data. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1213 of 1817 sep 19, 2011 (3) uf0 epnak register (uf0en) this register controls nak of endpoints other than endpoint0. this register can be read or written in 8-bit units (however, bits 5, 4, 1, and 0 can only be read). the bko2nk bit can be written only when the bko2nkm bit of the uf0enm register is 1 and the bko1nk bit can be written only when the bko1nkm bit of the uf0enm register is 1. the related bits are invalid if each endpo int is not supported by the setting of t he uf0enim register (n = 1 to 4, 7) and the current setting of the interface. it takes five usb clocks to reflect the status on this re gister after the uf0fic0 and uf0fic1 registers have been set. if it is necessary to read the status correctly, t herefore, separate a write signa l that accesses the uf0fic0 and uf0fic1 registers from a read signal that acce sses the uf0eps0, uf0eps1, uf0eps2, uf0e0n, and uf0en registers by at least four usb clocks. while nak is being transmitted to endpoint0 read, endpoi nt2, and endpoint4, a write access to the bko1nk and bko2nk bits is ignored. be sure to clear bits 7 to 5 to ?0?. if it is set to 1, the operation is not guaranteed. (1/4) 0 uf0en 0 0 it1nk 3 bko2nk 2 bko1nk 1 bki2nk bki1nk address 00200004h after reset 00h 0 4 6 7 bit position bit name function 4 it1nk this bit controls nak to endpoint7 (interrupt 1 transfer). it is automatically set to 1 and transmission is started when the uf0int1 register has become full as a result of writing data to it. to send a short packet that does not make the fifo full, set the it1dend bit of the uf0de nd register to 1. as soon as the it1dend bit has been set to 1, this bit is automatically set to 1. 1: do not transmit nak. 0: transmit nak (default value). this bit is also cleared to 0 when the uf0int1 register has been cleared. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1214 of 1817 sep 19, 2011 (2/4) bit position bit name function 3 bko2nk this bit controls nak to endpoint4 (bulk 2 transfer (out)). 1: transmit nak. 0: do not transmit nak (default value). this bit is set to 1 only when the fifo connected to the sie side of the uf0bo2 register (64-byte fifo of bank configuration) cannot receive data. it is cleared to 0 when a toggle operation is performed. the bank is changed (toggle operation) when the following conditions are satisfied. ? data correctly received is stored in the fifo connected to the sie side. ? the value of the fifo counter connect ed to the cpu side is 0 (completion of reading). fw should be used to read data of the uf0bo2l register when it has received the blko2dt interrupt request and read as many data from the uf0bo2 register as the value of that data. to not receive data from the usb bus for some reason even if usbf is ready to receive data, set this bit to 1 by fw. in this case, usbf keeps transmitting nak until the fw clears this bit to 0. this bit is also cleared to 0 as soon as the uf0bo2 register has been cleared. 2 bko1nk this bit controls nak to endpoint2 (bulk 1 transfer (out)). 1: transmit nak. 0: do not transmit nak (default value). this bit is set to 1 only when the fifo connected to the sie side of the uf0bo1 register (64-byte fifo of bank configuration) cannot receive data. it is cleared to 0 when a toggle operation is performed. the bank is changed (toggle operation) when the following conditions are satisfied. ? data correctly received is stored in the fifo connected to the sie side. ? the value of the fifo counter connect ed to the cpu side is 0 (completion of reading). fw should be used to read data of the uf0bo1l register when it has received the blko1dt interrupt request and read as many data from the uf0bo1 register as the value of that data. to not receive data from the usb bus for some reason even if usbf is ready to receive data, set this bit to 1 by fw. in this case, usbf keeps transmitting nak until the fw clears this bit to 0. this bit is also cleared to 0 as soon as the uf0bo1 register has been cleared. cautions 1. if dma is enabled while data is being read from the uf0bo2 register in the pio mode, a dma request is immediately issued. 2. if the last data of the fifo on the cpu side is read in the dma transfer mode, the dma request signal becomes inactive. 3. if the tc signal is received in the dm a transfer mode, the dma request signal becomes inactive. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1215 of 1817 sep 19, 2011 (3/4) bit position bit name function 1 bki2nk this bit controls nak to endpoi nt3 (bulk 2 transfer (in)). 1: do not transmit nak. 0: transmit nak (default value). this bit is cleared to 0 only when the fifo connected to the sie side of the uf0bi2 register (64-byte fifo of bank configuration) cannot receive data. it is set to 1 when a toggle operation is performed (the data of the uf0bi2 register is retained until transmission has been correctly completed) . the bank is changed (toggle operation) when the following conditions are satisfied. ? data is correctly written to the fifo connected to the cpu bus side (writing has been completed and the fifo is full or the uf0dend register is set). ? the value of the fifo counter connected to the sie side is 0. this bit is automatically set to 1 and data transmission is started when the fifo on the cpu side becomes full and a fifo toggle operation is performed as a result of writing data to the fifo. however, if the fifo on the cpu side becomes full as a result of writing data to it by dma while the bki2t bit of the uf0dend register is cleared to 0, the toggle operation is not performed because the conditi on of the toggle operation is not satisfied until the bki2ded bit of the uf0dend register is set to 1. to send a short packet that does not make the fifo on the cpu side full, set the bki2ded bit to 1 after completing writing data. when the bki2ded bit is set to 1, a toggle operation is performed and at the same time, this bit is automatically set to 1. this bit is also cleared to 0 as soon as the uf0bi2 register has been cleared. cautions 1. if dma is enabled wh ile data is being written to the uf0b i2 register in the pio mode, a dma request is immediately issued. 2. if 64-byte data is written in the dm a transfer mode, the dma request signal becomes inactive. if the bki2nk bit is then set to 1, da ta is transmitted in synchronization with an in token. the dma request signal becomes acti ve again as long as the dma request is not masked as soon as the fifo is toggled. if the bki2nk bit is not set, data is not transmitted even if an in token has been received. in this case, set th e bki2ded bit of the uf0dend register to 1. 3. if the tc signal is received in the dm a transfer mode, the dma request signal becomes inactive. at the same time, the dma request is masked. if th e bki2nk bit is not set to 1, data is not transmitted even if an in token is received. when th e bki2ded bit of the uf0dend register is set to 1 by fw, data is transmitted in synchronization with the in token. to execute dma transfer again, unmask the dma request. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1216 of 1817 sep 19, 2011 (4/4) bit position bit name function 0 bki1nk this bit controls nak to endpoi nt1 (bulk 1 transfer (in)). 1: do not transmit nak. 0: transmit nak (default value). this bit is cleared to 0 only when the fifo connected to the sie side of the uf0bi1 register (64-byte fifo of bank configuration) cannot receive data. it is set to 1 when a toggle operation is performed (the data of the uf0bi1 register is retained until transmission has been correctly completed) . the bank is changed (toggle operation) when the following conditions are satisfied. ? data is correctly written to the fifo connected to the cpu bus side (writing has been completed and the fifo is full or the uf0dend register is set). ? the value of the fifo counter connected to the sie side is 0. this bit is automatically set to 1 and data transmission is started when the fifo on the cpu side becomes full and a fifo toggle operation is performed as a result of writing data to the fifo. however, if the fifo on the cpu side becomes full as a result of writing data to it by dma while the bki1t bit of the uf0dend register is cleared to 0, the toggle operation is not performed because the conditi on of the toggle operation is not satisfied until the bki1ded bit of the uf0dend register is set to 1. to send a short packet that does not make the fifo on the cpu side full, set the bki1ded bit to 1 after completing writing data. when the bki1ded bit is set to 1, a toggle operation is performed and at the same time, this bit is automatically set to 1. this bit is also cleared to 0 as soon as the uf0bi1 register has been cleared. cautions 1. if dma is enabled wh ile data is being written to the uf0b i1 register in the pio mode, a dma request is immediately issued. 2. if 64-byte data is written in the dm a transfer mode, the dma request signal becomes inactive. if the bki1nk bit is then set to 1, da ta is transmitted in synchronization with an in token. the dma request signal becomes acti ve again as long as the dma request is not masked as soon as the fifo is toggled. if the bki1nk bit is not set, data is not transmitted even if an in token has been received. in this case, set th e bki1ded bit of the uf0dend register to 1. 3. if the tc signal is received in the dm a transfer mode, the dma request signal becomes inactive. at the same time, the dma request is masked. if th e bki1nk bit is not set to 1, data is not transmitted even if an in token is received. when th e bki1ded bit of the uf0dend register is set to 1 by fw, data is transmitted in synchronization with the in token. to execute dma transfer again, unmask the dma request. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1217 of 1817 sep 19, 2011 (4) uf0 epnak mask register (uf0enm) this register controls masking a wr ite access to the uf0en register. this register can be read or written in 8-bit units. be sure to clear bits 7 to 4, 1, and 0 to ?0?. if it is set to 1, the operation is not guaranteed. 0 uf0enm 0 5 00 3 bko2nkm 2 bko1nkm 1 00 address 00200006h after reset 00h 0 4 6 7 bit position bit name function 3 bko2nkm this bit specifies whether a write access to bit 3 (bko2nk) of the uf0en register is masked or not. 1: do not mask. 0: mask (default value). 2 bko1nkm this bit specifies whether a write access to bit 2 (bko1nk) of the uf0en register is masked or not. 1: do not mask. 0: mask (default value). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1218 of 1817 sep 19, 2011 (5) uf0 sndsie register (uf0sds) this register performs manipulation such as no handsha ke. it can directly manipulate the pins of sie. this register can be read or written in 8-bit units. be sure to clear bit 2 to ?0?. if it is set to 1, the operation is not guaranteed. 0 uf0sds 0 5 00 3 sndstl 2 0 1 0 rsumin address 00200008h after reset 00h 0 4 6 7 bit position bit name function 3 sndstl this bit makes endpoint0 issue a stall handshake. setting this bit to 1 if a request for cpudec processing is not supported by t he system results in a stall handshake response. if an unsupported wvalue is sent by the set_configuration or set_interface request, the hardware sets this bit to 1. if a problem occurs in endpoint0 due to overrun of an automatically exec uted request, this bit is also set to 1. however, the e0halt bit of the uf0e0sl register is not set to 1. 1: respond with stall handshake. 0: do not respond with stall handshake (default value). this bit is cleared to 0 and the handshake re sponse to the bus is other than stall when the next setup token is received. to set the sndstl bit to 1 by fw, do not write data to the uf0e0w register. depending on the timing of setting this bit, the stall response is not made in time, and it may be made to the next transfer after a nak response has been made. setting this bit is valid only while an fw-exe cuted request is under execution when this bit is set to 1. it is automatically cleared to 0 when the next setup token is received. remark the sndstl bit is valid only for an fw-executed request. 0 rsumin this bit outputs the resume signal onto the usb bus. writing this bit is invalid unless the rmwk bit of the uf0dstl register is set to 1. 1: generate the resume signal. 0: do not generate the resume signal (default value). while this bit is set to 1, the resume signal continues to be generated. clear this bit to 0 by fw after a specific time has elapsed. be cause the signal is internally sampled at the clock, the operation is guaranteed only while cl k is supplied. care must be exercised when clk of the system is stopped. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1219 of 1817 sep 19, 2011 (6) uf0 clr request register (uf0clr) this register indicates the target of the received clear_feature request. this register is read-only, in 8-bit units. this register is meaningful only when an interrupt request is generated. each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read. the related bits are invalid if each endpo int is not supported by the setting of t he uf0enim register (n = 1 to 4, 7) and the current setting of the interface. 0 uf0clr clrep7 5 clrep4 clrep3 3 clrep2 2 clrep1 1 clrep0 clrdev address 0020000ah after reset 00h 0 4 6 7 bit position bit name function 6 to 1 clrepn these bits indicate that a clear_feat ure endpoint n request is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) 0 clrdev this bit indicates that a clear_feature de vice request is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) remark n = 0 to 4, 7 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1220 of 1817 sep 19, 2011 (7) uf0 set request register (uf0set) this register indicates the target of the automatically processed set _xxxx (except set_interface) request. this register is read-only, in 8-bit units. this register is meaningful only when an interrupt request is generated. each bit is set to 1 after completion of the status stage, and automatically cleared to 0 when this register is read. setcon uf0set 0 5 00 3 0 2 setep 1 0 setdev address 0020000ch after reset 00h 0 4 6 7 bit position bit name function 7 setcon this bit indicates that a set_configuration request is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) 2 setep this bit indicates that a set_feature endpoint n request (n = 0 to 4, 7) is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) 0 setdev this bit indicates that a set_feature de vice request is received and automatically processed. 1: automatically processed 0: not automatically processed (default value) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1221 of 1817 sep 19, 2011 (8) uf0 ep status 0 register (uf0eps0) this register indicates the usb bus status a nd the presence or absence of register data. this register is read-only, in 8-bit units. the related bits are invalid if each endpo int is not supported by the setting of t he uf0enim register (n = 1 to 4, 7) and the current setting of the interface. it takes five usb clocks to reflect the status on this re gister after the uf0fic0 and uf0fic1 registers have been set. if it is necessary to read the status correctly, therefor e, separate writing to the uf0fic0 and uf0fic1 registers from reading from the uf0eps0, uf0eps1, uf0eps2, uf0e0n , and uf0en registers by at least four usb clocks. (1/2) 0 uf0eps0 it1 5 bkout2 bkout1 3 bkin2 2 bkin1 1 ep0w ep0r address 0020000eh after reset 00h 0 4 6 7 bit position bit name function 6 it1 these bits indicate that data is in the uf0int 1 register (fifo). by setting the it1ded bit of the uf0dend register to 1, the status in which data is in the uf0int1 register can be created even if data is not written to the regi ster (null data transmission). as soon as the it1ded bit of the uf0dend register is set to 1 even when the counter of the uf0int1 register is 0, this bit is set to 1 by hardwar e. it is cleared to 0 after correct transmission. 1: data is in the register. 0: no data is in the register (default value). 5, 4 bkoutn these bits indicate that data is in the uf0bon register (fifo) connected to the cpu side. when the fifo configuring the uf 0bon register is toggled, this bit is automatically set to 1 by hardware. it is automatically clear ed to 0 by hardware when reading the uf0bon register (fifo) connected to the cpu side has been completed (counter value = 0). it is not set to 1 when null data is received (toggling the fifo does not take place either). 1: data is in the register. 0: no data is in the register (default value). 3, 2 bkinn these bits indicate that data is in the uf0bin register (fifo) connected to the cpu side. by setting the bkinded bit of the uf0dend register to 1, the status in which data is in the uf0bin register can be created even if data is not written to the register (null data transmission). as soon as the bkinded bit of the uf0dend register has been set to 1 while the counter of the uf0bin register is 0, th is bit is set to 1 by hardware. it is cleared to 0 when a toggle operation is performed. 1: data is in the register. 0: no data is in the register (default value). remark n = 1, 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1222 of 1817 sep 19, 2011 (2/2) bit position bit name function 1 ep0w this bit indicates that data is in the uf0e0w register (fifo). by setting the e0ded bit of the uf0dend register to 1, the status in wh ich data is in the uf0e0w register can be created even if data is not written to the regi ster (null data transmission). as soon as the e0ded bit of the uf0dend register is set to 1 even when the counter of the uf0e0w register is 0, this bit is set to 1 by hardwar e. it is cleared to 0 after correct transmission. 1: data is in the register. 0: no data is in the register (default value). 0 ep0r this bit indicates that data is in the uf0e0r register (fifo). it is automatically cleared to 0 by hardware when reading the uf0e0r regist er (fifo) has been completed (counter value = 0). it is not set to 1 if null data is received. 1: data is in the register. 0: no data is in the register (default value). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1223 of 1817 sep 19, 2011 (9) uf0 ep status 1 register (uf0eps1) this register indicates the usb bus status a nd the presence or absence of register data. this register is read-only, in 8-bit units. rsum uf0eps1 0 5 00 3 0 2 0 1 00 address 00200010h after reset 00h 0 4 6 7 bit position bit name function 7 rsum this bit indicates that the usb bus is in the resume status. this bit is meaningful only when an interrupt request is generated. 1: suspend status 0: resume status (default value) because sampling is internally performed with the clock, the operation is guaranteed only when clk is supplied. care must be exercised when clk of the system is stopped. the intusbf1 signal of sie operates even when clk is stopped. it can therefore be supported by making the interrupt control register (ufic1) valid or lowering the frequency of clk to the usbf. this bit is automatically cl eared to 0 when it is read. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1224 of 1817 sep 19, 2011 (10) uf0 ep status 2 register (uf0eps2) this register indicates the usb bus status a nd the presence or absence of register data. this register is read-only, in 8-bit units. the related bits are invalid if each endpoi nt is not supported by the setting of t he uf0enim register (n = 1 to 4, 7) and the current setting of the interface. 0 uf0eps2 0 5 halt7 halt4 3 halt3 2 halt2 1 halt1 halt0 address 00200012h after reset 00h 0 4 6 7 bit position bit name function 5 to 0 haltn these bits indicate that endpoi nt n is currently stalled. they are set to 1 when a stall condition, such as occurrence of an over run and reception of an undefined request, is satisfied. these bits are automatically set to 1 by hardware. 1: endpoint is stalled. 0: endpoint is not stalled (default value). the sndstl bit is set to 1 as soon as the halt0 bit has been set to 1 as a result of occurrence of an overrun or reception of an undefined request. if the next setup token is received in this status, the sndstl bit is cleared to 0 and, therefore, the halt0 bit is also cleared to 0. if endpoint0 is stalled by the set_feature endpoint0 request, this bit is not cleared to 0 until the clear_feat ure endpoint0 request is received or halt feature is cleared by fw. if the get_status endpoint0, clear_feature endpoint0, or set_feature endpoint0 request is received, or if a request to be processed by fw is received due to the cpudec interrupt request, the halt0 bit is masked and cleared to 0, until the next setup token is received. the haltn bit is not cleared to 0 until endpoint n receives the clear_feature endpoint request, halt feature is cleared by the set_interface or set_configuration request to the interface to which the endpoint is linked, or halt feature is cleared by fw. when the set_interface or set_configuration request is correctly processed, the halt f eature of all the target endpoints, except endpoint0, is cleared after the request has been processed, even if the wvalue is the same as the currently set value, and these bits are also cleared to 0. halt feature of endpoint0 cannot be cleared if it is set be cause the stall response is made in response to the set_interface and set_configuration requests. remark n = 0 to 4, 7 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1225 of 1817 sep 19, 2011 (11) uf0 int status 0 register (uf0is0) this register indicates the interrupt source. if the cont ents of this register are changed, the epcint0b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusbf0) is generated from usbf, t he fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the uf0ic0 register. caution in the usbf, multiple interrupt sources, such as bus reset, resume, and short, are ored internally and are issued as a single interrupt request (intusbf 0). therefore, in the case of the occurrence of multiple interrupt sources, they are ored and issued as an intusbf0 interrupt request. for example, if a bus reset interrupt sour ce and resume interrupt source occur, the two sources are ored and an intusbf0 interrupt request is issued. under these conditions, if the bus reset interrupt source is cleared to 0 (uf0ic0.busrstc = 0), the v850es/jh3-e or v850es/jj3-e internal intusb f0 interrupt request may remain set to 1 since the resume interrupt source will still remain. the new interrupt request flag (us0bic.us0bif), therefore, might not be set to 1. in this case, after performing clear processing for each interrupt request with the intusbf0 interrupt servicing routine, confirm the flag stat us for the uf0is0 and uf0is1 registers again, and if there are any interrupt sources with flag s set to 1, perform flag clearing (only the applicable bits need to be cleared (do not perform a batch clearing)). (1/2) uf0is0 rsuspd 5 0 3 dmaed 2 setrq 1 clrrq address 00200020h after reset 00h 0 ephalt 4 short 6 7 busrst bit position bit name function 7 busrst this bit indicates that bus reset has occurred. 1: bus reset has occurred (interrupt request is generated). 0: not bus reset status (default value) 6 rsuspd this bit indicates that the resume or sus pend status has occurred. reference bit 7 of the uf0eps1 register by fw. 1: resume or suspend status has occurred (interrupt request is generated). 0: resume or suspend status has not occurred (default value). 4 short this bit indicates that data is read from the fifo of either the uf0bo1 or uf0bo2 register and that the usbspnb signal (n = 2, 4) is active. it is valid only when the fifo is full in the dma mode. 1: usbspnb signal is active (interrupt request is generated). 0: usbspnb signal is not active (default value). identify on which endpoint the operation is performed, by using the uf0dms1 register. this bit is not automatically cleared to 0 ev en when the uf0dms1 register is read by fw. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1226 of 1817 sep 19, 2011 (2/2) bit position bit name function 3 dmaed this bit indicates that the dma end (tc) signal for endpoint n (n = 1 to 4, 7) is active. 1: dma end signal for endpoint n has been input (interrupt request is generated). 0: dma end signal for endpoint n ha s not been input (default value). when this bit is set to 1, the dma request signal for endpoint n becomes inactive. the dma request signal for endpoint n does no t become active unless fw enables dma transfer. use the uf0dms0 register to confirm on which endpoint the operation is actually performed. however, this bit is not autom atically cleared to 0 even if the uf0dms0 register is read by fw. 2 setrq this bit indicates that the set_xxxx request to be automatically processed has been received and automatically processed (xxxx = configuration or feature). 1: set_xxxx request to be automatically processed has been received (interrupt request is generated). 0: set_xxxx request to be automatically processed has not been received (default value). this bit is set to 1 after completion of the status stage. reference the uf0set register to identify what is the target of the request. this bit is not automatically cleared to 0 even if the uf0set register is read by fw. the ephalt bit is also set to 1 when the set_feature endpoint request has been received. 1 clrrq this bit indicates that the clear_feature request has been received and automatically processed. 1: clear_feature request has been received (interrupt request is generated). 0: clear_feature request has not been received (default value). this bit is set to 1 after completion of the st atus stage. reference the uf0clr register to identify what is the target of the request. this bit is not automatically cleared to 0 even if the uf0clr register is read by fw. 0 ephalt this bit indicates that an endpoint has stalled. 1: endpoint has stalled (interrupt request is generated). 0: endpoint has not stalled (default value). this bit is also set to 1 when an endpoint has stalled by setting fw. identify the endpoint that has stalled, by referencing the uf0eps2 register. this bit is not automatically cleared to 0 even when the clear_feature endpoint, set_interface, or set_configuration request is received. it is not automatically cleared to 0, either, if the next setup token is received in case of overrun of endpoint0. caution even if halt feature of endpoint0 is set and this interrupt request is generated, bit 0 of the uf0eps2 register is masked and cleared to 0 between when a set_feature endpoint0, clear_feature endpoint0, or get_status endpoint0 request, or fw-processed request is received and when a setup token other than the above is received. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1227 of 1817 sep 19, 2011 (12) uf0 int status 1 register (uf0is1) this register indicates the interrupt source. if the cont ents of this register are changed, the epcint0b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusbf0) is generated from usbf, t he fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bi t of the uf0ic1 register. however, the suces and stg bits of the uf0is1 regist er are automatically cleared to 0 when the next setup token has been received. caution in the usbf, multiple interrupt sources, such as bus reset, resume, and short, are ored internally and are issued as a single interrupt request (intusbf 0). therefore, in the case of the occurrence of multiple interrupt sources, they are ored and issued as an intusbf0 interrupt request. for example, if a bus reset interrupt sour ce and resume interrupt source occur, the two sources are ored and an intusbf0 interrupt request is issued. under these conditions, if the bus reset interrupt source is cleared to 0 (uf0ic0.busrstc = 0), the v850es/jh3-e or v850es/jj3-e internal intusb f0 interrupt request may remain set to 1 since the resume interrupt sour ce will still be remaining. the new interrupt request flag (us0bic.us0bif), therefore, might not be set to 1. in this case, after performing clear processing for each interrupt request with the intusbf0 interrupt servicing routine, confirm the flag stat us for the uf0is0 and uf0is1 registers again, and if there are any interrupt sources with flag s set to 1, perform flag clearing (only the applicable bits need to be cleared (do not perform a batch clearing)). (1/2) uf0is1 cpu dec 5 e0indt 3 suces 2 stg 1 prot address 00200022h after reset 00h 0 4 e0odt 6 e0in 7 0 bit position bit name function 6 e0in this bit indicates that an in token for endpoint0 has been received and that the hardware has automatically transmitted nak. 1: in token is received and nak is trans mitted (interrupt request is generated). 0: in token is not received (default value). 5 e0indt this bit indicates that data has been correct ly transmitted from the uf0e0w register. 1: transmission from uf0e0w register is completed (interrupt request is generated). 0: transmission from uf0e0w register is not completed (default value). data is transmitted in synchronization with the in token next to the one that set the ep0nkw bit of the uf0e0n register to 1. this bit is automatically set to 1 by hardware when the host correctly receives that data. it is also set to 1 even if the data is a null packet. this bit is automatically cleared to 0 by hardware when the first write access is made to the uf0e0w register. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1228 of 1817 sep 19, 2011 (2/2) bit position bit name function 4 e0odt this bit indicates that data has been correctly received in the uf0e0r register. 1: data is in uf0e0r register (interrupt request is generated). 0: data is not in uf0e0r register (default value). this bit is automatically set to 1 by hardw are when data has been correctly received. at the same time, the ep0r bit of the uf0eps0 register is also set to 1. if a null packet has been received, this bit is not set to 1. it is automatically cleared to 0 by hardware when the fw reads the uf0e0r register and the value of the uf0e0l register becomes 0. 3 suces this bit indicates that either an fw-pro cessed or hardware-processed request has been received and that the status stage has been correctly completed. 1: control transfer has been correctly processed (interrupt request is generated). 0: control transfer has not been processed correctly (default value). this bit is set to 1 upon completion of the status stage. it is automatically cleared to 0 by hardware when the next setup token is received. this bit is also set to 1 when data with data pid of 0 (null data) is received in the status stage of control transfer. 2 stg this bit is set to 1 when the stage of control transfer has changed to the status stage. it is valid for both fw-processed and hardware-process ed requests. this bit is also set to 1 when the stage of control transfer (without data) has changed to the status stage. 1: status stage (interrupt request is generated) 0: not status stage (default value) this bit is automatically cleared to 0 by har dware when the next setup token is received. it is also set to 1 when the stage of control transfer has changed to the status stage while ack cannot be correctly received in the data stage. in this case, the ep0nkw bit of the uf0e0n register is also cleared to 0 as s oon as the uf0e0w register has been cleared, if the fw is processing control transfer (read). 1 prot this bit indicates that a setup token has been received. it is valid for both fw- processed and hardware-processed requests. 1: setup token is correctly received (interrupt request is generated). 0: setup token is not received (default value). this bit is set to 1 when data has been correctly received in the uf0e0st register. clear this bit to 0 by fw when the first read access is made to the uf0e0st register. if it is not cleared to 0 by fw, reception of the next setup token cannot be correctly recognized. this bit is used to accurately recognize that a setup transaction has been executed again during control transfer. if the setup transaction is re-executed during control transfer and if a second request is executed by hardware, the cpudec bit is not set to 1, but the prot bit can be used for recognition of the re-execution. 0 cpudec this bit indicates that the uf0e0st register has a request that is to be decoded by fw. 1: data is in uf0e0st register (interrupt request is generated). 0: data is not in uf0e0st register (default value). this bit is automatically cleared to 0 by hardware when all the data of the uf0e0st register is read. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1229 of 1817 sep 19, 2011 (13) uf0 int status 2 register (uf0is2) this register indicates the interrupt source. if the cont ents of this register are changed, the epcint1b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusbf0) is generated from usbf, t he fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the uf0ic2 register. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0eni m register (n = 1, 3, 7) and the current setting of the interface. bki2in uf0is2 bki2dt 5 bki1in bki1dt 3 0 2 0 1 0 it1dt address 00200024h after reset 00h 0 4 6 7 bit position bit name function 7, 5 bkinin these bits indicate that an in token has be en received in the uf0bin register (endpoint m) and that nak has been returned. 1: in token is received and nak is trans mitted (interrupt request is generated). 0: in token is not received (default value). 6, 4 bkindt these bits indicate that the fifo of the uf 0bin register (endpoint m) has been toggled. this means that data can be written to endpoint m. 1: fifo has been toggled (interrupt request is generated). 0: fifo has not been toggled (default value). the data written to endpoint m is transmitted in synchronization with the in token next to the one that set the bkinnk bit of the uf0en register to 1. when the fifo has been toggled and then data can be written from the cpu, this bit is automatically set to 1 by hardware. it is also set to 1 when the fifo has been toggled, even if the data is a null packet. this bit is automatically cleared to 0 by hardware when the first write access is made to the uf0bin register. 0 it1dt these bits indicate that data has been corre ctly received from the uf0int1 register (endpoint 7). 1: transmission is completed (interrupt request is generated). 0: transmission is not completed (default value). data is transmitted in synchronization with the in token next to the one that set the it1nk bit of the uf0en register to 1. this bit is automatically set to 1 by hardware when the host has correctly received that data. it is automatically cleared to 0 by hardware when the first write access is made to the uf0int1 r egister. this bit is also set to 1 even when the data is a null packet. remark n = 1, 2 m = 1 and x = 7 where n = 1 m = 3 where n = 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1230 of 1817 sep 19, 2011 (14) uf0 int status 3 register (uf0is3) this register indicates the interrupt source. if the cont ents of this register are changed, the epcint1b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusbf0) is generated from usbf, t he fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the uf0ic3 register. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0enim register (n = 2, 4) and the current setting of the interface. (1/2) uf0is3 bko1dt 5 bko2 nak 3 bko1fl 2 bko1nl 1 bko1 nak address 00200026h after reset 00h 0 4 bko2dt 6 bko2nl 7 bko2fl bit position bit name function 7, 3 bkonfl these bits indicate that data has been corre ctly received in the uf0bon register (endpoint m) and that both the fifos of the cpu and sie hold the data. 1: received data is in both the fifos of the uf0bon register (interrupt request is generated). 0: received data is not in the fifo on the sie side of the uf0bon register (default value). if data is held in both the fifos of the cpu and sie, these bits are automatically set to 1 by hardware. they are automatically cleared to 0 by hardware when the fifo is toggled. 6, 2 bkonnl these bits indicate that a null packet (packet with a length of 0) has been received in the uf0bon register (endpoint m). 1: null packet is received (interrupt request is generated). 0: null packet is not received (default value). these bits are set to 1 immediately after reception of a null packet when the fifo is empty. they are set to 1 when the fifo on the cpu side has been completely read if data is in that fifo. 5, 1 bkonnak these bits indicate that an out token ha s been received to the uf0bon register (endpoint m) and that nak has been returned. 1: out token is received and nak is transmitted (interrupt request is generated). 0: out token is not received (default value). remark n = 1, 2 m = 2 where n = 1 m = 4 where n = 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1231 of 1817 sep 19, 2011 (2/2) bit position bit name function 4, 0 bkondt these bits indicate that data has been corre ctly received in the uf0bon register (endpoint m). 1: reception has been completed correctly (interrupt request is generated). 0: reception has not been completed (default value). these bits are automatically set to 1 by hardware when data has been correctly received and the fifo has been toggled. at the same time, the corresponding bits of the uf0eps0 register are also set to 1. they are not set to 1 when the data is a null packet. these bits are automatically cleared to 0 by hardware when the value of the uf0bonl register becomes 0 as a result of reading the uf0bon register by fw. these bits are automatically cleared to 0 when all the contents of the fifo on the cpu side have been read. however, the interrupt request is not cleared if data is in the fifo on the sie side at this time, and the intusb f1 signal does not become inactive. the signal is kept active if data is successively received. remark n = 1, 2 m = 2 where n = 1 m = 4 where n = 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1232 of 1817 sep 19, 2011 (15) uf0 int status 4 register (uf0is4) this register indicates the interrupt source. if the cont ents of this register are changed, the epcint2b signal becomes active. this register is read-only, in 8-bit units. if an interrupt request (intusbf0) is generated from usbf, t he fw must read this register to identify the interrupt source. each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the uf0ic4 register. the related bits are invalid if each endpoi nt is not supported by the setting of t he uf0enim register (n = 1 to 4, 7) and the current setting of the interface. 0 uf0is4 0 5 setint 0 3 0 2 0 1 00 address 00200028h after reset 00h 0 4 6 7 bit position bit name function 5 setint this bit indicates that the set_interface request has been received and automatically processed. 1: the request has been automatically pr ocessed (interrupt request is generated). 0: the request has not been automat ically processed (default value). the current setting of this bit can be identifi ed by reading the uf0ass or uf0ifn register (n = 0 to 4). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1233 of 1817 sep 19, 2011 (16) uf0 int mask 0 register (uf0im0) this register controls masking of the interr upt sources indicated by the uf0is0 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from usbf (intusbf0) by writing 1 to the corresponding bit of this register. bus rstm uf0im0 rsu spdm 5 0 3 dma edm 2 set rqm 1 clr rqm ep haltm address 0020002eh after reset 00h 0 4 shortm 6 7 bit position bit name function 7 busrstm this bit masks the bus reset interrupt. 1: mask 0: do not mask (default value) 6 rsuspdm this bit masks the resume/suspend interrupt. 1: mask 0: do not mask (default value) 4 shortm this bit masks the short interrupt. 1: mask 0: do not mask (default value) 3 dmaedm this bit masks the dma_end interrupt. 1: mask 0: do not mask (default value) 2 setrqm this bit masks the set_rq interrupt. 1: mask 0: do not mask (default value) 1 clrrqm this bit masks the clr_rq interrupt. 1: mask 0: do not mask (default value) 0 ephaltm this bit masks the ep_halt interrupt. 1: mask 0: do not mask (default value) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1234 of 1817 sep 19, 2011 (17) uf0 int mask 1 register (uf0im1) this register controls masking of the interr upt sources indicated by the uf0is1 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from usbf (intusbf0) by writing 1 to the corresponding bit of this register. uf0im1 5 e0 indtm 3 sucesm 2 stgm 1 protm cpu decm address 00200030h after reset 00h 0 4 e0 odtm 6 e0inm 7 0 bit position bit name function 6 e0inm this bit masks the ep0in interrupt. 1: mask 0: do not mask (default value) 5 e0indtm this bit masks the ep0indt interrupt. 1: mask 0: do not mask (default value) 4 e0odtm this bit masks the ep0outdt interrupt. 1: mask 0: do not mask (default value) 3 sucesm this bit masks the success interrupt. 1: mask 0: do not mask (default value) 2 stgm this bit masks the stg interrupt. 1: mask 0: do not mask (default value) 1 protm this bit masks the protect interrupt. 1: mask 0: do not mask (default value) 0 cpudecm this bit masks the cpudec interrupt. 1: mask 0: do not mask (default value) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1235 of 1817 sep 19, 2011 (18) uf0 int mask 2 register (uf0im2) this register controls masking of the interr upt sources indicated by the uf0is2 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from usbf (intusbf0) by writing 1 to the corresponding bit of this register. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0eni m register (n = 1, 3, 7) and the current setting of the interface. uf0im2 5 bki1inm 3 0 2 0 1 0 address 00200032h after reset 00h 0 it1dtm 4 bki1 dtm 6 bki2 dtm 7 bki2inm bit position bit name function 7, 5 bkininm these bits mask the blkinin interrupt. 1: mask 0: do not mask (default value) 6, 4 bkindtm these bits mask the blkindt interrupt. 1: mask 0: do not mask (default value) 0 it1dtm these bits mask the int1dt interrupt. 1: mask 0: do not mask (default value) remark n = 1, 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1236 of 1817 sep 19, 2011 (19) uf0 int mask 3 register (uf0im3) this register controls masking of the interr upt sources indicated by the uf0is3 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from usbf (intusbf0) by writing 1 to the corresponding bit of this register. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0enim register (n = 2, 4) and the current setting of the interface. bko2 flm uf0im3 bko2 nlm 5 bko2 nakm 3 bko1 flm 2 bko1 nlm 1 bko1 nakm bko1 dtm address 00200034h after reset 00h 0 4 bko2 dtm 6 7 bit position bit name function 7, 3 bkonflm these bits mask the blkonfl interrupt. 1: mask 0: do not mask (default value) 6, 2 bkonnlm these bits mask the blkonnl interrupt. 1: mask 0: do not mask (default value) 5, 1 bkonnakm these bits mask the blkonnk interrupt. 1: mask 0: do not mask (default value) 4, 0 bkondtm these bits mask the blkondt interrupt. 1: mask 0: do not mask (default value) remark n = 1, 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1237 of 1817 sep 19, 2011 (20) uf0 int mask 4 register (uf0im4) this register controls masking of the interr upt sources indicated by the uf0is4 register. this register can be read or written in 8-bit units. fw can mask occurrence of an interrupt request from usbf (intusbf0) by writing 1 to the corresponding bit of this register. the related bits are invalid if each endpoi nt is not supported by the setting of t he uf0enim register (n = 1 to 4, 7) and the current setting of the interface. 0 uf0im4 0 5 setintm 0 3 0 2 0 1 00 address 00200036h after reset 00h 0 4 6 7 bit position bit name function 5 setintm this bit masks the set_int interrupt. 1: mask 0: do not mask (default value) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1238 of 1817 sep 19, 2011 (21) uf0 int clear 0 register (uf0ic0) this register controls clearing the interrup t sources indicated by the uf0is0 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw bef ore it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. bus rstc uf0ic0 rsu spdc 5 1 3 dma edc 2 set rqc 1 clr rqc ep haltc address 0020003ch after reset ffh 0 4 shortc 6 7 bit position bit name function 7 busrstc this bit clears the bus reset interrupt. 0: clear 6 rsuspdc this bit clears the resume/suspend interrupt. 0: clear 4 shortc this bit clears the short interrupt. 0: clear 3 dmaedc this bit clears the dma_end interrupt. 0: clear 2 setrqc this bit clears the set_rq interrupt. 0: clear 1 clrrqc this bit clears the clr_rq interrupt. 0: clear 0 ephaltc this bit clears the ep_halt interrupt. 0: clear v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1239 of 1817 sep 19, 2011 (22) uf0 int clear 1 register (uf0ic1) this register controls clearing the interrup t sources indicated by the uf0is1 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw bef ore it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. uf0ic1 5 e0 indtc 3 sucesc 2 stgc 1 protc cpu decc address 0020003eh after reset ffh 0 4 e0odtc 6 e0inc 7 1 bit position bit name function 6 e0inc this bit clears the ep0in interrupt. 0: clear 5 e0indtc this bit clears the ep0indt interrupt. 0: clear 4 e0odtc this bit clears the ep0outdt interrupt. 0: clear 3 sucesc this bit clears the success interrupt. 0: clear 2 stgc this bit clears the stg interrupt. 0: clear 1 protc this bit clears the protect interrupt. 0: clear 0 cpudecc this bit clears the cpudec interrupt. 0: clear v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1240 of 1817 sep 19, 2011 (23) uf0 int clear 2 register (uf0ic2) this register controls clearing the interrup t sources indicated by the uf0is2 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw bef ore it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0eni m register (n = 1, 3, 7) and the current setting of the interface. uf0ic2 5 bki1inc 3 1 2 1 1 1 address 00200040h after reset ffh 0 it1dtc 4 bki1 dtc 6 bki2 dtc 7 bki2inc bit position bit name function 7, 5 bkininc these bits clear the blkinin interrupt. 0: clear 6, 4 bkindtc these bits clear the blkindt interrupt. 0: clear 0 it1dtc these bits clear the int1dt interrupt. 0: clear remark n = 1, 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1241 of 1817 sep 19, 2011 (24) uf0 int clear 3 register (uf0ic3) this register controls clearing the interrup t sources indicated by the uf0is3 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw bef ore it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0enim register (n = 2, 4) and the current setting of the interface. bko2 flc uf0ic3 bko2 nlc 5 bko2 nakc bko2 dtc 3 bko1 flc 2 bko1 nlc 1 bko1 nakc bko1 dtc address 00200042h after reset ffh 0 4 6 7 bit position bit name function 7, 3 bkonflc these bits clear the blkonfl interrupt. 0: clear 6, 2 bkonnlc these bits clear the blkonnl interrupt. 0: clear 5, 1 bkonnakc these bits clear the blkonnk interrupt. 0: clear 4, 0 bkondtc these bits clear the blkondt interrupt. 0: clear remark n = 1, 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1242 of 1817 sep 19, 2011 (25) uf0 int clear 4 register (uf0ic4) this register controls clearing the interrup t sources indicated by the uf0is4 register. this register is write-only, in 8-bit units. if this register is read, the value ffh is read. fw can clear an interrupt source by writing 0 to the co rresponding bit of this register. even a bit that is automatically cleared to 0 by hardware can be cleared by fw bef ore it is cleared by hardware. writing 0 to a bit of this register automatically sets the bit to 1. writing 1 is invalid. the related bits are invalid if each endpoi nt is not supported by the setting of t he uf0enim register (n = 1 to 4, 7) and the current setting of the interface. 1 uf0ic4 1 5 setintc 1 3 1 2 1 1 11 address 00200044h after reset ffh 0 4 6 7 bit position bit name function 5 setintc this bit clears the set_int interrupt. 0: clear v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1243 of 1817 sep 19, 2011 (26) uf0 int & dmarq register (uf0idr) this register selects reporting via an interrupt request or starting dma. this register can be read or written in 8-bit units. if data exists in either the uf0bo1 or uf0bo1 register, or if data can be writt en to the uf0bi1 or uf0bi2 register, this register selects whether it is r eported to the fw by an interrupt request, or whether starting dma is requested. if starting dma is requested, the dma transfer mode can be selected according to the setting of bits 0 and 1. the related bits are invalid if each end point is not supported by the setting of the uf0enim register (n = 1 to 4) and the current setting of the interface. be sure to clear bits 3 and 2 to ?0?. if they are set to 1, the operation is not guaranteed. caution if the target endpoint is not supported by the set_interface request under dma transfer, the dma request signal becomes inact ive immediately, and the corresponding bit is automatically cleared to 0 by hardware. (1/2) dqbi2 ms uf0idr dqbi1 ms 5 dqbo2 ms dqbo1 ms 3 0 2 0 1 mode1 address 0020004ch after reset 00h 0 mode0 4 6 7 bit position bit name function 7, 6 dqbinms these bits enable (mask) a write dma transfer request (dma request signal for endpoint m) to the uf0bin register. when these bi ts are set to 1, the dma request signal for endpoint m becomes active while writing data can be acknowledged. if the dma end signal for endpoint m is input (if the dma controller issues tc), these bits are automatically cleared to 0 by hardware. to c ontinue dma transfer, re-set these bits to 1 by fw. 1: enables active dma request signal for endpoint m (masks bkindt interrupt). 0: disables active dma request si gnal for endpoint m (default value). 5, 4 dqbonms these bits enable (mask) a read dma transfe r request (dma request signal for endpoint x) to the uf0bon register. when these bi ts are set to 1, the dma request signal for endpoint x becomes active if the data to be read is prepared in the uf0bon register. if the dma end signal for endpoint x is input (if t he dma controller issues tc), these bits are automatically cleared to 0 by hardware. th ey are also cleared to 0 when the usbspxb signal is active. to continue dma transfer, re-set these bits to 1 by fw. 1: enables active dma request signal for endpoint x (masks bkondt interrupt). 0: disables active dma request si gnal for endpoint x (default value). remark n = 1, 2 m = 1 and x = 2 where n = 1 m = 3 and x = 4 where n = 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1244 of 1817 sep 19, 2011 (2/2) bit position bit name function these bits select the dma transfer mode. mode1 mode0 mode remark 1 0 demand mode dma request signal becomes active as long as there is data. it becomes inactive if there is no more data. other than above setting prohibited 1, 0 mode1, mode0 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1245 of 1817 sep 19, 2011 (27) uf0 dma status 0 register (uf0dms0) this register indicates the dma st atus of endpoint1 to endpoint4. this register is read-only, in 8-bit units. the related bits are invalid if each end point is not supported by the setting of the uf0enim register (n = 1 to 4) and the current setting of the interface. 0 uf0dms0 0 5 dqe4 dqe3 3 dqe2 2 dqe1 1 00 address 0020004eh after reset 00h 0 4 6 7 bit position bit name function 5 dqe4 this bit indicates that a dma read request is being issued from endpoint4 to memory. 1: dma read request from endpoint4 is being issued. 0: dma read request from endpoint4 is not being issued (default value). 4 dqe3 this bit indicates that a dma write request is being issued from memory to endpoint3. note that, even if data is in endpoint3 (when the fifo is not full and after the bki2ded bit has been set to 1), the dma request si gnal becomes active immediately and dma transfer is started when the dqbi2ms bit of the uf0idr register is set to 1. 1: dma write request for endpoint3 is being issued. 0: dma write request for endpoint3 is not being issued (default value). 3 dqe2 this bit indicates that a dma read request is being issued from endpoint2 to memory. 1: dma read request from endpoint2 is being issued. 0: dma read request from endpoint2 is not being issued (default value). 2 dqe1 this bit indicates that a dma write request is being issued from memory to endpoint1. note that, even if data is in endpoint1 (when the fifo is not full and after the bki1ded bit has been set to 1), the dma request si gnal becomes active immediately and dma transfer is started when the dqbi1ms bit of the uf0idr register is set to 1. 1: dma write request for endpoint1 is being issued. 0: dma write request for endpoint1 is not being issued (default value). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1246 of 1817 sep 19, 2011 (28) uf0 dma status 1 register (uf0dms1) this register indicates the dma st atus of endpoint1 to endpoint4. this register is read-only, in 8-bit units. the related bits are invalid if each end point is not supported by the setting of the uf0enim register (n = 1 to 4) and the current setting of the interface. each bit is automatically cleared to 0 when this register is read. even when this register is read, however, bits 4 and 3 of the uf0is0 register are not cleared to 0. if the target endpoint is no longer supported by the set_interface request, each bit is automatically cleared to 0 by hardware (however, the dma_end interrupt request and short interrupt request are not cleared). dede4 uf0dms1 dspe4 5 dede3 dede2 3 dspe2 2 dede1 1 00 address 00200050h after reset 00h 0 4 6 7 bit position bit name function 7, 5, 4, 2 deden these bits indicate that the dma end (tc) signal for endpoint n becomes active and dma is stopped while a dma read request is bei ng issued from endpoint n to memory. 1: dma end signal for endpoint n is active. 0: dma end signal for endpoint n is inactive (default value). 6, 3 dspem these bits indicate that, although a dma r ead request was being issued from endpoint m to memory, dma has been stopped because the received data is a short packet and there is no more data to be transferred. 1: dmastop_epm signal is active. 0: dmastop_epm signal is inactive (default value). remark n = 1 to 4 m = 2, 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1247 of 1817 sep 19, 2011 (29) uf0 fifo clear 0 register (uf0fic0) this register clears each fifo. this register is write-only, in 8-bit units . if this register is read, 00h is read. fw can clear the target fifo by writing 1 to the corres ponding bit of this register. the bit to which 1 has been written is automatically cleared to 0. writing 0 to the bit is invalid. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0eni m register (n = 1, 3, 7) and the current setting of the interface. bki2sc uf0fic0 bki2cc 5 bki1sc bki1cc 3 0 2 itr1c 1 ep0wc ep0rc address 00200060h after reset 00h 0 4 6 7 bit position bit name function 7, 5 bkinsc these bits clear only the fifo on the sie side of the uf0bin register (reset the counter). 1: clear writing these bits is invalid while an in tok en for endpoint m is being processed with the bkinnk bit set to 1. the bkinnk bit is automatically cleared to 0 by clearing the fifo. make sure that the fifo on the cpu side is empty when these bits are used. 6, 4 bkincc these bits clear only the fifo on the cpu side of the uf0bin register (reset the counter). 1: clear 2 itr1c these bits clear the uf0int1 register (reset the counter). 1: clear writing these bits is invalid while an in to ken for endpoint 7 is being processed with the it1nk bit set to 1. the it1nk bit is automatically cleared to 0 by clearing the fifo. 1 ep0wc this bit clears the uf0e0w r egister (resets the counter). 1: clear writing this bit is invalid while an in tok en for endpoint0 is being processed with the ep0nkw bit set to 1. the ep0nkw bit is automatically cleared to 0 by clearing the fifo. 0 ep0rc this bit clears the uf0e0r r egister (resets the counter). 1: clear when the ep0nkr bit is set to 1 (except when it has been set by fw), the ep0nkr bit is automatically cleared to 0 by clearing the fifo. remark n = 1, 2 m = 1 and x = 7 where n = 1 m = 3 where n = 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1248 of 1817 sep 19, 2011 (30) uf0 fifo clear 1 register (uf0fic1) this register clears each fifo. this register is write-only, in 8-bit units . if this register is read, 00h is read. fw can clear the target fifo by writing 1 to the corres ponding bit of this register. the bit to which 1 has been written is automatically cleared to 0. writing 0 to the bit is invalid. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0enim register (n = 2, 4) and the current setting of the interface. 0 uf0fic1 0 5 00 3 bko2c 2 bko2cc 1 bko1c bko1cc address 00200062h after reset 00h 0 4 6 7 bit position bit name function 3, 1 bkonc these bits clear the fifos on both the sie and cpu sides of the uf0bon register (reset the counter). 1: clear when the bkonnk bit is set to 1 (except when it has been set by fw), the bkonnk bit is automatically cleared to 0 by clearing the fifo. 2, 0 bkoncc these bits clear only the fifo on the cp u side of the uf0bon register (reset the counter). 1: clear when the bkonnk bit is set to 1 (except when it has been set by fw), the bkonnk bit is automatically cleared to 0 by clearing the fifo. remark n = 1, 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1249 of 1817 sep 19, 2011 (31) uf0 data end register (uf0dend) this register reports the end of writing to the transmission system. this register can be read or written in 8-bit units. fw can start data transfer of the target endpoint by writing 1 to the correspondi ng bit of this register. the bit to which 1 has been written is automatically cleared to 0. writing 0 to the bit is invalid. the related bits are invalid if each endpoint is not supporte d by the setting of the uf0eni m register (n = 1, 3, 7) and the current setting of the interface. (1/2) bki2t uf0dend bki1t 5 00 3 it1dend 2 bki2ded 1 bki1ded e0ded address 0020006ah after reset 00h 0 4 6 7 bit position bit name function 7, 6 bkint these bits specify whether toggling the fifo is automatically executed if the fifo on the cpu side of the uf0bin register becomes full as a result of dma. 1: automatically execute a toggle operation of the fifo as soon as the fifo has become full. 0: do not automatically execute a toggle operation of the fifo even if the fifo becomes full (default value). 3 it1dend set these bits to 1 to transmit the data of t he uf0int1 register. when these bits are set to 1, the it1nk bit is set to 1 and data transfer is executed. 1: transmit a short packet. 0: do not transmit a short packet (default value). if the itr1c bit of the uf0fic0 register is set to 1 and then these bits are set to 1 (counter of uf0int1 register = 0 and the corresponding bit of the uf0eps0 register = 1), a null packet (with a data length of 0) is transmitted. if data exists in the uf0int1 register and if these bits are set to 1 (counter of uf0int1 register 0 and the corresponding bit of the uf0eps0 register = 1), a short packet is transmitted. these bits are automatically controlled by hardware when the fifo is full. remark n = 1, 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1250 of 1817 sep 19, 2011 (2/2) bit position bit name function 2, 1 bkinded set these bits to 1 when writing transmit data to the uf0bin register has been completed. when these bits are set to 1, the fifo is to ggled as soon as possible, the bkinnk bit is set to 1, and data is transferred. 1: transmit a short packet. 0: do not transmit a short packet (default value). these bits control the fifo on the cpu side. if the bkincc bit of the uf0fic0 register is set to 1 and then these bits are set to 1 (counter of uf0bin register = 0), a null packet (with a data length of 0) is transmitted. if data exists in the uf0bin register and if th ese bits are set to 1 (counter of uf0bin register 0), and if the fifo is not full, a short packet is transmitted. if the fifo on the cpu side of the uf0bin regi ster becomes full as a result of dma, with the pio or bkint bit set to 1, the hardware starts data transmission even if these bits are not set to 1. if the fifo on the cpu side of the uf0bin regi ster becomes full as a result of dma, with the bkint bit cleared to 0, be sure to set these bits to 1 (see 22.6.3 (3) uf0 epnak register (uf0en) ). 0 e0ded set this bit to 1 to transmit data of the uf0e0w register. when this bit is set to 1, the ep0nkw bit is set to 1 and data is transferred. 1: transmit a short packet. 0: do not transmit a short packet (default value). if the ep0wc bit of the uf0fic0 register is set to 1 and if this bit is set to 1 (counter of uf0e0w register = 0 and bit 1 of uf0eps0 register = 1), a null packet (with a data length of 0) is transmitted. if data exists in the uf0e0w register and if this bit is set to 1 (counter of uf0e0w register 0 and bit 1 of the uf0eps0 register = 1), and if the fifo is not full, a short packet is transmitted. remark n = 1, 2 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1251 of 1817 sep 19, 2011 (32) uf0 gpr register (uf0gpr) this register controls usbf and the usb interface. this register is write-only, in 8-bit units. if this register is read, 00h is read. be sure to clear bi ts 7 to 1 to ?0?. fw can reset the usbf by writing 1 to bit 0 of this regist er. this bit is automatically cleared to 0 after 1 has been written to it. writing 0 to this bit is invalid. 0 uf0gpr 0 5 00 3 0 2 0 1 0 mrst address 0020006eh after reset 00h 0 4 6 7 bit position bit name function 0 mrst set this bit to 1 to reset usbf. 1: reset actually, usbf is reset two usb clocks after this bit has been set to 1 by fw and the write signal has become inactive. resetting usbf by the mrst bit while the system clock is operating has the same result as resetting by the reset pin (hardware rese t) (register value back to default value). however, the uf0cs and uf0bc registers are not reset by the mrst bit. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1252 of 1817 sep 19, 2011 (33) uf0 mode control register (uf0modc) this register controls cpudec processing. this register can be read or written in 8-bit units. by setting each bit of this register, the setting of the uf0mods register can be ch anged. the bit of this register is automatically cleared to 0 only at hardware reset and when the mrst bit of the uf0grp register has been set to 1. even if the bit of this register has automatically been set to 1 by hardware, the setting by fw takes precedence. be sure to clear bits 7 and 5 to 2 to ?0?. if th ey are set to 1, the operation is not guaranteed. caution this register is provided for debugging purpo ses. usually, do not set this register except for verifying the operation or when a special mode is used. uf0modc 5 0 3 0 2 0 1 0 address 00200074h after reset 00h 0 0 4 0 6 cdc gdst 7 0 bit position bit name function 6 cdcgdst set this bit to 1 to switch the get_descriptor configuration request to cpudec processing. by setting this bit to 1, the cdcgd bit of the uf0mods register can be forcibly set to 1. 1: forcibly change the get_descriptor configuration request to cpudec processing (sets the cdcgd bit of the uf0mods register to 1). 0: automatically process the get_des criptor configuration request (default value). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1253 of 1817 sep 19, 2011 (34) uf0 mode status register (uf0mods) this register indicates the configuration status. this register is read-only, in 8-bit units. 0 uf0mods cdcgd 5 0mpack 3 dflt 2 conf 1 00 address 00200078h after reset 00h 0 4 6 7 bit position bit name function 6 cdcgd this bit specifies whether cpudec processi ng is performed for the get_descriptor configuration request. 1: forcibly change the get_descriptor configuration request to cpudec processing. 0: automatically process the get_des criptor configuration request (default value). 4 mpack this bit indicates the transmit packet size of endpoint0. 1: transmit a packet of other than 8 bytes. 0: transmit a packet of 8 bytes (default value). this bit is automatically set to 1 by hardware after the get_descriptor device request has been processed (on normal completion of the status stage). it is not cleared to 0 until the usbf has been reset (it is not cleared to 0 by bus reset). if this bit is not set to 1, the hardware transfers only the automatically-executed request in 8-byte units. therefore, even if data of more than 8 bytes is sent by the out token to be processed by fw before completion of the get_descriptor device request, the data is correctly received. this bit is ignored if the size of endpoint0 is 8 bytes. 3 dflt this bit indicates the default status (dflt bit = 1). 1: enables response. 0: disables response (always no response) (default value). this bit is automatically set to 1 by bus re set. the transaction for all the endpoints is not responded to until this bit is set to 1. 2 conf this bit indicates whether the set_configuration request has been completed. 1: set_configuration request has been completed. 0: set_configuration request has not been completed (default value). this bit is set to 1 when configuration value = 1 is received by the set_configuration request. unless this bit is set to 1, access to an endpoint other than endpoint0 is ignored. this bit is cleared to 0 when configuration value = 0 is received by the set_configuration request. it is also cleared to 0 when bus reset is detected. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1254 of 1817 sep 19, 2011 (35) uf0 active interface number register (uf0aifn) this register sets the valid interface number that co rrectly responds to the get/set_interface request. because interface 0 is always valid, interfaces 1 to 4 can be selected. this register can be read or written in 8-bit units. addif uf0aifn 0 5 00 3 0 2 0 1 ifno1 ifno0 address 00200080h after reset 00h 0 4 6 7 bit position bit name function 7 addif this bit allows use of interfaces numbered other than 0. 1: support up to the interface number specified by the ifno1 and ifno0 bits. 0: support only interface 0 (default value). setting bits 1 and 0 of this register is invalid when this bit is not set to 1. these bits specify the range of interface numbers to be supported. ifno1 ifno0 valid interface no. 1 1 0, 1, 2, 3, 4 1 0 0, 1, 2, 3 0 1 0, 1, 2 0 0 0, 1 1, 0 ifno1, ifno0 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1255 of 1817 sep 19, 2011 (36) uf0 active alternati ve setting register (uf0aas) this register specifies a link between the interface number and alternative setting. this register can be read or written in 8-bit units. usbf of the v850es/jh3-e and v850es/jj3-e can set a five -series alternative setting (alternate setting 0, 1, 2, 3, and 4 can be defined) and a two-series alternative se tting (alternative setting 0 and 1 can be defined) for one interface. alt2 uf0aas ifal21 5 ifal20 alt2en 3 alt5 2 ifal51 1 ifal50 alt5en address 00200082h after reset 00h 0 4 6 7 bit position bit name function 7, 3 altn these bits specify whether an n-series alternative setting is linked with interface 0. when these bits are set to 1, the setting of the ifaln1 and ifaln0 bits is invalid. 1: link n-series alternative setting with interface 0. 0: do not link n-series alternative setting with interface 0 (default value). these bits specify the interface number to be linked with the n-series alternative setting. if the linked interface number is outside the range specified by the uf0aifn register, the n-series alternative setting is invalid (altnen bit = 0). ifaln1 ifaln0 interface number to be linked 1 1 links interface 4. 1 0 links interface 3. 0 1 links interface 2. 0 0 links interface 1. 6, 5, 2, 1 ifaln1, ifaln0 do not link a five-series alternative setting and a two-series alternative setting with the same interface number. 4, 0 altnen these bits validate the n-series alternative setting. unless these bits are set to 1, the setting of the altn, ifaln1, and ifaln0 bits is invalid. 1: validate the n-series alternative setting. 0: do not validate the n-series alternative setting (default value). remark n = 2, 5 for example, when the uf0aifn register is set to 82h and t he uf0aas register is set to 15h, interfaces 0, 1, 2, and 3 are valid. interfaces 0 and 2 support only alternative setting 0. interface 1 supports alternative setting 0 and 1, and interface 3 supports alternative setting 0, 1, 2, 3, and 4. with this setting, requests get_interface windex = 0/1/2/3, set_interface wv alue = 0 & windex = 0/2, set_inter face wvalue = 0/1 & windex = 1, and set_interface wvalue = 0/ 1/2/3/4 & windex = 3 are automatically responded to, and a stall response is made to the other get/set_interface requests. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1256 of 1817 sep 19, 2011 (37) uf0 alternative setting status register (uf0ass) this register indicates the current status of the alternative setting. this register is read-only, in 8-bit units. check this register when the set_int interrupt re quest has been issued. the value received by the set_interface request is reflected on the uf0ifn r egister (n = 0 to 4) as well as on this register. 0 uf0ass 0 5 00 3 al5st3 2 al5st2 1 al5st1 al2st address 00200084h after reset 00h 0 4 6 7 bit position bit name function these bits indicate the current status of the five-series alternative setting. al5st3 al5st2 al5st1 selected alternative setting number 1 0 0 alternative setting 4 0 1 1 alternative setting 3 0 1 0 alternative setting 2 0 0 1 alternative setting 1 0 0 0 alternative setting 0 3 to 1 al5st3 to al5st1 0 al2st this bit indicates the current status of the two-series alternative setting (selected alternative setting number). 1: alternative setting 1 0: alternative setting 0 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1257 of 1817 sep 19, 2011 (38) uf0 endpoint 1 interface mapping register (uf0e1im) this register specifies for which interface and alternative setting endpoint1 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setting selected by the set_i nterface request indicate whether endpoint1 is currently valid, and the hardware determines how the get_status/clear_feature/set_feat ure endpoint1 request and the in transaction to endpoint1 are responded to, and whether the related bits are valid or invalid. e1en2 uf0e1im e1en1 5 e1en0 e12al1 3 e15al4 2 e15al3 1 e15al2 e15al1 address 00200086h after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint1 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e1en2 e1en1 e1en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e1en2 to e1en0 when these bits are set to 110 or 111, they ar e invalid even if the e12al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint1 is valid. 4 e12al1 this bit validates endpoint1 when the two-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e15al4 to e15al1 bits are 0000. 3 to 0 e15aln these bits validate endpoint1 when the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1258 of 1817 sep 19, 2011 (39) uf0 endpoint 2 interface mapping register (uf0e2im) this register specifies for which interface and alternative setting endpoint2 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setting selected by the set_i nterface request indicate whether endpoint2 is currently valid, and the hardware determines how the get_status/clear_feature/set_feature endpoint2 request and the out transaction to endpoint2 are responded to, and whether the related bits are valid or invalid. e2en2 uf0e2im e2en1 5 e2en0 e22al1 3 e25al4 2 e25al3 1 e25al2 e25al1 address 00200088h after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint2 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e2en2 e2en1 e2en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e2en2 to e2en0 when these bits are set to 110 or 111, they ar e invalid even if the e22al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint2 is valid. 4 e22al1 this bit validates endpoint2 when the two-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e25al4 to e25al1 bits are 0000. 3 to 0 e25aln these bits validate endpoint2 when the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1259 of 1817 sep 19, 2011 (40) uf0 endpoint 3 interface mapping register (uf0e3im) this register specifies for which interface and alternative setting endpoint3 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setting selected by the set_i nterface request indicate whether endpoint3 is currently valid, and the hardware determines how the get_status/clear_feature/set_feat ure endpoint3 request and the in transaction to endpoint3 are responded to, and whether the related bits are valid or invalid. e3en2 uf0e3im e3en1 5 e3en0 e32al1 3 e35al4 2 e35al3 1 e35al2 e35al1 address 0020008ah after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint3 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e3en2 e3en1 e3en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e3en2 to e3en0 when these bits are set to 110 or 111, they ar e invalid even if the e32al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint3 is valid. 4 e32al1 this bit validates endpoint3 when the two-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e35al4 to e35al1 bits are 0000. 3 to 0 e35aln these bits validate endpoint3 when the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1260 of 1817 sep 19, 2011 (41) uf0 endpoint 4 interface mapping register (uf0e4im) this register specifies for which interface and alternative setting endpoint4 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setting selected by the set_i nterface request indicate whether endpoint4 is currently valid, and the hardware determines how the get_status/clear_feature/set_feature endpoint4 request and the out transaction to endpoint4 are responded to, and whether the related bits are valid or invalid. e4en2 uf0e4im e4en1 5 e4en0 e42al1 3 e45al4 2 e45al3 1 e45al2 e45al1 address 0020008ch after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint4 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e4en2 e4en1 e4en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e4en2 to e4en0 when these bits are set to 110 or 111, they ar e invalid even if the e42al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint4 is valid. 4 e42al1 this bit validates endpoint4 when the two-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e45al4 to e45al1 bits are 0000. 3 to 0 e45aln these bits validate endpoint4 when the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1261 of 1817 sep 19, 2011 (42) uf0 endpoint 7 interface mapping register (uf0e7im) this register specifies for which interface and alternative setting endpoint7 is valid. this register can be read or written in 8-bit units. the setting of this register and the alternative setting selected by the set_i nterface request indicate whether endpoint7 is currently valid, and the hardware determines how the get_status/clear_feature/set_feat ure endpoint7 request and the in transaction to endpoint7 are responded to, and whether the related bits are valid or invalid. e7en2 uf0e7im e7en1 5 e7en0 e72al1 3 e75al4 2 e75al3 1 e75al2 e75al1 address 00200092h after reset 00h 0 4 6 7 bit position bit name function these bits set a link between the interface of endpoint7 and the two-/five-series alternative setting. the endpoint is linked with alternative setting 0. the endpoint linked with alternative setting 0 cannot be excluded from alternative setting 1 to 4. e7en2 e7en1 e7en0 link status 1 1 1 1 1 0 not linked with interface 1 0 1 linked with interface 4 and alternative setting 0 1 0 0 linked with interface 3 and alternative setting 0 0 1 1 linked with interface 2 and alternative setting 0 0 1 0 linked with interface 1 and alternative setting 0 0 0 1 linked with interface 0 and alternative setting 0 0 0 0 not linked with interface (default value) 7 to 5 e7en2 to e7en0 when these bits are set to 110 or 111, they ar e invalid even if the e72al1 bit is cleared to 0. if the endpoint is linked, setting of the conf bi t of the uf0mods register to 1 indicates that endpoint7 is valid. 4 e72al1 this bit validates endpoint7 when the two-series alternative setting and the alternative setting of the linked interface are set to 1. 1: validate the endpoint when alternative setting 1 is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting 1 is set with conf bit = 1 (default value). this bit is valid when the e75al4 to e75al1 bits are 0000. 3 to 0 e75aln these bits validate endpoint7 when the five-series alternative setting and the alternative setting of the linked interface are set to n. 1: validate the endpoint when alternative setting n is set with conf bit = 1. 0: do not validate the endpoint even when alternative setting n is set with conf bit = 1 (default value). remark n = 1 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1262 of 1817 sep 19, 2011 22.6.4 data hold registers (1) uf0 ep0 read register (uf0e0r) the uf0e0r register is a 64-byte fifo that stores the out data sent from the host in the data stage of control transfer to/from endpoint0. this register is read-only, in 8-bit units. a write access to this register is ignored. the hardware automatically trans fers data to the uf0e0r register when it has received the data from the host. when the data has been correctly received, the e0odt bit of t he uf0is1 register is set to 1. the uf0e0l register holds the quantity of the received data, and an interrupt request (intusbf0) is issu ed. the uf0e0l register always updates the length of the received data while it is re ceiving data. if the final trans fer is correct reception, the interrupt request is generated. if the reception is abnorma l, the uf0e0l register is cleared to 0 and the interrupt request is not generated. the data held by the uf0e0r register must be read by fw up to the va lue of the amount of data read by the uf0e0l register. check that all dat a has been read by using the ep0r bit of the uf0eps0 register (ep0r bit = 0 when all data has been read). if the value of the uf0e0l r egister is 0, the ep0nkr bit of the uf0e0n register is cleared to 0, and the uf0e0r register is ready for reception. the uf0e0r register is cleared when the next setup token has been received. caution read all the data stored. clear the fifo to discard some data. e0r7 uf0e0r e0r6 5 e0r5 e0r4 3 e0r3 2 e0r2 1 e0r1 e0r0 address 00200100h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 e0r7 to e0r0 these bits store the out data sent from the host in the data stage of control transfer to/from endpoint0. the operation of the uf0e0r r egister is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1263 of 1817 sep 19, 2011 figure 22-4. operation of uf0e0r register status of uf0e0r register normal completion of reception normal completion of reception abnormal reception fifo hard- ware clear ep0nkr bit of uf0e0n register ep0r bit of uf0eps0 register e0odt bit of uf0is1 register hardware clear hardware clear hardware clear reading fifo starts reading fifo completed (2) uf0 ep0 length register (uf0e0l) the uf0e0l register stor es the data length held by the uf0e0r register. this register is read-only, in 8-bit units. a write access to this register is ignored. the uf0e0l register always updat es the length of the received data while it is receiving data. if the final transfer is abnormal reception, the uf0e0l register is cleared to 0 and the interrupt request is not generated. the interrupt request is generated only when the reception is norma l, and the fw can read as many data from the uf0e0r register as the value read from the uf 0e0l register. the value of the uf0e 0l register is decremented each time the uf0e0r register has been read. e0l7 uf0e0l e0l6 5 e0l5 e0l4 3 e0l3 2 e0l2 1 e0l1 e0l0 address 00200102h after reset 00h 0 4 6 7 bit position bit name function 7 to 0 e0l7 to e0l0 these bits store the data length held by the uf0e0r register. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1264 of 1817 sep 19, 2011 (3) uf0 ep0 setup register (uf0e0st) the uf0e0st register holds the setup data sent from the host. this register is read-only, in 8-bit units. a write access to this register is ignored. the uf0e0st register always writes data when a setup transaction has been received. the hardware sets the prot bit of the uf0is1 register when it has correctly received the setup transaction. it sets the cpudec bit of the uf0is1 register in the case of an fw-processed request. then an interrupt request (intusbf0) is issued. in the case of an fw-processed request, be sure to read the reques t in 8-byte units. if it is not read in 8-byte units, the subsequent requests cannot be correctly decoded. t he read counter of the uf0e0s t register is not cleared even when bus reset is received. always read this counter in 8-byte units regardless of whether bus reset is received or not. because the uf0e0st register always en ables writing, the hardwar e overwrites data to this register even if a setup transaction is received while the data of the regist er is being read. even if the setup transaction cannot be correctly received, the cpudec interrupt request and protect interrupt request are not generated, but the previous data is discarded. if a setup token of less than 8 bytes is received, however, the received setup token is discarded, and the previously received setup data is re tained. if the setup token is received more than once when control transfer is executed once, be sure to check the prot bit of the uf0is1 register under the conditions below. if prot bit = 1, read the uf0e0st register again because the setup transaction has been received more than once. <1> if a request is decoded by fw and the uf0e0r regi ster is read or the uf0e0w register is written <2> when preparing for a stall response for the request to which the decode result does not correspond caution be sure to read all the stored data. the uf 0e0st register is always updated by the request in the setup transaction. e0s7 uf0e0st e0s6 5 e0s5 e0s4 3 e0s3 2 e0s2 1 e0s1 e0s0 address 00200104h after reset 00h 0 4 6 7 bit position bit name function 7 to 0 e0s7 to e0s0 these bits hold the setup data sent from the host. the operation of the uf0e0st r egister is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1265 of 1817 sep 19, 2011 figure 22-5. operation of uf0e0st register (a) normal status of uf0e0st register completion of normal reception of setup token completion of normal reception of setup token cpudec bit of uf0is1 register prot bit of uf0is1 register hardware clear fw processing int clear (fw clear) completion of decoding request completion of reading fifo completion of decoding request start of reading fifo int clear (fw clear) hardware processing (b) when setup transaction is received more than once status of uf0e0st register completion of normal reception of setup token start of reception of second setup token completion of normal reception of second setup token cpudec bit of uf0is1 register prot bit of uf0is1 register hardware clear int clear (fw clear) int clear (fw clear) completion of decoding request completion of decoding request completion of reading fifo hardware clear on completion of reading 8 bytes v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1266 of 1817 sep 19, 2011 (4) uf0 ep0 write register (uf0e0w) the uf0e0w register is a 64-byte fifo t hat stores the in data (passes it to si e) sent to the host in the data stage to endpoint0. this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchroniza tion with an in token only when the ep0nkw bit of the uf0e0n register is set to 1 (when nak is not transmitt ed). when data is transmitted and when the host correctly receives the data, the ep0nkw bit of the uf0e0n register is automatically cleared to 0 by hardware. a short packet is transmitted when data is written to the uf0e0w register and the e0ded bit of the uf0dend register is set to 1 (ep0w bit of the uf0eps0 register = 1 (data exists)). a null packet is transmitted when the uf0e0w register is cleared and the e0ded bit of the uf0dend register is set to 1 ( ep0w bit of the uf0eps0 register = 1 (data exists)). the uf0e0w register is cleared to 0 when the next setup token is received while transmission has not been completed yet. if the stage of control transfer (read) cha nges to the status stage while ack has not been correctly received in the data stage, the uf0e0w regist er is automatically cleared to 0. at the same time, it is also cleared to 0 if the ep0nkw bit of the uf0e0n register is 1. if the uf0e0w register is read while no data is in it, 00h is read. e0w7 uf0e0w e0w6 5 e0w5 e0w4 3 e0w3 2 e0w2 1 e0w1 e0w0 address 00200106h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 e0w7 to e0w0 these bits store the in data sent to the host in the data stage to endpoint0. the operation of the uf0e0w r egister is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1267 of 1817 sep 19, 2011 figure 22-6. operation of uf0e0w register (a) 16-byte transmission status of uf0e0w register trans- mission starts trans- mission completed ack reception trans- mission starts trans- mission completed re- trans- mission starts ack reception ack cannot be received ep0nkw bit of uf0e0n register ep0w bit of uf0eps0 register e0indt bit of uf0is1 register fifo full hardware clear hardware clear hardware clear fifo full 16-byte transfer 16-byte transfer re-transfer int clear (fw clear) writing fifo starts writing fifo completed writing fifo starts writing fifo completed counter reloaded (b) when null packet or s hort packet is transmitted status of uf0e0w register transmission starts trans- mission completed ack reception transmission starts trans- mission completed ack reception ep0nkw bit of uf0e0n register ep0w bit of uf0eps0 register e0indt bit of uf0is1 register hardware clear e0ded bit of uf0dend register is set. e0ded bit of uf0dend register is set. hardware clear hardware clear short packet transfer transfer of null packet int clear (fw clear) writing fifo starts writing fifo completed fifo fw clear v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1268 of 1817 sep 19, 2011 (5) uf0 bulk-out 1 register (uf0bo1) the uf0bo1 register is a 64-byte 2 fifo that stores data for endpoint2. this register consists of two banks of 64-byte fifos each of which performs a toggle operation and repeatedly c onnects the buses on the sie and cpu sides. the toggle operation takes place when data is in the fifo on the sie side and w hen no data is in the fifo on the cpu side (counter value = 0). this register is read-only, in 8-bit units. a write access to this register is ignored. when the hardware receives data for endp oint2 from the host, it automatically transfers the data to the uf0bo1 register. when the register correctly receives the data, a fifo toggle operati on occurs. as a result, the bko1dt bit of the uf0is3 register is set to 1, the quantity of the received data is held by the uf0bo1l register, and an interrupt request or dma request is issued to the cpu. whether the interrupt request or dma request is issued can be selected by using the dqbo1m s bit of the uf0idr register. read the data held by the uf0bo1 register by fw, up to the value of the amount of data read by the uf0bo1l register. when the correct received data is held by t he fifo connected to the sie side and the value of the uf0bo1l register reaches 0, the toggle operation of the fifo occurs, and t he bko1nk bit of the uf0en register is automatically cleared to 0. if data greater than the val ue of the uf0bo1l register is read and if the fifo toggle condition is satisfied, the toggle operation of the fifo occu rs. as a result, the next packet may be read by mistake. note that, if the toggle condition is not sa tisfied, the first data is repeatedly read. if overrun data is received while data is held by the fi fo connected to the cpu side, endpoint2 stalls, and the fifo on the cpu side is cleared. when the uf0bo1 register is read while no data is in it, an undefined value is read. caution be sure to read all the data stored in this register. bko17 uf0bo1 bko16 5 bko15 bko14 3 bko13 2 bko12 1 bko11 bko10 address 00200108h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 bko17 to bko10 these bits store data for endpoint2. the operation of the uf0bo1 r egister is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1269 of 1817 sep 19, 2011 figure 22-7. operation of uf0bo1 register (1/2) (a) operation example 1 sie side cpu side status of uf0bo1 register reception completed fifo toggle fifo toggle ack transmission reception starts reception completed ack transmission bko1nk bit of uf0en register bko1fl bit of uf0is3 register bkout1 bit of uf0eps0 register bko1dt bit of uf0is3 register transfer of data less than 64 bytes 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 reading fifo starts reading fifo completed reading fifo starts reading fifo completed f w clear fifo_0 fifo_1 hardware clear hardware clear hardware clear v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1270 of 1817 sep 19, 2011 figure 22-7. operation of uf0bo1 register (2/2) (b) operation example 2 sie side cpu side status of uf0bo1 register reception completed reception starts null reception completed null reception completed fifo toggle fifo toggle ack transmission reception starts reception completed ack transmission bko1nl bit of uf0is3 register bkout1 bit of uf0eps0 register bko1dt bit of uf0is3 register transfer of data less than 64 bytes 0-byte transfer 0-byte transfer 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 reading fifo starts reading fifo completed fw clear fw clear fifo_0 fifo_1 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1271 of 1817 sep 19, 2011 (6) uf0 bulk-out 1 length register (uf0bo1l) the uf0bo1l register stores the length of the data held by the uf0bo1 register. this register is read-only, in 8-bit units. a write access to this register is ignored. the uf0bo1l register always updates t he received data length while it is receiving data. if the final transfer is abnormal reception, the uf0bo 1l register is cleared to 00h, and an interrupt request is not generated. only if the reception is normal, the interrupt req uest is generated, and fw can read as much data from the uf0bo1 register as the value read from the uf0bo1l register. the value of the uf0bo1l register is decremented each time the uf0bo1 register has been read. bko1l7 uf0bo1l bko1l6 5 bko1l5 bko1l4 3 bko1l3 2 bko1l2 1 bko1l1 bko1l0 address 0020010ah after reset 00h 0 4 6 7 bit position bit name function 7 to 0 bko1l7 to bko1l0 these bits store the length of the data held by the uf0bo1 register. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1272 of 1817 sep 19, 2011 (7) uf0 bulk-out 2 register (uf0bo2) the uf0bo2 register is a 64-byte 2 fifo that stores data for endpoint4. this register consists of two banks of 64-byte fifos each of which performs a toggle operation and repeatedly c onnects the buses on the sie and cpu sides. the toggle operation takes place when data is in the fifo on the sie side and w hen no data is in the fifo on the cpu side (counter value = 0). this register is read-only, in 8-bit units. a write access to this register is ignored. when the hardware receives data for endp oint4 from the host, it automatically transfers the data to the uf0bo2 register. when the register correctly receives the data, a fifo toggle operati on occurs. as a result, the bko2dt bit of the uf0is3 register is set to 1, the quantity of the received data is held by the uf0bo2l register, and an interrupt request or dma request is issued to the cpu. whether the interrupt request or dma request is issued can be selected by using the dqbo2m s bit of the uf0idr register. read the data held by the uf0bo2 register by fw, up to the value of the amount of data read by the uf0bo2l register. when the correct received data is held by t he fifo connected to the sie side and the value of the uf0bo2l register reaches 0, the toggle operation of the fifo occurs, and t he bko2nk bit of the uf0en register is automatically cleared to 0. if data greater than the val ue of the uf0bo2l register is read and if the fifo toggle condition is satisfied, the toggle operation of the fifo occu rs. as a result, the next packet may be read by mistake. note that, if the toggle condition is not sa tisfied, the first data is repeatedly read. if overrun data is received while data is held by the fi fo connected to the cpu side, endpoint4 stalls, and the fifo on the cpu side is cleared. when the uf0bo2 register is read while no data is in it, an undefined value is read. caution be sure to read all the data stored in this register. bko27 uf0bo2 bko26 5 bko25 bko24 3 bko23 2 bko22 1 bko21 bko20 address 0020010ch after reset undefined 0 4 6 7 bit position bit name function 7 to 0 bko27 to bko20 these bits store data for endpoint4. the operation of the uf0bo2 r egister is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1273 of 1817 sep 19, 2011 figure 22-8. operation of uf0bo2 register (1/2) (a) operation example 1 sie side cpu side status of uf0bo2 register reception completed fifo toggle fifo toggle ack transmission reception starts reception completed ack transmission bko2nk bit of uf0en register bko2fl bit of uf0is3 register bkout2 bit of uf0eps0 register bko2dt bit of uf0is3 register 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 reading fifo starts reading fifo completed reading fifo starts reading fifo completed f w clear fifo_0 fifo_1 transfer of data less than 64 bytes hardware clear hardware clear hardware clear v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1274 of 1817 sep 19, 2011 figure 22-8. operation of uf0bo2 register (2/2) (b) operation example 2 sie side cpu side status of uf0bo2 register reception completed reception starts null reception completed null reception completed fifo toggle fifo toggle ack transmission reception starts reception completed ack transmission bko2nl bit of uf0is3 register bkout2 bit of uf0eps0 register bko2dt bit of uf0is3 register transfer of data less than 64 bytes 0-byte transfer 0-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 reading fifo starts reading fifo completed f w clear f w clear fifo_0 fifo_1 64-byte transfer v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1275 of 1817 sep 19, 2011 (8) uf0 bulk-out 2 length register (uf0bo2l) the uf0bo2l register stores the length of the data held by the uf0bo2 register. this register is read-only, in 8-bit units. a write access to this register is ignored. the uf0bo2l register always updates t he received data length while it is receiving data. if the final transfer is abnormal reception, the uf0bo 2l register is cleared to 00h, and an interrupt request is not generated. only if the reception is normal, the interrupt req uest is generated, and fw can read as much data from the uf0bo2 register as the value read from the uf0bo2l register. the value of the uf0bo2l register is decremented each time the uf0bo2 register has been read. bko2l7 uf0bo2l bko2l6 5 bko2l5 bko2l4 3 bko2l3 2 bko2l2 1 bko2l1 bko2l0 address 0020010eh after reset 00h 0 4 6 7 bit position bit name function 7 to 0 bko2l7 to bko2l0 these bits store the length of the data held by the uf0bo2 register. (9) uf0 bulk-in 1 register (uf0bi1) the uf0bi1 register is a 64-byte 2 fifo that stores data for endpoint1. this register consists of two banks of 64- byte fifos each of which performs a toggle operation and repeatedly c onnects the buses on the sie and cpu sides. the toggle operation takes place when no data is in the fifo on the sie side (counter value = 0) and when the fifo on the cpu side is correctly written (fifo full or bki1ded bit = 1). this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchro nization with the in token for endpoint1 only when the bki1nk bit of the uf0en register is set to 1 (when nak is not transmitted). the address at which data is to be written or read is managed by the hardware. therefore, fw can transmit data to the host only by writing the data to the uf0bi1 register sequentially. a s hort packet is transmitted when data is wr itten to the uf0bi1 register and the bki1ded bit of the uf0dend register is set to 1 (bkin1 bit of uf0eps0 register = 1 (data exists)). a null packet is transmitted when the uf0bi1 register is cleared and t he bki1ded bit of the uf0dend register is set to 1 (bkin1 bit of the uf0eps0 register = 1 (data exists)). when the data is transmitted correctly, a fifo toggle operation occurs. the bki1dt bit of the uf0is2 register is set to 1, and an interrupt request is generated for the cpu. an interrupt request or dma request can be select ed by using the dqbi1ms bi t of the uf0idr register. bki17 uf0bi1 bki16 5 bki15 bki14 3 bki13 2 bki12 1 bki11 bki10 address 00200110h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 bki17 to bki10 these bits store data for endpoint1. the operation of the uf0bi1 regi ster is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1276 of 1817 sep 19, 2011 figure 22-9. operation of uf0bi1 register (1/3) (a) operation example 1 sie side cpu side status of uf0bi1 register transmission completed fifo toggle fifo toggle ack reception transmission starts transmission completed ack reception bki1nk bit of uf0en register 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 writing fifo starts writing fifo completed writing fifo starts writing fifo completed bki1dt bit of uf0is2 register hardware clear int clear (fw clear) bki1ded bit of uf0dend register is set or hardware set bki1ded bit of uf0dend register is set or hardware set fifo_0 fifo_1 64-byte transfer v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1277 of 1817 sep 19, 2011 figure 22-9. operation of uf0bi1 register (2/3) (b) operation example 2 sie side cpu side status of uf0bi1 register transmission completed fifo toggle ack reception transmission starts transmission completed ack reception re- transmission starts ack cannot be received bki1nk bit of uf0en register 64-byte transfer re-transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 writing fifo starts writing fifo completed writing fifo starts writing fifo completed bki1dt bit of uf0is2 register hardware clear int clear (fw clear) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1278 of 1817 sep 19, 2011 figure 22-9. operation of uf0bi1 register (3/3) (c) operation example 3 sie side cpu side status of uf0bi1 register transmission completed fifo toggle fifo toggle ack reception transmission starts transmission completed ack reception bki1nk bit of uf0en register transfer of null packet short packet transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 fifo clear writing fifo starts writing fifo completed bki1dt bit of uf0is2 register hardware clear int clear (fw clear) bki1ded bit of uf0dend register is set. bki1ded bit of uf0dend register is set. fifo_0 fifo_1 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1279 of 1817 sep 19, 2011 (10) uf0 bulk-in 2 register (uf0bi2) the uf0bi2 register is a 64-byte 2 fifo that stores data for endpoint3. this register consists of two banks of 64-byte fifos each of which performs a toggle operati on and repeatedly connects the buses on the sie and cpu sides. the toggle operation takes place when no data is in the fifo on the sie side (counter value = 0) and when the fifo on the cpu side is correctly written (fifo full or bki2ded bit = 1). this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchroni zation with the in token for endpoint3 only when the bki2nk bit of the uf0en register is set to 1 (when nak is not transmitted). the address at which data is to be written or read is managed by the hardw are. therefore, fw can transmit dat a to the host only by writing the data to the uf0bi2 register sequentially. a short packet is tran smitted when data is written to the uf0bi2 register and the bki2ded bit of the uf0de nd register is set to 1 (bkin2 bit of uf 0eps0 register = 1 (data exists)). a null packet is transmitted when the uf0bi2 register is cleared a nd the bki2ded bit of the uf0dend register is set to 1 (bkin2 bit of the uf0eps0 register = 1 (data exists)). when the data is transmitted correctly, a fifo toggle operation occurs. the bki2dt bit of the uf0is2 register is set to 1, and an interrupt request is generated for the cpu. an interrupt request or dma request can be select ed by using the dqbi2ms bi t of the uf0idr register. bki27 uf0bi2 bki26 5 bki25 bki24 3 bki23 2 bki22 1 bki21 bki20 address 00200112h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 bki27 to bki20 these bits store data for endpoint3. the operation of the uf0bi2 regi ster is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1280 of 1817 sep 19, 2011 figure 22-10. operation of uf0bi2 register (1/3) (a) operation example 1 sie side cpu side status of uf0bi2 register transmission completed fifo toggle fifo toggle ack reception transmission starts transmission completed ack reception bki2nk bit of uf0en register 64-byte transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 writing fifo starts writing fifo completed writing fifo starts writing fifo completed bki2dt bit of uf0is2 register hardware clear int clear (fw clear) bki2ded bit of uf0dend register is set or hardware set. bki2ded bit of uf0dend register is set or hardware set. fifo_0 fifo_1 64-byte transfer v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1281 of 1817 sep 19, 2011 figure 22-10. operation of uf0bi2 register (2/3) (b) operation example 2 sie side cpu side status of uf0bi2 register transmission completed fifo toggle ack reception transmission starts transmission completed ack reception re- transmission starts ack cannot be received bki2nk bit of uf0en register 64-byte transfer re-transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 writing fifo starts writing fifo completed writing fifo starts writing fifo completed bki2dt bit of uf0is2 register hardware clear int clear (fw clear) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1282 of 1817 sep 19, 2011 figure 22-10. operation of uf0bi2 register (3/3) (c) operation example 3 sie side cpu side status of uf0bi2 register transmission completed fifo toggle fifo toggle ack reception transmission starts transmission completed ack reception bki2nk bit of uf0en register short packet transfer 64-byte transfer fifo_0 fifo_1 fifo_1 fifo_0 fifo clear writing fifo starts writing fifo completed bki2dt bit of uf0is2 register hardware clear int clear (fw clear) bki2ded bit of uf0dend register is set. bki2ded bit of uf0dend register is set. fifo_0 fifo_1 transfer of null packet v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1283 of 1817 sep 19, 2011 (11) uf0 interrupt 1 register (uf0int1) the uf0int1 register is an 8-by te fifo that stores data for e ndpoint7 (to be passed to sie). this register is write-only, in 8-bit units. when this register is read, 00h is read. the hardware transmits data to the usb bus in synchroni zation with the in token for endpoint7 only when the it1nk bit of the uf0en register is set to 1 (when nak is not transmitted). when the data is transmitted and the host correctly receives it, the it1nk bit of the uf0en regi ster is automatically cleared to 0 by hardware. a short packet is transmitted when data is written to the uf0int 1 register and the it1dend bi t of the uf0dend register is set to 1 (it1 bit of the uf0eps0 register = 1 (dat a exists)). a null packet is transmitted when the uf0int1 register is cleared and the it1dend bit of the uf0dend register is set to 1 (it1 bit of the uf0eps0 register = 1 (data exists)). it17 uf0int1 it16 5 it15 it14 3 it13 2 it12 1 it11 it10 address 00200114h after reset undefined 0 4 6 7 bit position bit name function 7 to 0 it17 to it10 these bits store data for endpoint7. the operation of the uf 0int1 register is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1284 of 1817 sep 19, 2011 figure 22-11. operation of uf0int1 register (a) 8-byte transfer status of uf0int1 register transmission starts transmission completed ack reception transmission starts transmission completed re-transmission starts ack reception ack cannot be received it1nk bit of uf0en register it1 bit of uf0eps0 register it1dt bit of uf0is2 register fifo full hardware clear fifo full 8-byte transfer 8-byte transfer re-transfer int clear (fw clear) writing fifo starts writing fifo completed writing fifo starts writing fifo completed counter reloaded (b) when null packet or s hort packet is transmitted status of uf0int1 register transmission starts transmission completed ack reception transmission starts transmission completed ack reception it1nk bit of uf0en register it1 bit of uf0eps0 register it1dt bit of uf0is2 register hardware clear it1dend bit of uf0dend register is set. it1dend bit of uf0dend register is set. short packet transfer transfer of null packet int clear (fw clear) writing fifo starts writing fifo completed fifo fw clear v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1285 of 1817 sep 19, 2011 22.6.5 epc request data registers (1) uf0 device status register l (uf0dstl) this register stores the value that is to be retu rned in response to the get_status device request. this register can be read or written in 8-bit units. the hardware automatically transmits the contents of this register to the host when it has received the get_status device request. caution to rewrite this register, set the ep0nka bit to 1 before reading the register contents, and rewrite the register contents after conf irming that the bit has been set, in order to prevent conflict between a read access and a write access. 0 uf0dstl 0 5 00 3 0 2 0 1 rmwk sfpw address 00200144h after reset 00h 0 4 6 7 bit position bit name function 1 rmwk this bit specifies whether the remote wakeup function of the device is used. 1: enabled 0: disabled if the device supports a remote wakeup function, this bit is set to 1 by hardware when the set_feature device request has been received, and is cleared to 0 by hardware when the clear_feature device request has been received. if the device does not support a remote wakeup function, make sure that the set_feature device request is not issued from the host. 0 sfpw this bit indicates whether the device is self-powered or bus-powered. 1: self-powered 0: bus-powered v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1286 of 1817 sep 19, 2011 (2) uf0 ep0 status register l (uf0e0sl) this register stores the value that is to be retur ned in response to the get_status endpoint0 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in usbf, the e0halt bit is set to 1 by fw . a write access to this register is ignored while a usb- side access to endpoint0 is being received. when the e0halt bit is set to 1 by fw, it is not reflec ted until the next setup token is received if the control transfer immediately before is for the set_feature endpoint0, clear_feature endpoint0, get_status endpoint0 request, or an fw-processed request. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint0 request. if endpoint0 has stal led, the uf0e0w and uf0e0r registers are cleared, and the ep0nkw and ep0nkr bits of the uf 0e0n register are cleared to 0. caution to rewrite this register, set the ep0nka bit to 1 before reading the register contents, and rewrite the register contents after conf irming that the bit has been set, in order to prevent conflict between a read access and a write access. 0 uf0e0sl 0 5 00 3 0 2 0 1 0 e0halt address 0020014ch after reset 00h 0 4 6 7 bit position bit name function 0 e0halt this bit indicates the status of endpoint0. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint0 request has been received, and cleared to 0 by hardware when the clear_feature endpoint0 request has been received. data pid is initialized to data0. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1287 of 1817 sep 19, 2011 (3) uf0 ep1 status register l (uf0e1sl) this register stores the value that is to be retur ned in response to the get_status endpoint1 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint1, the e1halt bit is set to 1. a write access to this register is ignored while a usb- side access to endpoint1 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint1 request. if endpoint1 has stalled, the uf0bi1 register is cleared and the bki1nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint1, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bit to 1 before reading the register contents, and rewrite the register contents after conf irming that the bit has been set, in order to prevent conflict between a read access and a write access. 0 uf0e1sl 0 5 00 3 0 2 0 1 0 e1halt address 00200150h after reset 00h 0 4 6 7 bit position bit name function 0 e1halt this bit indicates the status of endpoint1. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint1 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint1 request, set_configuration request, or the set_interface request for the interface to which endpoint1 is linked has correctly been rece ived. data pid is initialized to data0. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1288 of 1817 sep 19, 2011 (4) uf0 ep2 status register l (uf0e2sl) this register stores the value that is to be retur ned in response to the get_status endpoint2 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint2, the e2halt bit is set to 1. a write access to this register is ignored while a usb- side access to endpoint2 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint2 request. if endpoint2 has stalled, the uf0bo1 register is cleared and the bko1nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint2, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bit to 1 before reading the register contents, and rewrite the register contents after conf irming that the bit has been set, in order to prevent conflict between a read access and a write access. 0 uf0e2sl 0 5 00 3 0 2 0 1 0 e2halt address 00200154h after reset 00h 0 4 6 7 bit position bit name function 0 e2halt this bit indicates the status of endpoint2. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint2 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint2 request, set_configuration request, or the set_interface request for the interface to which endpoint2 is linked has correctly been rece ived. data pid is initialized to data0. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1289 of 1817 sep 19, 2011 (5) uf0 ep3 status register l (uf0e3sl) this register stores the value that is to be retur ned in response to the get_status endpoint3 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint3, the e3halt bit is set to 1. a write access to this register is ignored while a usb- side access to endpoint3 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint3 request. if endpoint3 has stalled, the uf0bi2 register is cleared and the bki2nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint3, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bit to 1 before reading the register contents, and rewrite the register contents after conf irming that the bit has been set, in order to prevent conflict between a read access and a write access. 0 uf0e3sl 0 5 00 3 0 2 0 1 0 e3halt address 00200158h after reset 00h 0 4 6 7 bit position bit name function 0 e3halt this bit indicates the status of endpoint3. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint3 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint3 request, set_configuration request, or the set_interface request for the interface to which endpoint3 is linked has correctly been rece ived. data pid is initialized to data0. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1290 of 1817 sep 19, 2011 (6) uf0 ep4 status register l (uf0e4sl) this register stores the value that is to be retur ned in response to the get_status endpoint4 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint4, the e4halt bit is set to 1. a write access to this register is ignored while a usb- side access to endpoint4 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint4 request. if endpoint4 has stalled, the uf0bo2 register is cleared and the bko2nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint4, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bit to 1 before reading the register contents, and rewrite the register contents after conf irming that the bit has been set, in order to prevent conflict between a read access and a write access. 0 uf0e4sl 0 5 00 3 0 2 0 1 0 e4halt address 0020015ch after reset 00h 0 4 6 7 bit position bit name function 0 e4halt this bit indicates the status of endpoint4. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint4 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint4 request, set_configuration request, or the set_interface request for the interface to which endpoint4 is linked has correctly been rece ived. data pid is initialized to data0. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1291 of 1817 sep 19, 2011 (7) uf0 ep7 status register l (uf0e7sl) this register stores the value that is to be retur ned in response to the get_status endpoint7 request. this register can be read or written in 8-bit units. note, however, that data can be written to this register only when the ep0nka bit is set to 1. if an error occurs in endpoint7, the e7halt bit is set to 1. a write access to this register is ignored while a usb- side access to endpoint7 is being received. the hardware automatically transmits the contents of this register to the host when it has received the get_status endpoint7 request. if endpoint7 has stalled, the uf0int1 register is cleared and the it1nk bit is cleared to 0. because writing this register is always masked when transfer to endpoint7, rather than control transfer, is executed, be sure to check this register to see if data has been correctly written to it. caution to rewrite this register, set the ep0nka bit to 1 before reading the register contents, and rewrite the register contents after conf irming that the bit has been set, in order to prevent conflict between a read access and a write access. 0 uf0e7sl 0 5 00 3 0 2 0 1 0 e7halt address 00200168h after reset 00h 0 4 6 7 bit position bit name function 0 e7halt this bit indicates the status of endpoint7. 1: stalled 0: not stalled this bit is set to 1 by hardware when the set_feature endpoint7 request has been received. it is cleared to 0 by hardware when the clear_feature endpoint7 request, set_configuration request, or the set_interface request for the interface to which endpoint7 is linked has correctly been rece ived. data pid is initialized to data0. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1292 of 1817 sep 19, 2011 (8) uf0 address register (uf0adrs) this register stores the device address. this register is read-only, in 8-bit units. the device address sent by the set _address request is analyzed and the resultant value is automatically written to this register. if the set_address request is proc essed by fw, the value of this register is reflected as the device address when the success sig nal is received in the status stage. caution do not execute a write access to this regist er. if written, the oper ation is not guaranteed. 0 uf0adrs adrs6 5 adrs5 adrs4 3 adrs3 2 adrs2 1 adrs1 adrs0 address 00200180h after reset 00h 0 4 6 7 bit position bit name function 6 to 0 adrs6 to adrs0 these bits hold the device address of sie. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1293 of 1817 sep 19, 2011 (9) uf0 configuration register (uf0cnf) this register stores the value that is to be re turned in response to the get_configuration request. this register is read-only, in 8-bit units. when the set_configuration request is received, its wval ue is automatically written to this register. when a change of the value of this register from 00h to other than 00h is detected, the conf bit of the uf0mods register is set to 1. if the set_configuration request is processed by fw, the status of this register is immediately reflected on the uf0mods register as soon as data has been written to this register (conf bit = 1 before completion of the status stage). caution do not execute a write access to this regist er. if written, the oper ation is not guaranteed. 0 uf0cnf 0 5 00 3 0 2 0 1 conf1 conf0 address 00200182h after reset 00h 0 4 6 7 bit position bit name function 1, 0 conf1, conf0 these bits hold the data to be returned in response to the get_configuration request. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1294 of 1817 sep 19, 2011 (10) uf0 interface 0 register (uf0if0) this register stores the value that is to be retur ned in response to the get_interface windex = 0 request. this register is read-only, in 8-bit units. when the set_interface request is received, its wval ue is automatically written to this register. if the set_interface request is processed by fw, wi ndex and wvalue are decoded, and the setting of endpoint is automatically changed. at this time , the status bit of the ta rget endpoint and dpid are automatically cleared to 0, depending on the setting. the fi fo is not cleared automatically. caution do not execute a write access to this regist er. if written, the oper ation is not guaranteed. 0 uf0if0 0 5 00 3 0 2 if02 1 if01 if00 address 00200184h after reset 00h 0 4 6 7 bit position bit name function 2 to 0 if02 to if00 these bits hold the data to be returned in response to get_interface windex = 0 request. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1295 of 1817 sep 19, 2011 (11) uf0 interface 1 to 4 re gisters (uf0if1 to uf0if4) these registers store the va lue that is to be returned in response to the get_interface windex = n request (n = 1 to 4). these registers are read-only, in 8-bit units. when the set_interface request is received, its wval ue is automatically written to these registers. these registers are invalidated according to t he setting of the uf0aifn and uf0aas registers. if the set_interface request is processed by fw, wi ndex and wvalue are decoded, and the setting of endpoint is automatically changed. at this time , the status bit of the ta rget endpoint and dpid are automatically cleared to 0, depending on the setting. the fi fo is not cleared automatically. caution do not execute a write access to this regist er. if written, the oper ation is not guaranteed. 0 0 0 0 uf0if1 uf0if2 uf0if3 uf0if4 0 0 0 0 5 0 0 0 0 0 0 0 0 3 0 0 0 0 2 if12 if22 if32 if42 1 if11 if21 if31 if41 if10 if20 if30 if40 address 00200186h 00200188h 0020018ah 0020018ch after reset 00h 00h 00h 00h 0 4 6 7 bit position bit name function 2 to 0 ifn2 to ifn0 these bits hold the data to be returned in response to get_interface windex = n request. remark n = 1 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1296 of 1817 sep 19, 2011 (12) uf0 descriptor length register (uf0dscl) this register stores the length of the value that is to be returned in response to the get_descriptor configuration request. the value of th is register is the number of bytes of all the descriptors set by the uf0cien register minus 1 (n = 0 to 255). the total descripto r length that is to be returned in response to the get_descriptor configuration request is determine d according to the value of this register. this register can be read or written in 8-bit units. however, data can be written to this register only when the ep0nka bit is set to 1. processing of wlength is autom atically controlled. if this register is set to 00h, it means that the descriptor to be returned is 1 byte long. if the register is set to ff h, a descriptor length of 256 bytes is returned. when a descriptor exceeding 256 bytes in length is used, se t the cdcgdst bit of the uf 0modc register to 1 and process the get_descriptor request by fw (at this time , the cdcgd bit of the uf0mods register is also set to 1). caution to rewrite this register, set the ep0nka bit to 1 before reading the register contents, and rewrite the register contents after conf irming that the bit has been set, in order to prevent conflict between a read access and a write access. dpl7 uf0dscl dpl6 5 dpl5 dpl4 3 dpl3 2 dpl2 1 dpl1 dpl0 address 002001a0h after reset 00h 0 4 6 7 bit position bit name function 7 to 0 dpl7 to dpl0 these bits set the value of the number of bytes of all the descriptors to be returned in response to the get_descriptor configuration request minus 1. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1297 of 1817 sep 19, 2011 (13) uf0 device descriptor regist ers 0 to 17 (uf0dd0 to uf0dd17) these registers store the value to be returned in response to the get_descriptor device request. these registers can be read or written in 8-bit units. ho wever, data can be written to these registers only when the ep0nka bit is set to 1. cautions 1. to rewrite these registers, set the ep0 nka bit to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 2. use the value defined by usb specification ver. 2.0 and the latest class specification as the set value. uf0ddn (n = 0 to 17) 5 3 2 1 after reset 0 4 6 7 undefined address see table 22-5 . table 22-5. mapping and data of uf0 device descriptor registers symbol address field name contents uf0dd0 002001a2h blength size of this descriptor uf0dd1 002001a4h bdescriptortype device descriptor type uf0dd2 002001a6h value below decimal point of rev. number of usb specification uf0dd3 002001a8h bcdusb value above decimal point of rev. number of usb specification uf0dd4 002001aah bdeviceclass class code uf0dd5 002001ach bdevicesubc lass subclass code uf0dd6 002001aeh bdeviceprotocol protocol code uf0dd7 002001b0h bmaxpacketsize0 maximum packet size of endpoint0 uf0dd8 002001b2h lower value of vendor id uf0dd9 002001b4h idvendor higher value of vendor id uf0dd10 002001b6h lower value of product id uf0dd11 002001b8h idproduct higher value of product id uf0dd12 002001bah lower value of device release number uf0dd13 002001bch bcddevice higher value of device release number uf0dd14 002001beh imanufacturer index of string descriptor describing manufacturer uf0dd15 002001c0h iproduct index of string descriptor describing product uf0dd16 002001c2h lserialnumber index of string de scriptor describing device serial number uf0dd17 002001c4h bnumconfigurations number of settable configurations v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1298 of 1817 sep 19, 2011 (14) uf0 configuration/interf ace/endpoint descriptor registers 0 to 255 (uf0cie0 to uf0cie255) these registers store the value to be returned in re sponse to the get_descriptor configuration request. these registers can be read or written in 8-bit units. ho wever, data can be written to these registers only when the ep0nka bit is set to 1. descriptor information of up to 256 bytes can be stored in these registers. store each descriptor in the order of configuration, interface, and endpoint (see table 22-6 ). if there are two or more interfaces, repeatedly store the data following the interface descriptor. table 22-6. mapping of uf0cien register address descriptor stored 002001c6h configuration descriptor (9 bytes) 002001d8h interface descriptor (9 bytes) 002001eah endpoint1 descriptor (7 bytes) 002001f8h endpoint2 descriptor (7 bytes) 00200206h endpoint3 descriptor (7 bytes) : : 002002xxh interface descriptor (9 bytes) 002002xxh+9 endpoint1 descriptor (7 bytes) 002002xxh+16 endpoint2 descriptor (7 bytes) 002002xxh+23 endpoint3 descriptor (7 bytes) : : the range of the valid data that can be set to these registers varies ac cording to the setting of the uf0dscl register. in addition to the descriptors listed in table 22-7, descriptors peculiar to classes and vendors can also be stored. if all the values are fixed, they can be stored in rom. cautions 1. to rewrite these registers, set the ep0 nka bit to 1 before reading the register contents, and rewrite the register contents after confirming th at the bit has been set , in order to prevent conflict between a read access and a write access. 2. use the value defined by usb specification ver. 2.0 and the latest class specification as the set value. uf0cien (n = 0 to 255) 5 3 2 1 after reset 0 4 6 7 002001c6h to 002003c4h undefined address v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1299 of 1817 sep 19, 2011 table 22-7. data of uf0cien register (a) configuration descriptor (9 bytes) offset field name contents 0 blength size of this descriptor 1 bdescriptortype descriptor type 2 lower value of the total number of bytes of configuration, all interface, and all endpoint descriptors 3 wtotallength higher value of the total number of bytes of configuration, all interface, and all endpoint descriptors 4 bnuminterface number of interfaces 5 bconfigurationvalue value to select this configuration 6 iconfiguration index of string descriptor describing this configuration 7 bmattributes features of this configuration (self-powered, without remote wakeup) 8 maxpower maximum power consumption of this configuration (unit: ma) note note shown in 2 ma units. (example: 50 = 100 ma) (b) interface descriptor (9 bytes) offset field name contents 0 blength size of this descriptor 1 bdescriptortype descriptor type 2 binterfacenumber value of this interface 3 balternatesetting value to select alternative setting of interface 4 bnumendpoints number of usable endpoints 5 binterfaceclass class code 6 binterfacesubclass subclass code 7 binterfaceprotocol protocol code 8 interface index of string descriptor describing this interface (c) endpoint descriptor (7 bytes) offset field name contents 0 blength size of this descriptor 1 bdescriptortype descriptor type 2 bendpointaddress address/transfer direction of this endpoint 3 bmattributes transfer type 4 lower value of maximum number of transfer data 5 wmaxpaketsize higher value of maximum number of transfer data 6 binterval transfer interval v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1300 of 1817 sep 19, 2011 22.6.6 bridge register (1) bridge interrupt control register (brgintt) the brgintt register controls the dma transfer status of the interrupt g enerate status, and each end point (ep1 to ep4) from epc to bridge circuit. the brgintt register can be read or written in 16-bit units. after reset: 0000h r/w address: 00200400h 15 14 13 12 11 10 9 8 brgintt 0 0 0 0 ep4int ep3int ep2int ep1int 7 6 5 4 3 2 1 0 0 0 0 0 0 epcint2b epcint1b epcint0b bit position bit name function 11 ep4int in ep4, when the dma transfer is normal terminate, or the error finished in the dma transferring, this bit is setting. clearing to ?0? by writing ?1?. 0: dma transfer not completion 1: dma transfer completion 10 ep3nt in ep3, when the dma transfer is normal terminate, or the error finished in the dma transferring, this bit is setting. clearing to ?0? by writing ?1?. 0: dma transfer not completion 1: dma transfer completion 9 ep2nt in ep2, when the dma transfer is normal terminate, or the error finished in the dma transferring, this bit is setting. clearing to ?0? by writing ?1?. 0: dma transfer not completion 1: dma transfer completion 8 ep1nt in ep1, when the dma transfer is normal terminate, or the error finished in the dma transferring, this bit is setting. clearing to ?0? by writing ?1?. 0: dma transfer not completion 1: dma transfer completion 2 epcint2b showing the status of the interrupt signal ?epc_int2b? from epc. clear controlling from the request of epc register 0: interrupt not issued 1: interrupt issued 1 epcint1b showing the status of the interrupt signal ?epc_int1b? from epc. clear controlling from the request of epc register 0: interrupt not issued 1: interrupt issued 0 epcint0b showing the status of the interrupt signal ?epc_int0b? from epc. clear controlling from the request of epc register 0: interrupt not issued 1: interrupt issued v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1301 of 1817 sep 19, 2011 (2) bridge interrupt enable register (brginte) the brginte register controls whether the interrupt ge nerated in the bridge circuit is enabled or disabled. the brginte register can be read or written in 16-bit units. after reset: 0000h r/w address: 00200402h 15 14 13 12 11 10 9 8 brginte 0 0 0 0 ep4intn ep3intn ep2intn ep1intn 7 6 5 4 3 2 1 0 0 0 0 0 0 epc int2ben epc int1ben epc int0ben bit position bit name function 11 ep4intn setting the interrupt occur enable or disable when ep4int bit is setting. 0: interrupt disabled 1: interrupt enabled 10 ep3ntn setting the interrupt occur enable or disable when ep3int bit is setting. 0: interrupt disabled 1: interrupt enabled 9 ep2ntn setting the interrupt occur enable or disable when ep2int bit is setting. 0: interrupt disabled 1: interrupt enabled 8 ep1ntn setting the interrupt occur enable or disable when ep1int bit is setting. 0: interrupt disabled 1: interrupt enabled 2 epcint2ben setting the interrupt occur enable or disable when epcint2ben bit is setting. 0: interrupt disabled 1: interrupt enabled 1 epcint1ben setting the interrupt occur enable or disable when epcint1ben bit is setting. 0: interrupt disabled 1: interrupt enabled 0 epcint0ben setting the interrupt occur enable or disable when epcint0ben bit is setting. 0: interrupt disabled 1: interrupt enabled v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1302 of 1817 sep 19, 2011 (3) epc macro control register (epcclt) the epcclt register controls the re set generator to the epc macro. the epcclt register can be read or written in 16-bit units. after reset: 0000h r/w address: 00200404h 15 14 13 12 11 10 9 8 epcclt 0 0 0 0 0 0 0 0n 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 epcrst bit position bit name function 0 epcrst setting the reset occurs to epc. 0: reset released 1: reset issued v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1303 of 1817 sep 19, 2011 (4) cpu i/f bus control register (cpubctl) the cpubctl register controls the inte rface between bridge circuit and cpu. the cpubctl register can be read or written in 16-bit units. after reset: undefined r/w address: 00200408h 15 14 13 12 11 10 9 8 cpubctl 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 bulkwait datawait nowait bit position bit name function 2 bulkwait forcibly inserting the 1 wait (bulk wait ) when the bulk register is accessed. 0: no forcibly insert the bulk wait note (default value) 1: forcibly insert the bulk wait note the setting is invalid in write accessing, the bulk wait is forcibly inserted. 1 datawait forcibly inserting the 1 wait (data wait) after the cpu bus cycle. 0: no forcibly insert the data wait (default value) 1: forcibly insert the data wait 0 nowait setting enables/disable the no wait operation of cpu bus cycle. 0: no wait disables note (default value) 1: no wait enables note 1 wait or more is inserted. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1304 of 1817 sep 19, 2011 22.6.7 dma register (1) epn dma control register 1 (uf0e1dc1 to uf0e4dc1) the uf0e1dc1 to uf0e4dc1 regist er controls the dma transfer of end point n (epn). (n = 1 to 4) the uf0e1dc1 to uf0e4dc1 register can be read or written in 16-bit units. (1/2) after reset: 0000h r/w address: 00200500h 15 14 13 12 11 10 9 8 uf0e1dc1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 ep1bulk2 ep1bulk1 ep1bulk0 ep1stop ep1req ep1dmaen after reset: 0000h r/w address: 00200504h 15 14 13 12 11 10 9 8 uf0e2dc1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 ep2bulk2 ep2bulk1 ep2bulk0 ep2stop ep2req ep2dmaen after reset: 0000h r/w address: 00200508h 15 14 13 12 11 10 9 8 uf0e3dc1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 ep3bulk2 ep3bulk1 ep3bulk0 ep3stop ep3req ep3dmaen after reset: 0000h r/w address: 0020050ch 15 14 13 12 11 10 9 8 uf0e4dc1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 ep4bulk2 ep4bulk1 ep4bulk0 ep4stop ep4req ep4dmaen v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1305 of 1817 sep 19, 2011 (2/2) bit position bit name function 5 to 3 epnbulk2, epnbulk1, epnbulk0 shown the status the state machine ?bin_state? for bulk transfer of the internal bridge epnbulk2 epnbulk1 epnbulk0 ?bin_state? status 0 0 0 bin_idle 0 0 1 bin_cpu 0 1 0 bin_epc 0 1 1 bin_cmp 1 0 0 bin_end 2 epnstop showing the status (end factor of dma transfer) of dma transfer end from epc 0: end of dma transfer by epn_tcnt value ?0? 1: end of dma transfer by negate of ?epc_dmarq_epnb? automatically clear (0) by setting next ep1_dmaen to ?1?. 1 epnreq showing the status of ?epc_dmarq_epnb? signal from epc 0: no dma request signal 1: dma request signal 0 epndmaen setting the control of dma request from epc 0: masks dma request 1: enables dma request automatically clear (0) by complete number of packet transfer setting in epn_tcnt, or complete the dma transfer by the negate of dmarq_epnb. caution the setting value is not guaranteed in forcibly end. remark n = 1 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1306 of 1817 sep 19, 2011 (2) epn dma control register 2 (uf0e1dc2 to uf0e4dc2) the uf0e1dc2 to uf0e4dc2 regist er controls the dma transfer of end point n (epn). (n = 1 to 4) the uf0e1dc2 to uf0e4dc2 register can be read or written in 16-bit units. (1/2) after reset: 0000h r/w address: 00200502h 15 14 13 12 11 10 9 8 uf0e1dc2 ep1 tcnt15 ep1 tcnt14 ep1 tcnt13 ep1 tcnt12 ep1 tcnt11 ep1 tcnt10 ep1 tcnt9 ep1 tcnt8 7 6 5 4 3 2 1 0 ep1 tcnt7 ep1 tcnt6 ep1 tcnt5 ep1 tcnt4 ep1 tcnt3 ep1 tcnt2 ep1 tcnt1 ep1 tcnt0 after reset: 0000h r/w address: 00200506h 15 14 13 12 11 10 9 8 uf0e2dc2 ep2 tcnt15 ep2 tcnt14 ep2 tcnt13 ep2 tcnt12 ep2 tcnt11 ep2 tcnt10 ep2 tcnt9 ep2 tcnt8 7 6 5 4 3 2 1 0 ep2 tcnt7 ep2 tcnt6 ep2 tcnt5 ep2 tcnt4 ep2 tcnt3 ep2 tcnt2 ep2 tcnt1 ep2 tcnt0 after reset: 0000h r/w address: 0020050ah 15 14 13 12 11 10 9 8 uf0e3dc2 ep3 tcnt15 ep3 tcnt14 ep3 tcnt13 ep3 tcnt12 ep3 tcnt11 ep3 tcnt10 ep3 tcnt9 ep3 tcnt8 7 6 5 4 3 2 1 0 ep3 tcnt7 ep3 tcnt6 ep3 tcnt5 ep3 tcnt4 ep3 tcnt3 ep3 tcnt2 ep3 tcnt1 ep3 tcnt0 after reset: 0000h r/w address: 0020050eh 15 14 13 12 11 10 9 8 uf0e4dc2 ep4 tcnt15 ep4 tcnt14 ep4 tcnt13 ep4 tcnt12 ep4 tcnt11 ep4 tcnt10 ep4 tcnt9 ep4 tcnt8 7 6 5 4 3 2 1 0 ep4 tcnt7 ep4 tcnt6 ep4 tcnt5 ep4 tcnt4 ep4 tcnt3 ep4 tcnt2 ep4 tcnt1 ep4 tcnt0 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1307 of 1817 sep 19, 2011 (2/2) bit position bit name function 15 to 0 epntcnt15 to epntcnt0 setting the number of byte to dma transfer in epn. end the dma transfer after the value of epn_tcnt is ?0? to decrement each transfer. cautions 1. set this register when epn_dmaen = 0. 2. setting this register to ?0? is prohibited. be sure to set this register +1 value for the value of dma transfer count register dbc0 to dbc3. 3. the setting value of this register is reflected the counter bin_tcnt for bulk transfer of the bridge inside. and the value of bin_tcnt is ?0?, epn_tcn is ?0?, too. 4. update the value of the counter bin_tcnt for bulk transfer is stopped when forcibly terminated. remark n = 1 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1308 of 1817 sep 19, 2011 22.6.8 peripheral control registers (1) usbf dma request enable register (ufdrqen) the ufdrqen register specifies the dma channel to be used and the endpoint to be transferred. the ufdrqen register can be read or written in 8-bit or 16-bit units. (1/2) after reset: 0000h r/w address: 00240000h 15 14 13 12 11 10 9 8 ufdrqen rq3ur3e rq2ur3e rq1ur3e rq0 ur3e rq3ur2e rq2ur2e rq1ur2e rq0ur2e 7 6 5 4 3 2 1 0 rq3ur1e rq2ur1e rq1ur1e rq0ur1e rq3ur0e rq2ur0e rq1ur0e rq0ur0e bit position bit name function 15, 11, 7, 3 rq3ur3e, rq3ur2e, rq3ur1e, rq3ur0e specify the endpoint n (epn) to be transferred by dma channel 3. (n = 1 to 4) rq3ur3e rq3ur2e rq3ur1e rq3ur0e ep transferred by dma3 1 0 0 0 ep4 0 1 0 0 ep3 0 0 1 0 ep2 0 0 0 1 ep1 other than above dma3 does not transfer epn (dma3 not used) 14, 10, 6, 2 rq2ur3e, rq2ur2e, rq2ur1e, rq2ur0e specify the endpoint n (epn) to be transferred by dma channel 2. (n = 1 to 4) rq2ur3e rq2ur2e rq2ur1e rq2ur0e ep transferred by dma2 1 0 0 0 ep4 0 1 0 0 ep3 0 0 1 0 ep2 0 0 0 1 ep1 other than above dma2 does not transfer epn (dma2 not used) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1309 of 1817 sep 19, 2011 (2/2) bit position bit name function 13, 9, 5, 1 rq1ur3e, rq1ur2e, rq1ur1e, rq1ur0e specify the endpoint n (epn) to be transferred by dma channel 1. (n = 1 to 4) rq1ur3e rq1ur2e rq1ur1e rq1ur0e ep transferred by dma2 1 0 0 0 ep4 0 1 0 0 ep3 0 0 1 0 ep2 0 0 0 1 ep1 other than above dma1 does not transfer epn (dma1 not used) 12, 8, 4, 0 rq0ur3e, rq0ur2e, rq0ur1e, rq0ur0e specify the endpoint n (epn) to be transferred by dma channel 0. (n = 1 to 4) rq0ur3e rq0ur2e rq0ur1e rq0ur0e ep transferred by dma0 1 0 0 0 ep4 0 1 0 0 ep3 0 0 1 0 ep2 0 0 0 1 ep1 other than above dma0 does not transfer epn (dma0 not used) cautions 1. setting the same dma transfer target to multiple dma channels , and setting multiple dma transfer targets to the same dma channel are prohibited. 2. if using the function of this register, set the dma trigger factor register (dtfrn (n = 0 to 3)) to disable dma requests by interrupt (00h). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1310 of 1817 sep 19, 2011 the following flowcharts illustrate the program executio n when the host is disconnected and then reconnected, and the program execution when power is supplied. figure 22-12. flowchart of program when host is disconnected and then reconnected checks status of pin interrupt detecting host connection status masks intusbf0 and intusbf1 interrupts disables usb bus, enables measures against floating yes host disconnected? no start initialization processing of register area end checks status of pin interrupt detecting host connection status unmasks usb-related interrupts and discards interrupts automatic device setup by plug&play yes host connected? no v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1311 of 1817 sep 19, 2011 figure 22-13. flowchart of program when power is supplied masks intusbf0 and intusbf1 interrupts starts usbf clock supply start enables usb bus, disables measures against floating end checks status of pin interrupt detecting host connection status initializes register area, enables measures against floating unmasks usb-related interrupts and discards interrupts automatic device setup by plug&play yes host connected? no v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1312 of 1817 sep 19, 2011 22.7 stall handshake or no handshake errors of usbf are defined to be handled as follows. transfer type transaction target packet error type function response processing endpoint not supported no response none endpoint transfer direction mismatch no response none crc error no response none control transfer/ bulk transfer/ interrupt transfer in/out/setup token bit stuffing error no response none timeout no response none pid check error no response none unsupported pid (other than data pid) no response none crc error no response discard received data out/setup data bit stuffing error no response discard received data control transfer/ bulk transfer out data data pid mismatch ack discard received data control transfer (setup stage) setup data overrun no response discard received data control transfer (data stage) out data overrun no response note 1 set sndstl bit of uf0sds register to 1 and discard received data control transfer (status stage) out data overrun ack or no response note 2 set sndstl bit of uf0sds register to 1 and discard received data bulk transfer out data overrun no response note 1 set enhalt bit of uf0ensl register (n = 0 to 4, 7) to 1 pid check error ? hold transferred data and re-transfer data note 3 unsupported pid (other than ack pid) ? hold transferred data and re-transfer data note 3 control transfer/ bulk transfer/ interrupt transfer in handshake timeout ? hold transferred data and re-transfer data note 3 notes 1. a stall response is made to re-transfer by the host. 2. an ack response is made if the transfer data is of less than maxpacketsize and the data received in the status stage is discarded. if maxpacketsize is exc eeded, no response is made, the sndstl bit of the uf0sds register is set to 1, and the received data is discarded. 3. if an out transaction indicating a change from the data stage to the status stage is received during control transfer, an error is not handled and it is assum ed that reception has been correctly completed. cautions 1. it is judged by the alternative setting nu mber currently set whether the target endpoint is valid or invalid. 2. for the response to the requ est included in control transfer to/from endpoint0, see 22.5 requests. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1313 of 1817 sep 19, 2011 22.8 register values in specific status table 22-8. register values in specific status (1/2) register name after cpu reset (reset) after bus reset uf0e0n register 00h value is held. uf0e0na register 00h value is held. uf0en register 00h value is held. uf0enm register 00h value is held. uf0sds register 00h value is held. uf0clr register 00h value is held. uf0set register 00h value is held. uf0eps0 register 00h value is held. uf0eps1 register 00h value is held. uf0eps2 register 00h value is held. uf0is0 register 00h value is held. uf0is1 register 00h value is held. uf0is2 register 00h value is held. uf0is3 register 00h value is held. uf0is4 register 00h value is held. uf0im0 register 00h value is held. uf0im1 register 00h value is held. uf0im2 register 00h value is held. uf0im3 register 00h value is held. uf0im4 register 00h value is held. uf0ic0 register ffh value is held. uf0ic1 register ffh value is held. uf0ic2 register ffh value is held. uf0ic3 register ffh value is held. uf0ic4 register ffh value is held. uf0idr register 00h value is held. uf0dms0 register 00h value is held. uf0dms1 register 00h value is held. uf0fic0 register 00h value is held. uf0fic1 register 00h value is held. uf0dend register 00h value is held. uf0gpr register 00h value is held. uf0modc register 00h value is held. uf0mods register 00h bit 2 (conf): cleared (0), other bits: value is held. uf0aifn register 00h value is held. uf0aas register 00h value is held. uf0ass register 00h 00h uf0e1im register 00h value is held. uf0e2im register 00h value is held. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1314 of 1817 sep 19, 2011 table 22-8. register values in specific status (2/2) register name after cpu reset (reset) after bus reset uf0e3im register 00h value is held. uf0e4im register 00h value is held. uf0e7im register 00h value is held. uf0e0r register undefined note 1 value is held. uf0e0l register 00h value is held. uf0e0st register 00h 00h uf0e0w register undefined note 1 value is held. uf0bo1 register undefined note 1 value is held. uf0bo1l register 00h value is held. uf0bo2 register undefined note 1 value is held. uf0bo2l register 00h value is held. uf0bi1 register undefined note 1 value is held. uf0bi2 register undefined note 1 value is held. uf0int1 register undefined value is held. uf0dstl register 00h 00h uf0e0sl register 00h 00h uf0e1sl register 00h 00h uf0e2sl register 00h 00h uf0e3sl register 00h 00h uf0e4sl register 00h 00h uf0e7sl register 00h 00h uf0adrs register 00h 00h uf0cnf register 00h 00h uf0if0 register 00h 00h uf0if1 register 00h 00h uf0if2 register 00h 00h uf0if3 register 00h 00h uf0if4 register 00h 00h uf0dscl register 00h value is held. uf0ddn register (n = 0 to 17) note 2 note 2 uf0cien register (n = 0 to 255) note 2 note 2 notes 1. this register can be cleared to 0 by the reset signal because its write pointer, counter, and read pointer are cleared to 0 when the reset signal becomes active , in the same manner as clearing by the uf0ficn register, as the register is controlled by fifo. 2. this register cannot be cleared to 0. because data ca n be written to it by fw, however, any value can be written to the register (before doing so, however, be su re to set the ep0nka bit of the uf0e0na register to 1). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1315 of 1817 sep 19, 2011 22.9 fw processing the following fw processing is performed. ? setting processing on device side for the set_c onfiguration, set_inter face, set_feature, and clear_feature requests during enumeration processing ? analysis and processing of xxxxstandard, xxxxclass, and xxxxvendor requests not subject to automatic processing ? reading data following bulk-transferred out token from receive buffer ? writing data to be returned in response to bulk-transferred in token ? writing data to be returned in response to interrupt-transferred token the following table lists the requests supported by fw. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1316 of 1817 sep 19, 2011 table 22-9. fw-supported standard requests request reception side processing/ frequency explanation clear_feature interface automatic stall response it is considered that this request does not come to interface because there is no function selector value, though it is reserved for bmrequesttype. when this request is received, the hardware makes an automatic stall response. set_feature interface automatic stall response it is considered that this request does not come to interface because there is no function selector value, though it is reserved for bmrequesttype. when this request is received, the hardware makes an automatic stall response. get_descriptor string fw returns the string descriptor. when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and writes the data to be returned to the host, to the uf0e0w register. set_descriptor device fw rewrites the device descriptor. when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and the writes the data for the next control transfer (out) to the uf0ddn register (n = 0 to 17). set_descriptor configuration fw rewrites the configuration descriptor. when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and the writes the data for the next control transfer (out) to the uf0cien register (n = 0 to 255). set_descriptor string fw rewrites the string descriptor. when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and loads the data for the next control transfer (out). other na fw when this request is received by the setup token, the hardware generates the cpudec interrupt request for fw. fw decodes the contents of the request from the cpudec interrupt request, and performs the necessary processing. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1317 of 1817 sep 19, 2011 22.9.1 initialization processing initialization processing is executed in the following two ways. ? initialization of request data register ? setting of interrupt when a request data register is initiali zed, data for the get_xxxx request to wh ich a value is to be automatically returned is written and an endpoint is allocated to an interface. in the interrupt settings, the interrupt sources that do not have to be checked can be masked by using the uf0imn register (n = 0 to 4). the following flowcharts illus trate the above processing. figure 22-14. initializing request data register start end ep0nka = 1? (uf0e0na) cancels nak response to endpoint0. uf0e0na register = 01h initialization of request data register uf0modc register = 40h or 00h yes no : see figure 22-15 initialization of request data register . setting of interface and endpoint uf0e0na register = 00h : see figure 22-16 setting of interface and endpoint . if the total number of bytes of the uf0cien register exceeds 256, set the uf0modc register to 40h. no data has to be written to the uf0cien register. remark n = 0 to 255 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1318 of 1817 sep 19, 2011 figure 22-15. initialization setti ngs of request data register the value of 0xh depends on the power supply method. ? sfpw = 1: self-powered ? sfpw = 0: bus-powered n = 0 to 4, or 7. setting is unnecessary if the target endpoint is not used. if the total number of bytes of the uf0ciea register exceeds 256, set the uf0modc register to 40h. no data has to be written to the uf0ciea register. input the total number of bytes of the uf0ciea register. uf0dstl register = 0xh uf0ensl register = 00h setting of uf0dscl register inputting uf0ddm register inputting uf0ciea register remark m = 0 to 17 a = 0 to 255 figure 22-16. setting of interface and endpoint addif, ifno1, ifno0 = 000: interface number 0 is valid. addif, ifno1, ifno0 = 100: interface numbers 0 and 1 are valid. addif, ifno1, ifno0 = 101: interface numbers 0 to 2 are valid. addif, ifno1, ifno0 = 110: interface numbers 0 to 3 are valid. addif, ifno1, ifno0 = 111: interface numbers 0 to 4 are valid. set a link between the target interface of endpoint n and alternative setting. set 00h if the target endpoint is not used. set interface number(s) and a link with the 5- or 2-series alternative setting. setting of uf0aifn register setting of uf0aas register setting of uf0enim register remark n = 1 to 4, 7 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1319 of 1817 sep 19, 2011 figure 22-17. setting of interrupt start end mask the interrupt source to avoid issuance of an unnecessary interrupt request (intusbf0). setting of uf0imn register remark n = 0 to 4 v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1320 of 1817 sep 19, 2011 22.9.2 interrupt servicing the following flowchart illustrates how an interrupt is serviced. figure 22-18. interrupt servicing end (n = 0 to 4) reading uf0isn register servicing interrupt intusbf0 active target bit of uf0icn register = 0 start remark ? : processing by hardware the following bits of the uf0isn register are automatically cl eared by hardware when a given condition is satisfied (n = 0 to 4). ? e0indt, e0odt, suces, stg, and cpudec bits of uf0is1 register ? bki2dt, bki1dt, and it1dt bi ts of uf0is2 register ? bko2fl, bko2dt, bko1fl, and bko1dt bits of uf0is3 register because clearing an interrupt source by t he uf0icn register is given a lower prio rity than setting an interrupt source by hardware, the interrupt source may not be cl eared depending on the timing (n = 0 to 4). v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1321 of 1817 sep 19, 2011 22.9.3 usb main processing usb main processing involves processing usb transactions. the types of transactions to be processed are as follows. ? fully automatically processed request for control transfer ? automatically processed requests for control transfer (set_configuration, set_interface, set_feature, clear_feature) ? cpudec request for control transfer ? processing for bulk transfer (in) ? processing for bulk transfer (out) ? processing for interrupt transfer (in) processing for endpoint n involves writing or reading for data transfer. the flowchart shown below is for pio. (1) fully automatically processed request for control transfer because the fully automatically proce ssed request for control transfer is executed by hardware, it cannot be referenced by fw. therefore, fw does not have to perform any special processing for this request. (2) automatically processed requests for control transfer (set_configuration, set_interface, set_feature, clear_feature) processing to write a register for automatically processed requests for control transfer, such as set_configuration, set_interface , set_feature, and clear_feature requests, is automatically executed by hardware, but an interrupt request is issued for recognition on the device side. this processing may be ignored if there is no special processing to be executed. the flowcharts are shown below. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1322 of 1817 sep 19, 2011 figure 22-19. automatically proces sed requests for control transfer start end clear_feature? set_feature? receiving setup token clear_feature processing set_feature processing set_configuration? set_configuration processing set_interface? intusbf0 active decoding request (n = 0, 1) yes no yes no yes no yes no other automatically processed request? cpudec processing illegal processing yes no reading uf0isn register reading uf0set register fw processing for each request clrrq = 1? (uf0is0) setrq = 1? (uf0is0) reading uf0clr register fw processing for each request yes no yes no end end end automatic processing illegal processing reading uf0is4 register yes no setint = 1? (uf0is4) end setintc = 0 (uf0ic4) fw processing for set_interface : see figure 22-20 clear_feature processing. : see figure 22-21 set_feature processing. : see figure 22-22 set_configuration processing. : see figure 22-23 set_interface processing. set_interface processing remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1323 of 1817 sep 19, 2011 figure 22-20. clear_feature processing set the corresponding bit for the value of 0xh. the ephalt bit of the uf0is0 register is cleared to 0 only when all halt features are cleared. uf0clr register = 0xh clrrq = 1 (uf0is0) haltn = 0 (uf0eps2) clearing uf0dstl register clearing uf0ensl register remarks 1. n = 0 to 4, 7 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1324 of 1817 sep 19, 2011 figure 22-21. set_feature processing set the corresponding bit for the value of 0xh. the ephalt bit of the uf0is0 register is not set to 1 by setting the uf0dstl register. uf0set register = 0xh setrq = 1 (uf0is0) haltn = 1 (uf0eps2) ephalt = 1 (uf0is0) setting uf0dstl register setting uf0ensl register remarks 1. n = 0 to 4, 7 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1325 of 1817 sep 19, 2011 figure 22-22. set_configuration processing setcon = 1 (uf0set) setrq = 1 (uf0is0) conf = 1 (uf0mods) setting uf0cnf register remark ? : processing by hardware figure 22-23. set_interface processing setint = 1 (uf0is4) setting uf0ass register setting uf0ifn register remarks 1. n = 0 to 4 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1326 of 1817 sep 19, 2011 (3) cpudec request for control transfer the cpudec request can be classified into three types of processing: control transfer (write), control transfer (read), and control transfer (without data). control tr ansfer (write) indicates a request that uses the out transaction in the data stage (e.g., set_d escriptor), and control transfer (r ead) indicates a request that uses the in transaction in the data stage (e.g., get_descriptor). control transfer (without data) indicates a request that has no data stage (e.g., set_configuration). the flowcharts are shown below. figure 22-24. cpudec request for control transfer (1/12) (a) token phase (1/2) start cpudec = 1? (uf0is1) intusbf0 active appropriate interrupt servicing cpudec = 0 (uf0is1) reading uf0isn register protc = 0 (uf0ic1) stgm = 0 (uf0im1) cpudecm = 1 (uf0im1) reading uf0e0st register 8 times decoding fw request yes no g e a remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1327 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (2/12) (a) token phase (2/2) supported request? prot = 1? (uf0is1) control transfer (read)? control transfer (write)? reading uf0isn register sndstl = 1 (uf0sds) sndstl = 0 (uf0sds) ep0rc = 1 (uf0fic0) stgm = 1 (uf0im1) cpudecm = 0 (uf0im1) b yes no yes no yes no yes no setup token received? yes no stall handshake response end e c d a in the case of an unsupported request for control transfer (write), clear the fifo because data may be written to the fifo as a result of out transfer before the stall response is made. it is judged whether the request decoded by the device is supported. request that uses control transfer (in), such as get_descriptor string request that uses control transfer (out), such as set_descriptor string remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1328 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (3/12) (b) control transfer (read) (1/4) cpudec = 1? (uf0is1) e0in = 1? (uf0is1) transmitting nak e0in = 1 (uf0is1) fw request decode e0inm = 1 (uf0im1) yes no yes no b if return data greater than the fifo size exists, it is divided into fifo size units and sequentially written, starting from the lowest data byte. intusbf0 active reading uf0isn register i f illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1329 of 1817 sep 19, 2011 figure 22-24 cpudec request for control transfer (4/12) (b) control transfer (read) (2/4) fifo full? e0ded = 1 (uf0dend) ep0nkw = 1 (uf0e0n) transmitting data of uf0e0w register yes no in token received? yes no prot = 1? (uf0is1) no yes g h ack received? yes no ep0wc = 1 (uf0fic0) f remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1330 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (5/12) (b) control transfer (read) (3/4) i j no transmit data? e0indt = 1 (uf0is1) ep0nkw = 0 (uf0e0n) e0indtc = 0 (uf0ic1) stg = 1 (uf0is1) yes yes no h intusbf0 active reading uf0isn register e0indt = 1? (uf0is1) no yes data of null packet received? no illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1331 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (6/12) (b) control transfer (read) (4/4) intusbf0 active reading uf0isn register reading uf0isn register transmitting ack intusbf0 active cpudecm = 0 (uf0im1) e0inm = 0 (uf0im1) yes stg = 1? (uf0is1) no yes suces = 1? (uf0is1) no stgm = 1 (uf0im1) suces = 1 (uf0is1) sucesc = 0 (uf0ic1) e0inc = 0 (uf0ic1) end j illegal processing illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1332 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (7/12) (c) control transfer (write) (1/4) clearing uf0e0r register c k g intusbf0 active yes normal reception? no ep0rc = 1 (uf0fic0) no prot = 1? (uf0is1) yes yes out token received? no writing uf0e0r register e0odt = 1 (uf0is1) ep0r = 1 (uf0eps0) ep0nkr = 1 (uf0e0n) reading uf0isn register remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1333 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (8/12) (c) control transfer (write) (2/4) c data length other than 0? no yes l e0odt = 0 (uf0is1) ep0r = 0 (uf0eps0) ep0nkr = 0 (uf0e0n) yes data length other than 0? no yes e0odt = 1? (uf0is1) no reading uf0e0r register data length = data length ? 1 no data length other than 0? yes updating data length of uf0e0l register updating data length of uf0e0l register uf0e0l register data is read up to the value read by the uf0e0r register. k illegal processing remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1334 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (9/12) (c) control transfer (write) (3/4) l intusbf0 active no stg = 1? (uf0is1) yes stg = 1 (uf0is1) e0in = 1 (uf0is1) reading uf0isn register g clearing read data no prot = 1? (uf0is1) yes request processing ep0wc = 1 (uf0fic0) e0ded = 1 (uf0dend) m illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1335 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (10/12) (c) control transfer (write) (4/4) yes yes in token received? no yes suces = 1? (uf0is1) no intusbf0 active transmitting data of null packet reading uf0isn register suces = 1 (uf0is1) e0indt = 1 (uf0is1) sucesc = 0 (uf0ic1) e0indtc = 0 (uf0ic1) e0inc = 0 (uf0ic1) cpudecm = 0 (uf0im1) e0inm = 0 (uf0im1) stgm = 1 (uf0im1) e0inm = 1 (uf0im1) ack received? no end m illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1336 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (11/12) (d) control transfer (without data stage) (1/2) d yes stg = 1? (uf0is1) no yes in token received? no e0ded = 1 (uf0dend) e0in = 1 (uf0is1) stg = 1 (uf0is1) intusbf0 active reading uf0isn register ep0wc = 1 (uf0fic0) g request processing aborted no prot = 1? (uf0is1) yes in token of status phase n illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1337 of 1817 sep 19, 2011 figure 22-24. cpudec request for control transfer (12/12) (d) control transfer (without data stage) (2/2) yes yes in token received? no yes suces = 1? (uf0is1) no intusbf0 active transmitting data of null packet reading uf0isn register suces = 1 (uf0is1) e0indt = 1 (uf0is1) sucesc = 0 (uf0ic1) e0inc = 0 (uf0ic1) e0indtc = 0 (uf0ic1) e0inm = 0 (uf0im1) cpudecm = 0 (uf0im1) e0inm = 1 (uf0im1) stgm = 1 (uf0im1) ack received? no end request processing n illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1338 of 1817 sep 19, 2011 (4) processing for bulk transfer (in) bulk transfer (in) is allocated to endpoint1 and endpoint 3. the flowchart shown below illustrates how endpoint1 is controlled. endpoint3 can also be controlled in the same s equence. to use this flowchart as the control flow of endpoint3, therefore, read the bit names of endp oint1 in the flowchart as those of endpoint3. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1339 of 1817 sep 19, 2011 figure 22-25. processing for bulk transfer (in) (endpoint1) yes bki1in = 1? (uf0is2) no yes bki1dt = 1? (uf0is2) no yes no transmit data? no yes in token received? no parallel processing by hardware end end start bki1in = 1 (uf0is2) returning nak intusbf0 active bki1ded = 1 (uf0dend) no yes bki1cc = 1 (uf0fic0) intusbf0 active reading uf0isn register bki1inc = 0 (uf0ic2) bki1dtc = 0 (uf0ic2) bki1inm = 0 (uf0im2) data error? reading uf0isn register writing uf0bi1 register bki1nk = 1 (uf0en) bki1dt = 1 (uf0is2) bki1inm = 1 (uf0im2) if return data greater than the fifo size exists, it is divided into fifo size units and sequentially written, starting from the lowest data byte. the timing of the bit value varies depending on the situation on the sie side. illegal processing illegal processing : see figure 22-26 parallel processing by hardware . fifo full? no yes remarks 1. n = 2, 3 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1340 of 1817 sep 19, 2011 figure 22-26. parallel processing by hardware yes yes in token received? no transmitting data of uf0bi1 register ack received? no yes no transmit data? no bki1nk = 0 (uf0en) remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1341 of 1817 sep 19, 2011 (5) processing for bulk transfer (out) bulk transfer (out) is allocated to endpoint2 and endpoi nt4. the flowchart shown below illustrates how endpoint2 is controlled. endpoint4 can also be controlled in the same sequence. to use this flowchart as the control flow of endpoint4, therefore, read the bit names of endp oint2 in the flowchart as those of endpoint4. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1342 of 1817 sep 19, 2011 figure 22-27. normal processing for bulk transfer (out) (endpoint2) yes out token received? no yes bko1dt = 1? (uf0is3) no yes data length = 0? no no out token received? yes end start writing uf0bo1 register bko1dt = 1 (uf0is3) bkout1 = 1 (uf0eps0) clearing uf0bo1 register yes no normal reception? intusbf0 active reading uf0isn register bko1dt = 0 (uf0is3) bkout1 = 0 (uf0eps0) updating data length of uf0bo1l register reading uf0bo1 register data length = data length ? 1 updating data length of uf0bo1l register no data length other than 0? yes uf0bo1 register data is read up to the value read by the uf0bo1l register. illegal processing illegal processing remarks 1. n = 2, 3 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1343 of 1817 sep 19, 2011 during bulk transfer (out), more data may be transmitte d from the host than expected by the system. endpoint2 and endpoint4 for bulk transfer (out) of the v850es/jh3- e and v850es/jj3-e consist of two 64-byte buffers so that nak responses are suppressed as much as possible and data can be read from the cpu side even while the bus side is being accessed as the transfer rate of the usb bus increases. consequently, if the host sends more data than expected by the system, up to 128 bytes of extr a data may be automatically received in the worst case. in this case, change the control flow from that of the normal processing of endpoint2 and endpoint4 to the flow illustrated below when the qu antity of data expected by the system has de creased to two packets. this flowchart illustrates how endpoint2 is controlled. endpoint4 can al so be controlled in the same sequence. to use this flowchart as the control flow of endpoint4, therefore, read the bit names of endpoint2 in the flowchart as those of endpoint4. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1344 of 1817 sep 19, 2011 figure 22-28. processing if more data than expect ed by system is transm itted (endpoint2) (1/2) yes out token received? no yes out token received? no yes bko1fl = 1? (uf0is3) no start writing uf0bo1 register bko1dt = 1 (uf0is3) bkout1 = 1 (uf0eps0) intusbf0 active clearing uf0bo1 register yes normal reception? no writing uf0bo1 register reading uf0isn register bko1nkm = 1 (uf0enm) bko1fl = 1 (uf0is3) bko1nk = 1 (uf0en) clearing uf0bo1 register yes normal reception? no i updating data length of uf0bo1l register bko1nk = 1 (uf0en) illegal processing remarks 1. n = 2, 3 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1345 of 1817 sep 19, 2011 figure 22-28. processing if more data than expect ed by system is transm itted (endpoint2) (2/2) yes out token received? no yes next system sequence? no bko1nak = 1 (uf0is3) nak response intusbf0 active bko1nkm = 0 (uf0enm) bko1nk = 0 (uf0en) expected system sequence processing expected processing such as endpoint stall bko1nkm = 0 (uf0enm) bko1nk = 0 (uf0en) bko1nakc = 0 (uf0ic3) yes bko1nak = 1? (uf0is3) no end end reading uf0bo1 register bko1fl = 0 (uf0is3) reading uf0bo1 register data length = data length ? 1 no data length other than 0? yes uf0bo1 register data is read up to the value read by the uf0bo1l register. uf0bo1 register data is read up to the value read by the uf0bo1l register. updating data length of uf0bo1l register bko1dt= 0 (uf0is3) bkout1 = 0 (uf0eps0) data length = data length ? 1 no data length other than 0? yes i illegal processing remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1346 of 1817 sep 19, 2011 (6) processing for interrupt transfer (in) interrupt transfer (in) is allocated to endpoint7. the flowchart is shown in figure 22-29 . figure 22-29. processing for interrupt transfer (in) (endpoint7) reading uf0eps0 register writing uf0int1 register transmitting data of uf0int1 register it1nk = 1 (uf0en) fif o full? no no data error? yes it1dend = 1 (uf0dend) itr1c = 1 (uf0fic0) yes in token received? no yes it1dt = 1? (uf0is2) no yes ac k received? no yes yes it1 = 0? (uf0eps0) no end start it1dt = 1 (uf0is2) it1 = 0 (uf0eps0) it1nk = 0 (uf0en) intusbf0 active reading uf0isn register it1dtc = 0 (uf0ic2) yes no transmit data? no illegal processing remarks 1. n = 2, 3 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1347 of 1817 sep 19, 2011 22.9.4 suspend/resume processing how suspend/resume processing is performed differs depending on the configuration of t he system. one example is given below. figure 22-30. example of suspend/resume processing (1/3) (a) example of suspend processing rsuspd = 1 (uf0is0) rsum = 1 (uf0eps1) yes suspend detected? no yes rsuspd = 1? (uf0is0) no yes rsum = 1? (uf0eps1) no start end intusbf0 active reading uf0isn register reading uf0eps1 register fw suspend processing rsuspdc = 0 (uf0ic0) illegal processing illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1348 of 1817 sep 19, 2011 figure 22-30. example of suspend/resume processing (2/3) (b) example of resume processing rsuspd = 1 (uf0is0) rsum = 0 (uf0eps1) yes resume detected? no yes rsuspd = 1? (uf0is0) no yes rsum = 0? (uf0eps1) no start end intusbf0 active reading uf0isn register reading uf0eps1 register fw resume processing rsuspdc = 0 (uf0ic0) illegal processing illegal processing remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1349 of 1817 sep 19, 2011 figure 22-30. example of suspend/resume processing (3/3) (c) example of resume processing (when supply of usb clock to usbf is stopped) intusbf1 active yes resum e detected? no start end executing interrupt servicing supplying usb clock fw resum e processing remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1350 of 1817 sep 19, 2011 22.9.5 processing after power application the processing to be performed after power application differs depending on the configuration of the system. one example is given below. figure 22-31. example of processing afte r power application/power failure (1/3) (a) processing after power application (1/2) yes resume detected? no start start controlling port note 2 pull-up processing of d+ inactive note 1 pull-up processing of d+ active note 1 connection controlling port note 2 busrst = 1 (uf0is0) dflt = 1 (uf0mods) initialization of request data register initialization of request data register : see figure 22-15 initialization settings of request data register . : see figure 22-15 initialization settings of request data register . (a) notes 1. use one general-purpose port pin for the signal that controls switching of the pull-up resistor of the usb bus. 2. the input mode or control mode of th e general-purpose port pin allocated in note 1 may be selected as the default value. note the active level of pull-up processing of d+ on power application. remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1351 of 1817 sep 19, 2011 figure 22-31. example of processing afte r power application/power failure (2/3) (a) processing after power application (2/2) receiving get_descriptor device request mpack = 1 (uf0mods) receiving set_address request writing uf0adrs register receiving set_configuration 1 request receiving set_interface request processing continues setcon = 1 (uf0set) setrq = 1 (uf0is0) conf = 1 (uf0mods) uf0cnf register = 01h valid endpoint = data0 setint = 1 (uf0is4) setting of uf0ass register setting of uf0ifm register valid endpoint = data0 (a) remarks 1. m = 0 to 4 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1352 of 1817 sep 19, 2011 figure 22-31. example of processing afte r power application/power failure (3/3) (b) processing on power failure yes intpxx active note ? no interrupt servicing processing such as clearing fifo or mrst = 1 (uf0gpr) start end power failure note intpxx indicates the external interrupt pins of the v850es/jh3-e and v850es/jj3-e (intp00 to intp25), and also indicates interrupts input by the external trigger pins (tiaa00, taa01, tiaa10, tiaa11, tiaa20, tiaa21, tiaa30, tiaa31, tiaa40, tiaa40, tiaa 50, tiaa51, tiab00, trgab1, tenc00) of the timer. allocate one external interrupt pin to the following applications. ? detecting disconnection of the connector in the case of self-powered m ode (sfpw bit of uf0dstl register = 1). in this case, monitor the vdd li ne of the usb connector, and input the result to the external interrupt pin at the edge. note that the nois e elimination time is that of the interrupt input pin, and that of each timer. ? detecting turning off power from the hub when the device is mounted on the same board as a hub chip. remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1353 of 1817 sep 19, 2011 22.9.6 receiving data for bulk transfer (out) in dma mode bulk transfer (out) is allocated to endpoint2 and endpoint4. the flowchart shown below illustrates how endpoint2 is controlled when dma is used. endpoint4 can also be controlled in the same sequence. to use this flowchart as the control flow of endpoint4, therefore, re ad the bit names of endpoint2 in the flowchart as those of endpoint4. the control flowchart shown below illustrates how remaining data is read by the cpu. if data for bulk transfer (out) has been correctly received by setting the dqbo1ms bit of t he uf0idr register to 1, the dma request signal for endpoint2, instead of an interrupt re quest (intusbf0), becomes active. this dma request signal for endpoint2 operates according to the setti ng of the moden bit of the uf0idr register (n = 0, 1). if all the data stored in the uf0bo1 register has been read by dma, the dma request signal for endpoint2 becomes inactive. in this status, if data for the next bulk transfer (out) has been correctly re ceived, the dma request signal for endpoint2 becomes active again. if the data for bulk transfer (out) that has been receiv ed is equal to or less than the fifo size, a short interrupt request is issued and the intusbf0 (ep 2_endint) signal becomes active, as soon as reading the data by dma is completed. to read data by dma again, set the dqbo1ms bit to 1 again. if dma is completed by the dma end signal for endpoint2, the dqbo1ms bit of the uf0idr register is cleared to 0, and the dma request signal for endpoint2 becomes inactive. at the same time, the dma_end interrupt request is issued. if data remains in the uf0bo1 register at this time, dma can be started again by setting the dqbo1ms bit of the uf 0idr register again. however, the data for bulk transfer (out) is always equal to or less than the fifo size. cons equently, a short interrupt request is issued, the intusbf0 (ep2_endint) signal becomes active, the dqbo1ms bit is cleared, and the dma request signal for endpoint2 becomes inactive, as soon as the data is read by dma. cautions 1. the dma request signal for endpoint n (n = 2, 4) becomes active in the demand mode (mode1 and mode0 bits of the uf0idr register = 10), as long as there is data to be transferred. 2. for a dma transfer for which the data for a bulk transfer (out) is a short packet (63 bytes or less), after the transfer finishes, clear the uf0ic0.shortc and uf0is0.short bits. if the short bits are not cleared, the dmastop_epnb signal is asserted and the next dma transfer operation is not performed. v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1354 of 1817 sep 19, 2011 (1) initial settings for a bulk transfer (out: ep2, ep4) (a) initial settings for dmac - the dsan registers (n = 0 to 3) are set to 00210000h (for ep2) or 00220000h (for ep4). - the dadcn registers (n = 0 to 3) are set to 0080h. (8-bit transfer, transfer source address: fixed, transfer destination address: incremental) - the dtfrn registers (n = 0 to 3) are set to 0000h. - the ufdrqen register is set up acco rding to the dma channel to be used. (for details, see 21.6.10 (1) usbf dm a request enable register (ufdrqen).) (b) initial settings for epc - the uf0idr register is set to 12h (for ep2) or 22h (for ep4) (demand mode). - the uf0im0.dmaedm bit = 0 - the uf0im3.bko1nlm bit = 0 (for ep2) - the uf0im3.bko1dtm bit = 0 (for ep2) - the uf0im3.bko2nlm bit = 0 (for ep4) - the uf0im3.bko2dtm bit = 0 (for ep4) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1355 of 1817 sep 19, 2011 figure 22-32. dma processing by bulk transfer (out) (1/3) start setting dma channel 2 setting address (dda2) of transfer destination (internal data ram) setting address (dsa2) of transfer source (endpoint2 (uf0bo1)) dbc2 dadc2 register = 0080h setting dma channel 3 setting address (dda3) of transfer destination (endpoint1 (uf0bi1)) setting address (dsa3) of transfer source (internal data ram) dbc3l register = 003fh* dadc3 register = 0020h (4) (3) *: when transferring less than 64 bytes, change the set value. *: release the mask setting of the necessary interrupts yes transfer of dma channel 3 is completed? no (2) (1) usb setting (dma related) ? dmaedm = 0 (uf0im0)* ? bki1nm = 0 (uf0im2) ? bki1dtm = 0 (uf0im2) ? bko1nlm = 0 (uf0im3) ? bko1dtm = 0 (uf0im3) setting dma channel 2 e22 = 1 (dchc2) dtfr2 register = 00h the use of an interrupt request signal as the dma start trigger is disabled. dqbo1ms = 1(uf0idr) uf0e2dc1 = 0001h setting dma channel 3 e33 = 1 (dchc3) dtfr3 register = 00h the use of an interrupt request signal as the dma start trigger is disabled. dqbi1ms = 1 (uf0idr) uf0e1dc1 = 0001h specifying dma channel and transfer destination endpoint using ufdrqen register uf0idr register = 02h (setting demand mode) remarks 1. the above flowchart shows the case where the tr ansfer by dma channel 2 is from endpoint2 to internal data ram, and the transfer by dma channel 3 is from internal data ram to endpoint1. 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1356 of 1817 sep 19, 2011 figure 22-32. dma processing by bulk transfer (out) (2/3) (3) yes the number of dma channel 3 transfers has been changed? no moving to intdma3 interrupt vector changing the set value of dbc3l register (1) (3) dma channel 3 transfer completion tc3 = 1 (dchc3) dqbi1ms = 0 (uf0idr) clearing dma channel 3 transfer request *: re-set dma channel 3 setting dma channel 3 e33 = 1 (dchc3) dqbi1ms = 1 (uf0idr)* each bit cleared by reading uf0dmsi tc3 bit cleared by reading dchc3 remarks 1. the above flowchart shows the case where the tr ansfer by dma channel 2 is from endpoint2 to internal data ram, and the transfer by dma channel 3 is from internal data ram to endpoint1. 2. n = 0, 1 3. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1357 of 1817 sep 19, 2011 figure 22-32. dma processing by bulk transfer (out) (3/3) (2) yes dma channel 2 transfer completed? no moving to intdma2 interrupt vector dma channel 2 transfer completion tc2 = 1 (dchc2) dqbo1ms = 0 (uf0idr) clearing dma channel 2 transfer request each bit cleared by reading uf0dmsi tc2 bit cleared by reading dchc2 an interrupt occurred when receiving endpoint2 data. confirm data reception. cancel transfer when null packet is received. *: after setting the number of dma channel 2 transfers moving to intusbf0 interrupt vector reading uf0is3 register reading uf0bo1 register starting transfer of dma channel 2 yes intusbf0 interrupt occurred? no yes bko1dt = 1 (uf0is3)? no yes bko1nl = 1? (uf0is3) no setting dma channel 2 dbc2l = uf0bo1l ? 1* e22 = 1 (dchc2) dqbo1ms = 1 (uf0idr) (4) (4) remarks 1. the above flowchart shows the case where the tr ansfer by dma channel 2 is from endpoint2 to internal data ram, and the transfer by dma channel 3 is from internal data ram to endpoint1. 2. n = 0, 1 m = 2, 3 3. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1358 of 1817 sep 19, 2011 22.9.7 transmitting data for bulk transfer (in) in dma mode bulk transfer (in) is allocated to endpoint1 and endpoint3. the flowchart shown below illustrates how endpoint1 is controlled when dma is used. endpoint3 can also be controlled in the same sequence. to use this flowchart as the control flow of endpoint3, therefore, read the bit names of endpoint1 in the flowchart as those of endpoint3. if data for bulk transfer (in) can be written by setting the dqbi1ms bit of the uf0idr regi ster to 1, the dma request signal for endpoint1, instead of an interr upt request (intusbf0), becomes active. this dma request signal for endpoint1 operates according to the setting of the mo den bit of the uf0idr register (n = 0, 1). if all the data that can be written to the uf0bi1 register has been written by dma, the dma request signal for endpoint1 becomes inactive. in this status, the toggle operation of the fifo takes place and, if data for bulk transfer (in) can be written, the dma request signal for endpoint1 becomes active again. the automatic toggle opera tion of the fifo is not ex ecuted even if the fifo has become full as a result of dma transfer, unl ess the bki1t bit of the uf0dend register is set to 1. therefore, be sure to set the bki1ded bit of the uf0dend register to 1 to trans fer data. if dma is completed by the dma end signal for endpoint1, the dqbi1ms bit of the uf0idr register is cl eared to 0, and the dma request signal for endpoint1 becomes inactive. at the same time, the dma_end interrupt request is issued. to transmit a short packet at this time when the fifo is not full, set the bki1ded bi t of the uf0dend register to 1. cautions 1. the dma request signal for endpoint n (n = 1, 3) becomes active in the demand mode (mode1 and mode0 bits of the uf0idr register = 10), as long as data can be transferred. 2. the dma request signal for endpoint n (n = 1, 3) becomes active in th e single mode (mode1 and mode0 bits of the uf0idr re gister = 0x (x: don?t care)) if data can be transferred, but this signal becomes inactive each time one byte has been transferred. this op eration is repeated until there is no more data to be transferred. (1) initial settings for a bulk transfer (in: ep1, ep3) (a) initial settings for dmac - the ddan registers (n = 0 to 3) are set to 00201000h (for ep1) or 00202000h (for ep3). - the dadcn registers (n = 0 to 3) are set to 0020h. (8-bit transfer, transfer source address: incremental, transfer destination address: fixed) - the dtfrn registers (n = 0 to 3) are set to 0000h. - the ufdrqen register is set up acco rding to the dma channel to be used. (for details, see 21.6.10 (1) usbf dm a request enable register (ufdrqen).) (b) initial settings for epc - the uf0idr register is set to 42h (for ep1) or 82h (for ep3) (demand mode). - the uf0im0.dmaedm bit = 0 - the uf0im2.bki1nlm bit = 0 (for ep1) - the uf0im2.bki1dtm bit = 0 (for ep1) - the uf0im2.bki2nlm bit = 0 (for ep3) - the uf0im2.bki2dtm bit = 0 (for ep3) v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1359 of 1817 sep 19, 2011 figure 22-33. dma processing by bulk transfer (in) (1/4) start setting modex (uf0idr) dqbi1ms = 1 (uf0idr) dqe1 = 1 (uf0dms0) no fifo on cpu side full? yes mode1, mode0 = 1 0: demand mode mode1, mode0 = 0 x: single mode (x = don?t care) yes fifo full? no no tc signal received? yes dma request for endpoint1 active writing uf0bi1 register by dma if return data greater than the fifo size exists, it is divided into fifo size units, and sequentially written, starting from the lowest data byte. (3) (5) (1) yes bki1t = 1? (uf0dend) no (2) remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1360 of 1817 sep 19, 2011 figure 22-33. dma processing by bulk transfer (in) (2/4) end bki1nk = 1 (uf0en) note bki1dt = 1 (uf0is2) note dqe1 = 0 (uf0dms0) dma request for endpoint1 inactive parallel processing by hardware (3) (2) : see figure 22-26 parallel processing by hardware . note the timing of the bit value changes depending on the status on the sie side. remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1361 of 1817 sep 19, 2011 figure 22-33. dma processing by bulk transfer (in) (3/4) (1) intusbf0 active dma request for endpoint1 inactive bki1nk = 1 (uf0en) note bki1dt = 1 (uf0is2) note dqe1 = 0 (uf0dms0) dede1 = 1 (uf0dms1) dmaed = 1 (uf0is0) dqbi1ms = 0 (uf0idr) dqe1 = 0 (uf0dms0) dede1 = 1 (uf0dms1) dmaed = 1 (uf0is0) dqbi1ms = 0 (uf0idr) yes dmaed = 1? (uf0is0) no yes dede1 = 1? (uf0dms1) no no yes yes bki1t = 1? (uf0dend) fifo full? no reading uf0isn register reading uf0dmsn register (4) illegal processing illegal processing note the timing of the bit value changes depending on the status on the sie side. remarks 1. n = 0, 1 2. ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 22 usb function controller (usbf) r01uh0290ej0300 rev.3.00 page 1362 of 1817 sep 19, 2011 figure 22-33. dma processing by bulk transfer (in) (4/4) (5) end dmaedc = 0 (uf0ic0) (5) no yes yes bki1t = 1? (uf0dend) fifo full? no bki1ded = 1 (uf0dend) bki1nk = 1 (uf0en) note bki1dt = 1 (uf0is2) note bki1cc = 1 (uf0fic0) dmaedc = 0 (uf0ic0) no data error? yes (4) parallel processing by hardware : see figure 22-26 parallel processing by hardware . note the timing of the bit value changes depending on the status on the sie side. remark ? : processing by hardware v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1363 of 1817 sep 19, 2011 chapter 23 ethernet controller 23.1 general the ethernet controller includes a 10/ 100 mbps ethernet media access controll er (mac) conforming to ieee802.3, a fifo controller for flow control, and a checksum calculatio n unit (only for received packets) conforming to rfc1071. 23.1.1 functions (1) mac ? 10/100 mbps full-duplex communication, half-duplex co mmunication, and flow control conforming to ieee802.3 (1998 edition) supported ? mii supported as physical layer device (phy) interface ? accessing phy registers via serial management interface supported ? statistics counter to support rmon/snmp (rfc2665, rfc2819) ? packet filtering based on address types ? vlan frame detection (2) fifo ? transmit/receive fifo size: transmit fifo = 2 kb, receive fifo = 2 kb ? fifo status register ? interrupts generated by transmission/ reception status and fifo status (3) dmac in ethernet controller ? data transfer (dma) ? reception status dma transfer ? reading (in pointer chain format), analyzing, and writing back buffer descriptors ? controlling interrupts in packet transfers (4) checksum calculation ? receive checksum calculation conforming to rfc1071 the mac header and fcs of a received packet are autom atically identified and t he checksum, excluding the dummy header, for verifying the received packet is generated. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1364 of 1817 sep 19, 2011 23.2 configuration 23.2.1 system configuration the ethernet controller transmits or re ceives data by using a dedicated direct memory access controller (dmac). the ethernet controller supports the mii (medi a independent interface) of ieee802.3 an d can create a 10 mbps or 100 mbps ethernet environment when it is connected to a phy device c onforming to mii. in addition, data can be communicated in full-duplex or half-duplex mode, which can be selected. figure 23-1. configuration of ethernet controller mii i/o buffer tpo+ tpo ? tpi+ tpi ? phy mac fifo controller transmit fifo (2 kb) receive fifo (2 kb) receive checksum unit dmac in ethernet controller internal bus (1) mac this unit executes mac functions and supports mii-based interfacing with an external phy device. ? receive checksum unit this unit calculates the receive checksum. (2) fifo controller this unit controls the transmit/receive fifo buffers. a 2 kb fifo is available for both transmission and reception. (3) dmac in ethernet controller this dma controller controls data transmission and reception to and from the internal bus. caution the dmac in the ethernet controller processes all the data the ethernet controller transmits and receives. data cannot be transmi tted or received in packet units by reading or writing a register. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1365 of 1817 sep 19, 2011 23.2.2 interrupt requests the interrupt sources of the ether net controller are listed below. table 23-1. interrupt request signals interrupt request interrupt source intetmrq ethernet receive data ready interrupt received packet read request packet reception (dma) completion interrupt (rxi) reception (dma) end of chain interrupt (reci) intetmrx ethernet packet reception interrupt receive data buffer access error interrupt (rbei) packet transmission (dma) completion interrupt (txi) transmission (dma) end of chain interrupt (teci) intetmtx ethernet packet transmission interrupt transmit data buffer access error interrupt (tbei) intetmfs ethernet fifo status interrupt fifo status (fstatus) interrupt intetmts ethernet transmission status interrupt transmission status (txstatus) interrupt intetmrs ethernet reception status interrupt reception status (rxstatus) interrupt intetmov ethernet mac interrupt statis tics counter overflow (carry status) intetber ethernet error interrupt occurrence of communication error ? each interrupt source can be masked. if an interrupt source is generated while the interrupt is masked, the corresponding status register is set but the interrupt request is not generated. ? it is recommended to read the interrupt register if two or more sources are generated at the same time. 23.3 initialization before using the ethernet controlle r of the v850es/jx3-e, initialize it using the following procedure. <1> enable operation of the ethernet controller. <2> initialize media access controller (mac). <3> initialize fifo controller. <4> initialize dma controller. <5> set the relevant interrupts. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1366 of 1817 sep 19, 2011 figure 23-2. initializing the ethernet controller (1/2) start a execute a software reset on the mac block. execute a software reset on the serial management interface block. specify the mac operating mode. set the miien bit of the miictl register to 1 to enable operation of the ports related to the ethernet controller. access the miictl register in 8-bit units. clear the statistics count register. after specifying the operating mode of the mac, execute a software reset on the mac block by using the mcrst, rfrst, and tfrst bits of the macc2 register note 1 . specify the operating mode of the mac by using the macc1 and macc2 registers. after executing a software reset on the fifo block, specify the operating mode of the fifo block by using the mffcont register. execute a software reset on the serial management interface block by using the mirst bit of the miic register note 2 . execute a software reset on the fifo block by using the sftrst bit of the rstcnt register note 3 . set the ipgt, ipgr, clrt, lmax, lsa1, lsa2, vlpt, afr, ht1, ht2, car1, and car2 registers. after executing a software reset on the serial management interface block, specify the operating mode of the mii by using the miic register. execute a software reset on the fifo block. specify the operating mode of the fifo block. specify the mii operating mode clear the statistics counter. set the registers of the mac. miictl = 01h notes 1. cancel the mac block software reset by setti ng the mcrst, rfrst, and tfrst bits of the macc2 register to 1 simultaneously, then simultaneously cl earing them to 0. leave an interval of at least 5 txclk clock cycles between setting and clear ing the mcrst, rfrst, and tfrst bits. 2. cancel the serial management interface block softw are reset by setting the mirst bit of the miic register to 1 and then clearing it to 0. leave an interval of at least 5 ethernet controller clock (f ec ) cycles between setting and clearing the mirst bit. 3. the sftrst bit of the rstcnt register clears automatically after being set to 1. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1367 of 1817 sep 19, 2011 figure 23-2. initializing the ethernet controller (2/2) end a execute a software reset on the dmac block clear the status interrupt sources of the fifo block enable or disable reception checksum addition by using the rxchksmen bit of the transctl register. enable fifo transmission and reception by setting the rxen and txen bits of the mffcont register to 1. enable dma controller transmission and reception by setting the rxen and txen bits of the transctl register to 1. enable the mac block reception data interface by setting the rxen and txen bits of the macc1 register to 1. clear the intms register note 3 . after resetting the dmac block, stop dma transmission and reception by using the txen and rxen bits of the transctl register. the dma operating status is reflected in the txen_sta and rxen_sta bits of the transctl register. specify the type of dma transfer executed by the dma controller by using the dmacm register. mask interrupts by using the fstatus_mask, tx_status_mask, rxstatus_mask, and intms registers. prohibit or allow cpu interrupts by using the etmrxic, etmtxic, etmrqic, etmfsic, etmtsic, etmrsic, etmovic, and etberic registers. set the flowthresh, pausetm, rxersel, txabtcnt, and rxabtcnt registers. clear the fstatus, txstatus, and rxstatus registers note 1 . execute a software reset on the dmac block by using the sftrst bit of the sftrst register note 2 . enable mac reception enable dmac transmission and reception prohibit or allow interrupts enable fifo transmission and reception stop dma transmission and reception specify the dma transfer type clear the interrupt sources of the dmac block enable or disable reception checksum addition mask interrupts set the registers of the fifo block notes 1. the fstatus, txstatus, and rxstatus registers are cleared when they are read. 2. the sftrst bit of the sftrst register clears automatically after being set to 1. 3. the source bits of the intms register (rbei, reci, rxi , tbei, teci, and txi) are cleared when they are read. remark for details of the etmrxic, etmtxic, etmrqic , etmfsic, etmtsic, etmrsic, etmovic, and etberic registers, see chapter 25 interrupt/exception processing function . v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1368 of 1817 sep 19, 2011 23.4 registers for controlling the ethernet controller (1) register setting procedure to update the values of the control re gisters, make sure that transmission and reception of frames and dma are stopped. if these registers are updated while fr ames are being transmitted and received, or while dma is in progress, the operation is not guaranteed. when using the ethernet controller, the ethernet control register (miictl) mu st be set in order to enable operation of the used ports. (2) miictl: ethernet control register access this register can be read and written in 8-bit units. address ffff fbe0h default value 00h. this register is cleared to its default value by all types of resets. 7 6 5 4 3 2 1 <0> 0 0 0 0 0 0 0 miien r r r r r r r r/w bit name function 0 miien controls the operation of the ports related to the ethernet controller. 0: disable operation 1: enables operation caution after setting the miictl register , set the fifo controller control re gister (mffcont). for details, see 23.4.3 (1) mffcont: fifo controller control register. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1369 of 1817 sep 19, 2011 (3) register list table 23-2. register list (mac) (1/2) r/w bit manipulation unit offset address symbol register name 8 16 32 default value 002e 0000h macc1 mac setting register 1 r/w 00000000h 002e 0004h macc2 mac setting register 2 r/w 00000000h 002e 0008h ipgt back-to-back ipg register r/w 00000013h 002e 000ch ipgr non back-to-back ipg register r/w 00000e13h 002e 0010h clrt collision register r/w 0000380fh 002e 0014h lmax maximum packet length register r/w 00000600h 002e 0054h lsa1 station address register 1 r/w 00000000h 002e 0058h lsa2 station address register 2 r/w 00000000h 002e 005ch ptvr pause timer value read register r 00000000h 002e 0064h vltp vlan type register r/w 00000000h 002e 0080h miic mii configuration register r/w 00000000h 002e 0094h mcmd mii command register w 00000000h 002e 0098h madr mii address register r/w 00000000h 002e 009ch mwtd mii write data register r/w 00000000h 002e 00a0h mrdd mii read data register r/w 00000000h 002e 00a4h mind mii indicator register r 00000000h 002e 00c8h afr address filter register r/w 00000000h 002e 00cch ht1 hash table register 1 r/w 00000000h 002e 00d0h ht2 hash table register 2 r/w 00000000h 002e 00dch car1 carry register 1 r/w 00000000h 002e 00e0h car2 carry register 2 r/w 00000000h 002e 0130h cam1 carry mask register 1 r/w 00000000h 002e 0134h cam2 carry mask register 2 r/w 00000000h 002e 0140h rbyt reception byte counter r/w 00000000h 002e 0144h rpkt reception packet counter r/w 00000000h 002e 0148h rfcs reception fcs error frame counter r/w 00000000h 002e 014ch rmca reception multicast packet counter r/w 00000000h 0002e 150h rbca reception broadcast packet counter r/w 00000000h 002e 0154h rxcf reception control frame packet counter r/w 00000000h 002e 0158h rxpf reception pause frame packet counter r/w 00000000h 002e 015ch rxuo reception undefined control packet counter r/w 00000000h 002e 0160h raln reception alignment error counter r/w 00000000h 002e 0164h rflr reception frame length error counter r/w 00000000h 002e 0168h rcde reception code error counter r/w 00000000h 002e 016ch rfcr reception false carrier counter r/w 00000000h 002e 0170h rund reception undersize packet counter r/w 00000000h 002e 0174h rovr reception oversize packet counter r/w 00000000h 002e 0178h rfrg reception fragment counter r/w 00000000h 002e 017ch rjbr reception jabber counter r/w 00000000h v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1370 of 1817 sep 19, 2011 table 23-2. register list (mac) (2/2) r/w bit manipulation unit offset address symbol register name 8 16 32 default value 002e 0180h r64 receive 64-byte frame counter r/w 00000000h 002e 0184h r127 receive 65- to 127-byte frame counter r/w 00000000h 002e 0188h r255 receive 128- to 255-byte frame counter r/w 00000000h 002e 018ch r511 receive 256- to 511-byte frame counter r/w 00000000h 002e 0190h r1k receive 512- to 1023-byte frame counter r/w 00000000h 002e 0194h rmax receive 1024- to rmax-byte frame counter r/w 00000000h 002e 0198h rvbt receive valid byte counter r/w 00000000h 002e 01c0h tbyt transmission byte counter r/w 00000000h 002e 01c4h tpkt transmission packet counter r/w 00000000h 002e 01c8h tfcs transmission fcs error frame counter r/w 00000000h 002e 01cch tmca transmission multicast packet counter r/w 00000000h 002e 01d0h tbca transmission broadcast packet counter r/w 00000000h 002e 01d4h tuca transmission unicast packet counter r/w 00000000h 002e 01d8h txpf transmission paus e control frame counter r/w 00000000h 002e 01dch tdfr transmission delay packet counter r/w 00000000h 002e 01e0h txdf transmission exce ssive delay packet counter r/w 00000000h 002e 01e4h tscl transmission single collision packet counter r/w 00000000h 002e 01e8h tmcl transmission multiple collision packet counter r/w 00000000h 002e 01ech tlcl transmission late collision packet counter r/w 00000000h 002e 01f0h txcl transmission excessive collision packet counter r/w 00000000h 002e 01f4h tncl transmission total collision counter r/w 00000000h 002e 01f8h tcse transmission carrier sense error counter r/w 00000000h 002e 01fch time mac internal error counter r/w 00000000h v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1371 of 1817 sep 19, 2011 table 23-3. register list (fifo controller) r/w bit manipulation unit offset address symbol register name 8 16 32 default value 002e 0200h mffcont fifo controller control register r/w 00000000h 002e 0204h rstcnt software reset control register r/w 00000000h 002e 0218h flowthresh flow control threshold value register r/w 06000200h 002e 021ch pausetm pause timer value register r/w 7fffffffh 002e 0220h rxersel receive error selection register r/w 00000001h 002e 0230h txstmoni1 transmission status monitor 1 register r 00000000h 002e 0234h txstmoni2 transmission status monitor 2 register r 00000000h 002e 0238h txfinf1 transmission status 1 register r 00000800h 002e 023ch txfinf2 transmission status 2 register r 00000001h 002e 0240h rxstmoni reception status monitor register r 00000000h 002e 0244h rxfinf1 reception status 1 register r 00000000h 002e 0248h rxfinf2 reception status 2 register r 00000800h 002e 024ch rxfinf3 reception status 3 register r 00000001h 002e 0250h fstatus fifo status interrupt register r 00000000h 002e 0254h fstatus_mask fifo status interrupt mask register r/w 01011fffh 002e 0258h txstatus transmission st atus interrupt register r 00000000h 002e 025ch txstatus_mask transmission stat us interrupt mask register r/w 000101ffh 002e 0260h rxstatus reception status interrupt register r 00000000h 002e 0264h rxstatus_mask reception stat us interrupt mask register r/w 00007fffh 002e 0270h txabtcnt transmission abort counter r/w 00000000h 002e 0274h rxabtcnt reception abort counter r/w 00000000h table 23-4. register list (dmac in ethernet controller) r/w bit manipulation unit offset address symbol register name 8 16 32 default value 002e 0300h ethmode core function control register r/w 00000000h 002e 0304h intms interrupt register r/w 07000700h 002e 0308h transctl transmission control register r/w 00030000h 002e 030ch sftrst software reset register r/w 00000000h 002e 0310h dmacm dma controller mode control register r/w 00000010h 002e 0320h rxdp reception descri ptor pointer register r/w fffffffch 002e 0324h lstrxdp last reception de scriptor pointer register r fffffffch 002e 0328h txdp transmission desc riptor pointer register r/w fffffffch 002e 032ch lsttxdp last transmission descriptor pointer register r fffffffch v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1372 of 1817 sep 19, 2011 23.4.1 mac control registers (1) macc1: mac setting register access this register can be read and written in 32-bit units. address 002e 0000h default value 0000 0000h. this register is cleared to its default value by all types of resets. cautions 1. be sure to execute a software reset after setting the oper ation mode. to execute a software reset, set the mcrst, rfrst, and tfrst bits of the macc2 register to 1 at the same time. cancel the software reset by cleari ng these bits to 0 at the same time. 2. be sure to set bits 31 to 15, 13, 12, and 4 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 maclb 0 0 txfc rxfc srxen parf r r/w r r r/w r/w r/w r/w 7 6 5 4 3 2 1 0 purep flcht nobo 0 crcen paden fulld hugen r/w r/w r/w r r/w r/w r/w r/w (1/2) bit name description 14 maclb mac loopback 0: disables loopback operation. 1: operation loops back fr om transmission block to reception block in mac. to execute the loopback operation, set the fulld bit to 1 and enable full-duplex operation. 11 txfc transmission flow control enable 0: disables transmission of a pause contro l frame executed by inputting the tpcf signal. 1: enables transmission of a pause control fr ame executed by inputting the tpcf signal. 10 rxfc reception flow control enable 0: a pause operation is not executed. 1: a pause operation is executed for the pause period set to the pause timer. the value of the pause timer is updated, regardless of the setting of this bit, when a valid pause control frame is received. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1373 of 1817 sep 19, 2011 (2/2) bit name description 9 srxen reception enable 0: reception is disabled. 1: the function of the reception data interface is enabled. if the setting of this bit is changed while the crs signal is asserted, the new setting becomes valid after the crs signal has been deasserted, regardless of the setting of the fulld bit. 8 parf control packet pass 0: a control frame is judged as a control frame. 1: no received packet, including a control frame, is judged as a control frame. the value of the pause timer is not updated even if a valid pause control frame is received, regardless of the setting of the rxfc bit. 7 purep pure preamble 0: the data of a preamble is not checked. 1: a reception status interrupt is generated if an illegal preamble is detected. 6 flcht length field check 0: the length field is not checked. 1: the value of the length field and data field is checked, and a status interrupt is generated. 5 nobo no backoff 0: packets are transmitted by using the backoff algorithm. 1: packets are always transmitted wi thout using the backoff algorithm. 3 crcen crc appending 0: crc is not appended. the end of a transmission packet must be a valid fcs. the mac checks the fcs. if the fcs value is not correct, the mac reports an erro r by using the transmission status interrupt (txstatus). 1: crc is automatically appended to the end of a packet. an internally generated frame check sequenc e (fcs) is appended to the end of a transmission packet. 2 paden pad appending 0: pad is not appended. 1: pad is appended to packet if its length is less th an 64 bytes. at this time, crc is automatically appended to the end of the packet regardless of the setting of the crcen bit. 1 fulld full-duplex enable 0: half-duplex operation 1: full-duplex operation 0 hugen huge packet enable 0: transmission/reception of a packet that e xceeds the value of the maximum packet length register (lmax) is stopped. 1: transmission/reception of a packet that e xceeds the value of the maximum packet length register (lmax) is not stopped. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1374 of 1817 sep 19, 2011 (2) macc2: mac setting register access this register can be read and written in 32-bit units. address 002e 0004h default value 0000 0000h. this register is cleared to its default value by all types of resets. cautions 1. be sure to execute a so ftware reset after setting the operation mode. to execute a software reset, set the mcrst, rfrst, and tfrst bits of the macc2 register to 1 at the same time. cancel the software reset by clearing these bits or more to 0 at the same time. manipulate these reset bits at an interval of five or more rxclk or txclk clock cycles. 2. be sure to set bits 31 to 11, 7, and 3 to 0 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 mcrst rfrst tfrst r r r r r r/w r/w r/w 7 6 5 4 3 2 1 0 0 bpnb apd vpd 0 0 0 0 r r/w r/w r/w r r r r bit name description 10 mcrst mac control block software reset 0: cancels a software reset of the mac control block. 1: executes a software reset of the mac control block. 9 rfrst reception block software reset 0: cancels a software reset of the reception block. 1: executes a software reset of the reception block. 8 tfrst transmission block software reset 0: cancels a software reset of the transmission block. 1: executes a software reset of the transmission block. 6 bpnb no backoff after back pressure when this bit is set to 1, backoff is not per formed for a transmission after back pressure. 5 apd auto vlan pad if a packet that matches the vlan type registered to t he vltp register is transmitted, it is treated as a vlan packet and pad is appended. 4 vpd vlan pad mode the packet to be transmitted is always tr eated as a vlan packet and pad is appended. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1375 of 1817 sep 19, 2011 (3) ipgt: back-to-back ipg register access this register can be read and written in 32-bit units. address 002e 0008h default value 0000 0013h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 7 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 ipgt r r/w r/w r/w r/w r/w r/w r/w bit name description 6 to 0 ipgt ipg in back-to-back transmission: these bits set the gap between packets (or an inter-packet gap (ipg)) in back-to-back transmission. the expression used to calculate ipg is as follows. ? ipg = (5 + ipgt) x time r equired to transmit 4 bits (time required to transmit 1 bit = 100 ns when t he data rate is 10 mbps or 10 ns when the data rate is 100 mbps) set ipg to the time required to transmit at least 96 bits to satisfy the specification of ieee802.3 (refer to 23.5.2 (5) inter-packet gap (ipg) ). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1376 of 1817 sep 19, 2011 (4) ipgr: non back-to-back ipg register access this register can be read and written in 32-bit units. address 002e 000ch default value 0000 0e13h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 15 and 7 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 ipgr1 r r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 ipgr2 r r/w r/w r/w r/w r/w r/w r/w bit name description 14 to 8 ipgr1 carrier sense period these bits set the carrier sense pe riod of the first half of the ipg in transmission other than back-to- back transmission. the calculat ion expression used to calculate the carrier sense period is as follows. ? carrier sense period = (2 + ipgr1) x time required to transmit 4 bits set the carrier sense period to 2/3ipg to satisfy the specification of ieee802.3 (refer to 23.5.2 (5) inter-packet gap (ipg) ). 6 to 0 ipgr2 ipg in transmission other th an back-to-back transmission these bits set the ipg in tran smission other than back-to-back tr ansmission. the expression used to calculate the ipg is as follows. ? ipg = (5 + ipgr2) x time required to transmit 4 bits the carrier sense period set by ipgr1 is included in the ipg set by ipgr2. set the ipg to the time required to transmit at least 96 bits to sati sfy the specification of ieee802.3 (refer to 23.5.2 (5) inter-packet gap (ipg) ). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1377 of 1817 sep 19, 2011 (5) clrt: collision register access this register can be read and written in 32-bit units. address 002e 0010h default value 0000 380fh. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 14 and 7 to 4 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 lcol r r r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 retry r r r r r/w r/w r/w r/w bit name description 13 to 8 lcol collision window these bits set the collision window width. the widt h of the collision window to be set is calculated by the following expression. ? collision window width = (lcol + 8) x time required to transmit 8 bits the specification of ieee802.3 is that the collisi on window width is time required to transmit 512 bits. 3 to 0 retry maximum number of times of retransmission in case of collision these bits set the maximum number of times retr ansmission is executed when a collision occurs. if retransmission is not completed within the value se t by these bits, transmission is aborted. this value indicates the maximu m number of collisions. the specification of ieee802.3 is that the maximum number of collisions is 15. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1378 of 1817 sep 19, 2011 (6) lmax: maximum packet length register access this register can be read and written in 32-bit units. address 002e 0014h default value 0000 0600h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 maxf15 maxf14 maxf13 maxf12 maxf11 maxf10 maxf9 maxf8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 maxf7 maxf6 maxf5 maxf4 maxf3 maxf2 maxf1 maxf0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 0 maxf[15:0] maximum packet length (bytes) when the macc1.hugen bit is 0, the transmit and receive packet length is limited by the value of these bits. during reception: reception is terminated immedi ately when the receive frame length exceeds the value of maxf. during transmission: transmission is aborted imm ediately when the transmit frame length exceeds the value of maxf. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1379 of 1817 sep 19, 2011 (7) lsa1: station address register 1 this register is used to compare a source address wh en a pause control frame is assembled and a destination address when address filtering is used. this register is us ed together with the lsa2 register as a 48-bit register. access this register can be read and written in 32-bit units. address 002e 0054h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 lsa115 lsa114 lsa113 lsa112 lsa111 lsa110 lsa19 lsa18 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 lsa17 lsa16 lsa15 lsa14 lsa13 lsa12 lsa11 lsa10 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 0 lsa1[15:0] station address (sa) (47:32) the sa bits (47:0) are used to compare a source address when a pause control frame is assembled and a destination address when add ress filtering is used (refer to 23.5.7 (1) (a) filtering of unicast address ). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1380 of 1817 sep 19, 2011 (8) lsa2: station address register 2 this register is used to compare a source address wh en a pause control frame is assembled and a destination address when address filtering is used. this register is us ed together with the lsa1 register as a 48-bit register. access this register can be read and written in 32-bit units. address 002e 0058h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 lsa231 lsa230 lsa229 lsa228 lsa227 lsa226 lsa225 lsa224 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 lsa223 lsa222 lsa221 lsa220 lsa219 lsa218 lsa21 lsa216 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 lsa215 lsa214 lsa213 lsa212 lsa211 lsa210 lsa29 lsa28 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 lsa27 lsa26 lsa25 lsa24 lsa23 lsa22 lsa21 lsa20 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 lsa2[31:0] station address (sa) (31:0) the sa bits (47:0) are used to compare a source address when a pause control frame is assembled and a destination address when add ress filtering is used (refer to 23.5.7 (1) (a) filtering of unicast address ). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1381 of 1817 sep 19, 2011 (9) pause timer value read register this register is used to read the value of the pause timer counter. access this register can be read-only, in 32-bit units. address 002e 005ch default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 ptct15 ptct14 ptct13 ptct12 ptct11 ptct10 ptct9 ptct8 r r r r r r r r 7 6 5 4 3 2 1 0 ptct7 ptct6 ptct5 ptct4 ptct3 ptct2 ptct1 ptct0 r r r r r r r r bit name description 15 to 0 ptct[15:0] pause timer counter these bits indicate the val ue currently set to the pause timer. t he value of this register is valid only when reception flow control is enabled (the macc1.rxfc bit = 1) (refer to 23.5.4 (1) flow control ). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1382 of 1817 sep 19, 2011 (10) vltp: vlan type register this register is used to specify the operation to be performed on a vlan frame. access this register can be read and written in 32-bit units. address 002e 0064h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 vltp15 vltp14 vltp13 vltp12 vltp11 vltp10 vltp9 vltp8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 vltp7 vltp6 vltp5 vltp4 vltp3 vltp2 vltp1 vltp0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 0 vltp[15:0] vlan frame operation these bits specify the operation to be performed or a vlan frame (refer to 23.5.4 (3) operations related to vlan frame ). during reception: the value of vltp[15:0] is com pared with the value of the tpid field (2 bytes following the source address) of a frame to detect a vlan frame. during transmission: if the value of the vlan fi eld matches the value of vltp[15:0] when the macc2.apd bit is set to 1, pad is appended to the vlan frame. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1383 of 1817 sep 19, 2011 (11) miic: serial management in terface configuration register this register is used to set the operation mode of the serial management interface block. access this register can be read and written in 32-bit units. address 002e 0080h default value 0000 0000h. this register is cleared to its default value by all types of resets. cautions 1. manipulate the mirst bit at an interval of five or more ethernet controller clock cycles (f ec ). 2. be sure to set bits 31 to 16, 14 to 5, and 0 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 mirst 0 0 0 0 0 0 0 r/w r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 clks2 clks1 clks0 physel 0 r r r r/w r/w r/w r/w r bit name description 15 mirst serial management inte rface block software reset 0: cancels a software reset of the serial management interface block. 1: executes a software reset of the serial management interface block. mdc division ratio these bits select a divisi on ratio according to an ethernet controller clock (f ec ) to be used (refer to 23.5.6 (1) (a) mdc clock ). to satisfy the specification of ieee802.3, set a di vision ratio so that the mdc is 2.5 mhz or less. clks2 clks1 clks0 input frequency of f ec 0 0 1 33 mhz or less (dividing by 14) 0 1 0 50 mhz or less (divided by 20) other the above setting prohibited 4 to 2 clks[2:0] 1 physel setting to output mdc set this bit to 1 if data is not correctly transferred during communication with phy when the mdc is stopped. 1: always output mdc even when a frame other than the management frame is transmitted. 0: stop mdc when a frame other than the management frame is transmitted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1384 of 1817 sep 19, 2011 (12) mcmd: mii command register this register is used to read an external phy device by using the scan command and mii management interface. access this register can be written-only in 32-bit units. read the result of writing the mcmd register from the mind register. address 002e 0094h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 2 to ?0 ?. bits 1 and 0 can only be written. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 0 scanc rstat r r r r r r w w bit name description 1 scanc scan command when this bit is set to 1, the scan command is executed. 0 rstat mii management read when this bit is set to 1, the mii management interface reads the external phy device. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1385 of 1817 sep 19, 2011 (13) madr: mii address register this register is used to set a phy address and a phy register address. access this register can be read and written in 32-bit units. address 002e 0098h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 13 and 7 to 5 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 fiad r r r r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 rgad r r r r/w r/w r/w r/w r/w bit name description 12 to 8 fiad phy address this bit sets a phy address. one ethernet controller can contro l up to thirty one phy devices. 4 to 0 rgad phy register address this bit sets the address of the register to be acce ssed. the ethernet controller can access thirty- two 16-bit registers in one phy device. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1386 of 1817 sep 19, 2011 (14) mwtd: mii write data register this register is used to set the data to be written to an external phy device when the mii management interface writes a phy device. access this register can be read and written in 32-bit units. address 002e 009ch default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 ctld15 ctld14 ctld13 ctld12 ctld11 ctld10 ctld9 ctld8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 ctld7 ctld6 ctld5 ctld4 ctld3 ctld2 ctld1 ctld0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 0 ctld[15:0] mii write data this is a write data field when the mii managem ent interface writes an external phy device. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1387 of 1817 sep 19, 2011 (15) mrdd: mii read data register this register is used to read data that has been read from an external phy device by the mii management interface. access this register is read-only, in 32-bit units. address 002e 00a0h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 prsd15 prsd14 prsd13 prsd12 prsd11 prsd10 prsd9 prsd8 r r r r r r r r 7 6 5 4 3 2 1 0 prsd7 prsd6 prsd5 prsd4 prsd3 prsd2 prsd1 prsd0 r r r r r r r r bit name description 15 to 0 prsd[15:0] mii read data this is a read data field when the mii managem ent interface reads an external phy device. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1388 of 1817 sep 19, 2011 (16) mind: mii indicator register this register indicates the status of scan co mmand execution and mii management interface access. access this register is read-only, in 32-bit units. address 002e 00a4h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 3 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 nvalid scana busy r r r r r r r r bit name description 2 nvalid scan command start status 1: the scan command is under execution and the first read access is not complete. 0: normal status 1 scana scan command active 1: the scan command is under execution. 0: normal status 0 busy busy 1: the mii management interface is accessing an external phy device. 0: the mii management interface is not accessing an external phy device. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1389 of 1817 sep 19, 2011 (17) afr: address filter register this register is used to set the conditions under which a receive packet is received. access this register can be read and written in 32-bit units. address 002e 00c8h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 4 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 pro prm amc abc r r r r r/w r/w r/w r/w bit name description 3 pro promiscuous mode all packets are valid in this mode. 2 prm multicast reception in this mode, all multic ast packets are valid. other packets are discarded. 1 amc conditional multicast reception a multicast packet that satisfies the conditions is valid and other packets are discarded in this mode. only a multicast packet whose multicast address ma tches the values of the hash table specified by the ht1 and ht2 registers is received. 0 abc broadcast reception broadcast packets are valid and other packets are discarded in this mode. for details of the settings of the afr regist er and the packets to be filtered, refer to table 23-9 . v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1390 of 1817 sep 19, 2011 (18) ht1: hash table register 1 this register is used to set the higher 32 bits of t he hash table that is used for conditional multicast packet detection. access this register can be read and written in 32-bit units. address 002e 00cch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 ht131 ht130 ht129 ht128 ht127 ht126 ht125 ht124 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 ht123 ht122 ht121 ht120 ht119 ht118 ht11 ht116 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 ht115 ht114 ht113 ht112 ht111 ht110 ht19 ht18 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 ht17 ht16 ht15 ht14 ht13 ht12 ht11 ht10 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 ht1[31:0] hash table 1 the hash table is used for conditi onal multicast packet detection. these bits indicate the higher 32 bits of the hash table. ht (63:32) v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1391 of 1817 sep 19, 2011 (19) ht2: hash table register 2 this register is used to set the lower 32 bits of the hash ta ble that is used for conditional multicast packet detection. access this register can be read and written in 32-bit units. address 002e00d0h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 ht231 ht230 ht1229 ht228 ht227 ht226 ht225 ht224 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 ht223 ht222 ht221 ht220 ht219 ht218 ht217 ht216 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 ht215 ht214 ht213 ht212 ht211 ht210 ht29 ht28 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 ht27 ht26 ht25 ht24 ht23 ht22 ht21 ht20 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 ht2[31:0] hash table 2 the hash table is used for conditi onal multicast packet detection. these bits indicate the lower 32 bi ts of the hash table. ht (31:0) v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1392 of 1817 sep 19, 2011 (20) car1: carry register 1 this register indicates that a statistics counter has overflowed. each bit of this register corresponds to a statistics counter. when a statistics counter overflows, the corresponding bit of this register is set to 1. each bit is cleared when it is read. access this register can be read and written in 32-bit units. address 002e 00dch default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 c1vt c1ut c1bt c1mt c1pt c1tb c1mx c11k r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 c1fe c1tf c1ot c1sf c1br c1mr c1pr c1rb r/w r/w r/w r/w r/w r/w r/w r/w (1/2) bit name description 15 c1vt overflow of rvbt counter 0: counter did not overflow. 1: counter overflowed. 14 c1ut overflow of tuca counter 0: counter did not overflow. 1: counter overflowed. 13 c1bt overflow of tbca counter 0: counter did not overflow. 1: counter overflowed. 12 c1mt overflow of tmca counter 0: counter did not overflow. 1: counter overflowed. 11 c1pt overflow of tpct counter 0: counter did not overflow. 1: counter overflowed. 10 c1tb overflow of tbyt counter 0: counter did not overflow. 1: counter overflowed. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1393 of 1817 sep 19, 2011 (2/2) bit name description 9 c1mx overflow of rmax counter 0: counter did not overflow. 1: counter overflowed. 8 c11k overflow of r1k counter 0: counter did not overflow. 1: counter overflowed. 7 c1fe overflow of r511 counter 0: counter did not overflow. 1: counter overflowed. 6 c1tf overflow of r255 counter 0: counter did not overflow. 1: counter overflowed. 5 c1ot overflow of r127 counter 0: counter did not overflow. 1: counter overflowed. 4 c1sf overflow of r64 counter 0: counter did not overflow. 1: counter overflowed. 3 c1br overflow of rbca counter 0: counter did not overflow. 1: counter overflowed. 2 c1mr overflow of rmca counter 0: counter did not overflow. 1: counter overflowed. 1 c1pr overflow of rpkt counter 0: counter did not overflow. 1: counter overflowed. 0 c1rb overflow of rbyt counter 0: counter did not overflow. 1: counter overflowed. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1394 of 1817 sep 19, 2011 (21) car2: carry register 2 this register indicates that a statistics counter has overflowed. each bit of this register corresponds to a statistics counter. when a statistics counter overflows, the corresponding bit of this register is set to 1. each bit is cleared when it is read. access this register can be read and written in 32-bit units. address 002e 00e0h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 30 to 23 to ?0?. 31 30 29 28 27 26 25 24 c2dv 0 0 0 0 0 0 0 r/w r r r r r r r 23 22 21 20 19 18 17 16 0 c2im c2cs c2nc c2xc c2lc c2mc c2sc r r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 c2xd c2df c2xf c2te c2jb c2fg c2ov c2un r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 c2fc c2cd c2fo c2al c2uo c2pf c2cf c2re r/w r/w r/w r/w r/w r/w r/w r/w (1/3) bit name description 31 c2dv overrunning of status vector 0: status vector does not overrun. 1: status vector overruns. 22 c2im overflow of time counter 0: counter did not overflow. 1: counter overflowed. 21 c2cs overflow of tcse counter 0: counter did not overflow. 1: counter overflowed. 20 c2nc overflow of tncl counter 0: counter did not overflow. 1: counter overflowed. 19 c2xc overflow of txcl counter 0: counter did not overflow. 1: counter overflowed. 18 c2lc overflow of tlcl counter 0: counter did not overflow. 1: counter overflowed. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1395 of 1817 sep 19, 2011 (2/3) bit name description 17 c2mc overflow of tmcl counter 0: counter did not overflow. 1: counter overflowed. 16 c2sc overflow of tscl counter 0: counter did not overflow. 1: counter overflowed. 15 c2xd overflow of txdf counter 0: counter did not overflow. 1: counter overflowed. 14 c2df overflow of tdfr counter 0: counter did not overflow. 1: counter overflowed. 13 c2xf overflow of txpf counter 0: counter did not overflow. 1: counter overflowed. 12 c2te overflow of tfcs counter 0: counter did not overflow. 1: counter overflowed. 11 c2jb overflow of rbjr counter 0: counter did not overflow. 1: counter overflowed. 10 c2fg overflow of rfrg counter 0: counter did not overflow. 1: counter overflowed. 9 c2ov overflow of rovr counter 0: counter did not overflow. 1: counter overflowed. 8 c2un overflow of rund counter 0: counter did not overflow. 1: counter overflowed. 7 c2fc overflow of rfcr counter 0: counter did not overflow. 1: counter overflowed. 6 c2cd overflow of rcde counter 0: counter did not overflow. 1: counter overflowed. 5 c2fo overflow of rflr counter 0: counter did not overflow. 1: counter overflowed. 4 c2al overflow of raln counter 0: counter did not overflow. 1: counter overflowed. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1396 of 1817 sep 19, 2011 (3/3) bit name description 3 c2uo overflow of rxuo counter 0: counter did not overflow. 1: counter overflowed. 2 c2pf overflow of rxpf counter 0: counter did not overflow. 1: counter overflowed. 1 c2cf overflow of rxcf counter 0: counter did not overflow. 1: counter overflowed. 0 c2re overflow of rfcs counter 0: counter did not overflow. 1: counter overflowed. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1397 of 1817 sep 19, 2011 (22) cam1: carry mask register 1 this register is used to mask the intftmov signal that is generated when a statistics counter has overflowed and the corresponding bit of the car1 register has been set to 1. each bit of this register can be masked. access this register can be read and written in 32-bit units. address 002e 0130h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 m1vt m1ut m1bt m1mt m1pt m1tb m1mx m11k r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 m1fe m1tf m1ot m1sf m1br m1mr m1pr m1rb r/w r/w r/w r/w r/w r/w r/w r/w (1/2) bit name description 15 m1vt rvbt counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 14 m1ut tuca counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 13 m1bt tbca counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 12 m1mt tmca counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 11 m1pt tpkt counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 10 m1tb tbyt counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1398 of 1817 sep 19, 2011 (2/2) bit name description 9 m1mx rmax counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 8 m11k r1k counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 7 m1fe r511 counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 6 m1tf r255 counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 5 m1ot r127 counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 4 m1sf r64 counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 3 m1br rbca counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 2 m1mr rmca counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 1 m1pr rpkt counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 0 m1rb rbyt counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1399 of 1817 sep 19, 2011 (23) cam2: carry mask register 2 this register is used to mask the caint signal that is generated when a statistics counter has overflowed and the corresponding bit of the car2 register has been set to 1. each bit of this register can be masked. access this register can be read and written in 32-bit units. address 002e 00e0h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 30 to 23 to ?0?. 31 30 29 28 27 26 25 24 m2dv 0 0 0 0 0 0 0 r/w r r r r r r r 23 22 21 20 19 18 17 16 0 m2im m2cs m2nc m2xc m2lc m2mc m2sc r r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 m2xd m2df m2xf m2te m2jb m2fg m2ov m2un r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 m2fc m2cd m2fo m2al m2uo m2pf m2cf m2re r/w r/w r/w r/w r/w r/w r/w r/w (1/3) bit name description 31 m2dv status vector overrun interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 22 m2im time counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 21 m2cs tcse counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 20 m2nc tncl counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 19 m2xc txcl counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 18 m2lc tlcl counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1400 of 1817 sep 19, 2011 (2/3) bit name description 17 m2mc tmcl counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 16 m2sc tscl counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 15 m2xd txdf counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 14 m2df tdfr counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 13 m2xf txpf counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 12 m2te tfcs counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 11 m2jb rbjr counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 10 m2fg rfrg counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 9 m2ov rovr counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 8 m2un rund counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 7 m2fc rfcr counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 6 m2cd rcde counter overflow interrupt mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 5 m2fo rflr counter carry mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 4 m2al raln counter carry mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1401 of 1817 sep 19, 2011 (3/3) bit name description 3 m2uo rxuo counter carry mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 2 m2pf rxpf counter carry mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 1 m2cf rxcf counter carry mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). 0 m2re rfcs counter carry mask bit 0: interrupt generation is enabled (not masked). 1: interrupt generation is disabled (masked). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1402 of 1817 sep 19, 2011 23.4.2 statistics counters (1) rbyt: receive byte counter access this register can be read and written in 32-bit units. address 002e 0140h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rbyt31 rbyt30 rbyt29 rbyt28 rbyt27 rbyt26 rbyt25 rbyt24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rbyt23 rbyt22 rbyt21 rbyt20 rbyt19 rbyt18 rbyt17 rbyt16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rbyt15 rbyt14 rbyt13 rbyt12 rbyt11 rbyt10 rbyt9 rbyt8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rbyt7 rbyt6 rbyt5 rbyt4 rbyt3 rbyt2 rbyt1 rbyt0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rbyt[31:0] this counter indicates the number of by tes in a received packet. it counts from the destination address byte to the fcs byte. it counts bytes even if an error occurs. if a packet exceeding the length set to the lmax r egister is received when the macc1.hugen bit is set to 0, the value of the lmax register is used as the packet length. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1403 of 1817 sep 19, 2011 (2) rpkt: receive packet counter access this register can be read and written in 32-bit units. address 002e 0144h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rpkt31 rpkt30 rpkt29 rpkt28 rpkt27 rpkt26 rpkt25 rpkt24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rpkt23 rpkt22 rpkt21 rpkt20 rpkt19 rpkt18 rpkt1 rpkt16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rpkt15 rpkt14 rpkt13 rpkt12 rpkt11 rpkt10 rpkt9 rpkt8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rpkt7 rpkt6 rpkt5 rpkt4 rpkt3 rpkt2 rpkt1 rpkt0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rpkt[31:0] this counter is incremented when any packet, including packets in which an error has occurred, all unicast packets, all multicast packets, and broadcast packets, is received. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1404 of 1817 sep 19, 2011 (3) rfcs: receive fcs error frame counter access this register can be read and written in 32-bit units. address 002e 0148h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rfcs31 rfcs30 rfcs29 rfcs28 rfcs27 rfcs26 rfcs25 rfcs24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rfcs23 rfcs22 rfcs21 rfcs20 rfcs19 rfcs18 rfcs17 rfcs16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rfcs15 rfcs14 rfcs13 rfcs12 rfcs11 rfcs10 rfcs9 rfcs8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rfcs7 rfcs6 rfcs5 rfcs4 rfcs3 rfcs2 rfcs1 rfcs0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rfcs[31:0] this counter is increment ed when a crc error occurs in a receive packet. if a packet exceeding the length set to the lmax r egister is received when the macc1.hugen bit is set to 0, a crc check is executed when the packet length has reached the set value of the lmax register. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1405 of 1817 sep 19, 2011 (4) rmca: receive multicast packet counter access this register can be read and written in 32-bit units. address 002e 014ch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rmca31 rmca30 rmca29 rmca28 rmca27 rmca26 rmca25 rmca24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rmca23 rmca22 rmca21 rmca20 rmca19 rmca18 rmca17 rmca16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rmca15 rmca14 rmca13 rmca12 rmca11 rmca10 rmca9 rmca8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rmca7 rmca6 rmca5 rmca4 rmca3 rmca2 rmca1 rmca0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rmca[31:0] this counter is incremented when a mu lticast packet whose length is 64 bytes to 1,518 bytes (1,522 bytes in the case of a vlan frame) is received. broadcast packets do not cause this counter to increment, nor do receive packe ts in which a crc error has occurred. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1406 of 1817 sep 19, 2011 (5) rbca: receive broadcast packet counter access this register can be read and written in 32-bit units. address 002e 0150h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rbca31 rbca30 rbca29 rbca28 rbca27 rbca26 rbca25 rbca24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rbca23 rbca22 rbca21 rbca20 rbca19 rbca18 rbca17 rbca16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rbca15 rbca14 rbca13 rbca12 rbca11 rbca10 rbca9 rbca8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rbca7 rbca6 rbca5 rbca4 rbca3 rbca2 rbca1 rbca0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rbca[31:0] this counter is incremented when a br oadcast packet whose length is 64 bytes to 1,518 bytes is incremented when a (1,522 bytes in the case of a vlan frame is received). multicast packets do not cause this counter to increment, nor do rece ive packets in which a crc error has occurred. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1407 of 1817 sep 19, 2011 (6) rxcf: receive control frame packet counter access this register can be read and written in 32-bit units. address 002e 0154h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rxcf31 rxcf30 rxcf29 rxcf28 rxcf27 rxcf26 rxcf25 rxcf24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rxcf23 rxcf22 rxcf21 rxcf20 rxcf19 rxcf18 rxcf17 rxcf16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rxcf15 rxcf14 rxcf13 rxcf12 rxcf11 rxcf10 rxcf9 rxcf8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rxcf7 rxcf6 rxcf5 rxcf4 rxcf3 rxcf2 rxcf1 rxcf0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rxcf[31:0] this counter is incremented when any control frame, including pause control frames and unsupported control frames is received. a control frame in which a crc error has been detected does not cause this counter to increment. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1408 of 1817 sep 19, 2011 (7) rxpf: receive pause cont rol frame packet counter access this register can be read and written in 32-bit units. address 002e 0158h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rxpf31 rxpf30 rxpf29 rxpf28 rxpf27 rxpf26 rxpf25 rxpf24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rxpf23 rxpf22 rxpf21 rxpf20 rxpf19 rxpf18 rxpf17 rxpf16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rxpf15 rxpf14 rxpf13 rxpf12 rxpf11 rxpf10 rxpf9 rxpf8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rxpf7 rxpf6 rxpf5 rxpf4 rxpf3 rxpf2 rxpf1 rxpf0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rxpf[31:0] this counter is increment ed when a valid pause control frame is received. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1409 of 1817 sep 19, 2011 (8) rxuo: receive undefined control packet counter access this register can be read and written in 32-bit units. address 002e 015ch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rxuo31 rxuo30 rxuo29 rxuo28 rxuo27 rxuo26 rxuo25 rxuo24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rxuo23 rxuo22 rxuo21 rxuo20 rxuo19 rxuo18 rxuo17 rxuo16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rxuo15 rxuo14 rxuo13 rxuo12 rxuo11 rxuo10 rxuo9 rxuo8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rxuo7 rxuo6 rxuo5 rxuo4 rxuo3 rxuo2 rxuo1 rxuo0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rxuo[31:0] this counter is incremented when a control frame having an op code other than pause or a pause control frame having an invalid destination addr ess is received. a frame in which a crc error has been detected does not caus e this counter to increment. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1410 of 1817 sep 19, 2011 (9) raln: receive alignment error counter access this register can be read and written in 32-bit units. address 002e 0160h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 raln31 raln30 raln29 raln28 raln27 raln26 raln25 raln24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 raln23 raln22 raln21 raln20 raln19 raln18 raln17 raln16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 raln15 raln14 raln13 raln12 raln11 raln10 raln9 raln8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 raln7 raln6 raln5 raln4 raln3 raln2 raln1 raln0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 raln[31:0] this counter is incremented when a crc error and a dribble nibble occur in a received packet. if a packet exceeding the length set to the lmax r egister is received when the macc1.hugen bit is set to 0, an alignment error ch eck is executed as soon as the set value (in bytes) of the lmax register has been reached. this check d oes not cause this counter to increment. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1411 of 1817 sep 19, 2011 (10) rflr: receive frame length error counter access this register can be read and written in 32-bit units. address 002e 0164h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rflr31 rflr30 rflr29 rflr28 rflr27 rflr26 rflr25 rflr24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rflr23 rflr22 rflr21 rflr20 rflr19 rflr18 rflr17 rflr16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rflr15 rflr14 rflr13 rflr12 rflr11 rflr10 rflr9 rflr8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rflr7 rflr6 rflr5 rflr4 rflr3 rflr2 rflr1 rflr0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rflr[31:0] this counter is incremented if the value of the length field of a receive packet does not mach the data field length of a packet actually received. if t he value of the length field is 1,501 or more (for example, when the bytes equivalent to the length fi eld are used as the ethernet type field), this counter is not incremented. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1412 of 1817 sep 19, 2011 (11) rcde: receive code error counter access this register can be read and written in 32-bit units. address 002e 0168h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rcde31 rcde30 rcde29 rcde28 rcde27 rcde26 rcde25 rcde24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rcde23 rcde22 rcde21 rcde20 rcde19 rcde18 rcde17 rcde16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rcde15 rcde14 rcde13 rcde12 rcde11 rcde10 rcde9 rcde8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rcde7 rcde6 rcde5 rcde4 rcde3 rcde2 rcde1 rcde0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rcde[31:0] this counter is incremented if an illegal data symbol has been detected at least once while a carrier is being detected. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1413 of 1817 sep 19, 2011 (12) rfcr: receive fa lse carrier counter access this register can be read and written in 32-bit units. address 002e 016ch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rfcr31 rfcr30 rfcr29 rfcr28 rfcr27 rfcr26 rfcr25 rfcr24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rfcr23 rfcr22 rfcr21 rfcr20 rfcr19 rfcr18 rfcr17 rfcr16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rfcr15 rfcr14 rfcr13 rfcr12 rfcr11 rfcr10 rfcr9 rfcr8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rfcr7 rfcr6 rfcr5 rfcr4 rfcr3 rfcr2 rfcr1 rfcr0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rfcr[31:0] if a false carrier is generated in the idle status, this counter is incremented after the next packet is received. it is assumed that a false carrier has occurred if 1110b is input as nibble data from rxd while rxer is high. this counter is incremented only once even if two or more false carriers are generated in the idle status. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1414 of 1817 sep 19, 2011 (13) rund: receive undersize packet counter access this register can be read and written in 32-bit units. address 002e 0170h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rund31 rund30 rund29 rund28 rund27 rund26 rund25 rund24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rund23 rund22 rund21 rund20 rund19 rund18 rund1 rund16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rund15 rund14 rund13 rund12 rund11 rund10 rund9 rund8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rund7 rund6 rund5 rund4 rund3 rund2 rund1 rund0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rund[31:0] this counter is incremented if the rece ive packet length is less than 64 bytes and the packet contains a valid fcs field. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1415 of 1817 sep 19, 2011 (14) rovr: receive oversize packet counter access this register can be read and written in 32-bit units. address 002e 0174h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rovr31 rovr30 rovr29 rovr28 rovr27 rovr26 rovr25 rovr24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rovr23 rovr22 rovr21 rovr20 rovr19 rovr18 rovr17 rovr16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rovr15 rovr14 rovr13 rovr12 rovr11 rovr10 rovr9 rovr8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rovr7 rovr6 rovr5 rovr4 rovr3 rovr2 rovr1 rovr0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rovr[31:0] this counter is incremented if the re ceive packet length exceeds 1,518 bytes (1,522 bytes when a vlan frame is received) and the packet contains a valid fcs field. if a packet exceeding the length set to the lmax r egister is received when the macc1.hugen bit is set to 0, a crc check is executed as soon as the set value of the lmax register has been reached. consequently, a crc error may be detect ed at that point and this counter may not be incremented. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1416 of 1817 sep 19, 2011 (15) rfrg: receive fragment counter access this register can be read and written in 32-bit units. address 002e 0178h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rfrg31 rfrg30 rfrg29 rfrg28 rfrg27 rfrg26 rfrg25 rfrg24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rfrg23 rfrg22 rfrg21 rfrg20 rfrg19 rfrg18 rfrg1 rfrg16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rfrg15 rfrg14 rfrg13 rfrg12 rfrg11 rfrg10 rfrg9 rfrg8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rfrg7 rfrg6 rfrg5 rfrg4 rfrg3 rfrg2 rfrg1 rfrg0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rfrg[31:0] this counter is incremented if the re ceive packet length is less than 64 bytes and the packet contains a crc error or an alignment error. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1417 of 1817 sep 19, 2011 (16) rjbr: receive jabber counter access this register can be read and written in 32-bit units. address 002e 017ch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rjbr31 rjbr30 rjbr29 rjbr28 rjbr27 rjbr26 rjbr25 rjbr24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rjbr23 rjbr22 rjbr21 rjbr20 rjbr19 rjbr18 rjbr17 rjbr16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rjbr15 rjbr14 rjbr13 rjbr12 rjbr11 rjbr10 rjbr9 rjbr8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rjbr7 rjbr6 rjbr5 rjbr4 rjbr3 rjbr2 rjbr1 rjbr0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rjbr[31:0] this counter is incremented if the re ceive packet length exceeds 1,518 bytes (1,522 bytes when a vlan frame is received) and the packet contains a crc error or an alignment error. if a packet exceeding the length set to the lmax r egister is received when the macc1.hugen bit is set to 0, a crc check is executed as soon as the set value of the lmax register has been reached. consequently, a crc error may be detect ed at that point and this counter may not be incremented. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1418 of 1817 sep 19, 2011 (17) r64: receive 64- byte frame counter access this register can be read and written in 32-bit units. address 002e 0180h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 r6431 r6430 r6429 r6428 r6427 r6426 r6425 r6424 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 r6423 r6422 r6421 r6420 r6419 r6418 r6417 r6416 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 r6415 r6414 r6413 r6412 r6411 r6410 r649 r648 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 r647 r646 r645 r644 r643 r642 r641 r640 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 r64[31:0] this counter is incremented if the receiv e packet length is 64 bytes. a packet containing a crc error, symbol error, or length/type error also causes this counter to increment. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1419 of 1817 sep 19, 2011 (18) r127: receive 65- to 127-byte frame counter access this register can be read and written in 32-bit units. address 002e 0184h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 r12731 r12730 r12729 r12728 r12727 r12726 r12725 r12724 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 r12723 r12722 r12721 r12720 r12719 r12718 r12717 r12716 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 r12715 r12714 r12713 r12712 r12711 r12710 r1279 r1278 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 r1277 r1276 r1275 r1274 r1273 r1272 r1271 r1270 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 r127[31:0] this counter is incremented if the receiv e packet length is 64 to 127 bytes. a packet containing a crc error, symbol error, or length/type error is also counted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1420 of 1817 sep 19, 2011 (19) r255: receive 128- to 255-byte frame counter access this register can be read and written in 32-bit units. address 0188h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 r25531 r25530 r25529 r25528 r25527 r25526 r25525 r25524 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 r25523 r25522 r25521 r25520 r25519 r25518 r25517 r25516 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 r25515 r25514 r25513 r25512 r25511 r25510 r2559 r2558 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 r2557 r2556 r2555 r2554 r2553 r2552 r2551 r2550 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 r255[31:0] this counter is incremented if the receiv e packet length is 128 to 255 bytes. a packet containing a crc error, symbol error, or length/type error is also counted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1421 of 1817 sep 19, 2011 (20) r511: receive 256- to 511-byte frame counter access this register can be read and written in 32-bit units. address 002e 018ch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 r51131 r51130 r51129 r51128 r51127 r51126 r51125 r51124 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 r51123 r51122 r51121 r51120 r51119 r51118 r51117 r51116 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 r51115 r51114 r51113 r51112 r51111 r51110 r5119 r5118 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 r5117 r5116 r5115 r5114 r5113 r5112 r5111 r5110 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 r511[31:0] this counter is incremented if the receiv e packet length is 256 to 511 bytes. a packet containing a crc error, symbol error, or length/type error is also counted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1422 of 1817 sep 19, 2011 (21) r1k: receive 512- to 1023-byte frame counter access this register can be read and written in 32-bit units. address 002e 0190h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 r1k31 r1k30 r1k29 r1k28 r1k27 r1k26 r1k25 r1k24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 r1k23 r1k22 r1k21 r1k20 r1k19 r1k18 r1k17 r1k16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 r1k15 r1k14 r1k13 r1k12 r1k11 r1k10 r1k9 r1k8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 r1k7 r1k6 r1k5 r1k4 r1k3 r1k2 r1k1 r1k0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 r1k[31:0] this counter is incremented if the receiv e packet length is 512 to 1023 bytes. a packet containing a crc error, symbol error, or length/type error is also counted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1423 of 1817 sep 19, 2011 (22) rmax: receive 1024- to max-byte frame counter access this register can be read and written in 32-bit units. address 002e 0194h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rmax31 rmax30 rmax29 rmax28 rmax27 rmax26 rmax25 rmax24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rmax23 rmax22 rmax21 rmax20 rmax19 rmax18 rmax17 rmax16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rmax15 rmax14 rmax13 rmax12 rmax11 rmax10 rmax9 rmax8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rmax7 rmax6 rmax5 rmax4 rmax3 rmax2 rmax1 rmax0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rmax[31:0] this counter is incremented if the re ceive packet length is 1024 to 1518 bytes (1,024 to 1,522 bytes when a vlan frame is received). a pac ket containing a crc error, symbol error, or length/type error is also counted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1424 of 1817 sep 19, 2011 (23) rvbt: receive valid byte counter access this register can be read and written in 32-bit units. address 002e 0198h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rvbt31 rvbt30 rvbt29 rvbt28 rvbt27 rvbt26 rvbt25 rvbt24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rvbt23 rvbt22 rvbt21 rvbt20 rvbt19 rvbt18 rvbt17 rvbt16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rvbt15 rvbt14 rvbt13 rvbt12 rvbt11 rvbt10 rvbt9 rvbt8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rvbt7 rvbt6 rvbt5 rvbt4 rvbt3 rvbt2 rvbt1 rvbt0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 rvbt[31:0] this counter indicates the byte count of a valid packet. it counts from the destination address byte to the fcs byte. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1425 of 1817 sep 19, 2011 (24) tbyt: transmit byte counter access this register can be read and written in 32-bit units. address 002e 01c0h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tbyt31 tbyt30 tbyt29 tbyt28 tbyt27 tbyt26 tbyt25 tbyt24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tbyt23 tbyt22 tbyt21 tbyt20 tbyt19 tbyt18 tbyt17 tbyt16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tbyt15 tbyt14 tbyt13 tbyt12 tbyt11 tbyt10 tbyt9 tbyt8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tbyt7 tbyt6 tbyt5 tbyt4 tbyt3 tbyt2 tbyt1 tbyt0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tbyt[31:0] this counter indicates the number of bytes in a transmit packet. when a collision occurs before transmission is completed or aborted, the byte at which the collision occurred is also counted. the preamble and sfd are not included in the byte count indication. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1426 of 1817 sep 19, 2011 (25) tpkt: transmit packet counter access this register can be read and written in 32-bit units. address 002e 01c4h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tpkt31 tpkt30 tpkt29 tpkt28 tpkt27 tpkt26 tpkt25 tpkt24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tpkt23 tpkt22 tpkt21 tpkt20 tpkt19 tpkt18 tpkt17 tpkt16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tpkt15 tpkt14 tpkt13 tpkt12 tpkt11 tpkt10 tpkt9 tpkt8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tpkt7 tpkt6 tpkt5 tpkt4 tpkt3 tpkt2 tpkt1 tpkt0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tpkt[31:0] this counter is incremented when any packet is tr ansmitted. it is also incremented when packets in which an error has occurred, all unicast packe ts, multicast packets, and broadcast packets are transmitted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1427 of 1817 sep 19, 2011 (26) tfcs: transmit fcs error frame counter access this register can be read and written in 32-bit units. address 002e 01c8h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tfcs31 tfcs30 tfcs29 tfcs28 tfcs27 tfcs26 tfcs25 tfcs24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tfcs23 tfcs22 tfcs21 tfcs20 tfcs19 tfcs18 tfcs17 tfcs16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tfcs15 tfcs14 tfcs13 tfcs12 tfcs11 tfcs10 tfcs9 tfcs8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tfcs7 tfcs6 tfcs5 tfcs4 tfcs3 tfcs2 tfcs1 tfcs0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tfcs[31:0] this counter is incremented when a crc error has been detected in the fcs field that is appended to a transmit packet. it is not incremented if transmission has been aborted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1428 of 1817 sep 19, 2011 (27) tmca: transmit multicast packet counter access this register can be read and written in 32-bit units. address 002e 01cch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tmca31 tmca30 tmca29 tmca28 tmca27 tmca26 tmca25 tmca24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tmca23 tmca22 tmca21 tmca20 tmca19 tmca18 tmca17 tmca16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tmca15 tmca14 tmca13 tmca12 tmca11 tmca10 tmca9 tmca8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tmca7 tmca6 tmca5 tmca4 tmca3 tmca2 tmca1 tmca0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tmca[31:0] this counter is incremented when a mu lticast packet has been transmitt ed. it is not incremented when broadcast packets are transmitted. nor is it incremented if transmission has been aborted or if a crc error has been detected. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1429 of 1817 sep 19, 2011 (28) tbca: transmit broadcast packet counter access this register can be read and written in 32-bit units. address 002e 01d0h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tbca31 tbca30 tbca29 tbca28 tbca27 tbca26 tbca25 tbca24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tbca23 tbca22 tbca21 tbca20 tbca19 tbca18 tbca17 tbca16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tbca15 tbca14 tbca13 tbca12 tbca11 tbca10 tbca9 tbca8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tbca7 tbca6 tbca5 tbca4 tbca3 tbca2 tbca1 tbca0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tbca[31:0] this counter is incremented when a br oadcast packet has been transmitted. it is not incremented when multicast packets are transmitted. nor does it count if transmission has been aborted or if a crc error has been detected. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1430 of 1817 sep 19, 2011 (29) tuca: transmit unicast packet counter access this register can be read and written in 32-bit units. address 002e 01d4h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tuca31 tuca30 tuca29 tuca28 tuca27 tuca26 tuca25 tuca24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tuca23 tuca22 tuca21 tuca20 tuca19 tuca18 tuca17 tuca16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tuca15 tuca14 tuca13 tuca12 tuca11 tuca10 tuca9 tuca8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tuca7 tuca6 tuca5 tuca4 tuca3 tuca2 tuca1 tuca0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tuca[31:0] this counter is incremented when a unica st packet has been transmitted. it is not incremented if transmission has been aborted or if a crc error has been detected. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1431 of 1817 sep 19, 2011 (30) txpf: transmit pause control frame counter access this register can be read and written in 32-bit units. address 002e 01d8h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 txpf31 txpf30 txpf29 txpf28 txpf27 txpf26 txpf25 txpf24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 txpf23 txpf22 txpf21 txpf20 txpf19 txpf18 txpf17 txpf16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 txpf15 txpf14 txpf13 txpf12 txpf11 txpf10 txpf9 txpf8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 txpf7 txpf6 txpf5 txpf4 txpf3 txpf2 txpf1 txpf0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 txpf[31:0] this counter is incremented each ti me a pause control frame has been transmitted when the maximum amount of data has been stored in the receive fifo. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1432 of 1817 sep 19, 2011 (31) tdfr: transmit delay packet counter access this register can be read and written in 32-bit units. address 002e 01dch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tdfr31 tdfr30 tdfr29 tdfr28 tdfr27 tdfr26 tdfr25 tdfr24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tdfr23 tdfr22 tdfr21 tdfr20 tdfr19 tdfr18 tdfr17 tdfr16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tdfr15 tdfr14 tdfr13 tdfr12 tdfr11 tdfr10 tdfr9 tdfr8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tdfr7 tdfr6 tdfr5 tdfr4 tdfr3 tdfr2 tdfr1 tdfr0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tdfr[31:0] this counter is incremented if a transmit delay occurs becaus e of carrier detection when transmission is about to start. it is not incremented if a collision has occurred during transmission that was started after the delay occurred. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1433 of 1817 sep 19, 2011 (32) txdf: transmit excessive delay packet counter access this register can be read and written in 32-bit units. address 002e 01e0h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 txdf31 txdf30 txdf29 txdf28 txdf27 txdf26 txdf25 txdf24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 txdf23 txdf22 txdf21 txdf20 txdf19 txdf18 txdf17 txdf16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 txdf15 txdf14 txdf13 txdf12 txdf11 txdf10 txdf9 txdf8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 txdf7 txdf6 txdf5 txdf4 txdf3 txdf2 txdf1 txdf0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 txdf[31:0] this counter is incremented if transmission has been abort ed by an excessive delay. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1434 of 1817 sep 19, 2011 (33) tscl: transmit single collision packet counter access this register can be read and written in 32-bit units. address 002e 01e4h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tscl31 tscl30 tscl29 tscl28 tscl27 tscl26 tscl25 tscl24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tscl23 tscl22 tscl21 tscl20 tscl19 tscl18 tscl17 tscl16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tscl15 tscl14 tscl13 tscl12 tscl11 tscl10 tscl9 tscl8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tscl7 tscl6 tscl5 tscl4 tscl3 tscl2 tscl1 tscl0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tscl[31:0] this counter is incremented if a transmission has succeeded after a single collision occurred during the transmission. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1435 of 1817 sep 19, 2011 (34) tmcl: transmit multiple collision packet counter access this register can be read and written in 32-bit units. address 002e 01e8h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tmcl31 tmcl30 tmcl29 tmcl28 tmcl27 tmcl26 tmcl25 tmcl24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tmcl23 tmcl22 tmcl21 tmcl20 tmcl19 tmcl18 tmcl17 tmcl16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tmcl15 tmcl14 tmcl13 tmcl12 tmcl11 tmcl10 tmcl9 tmcl8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tmcl7 tmcl6 tmcl5 tmcl4 tmcl3 tmcl2 tmcl1 tmcl0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tmcl[31:0] this counter is incremented if a transmission has succeeded after a collision occurred two or more times (but less than the set value of clrt.retry) during the transmission. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1436 of 1817 sep 19, 2011 (35) tlcl: transmit late collision packet counter access this register can be read and written in 32-bit units. address 002e 01ech default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tlcl31 tlcl30 tlcl29 tlcl28 tlcl27 tlcl26 tlcl25 tlcl24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tlcl23 tlcl22 tlcl21 tlcl20 tlcl19 tlcl18 tlcl17 tlcl16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tlcl15 tlcl14 tlcl13 tlcl12 tlcl11 tlcl10 tlcl9 tlcl8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tlcl7 tlcl6 tlcl5 tlcl4 tlcl3 tlcl2 tlcl1 tlcl0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tlcl[31:0] this counter is incremented if a late collision has occurred during transmission. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1437 of 1817 sep 19, 2011 (36) txcl: transmit excessive collision packet counter access this register can be read and written in 32-bit units. address 002e 01f0h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 txcl31 txcl30 txcl29 txcl28 txcl27 txcl26 txcl25 txcl24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 txcl23 txcl22 txcl21 txcl20 txcl19 txcl18 txcl17 txcl16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 txcl15 txcl14 txcl13 txcl12 txcl11 txcl10 txcl9 txcl8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 txcl7 txcl6 txcl5 txcl4 txcl3 txcl2 txcl1 txcl0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 txcl[31:0] this counter is incremented if collision exceeding the value set by clrt.retry have occurred in a single transmission. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1438 of 1817 sep 19, 2011 (37) tncl: transmit total collision counter access this register can be read and written in 32-bit units. address 002e 01f4h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tncl31 tncl30 tncl29 tncl28 tncl27 tncl26 tncl25 tncl24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tncl23 tncl22 tncl21 tncl20 tncl19 tncl18 tncl17 tncl16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tncl15 tncl14 tncl13 tncl12 tncl11 tncl10 tncl9 tncl8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tncl7 tncl6 tncl5 tncl4 tncl3 tncl2 tncl1 tncl0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tncl[31:0] this counter counts the number of collisions after which transmission succeeded. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1439 of 1817 sep 19, 2011 (38) tcse: transmit carrier sense error counter access this register can be read and written in 32-bit units. address 002e 01f8h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tcse31 tcse30 tcse29 tcse28 tcse27 tcse26 tcse25 tcse24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 tcse23 tcse22 tcse21 tcse20 tcse19 tcse18 tcse17 tcse16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 tcse15 tcse14 tcse13 tcse12 tcse11 tcse10 tcse9 tcse8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tcse7 tcse6 tcse5 tcse4 tcse3 tcse2 tcse1 tcse0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 tcse[31:0] this counter is incremented if a carrier sense error has occurred during transmission. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1440 of 1817 sep 19, 2011 (39) time: mac internal error counter access this register can be read and written in 32-bit units. address 002e 01fch default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 time31 time30 time29 time28 time27 time26 time25 time24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 time23 time22 time21 time20 time19 time18 time17 time16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 time15 time14 time13 time12 time11 time10 time9 time8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 time7 time6 time5 time4 time3 time2 time1 time0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 0 time[31:0] this counter is incremented if an inte rnal error has occurred in mac during transmission or if a packet when length exceeds the value of the lmax register has been transmitted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1441 of 1817 sep 19, 2011 23.4.3 fifo controller control registers (1) mffcont: fifo cont roller control register access this register can be read and written in 32-bit units. address 002e 0200h default value 0000 0000h. this register is cleared to its default value by all types of resets. cautions 1. be sure to set the following bits to the va lues specified below (fixed va lues). if other values are set, the correct operation cannot be guaranteed. ? rxsdma[1:0] = 10 ? asoe = 0 ? aps = 1 ? apl = 1 ? rxthrc = 0 ? txthrc = 0 2. be sure to set bits 29, 28, 23 to 19, 13, and 7 to 3 to ?0?. 31 30 29 28 27 26 25 24 loopback rcsel 0 0 imlp3 imlp2 imlp1 imlp0 r/w r/w r r r/w r/w r/w r/w 23 22 21 20 19 18 17 16 0 0 0 0 0 flowcnt ivpause zeropause r r r r r r/w r/w r/w 15 14 13 12 11 10 9 8 rxsdma1 rxsdma0 0 asoe aps apl rxthrc rxen r/w r/w r r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 0 tabt txthrc txen r r r r r r/w r/w r/w (1/2) bit name description 31 loopback loopback mode loopback between the transmit fifo and receive fifo is performed. 0: normal mode 1: loopback mode 30 rcsel rxclk selection txclk is selected to be internally connected, instead of rxclk. set this bit if it is necessary to change rxclk to txclk when the mac and the fifo controller are in the loopback mode. 0: normal mode 1: clock switch mode (rxclk switched to txclk) 27 to 24 imlp[3:0] set these bits to ?0000?. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1442 of 1817 sep 19, 2011 (2/2) bit name description 18 flowcnt flow control enable/disable 0: flow control is disabled 1: flow control is enabled 17 ivpause interval pause packet transmission control this bit specifies the method of retransmitting a pause packet. 0: retransmission by threshold value of fifo internal pause timer (pausetm.iptime) is not used. 1: retransmission by internal pause timer internal pause timer (pausetm.iptime) is used. 16 zeropause zero pause packet output enable/disable 0: zero pause packet transmission is disabled 1: zero pause packet transmission is enabled 15, 14 rxsdma [1:0] fix these bits to 1 and 0, respectively: 12 asoe fix this bit to 0. 11 aps fix this bit to 1. 10 apl fix this bit to 1. 9 rxthrc fix this bit to 0. 8 rxen reception enable 0: stops reception. 1: enables reception. [timing of setting reception stop] if the bit is set to 0 (reception stop) while a pa cket is being written from the mac to the receive fifo, the receive fifo write circuit is stopped after the packet has been written. the receive fifo of the system stops after all the packets written to the receive fifo have been read. the flow control circuit is not stopped by this bit. 2 tabt transmission abort control this bit retransmits a packet whose transmission has been aborted by the mac. 0: packet is discarded. 1: packet is retransmitted. 1 txthrc fix this bit to 0. 0 txen transmission enable 0: stops transmission. 1: enables transmission [timing of setting transmission stop] if this bit is set to 0 (transmission stop) while a packet is being written to the transmit fifo, writing the transmit fifo is stopped after the packet has been written (after the end flag has been written), and a request for writing the next pa cket is not made. packet transfer to the mac is stopped after all the packets in the transmit fifo have been transferred (after the empty status is indicated). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1443 of 1817 sep 19, 2011 (2) rstcnt: software reset control register this register is used to control software reset. access this register can be read and written in 32-bit units. address 002e 0204h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 17, 15 to 9, and 7 to 1 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 rfflsh r r r r r r r r/w 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 tfflsh r r r r r r r r/w 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 sftrst r r r r r r r r/w bit name description 16 rfflsh receive fifo clear (flush) this bit clears the receive fifo, reception control circuit, flow c ontrol circuit, reception status register, and interrupt registers related to recepti on. when 1 is written to this bit, resetting is started and the circuits are cleared automatic ally. when read, 0 is always returned. 8 tfflsh transmit fifo clear (flush) this bit clears the transmit fifo , transmission control circuit, tr ansmission status register, and interrupt registers related to transmission. when 1 is written to this bit, resetting is started and the circuits are cleared automatically. 0 sftrst software reset this bit resets all the circuits of the fifo controlle r (mff). when 1 is written to this bit, resetting is started and the circuits are cleared automatically. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1444 of 1817 sep 19, 2011 (3) flowthresh: flow control threshold value register this register is used to set threshold values of the rece ive fifo at which flow control and zero pause control frame transmission are started. access this register can be read and written in 32-bit units. address 002e 0218h default value 0600 0200h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 27 and 15 to 11 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 flowthr10 flowthr9 flowthr8 r r r r r r/w r/w r/w 23 22 21 20 19 18 17 16 flowthr7 flowthr6 flowthr5 flowthr4 flowthr3 flowthr2 flowthr1 flowthr0 r/w r/w r/w r/w r/w r/w r r 15 14 13 12 11 10 9 8 0 0 0 0 0 zpthr10 zpthr9 zpthr8 r r r r r r/w r/w r/w 7 6 5 4 3 2 1 0 zpthr7 zpthr6 zpthr5 zpthr4 zpthr3 zpthr2 zpthr1 zpthr0 r/w r/w r/w r/w r/w r/w r r bit name description 26 to 16 flowthr [10:0] these bits specify in bytes the threshold value of the receive fifo at which flow control is started. flow control is started when the amount of data in the receive fifo reaches to the value set to these bits. back pressure tr ansmission is executed in the half- duplex mode and pause control packets are transmitted in the full-duplex mode. writing bits 17 and 16 is ignored because the receive fifo can only be writt en in 32-bit (4-byte) units. when bits 17 and 16 are read, 0 is always returned for each bit. 10 to 0 zpthr[10:0] these bits set in bytes the threshold val ue of zero pause control packet transmission. when zero pause packet transmission is enabled by setting the mffcnt.zeropause bit to 1 (high level) and flow is controlled by pause cont rol packets, the zero pause packet is transmitted when the amount of data in the receive fifo falls below the threshold value set to these bits. writing bits 1 and 0 is ignored because the receive fifo can only be written in 32-bit (4-byte) units. when bits 1 and 0 are read, 0 is always returned for each bit. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1445 of 1817 sep 19, 2011 (4) pausetm: pause timer value register this register is used to set the pause time. access this register can be read and written in 32-bit units. address 002e 0021ch default value 7fff ffffh. this r egister is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 iptime15 iptime14 iptime13 iptime12 iptime11 iptime10 iptime9 iptime8 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 iptime7 iptime6 iptime5 iptime4 iptime3 iptime2 iptime1 iptime0 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 pausetm_ max15 pausetm_ max14 pausetm_ max13 pausetm_ max12 pausetm_ max11 pausetm_ max10 pausetm_ max9 pausetm_ max8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 pausetm_ max7 pausetm_ max6 pausetm_ max5 pausetm_ max4 pausetm_ max3 pausetm_ max2 pausetm_ max1 pausetm_ max0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 31 to 16 iptime [15:0] interval pause packet timer value these bits set the interval between transmitti ng pause packets when interval pause packet transmission is enabled by setting the mffcnt.ivpause bit to high level. time required to transmit one packet = time re quired to transmit 512 bits (circuit size) = 128 txclk cycles default value: about 168 ms when the data rate is 100 mbps, and about 1.68 seconds when the data rate is 10 mbps 15 to 0 pausetm_ max [15:0] pause control timer value of max pause packet these bits set the value of tptv[15:0] when a pause control request is issued to the mac. time required to transmit one packet = time re quired to transmit 512 bits (circuit size) = 128 txclk cycles default value: about 336 ms when the data rate is 100 mbps, and about 3.36 seconds when the data rate is 10 mbps v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1446 of 1817 sep 19, 2011 (5) rxersel: receive error selection register this register is used to select whether to receiv e or discard packets when a reception error occurs. access this register can be read and written in 32-bit units. address 002e 0220h default value 0000 0001h. this register is cleared to its default value by all types of resets. caution be sure to set bits 25 to 23 and 15 to 2 to ?0?. 31 30 29 28 27 26 25 24 rlene vlan usop rpcf rcfr dbnb 0 0 r/w r/w r/w r/w r/w r/w r r 23 22 21 20 19 18 17 16 0 rlor rler rcrce rxer ceps reps paig r r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 0 txrx dvcf r r r r r r r/w r/w (1/2) bit name description 31 rlene receive packet length error 0: receive the packet. 1: discard the packet. 30 vlan vlan packet reception 0: receive the packet. 1: discard the packet. 29 usop undefined opcode control packet 0: receive the packet. 1: discard the packet. 28 rpcf pause control packet 0: receive the packet. 1: discard the packet. 27 rcfr control packet 0: receive the packet. 1: discard the packet. 26 dbnb packet containi ng dribble nibble 0: receive the packet. 1: discard the packet. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1447 of 1817 sep 19, 2011 (2/2) bit name description 22 rlor packet with length field exceeding 1,500 0: receive the packet. 1: discard the packet. 21 rler the length field does not match the data field length. 0: receive the packet. 1: discard the packet. 20 rcrce crc error 0: receive the packet. 1: discard the packet. 19 rxer rxer detection 0: receive the packet. 1: discard the packet. 18 ceps false carrier detection 0: receive the packet. 1: discard the packet. 17 reps a packet of preamble + sfd or a packet whose data field ends with 1 nibble. 0: receive the packet. 1: discard the packet. 16 paig this bit indicates that any of the following condi tions has occurred after the previous reception. ? a carrier length exceeding 6,072 nibbles (3,036 bytes) has been detected. ? the next packet with ifg + preamble + sfd has been received before the time required to transmit 80 bits has elapsed after a packet has been received. ? an illegal preamble or sfd has been received when a pure preamble has been set. 0: receive the packet. 1: discard the packet. 1 txrx if the mac detects a collision in a packet it is receiving 0: receive the packet. 1: discard the packet. 0 dvcf if it is judged that the packet that the mac has received is a valid control packet 0: receive the packet. 1: discard the packet. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1448 of 1817 sep 19, 2011 (6) txstmoni1: transmission status monitor 1 register access this register is read-only, in 32-bit units. address 002e 0230h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 21 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 cse tbp tpp tpcf tcfr r r r r r r r r 15 14 13 12 11 10 9 8 ttbc15 ttbc14 ttbc13 ttbc12 ttbc11 ttbc10 ttbc9 ttbc8 r r r r r r r r 7 6 5 4 3 2 1 0 ttbc7 ttbc6 ttbc5 ttbc4 ttbc3 ttbc2 ttbc1 ttbc0 r r r r r r r r bit name description 20 cse carrier loss was detected during transmission. 19 tbp a collision occurred due to the back pressure function after the previous transmission note 1 . 18 tpp transmission of a transmit pac ket requested during pausing has finished note 2 . 17 tpcf a pause control packet is being transmitted. 16 tcfr a control packet is being transmitted. 15 to 0 ttbc[15:0] indicate the total number of bytes trans mitted, including packets in which a collision has occurred notes 1. this bit indicates that a collision has occurred between when the transmission status was previously updated and when the status is updated this time. 2. this bit is not set to 1 if the packet requested during pausing is a control frame. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1449 of 1817 sep 19, 2011 (7) txstmoni2: transmission status monitor 2 register access this register is read-only, in 32-bit units. address 002e 0234h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 tudr tgnt lcol ecol tedfr tdfr tbro tmul r r r r r r r r 23 22 21 20 19 18 17 16 tdone tflor tfler tcrce tcbc3 tcbc2 tcbc1 tcbc0 r r r r r r r r 15 14 13 12 11 10 9 8 tbyt15 tbyt14 tbyt13 tbyt12 tbyt11 tbyt10 tbyt9 tbyt8 r r r r r r r r 7 6 5 4 3 2 1 0 tbyt7 tbyt6 tbyt5 tbyt4 tbyt3 tbyt2 tbyt1 tbyt0 r r r r r r r r bit name description 31 tudr a transmit packet underrun has been detected note 1 . 30 tgnt a packet exceeding in length sp ecified by lmax has been transmitted note 2 . 29 lcol a late the collision occurred. 28 ecol collisions exceeding the maximum number of collisions occurred. 27 tedfr there was an excessive transmission delay. 26 tdfr transmission delay 25 tbro a broadcast packet was transmitted. 24 tmul a multicast packet was transmitted. 23 tdone end of transmission note 3 22 tflor the length field is greater than 1,500 note 4 . 21 tfler the length field does not match the data field notes 4, 5 . 20 tcrce a crc error occurred when crc automatic appending mode was disabled. 19 to 16 tcbc[3:0] indicates the number time s of retransmission occurred due to a collision note 6 15 to 0 tbyt[15:0] indicates the transmit packet length (number of bytes) when transmission was completed normally note 6 notes 1. this bit is set to 1 only if no collision has occurred. 2. this bit is set to 1 only when the macc1.hugen bit is set to 0. 3. this bit is not set to 1 if transmission has been aborted. 4. this bit is not set to 1 if the macc1.flcht bit is set to 0. 5. a length field exceeding 1,500 bytes se ts tflor (1) and does not set tfler to 1. 6. the value of this field is not co rrect if transmission has been aborted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1450 of 1817 sep 19, 2011 (8) txfinf1: transmission status 1 register access this register is read-only, in 32-bit units. address 002e 0238h default value 0000 0800h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 25 and 15 to 12 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 tpcnt8 r r r r r r r r 23 22 21 20 19 18 17 16 tpcnt7 tpcnt6 tpcnt5 tpcnt4 tpcnt3 tpcnt2 tpcnt1 tpcnt0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 tremain11 tremain10 tremain9 tremain8 r r r r r r r r 7 6 5 4 3 2 1 0 tremain7 tremain6 tremain5 tremain4 tremain3 tremain2 tremain1 tremain0 r r r r r r r r bit name description 24 to 16 tpcnt[8:0] these bits indicate the number of packets (start flag to end flag) that exist in the transmit fifo. the value of this field is incremented w hen one packet has been written by the system. it is decremented when one packet has been read by the mac (upon completion or halting of transmission). 11 to 0 tremain [11:0] these bits indicate the remaining transmit fifo capacity (in bytes) bits 1 and 0 are ignored and always i ndicate 0, 0, because the size of the transmit fifo is 32 bits (4 bytes). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1451 of 1817 sep 19, 2011 (9) txfinf2: transmission status 2 register access this register is read-only, in 32-bit units. address 002e 023ch default value 0000 0001h. this register is cleared to its default value by all types of resets. cautions 1. before rewriting a m ode register related to transmissi on, be sure to confirm that the txfinf2.txstop bit is set to 1. 2. be sure to set bits 31 to 1 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 txstop r r r r r r r r bit name description 0 txstop this bit is set to 1 if no data is in t he transmit fifo while transm ission is stopped (by setting mffcont.txen to 0). before rewriting a mode setting register related to tr ansmission, be sure to confirm that this bit is set to 1. 0: the transmit fifo is operating. 1: the transmit fifo is not operating. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1452 of 1817 sep 19, 2011 (10) rxstmoni: reception status monitor register access this register is read-only, in 32-bit units. address 002e 0240h default value 0000 0000h. this register is cleared to its default value by all types of resets. 31 30 29 28 27 26 25 24 rlene vlan usop rpcf rcfr dbnb rbro rmul r r r r r r r r 23 22 21 20 19 18 17 16 rxok rlor rler rcrce rxer ceps reps paig r r r r r r r r 15 14 13 12 11 10 9 8 rbyt15 rbyt14 rbyt13 rbyt12 rbyt11 rbyt10 rbyt9 rbyt8 r r r r r r r r 7 6 5 4 3 2 1 0 rbyt7 rbyt6 rbyt5 rbyt4 rbyt3 rbyt2 rbyt1 rbyt0 r r r r r r r r (1/2) bit name description 31 rlene receive packet length error this bit indicates that the received packet is less than 64 bytes or greater than 1,518 bytes (less than 64 bytes or greater than 1,522 bytes in the case of vlan). 30 vlan vlan packet this bit indicates that a packet whose tpid field matches vltp has been received note 1 . 29 usop an undefined opcode control packet was received note 2 . 28 rpcf a pause control packet was received note 2 27 rcfr a control packet was received note 2 26 dbnb a packet c ontaining dribble nibble 25 rbro a broadcast packet was received. 24 rmul a multicast packet was received. 23 rxok end of reception note 1 22 rlor a packet with a l ength field exceeding 1,500 bytes note 3 was received. 21 rler the length field does not match the data field length notes 3, 4 . 20 rcrce a crc error has occurred. 19 rxer rxer detection notes 1. this bit is not set to 1 if a crc error or rxer has occurred. 2. this bit is not set to 1 if a crc error has occurred. 3. this bit is not set to 1 if the macc1.flcht bit is set to 0. 4. rlor is set to 1 and rler is not set to 1 if the length field exceeds 1,500. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1453 of 1817 sep 19, 2011 (2/2) bit name description 18 ceps a false carrier was detected note 1 . 17 reps a packet of preamble + sfd or a packet whose data field ends with 1 nibble has been received notes 1 , 2 . 16 paig this bit indicates that any of the followi ng events has occurred after the previous reception note 1 . ? a carrier length exceeding 6,072 nibbles (3,036 bytes) has been detected. ? the next packet with ifg + preamble + sfd has been received before the time required to transmit 80 bits has elapsed after a packet has been received note 2 . ? an illegal preamble or sfd has been received when a pure preamble has been set note 2 . 15 to 0 rbyt[15:0] indicate the number of received bytes notes 1. the event occurred between when the reception stat us was updated previously and when it is updated this time. 2. a packet in which any of these events has occurr ed is ignored and not transferred to the upstream system. the rxstmoni register is updated when dma transfer of the receive packet has been completed (this register indicates the status of the packet transferred by dma). the rxfinf1 register is also updated at the same time. the rxstatus register is updated when dma trans fer of the receive packet has been completed. reception status register 1 (rxfinf1 ) is also updated at the same time. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1454 of 1817 sep 19, 2011 (11) rxfinf1: reception status 1 register access this register is read-only, in 32-bit units. address 002e 0244h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 rplen15 rplen14 rplen13 rplen12 rplen11 rplen10 rplen9 rplen8 r r r r r r r r 7 6 5 4 3 2 1 0 rplen7 rplen6 rplen5 rplen4 rplen3 rplen2 rplen1 rplen0 r r r r r r r r bit name description 15 to 0 rplen[15:0] these bits indicate the receive packet length in bytes. the ethernet controller uses the value of rplen for the size field when writing back the receive descriptor. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1455 of 1817 sep 19, 2011 (12) rxfinf2: reception status 2 register access this register is read-only, in 32-bit units. address 002e 0248h default value 0000 0800h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 25 and 15 to 12 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 rpcnt8 r r r r r r r r 23 22 21 20 19 18 17 16 rpcnt7 rpcnt6 rpcnt5 rpcnt4 rpcnt3 rpcnt2 rpcnt1 rpcnt0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 rremain11 rremain10 rremain9 rremain8 r r r r r r r r 7 6 5 4 3 2 1 0 rremain7 rremain6 rremain5 rremain4 rremain3 rremain2 rremain1 rremain0 r r r r r r r r bit name description 24 to 16 rpcnt[8:0] these bits indicate the number of packets (start flag to end flag) in the receive fifo. the value of this field is incremented when one pac ket has been written by the mac (a packet that has not been received but discarded does not caus e the value of this field to increment). the value of this field is decremented when a packet has been read from the dmac in the ethernet controller or, if the packe t is canceled, when the internal operation to cancel the packet (discard the packet) has been completed. 11 to 0 rremain [11:0] these bits indicates the remaining receive fifo capacity (in bytes). bits 1 and 0 are ignored and always indicate 0, 0, because the size of the receive fifo is 32 bits (4 bytes). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1456 of 1817 sep 19, 2011 (13) rxfinf3: reception status 3 register this register indicates the status of the receive fifo while reception is stopped. access this register is read-only, in 32-bit units. address 002e 024ch default value 0000 0001h. this register is cleared to its default value by all types of resets. cautions 1. before rewriting a mode register related to reception or flow control, be sure to confirm that the rxfinf3.rxstop bit is set to 1. 2. be sure to set bits 31 to 1 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 rxstop r r r r r r r r bit name description 0 rxstop this bit is set to 1 if no data is in th e receive fifo while reception is stopped (by setting mffcont.rxen to 0). before rewriting a mode setting register related to reception or flow control, confirm that the rxstop bit is set to 1. 0: receive fifo is operating. 1: receive fifo is not operating. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1457 of 1817 sep 19, 2011 (14) fstatus: fifo status interrupt register an intetmfs interrupt (fifo status in terrupt) is generated if it is not masked by the fstatus_mask register. the intetmfs interrupt signal is kept asserted while any bit of this register is set. if the interrupt source masked by a bit of the fstatus_mask register has been generated, the corresponding bit of this register is set as well. all the bits of the fstatus register are cleared when the register is read. access this register is read-only, in 32-bit units. address 002e 0250h default value 0000 0000h. this register is cleared to its default value by all types of resets. cautions 1. the fifo status interrupt status register is cleared when it is read. it is recommended to copy interrupt sources to variabl es so that several interrupt so urces that are generated at the same time can be detected. 2. be sure to set bits 31 to 25, 23 to 17, 15 to 13, 9, 8, 5, and 2 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 tacof r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 racof r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 tsup tfnrty tfwe 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 rffe rsup 0 rfwe rfof 0 rfflw rfzp r r r r r r r r (1/2) bit name description 24 tacof this bit is set to 1 when the txab tcnt register (tx abor t counter) overflows. 16 racof this bit is set to 1 when the r xabcnt register (rx abort counter) overflows. 12 tsup tx status update this bit is set to 1 when the transmission st atus is updated in the txstmoni1 and txstmoni2 registers. 11 tfnrty transmit fifo abort (transmit fifo no retry) this bit is set to 1 if transmission has fa iled and the data in the fifo has been discarded. in this case, txabtcnt is incremented. 10 tfwe this bit is set to 1 if a tr ansmit fifo write error has occurred. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1458 of 1817 sep 19, 2011 (2/2) bit name description 7 rffe receive fifo flag error this bit indicates that handshaking was not corre ctly performed when receive data was written from the mac to the receive fifo. the receive packet and reception status are invalid but reception is not canceled. ? if the reception status is updated before all receive data is stored in the fifo, the end of the packet is assumed as soon as the reception status has been updated. ? if the reception status is not updated after all receive data has been stored in the fifo, the reception status is assumed to be all ?0?. 6 rsup this bit is set to 1 when the reception stat us monitor register (rxstmoni) is updated. this bit indicates that a valid value can be read from the rxstmoni or rxfinf1 register. 4 rfwe receive fifo write error this bit is set to 1 if a packet of 32 bits (4 bytes) or less has been received and could not be written to the receive fifo. 3 rfof this bit is set to 1 if the receive fifo overflows. 1 rfflw this bit indicates that the data in the receive fifo is greater than the set value of the flowthrsh.flowthr bit. 0 rfzp this bit indicates that the data in the receive fifo is greater than the set value of the flowthrsh.zpthr bit. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1459 of 1817 sep 19, 2011 (15) fstatus_mask: fifo status interrupt mask register access this register can be read and written in 32-bit units. address 002e 0254h default value 0101 1fffh. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 25, 23 to 17, 15 to 13 to ?0? and bits 9, 8, 5, and 2 to ?1?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 tacof r r r r r r r r/w 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 racof r r r r r r r r/w 15 14 13 12 11 10 9 8 0 0 0 tsup tfnrty tfwe 1 1 r r r r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rffe rsup 1 rfwe rfof 1 rfflw rfzp r/w r/w r/w r/w r/w r/w r/w r/w bit name description 24 tacof 0: interrupt enabled 1: interrupt disabled (interrupt masked) 16 racof 0: interrupt enabled 1: interrupt disabled (interrupt masked) 12 tsup 0: interrupt enabled 1: interrupt disabled (interrupt masked) 11 tfnrty 0: interrupt enabled 1: interrupt disabled (interrupt masked) 10 tfwe 0: interrupt enabled 1: interrupt disabled (interrupt masked) 7 rffe 0: interrupt enabled 1: interrupt disabled (interrupt masked) 6 rsup 0: interrupt enabled 1: interrupt disabled (interrupt masked) 4 rfwe 0: interrupt enabled 1: interrupt disabled (interrupt masked) 3 rfof 0: interrupt enabled 1: interrupt disabled (interrupt masked) 1 rfflw 0: interrupt enabled 1: interrupt disabled (interrupt masked) 0 rfzp 0: interrupt enabled 1: interrupt disabled (interrupt masked) v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1460 of 1817 sep 19, 2011 (16) txstatus: transmission status interrupt register this register stores the cumulative result of the transmi ssion status. an intetmts interrupt (transmission status interrupt) is generated if it is not masked by the setti ng of the txstatus_mask register . the intetmts interrupt signal is kept asserted while any bit of this register is set. if an interrupt source masked by a bit of the txstatus _mask register has been generat ed, the corresponding bit of this register is set as well. all the bits of the txstatus register are clear ed when the register is read. access this register is read-only, in 32-bit units. address 002e 0258h default value 0000 0000h. this register is cleared to its default value by all types of resets. cautions 1. the transmission status in terrupt register is cleared when it is read. it is recommended to copy interrupt sources to variabl es so that several interrupt so urces that are generated at the same time can be detected. 2. be sure to set bits 31 to 17 and 15 to 8 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 tab r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 tgnt lcol ecol tedfr tdfr tflor tfler tcrce r r r r r r r r bit name description 16 tab transmission has been aborted. 7 tgnt a packet exceeding lmax has been transmitted (tab source). this bit is not set to 1 if macc.hugen = 1. 6 lcol a late collision has been detected (tab source). 5 ecol collisions have occurred exceeding the maximum number of collisions (tab source). 4 tedfr an excessive transmission delay has been detected (tab source). 3 tdfr a transmission delay has occurred. 2 tflor the length field is greater than 1,500. this bit is also set to 1 when a vlan packet pause control frame is transmitted. it is not set to 1 if macc1.flcht = 0. 1 tfler the length field does not match the data field length. this bit is not set to 1 if macc1.flcht = 0. a length field exceeding 1,500 is reported to tflor and tfler is not set to 1. 0 tcrce crc error this bit is set to 1 if trans mission is performed with the crc automatic appending mode disable (macc1.paden = 0 and crcen = 0). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1461 of 1817 sep 19, 2011 (17) txstatus_mask: transmission status interrupt mask/register this register is used to mask the trans mission status interrupt (intetmts). if an interrupt source that is unmasked by this register is generated, intcts is generated. intcts is kept asserted while the source is being generated. if an interrupt source that is masked by the txstatus_mask register is generated, the corresponding bit of the txstatus register is set to 1. access this register can be read and written in 32-bit units. address 002e 025ch default value 0001 01ffh. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 17 and 15 to 8 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 tab r r r r r r r r/w 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 tgnt lcol ecol tedfr tdfr tflor tfler tcrce r/w r/w r/w r/w r/w r/w r/w r/w bit name description 16 tab 0: interrupt enabled 1: interrupt masked 7 tgnt 0: interrupt enabled 1: interrupt masked 6 lcol 0: interrupt enabled 1: interrupt masked 5 ecol 0: interrupt enabled 1: interrupt masked 4 tedfr 0: interrupt enabled 1: interrupt masked 3 tdfr 0: interrupt enabled 1: interrupt masked 2 tflor 0: interrupt enabled 1: interrupt masked 1 tfler 0: interrupt enabled 1: interrupt masked 0 tcrce 0: interrupt enabled 1: interrupt masked v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1462 of 1817 sep 19, 2011 (18) rxstatus: reception status interrupt register this register stores the cumulative re sult of the reception status. if an inte rrupt source that is not masked by the setting of the rxstatus_mask register has been generat ed, the intetmrs interrupt is generated. the intetmrs interrupt signal is kept assert ed while any bit of this register is set. if an interrupt source masked by the rxstatus_mask regist er has been generat ed, the corresponding bit of this register is set as well. this register is not affected by the setting of rxersel (receive error selection register). all the bits of the rxstatus register are cleared when the register is read. access this register is read-only, in 32-bit units. address 002e 0260h default value 0000 0000h. this register is cleared to its default value by all types of resets. cautions 1. the reception status interrupt status register is cleared when it is re ad. it is recommended to copy interrupt sources to variabl es so that several interrupt so urces that are generated at the same time can be detected. 2. be sure to set bits 31 to 15 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 rlene vlan usop rpcf rcfr dbnb rlor r r r r r r r r 7 6 5 4 3 2 1 0 rler rcrce rxer ceps reps paig txrx dvcf r r r r r r r r (1/2) bit name description 14 rlene receive packet length error this bit indicates that the received packet is less than 64 bytes or greater than 1,518 bytes (less than 64 bytes or greater than 1,522 bytes in the case of a vlan packet). 13 vlan vlan packet reception a packet whose tpid field matches vltp has been received note 1 . 12 usop a control packet with an undefined opcode has been received note 2 . 11 rpcf a pause control packet received note 2 . 10 rcfr a control packet has been received note 2 . 9 dbnb a packet containing dr ibble nibble has been received. 8 rlor the length field is greater than 1,500. 7 rler the length field does not match the data field length notes 3, 4 . 6 rcrce a receive crc error occurred. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1463 of 1817 sep 19, 2011 (2/2) bit name description 5 rxer rxer has been detected. 4 ceps a false carrier has been detected note 5 . 3 reps a packet of preamble + sfd or a packet whose data field ends with 1 nibble has been received notes 5, 6 . 2 paig this bit indicates that any of the followi ng events has occurred after the previous reception note 5 . ? a carrier length exceeding 6,072 nibbles (3,036 bytes) has been detected. ? the next packet with ifg + preamble + sfd has been received before the time required to transmit 80 bits has elapsed after a packet has been received. ? an illegal preamble or sfd has been received when the macc1.purep bit is set. 1 txrx transmission is started (collision occurs) duri ng half-duplex reception (immediately after reception has been started). 0 dvcf the received packet is a valid cont rol packet (that does not contain an error). notes 1. this bit is not set to 1 if a crc error or rxer has occurred. 2. this bit is not set to 1 if a crc error has occurred. 3. this bit is not set to 1 if the macc1.flcht bit is 0. 4. rlor is set to 1 and rler is not set to 1 if the length field exceeds 1,500. 5. this bit indicates that one of the events has o ccurred between when the reception status was updated previously and when it is updated this time. 6. a packet in which these events have occurred is ignored and not transferred to the upstream system. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1464 of 1817 sep 19, 2011 (19) rxstatus_mask: reception status interrupt mask register this register masks the recepti on status interrupt (intetmrs). if an interrupt source that is unmasked by this register is generated, intetmrs is generated. intetmrs is kept asserted while the source is being generated. if an interrup t source that is masked by this register is generated, the corresponding bit of the rxstatus register is set to 1. access this register can be read and written in 32-bit units. address 002e 0264h default value 0000 07ffh. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 15 to ?1?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 rlene vlan usop rpcf rcfr dbnb rlor r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rler rcrce rxer ceps reps paig txrx dvcf r/w r/w r/w r/w r/w r/w r/w r/w (1/2) bit name description 14 rlene 0: interrupt generated 1: interrupt masked 13 vlan 0: interrupt generated 1: interrupt masked 12 usop 0: interrupt generated 1: interrupt masked 11 rpcf 0: interrupt generated 1: interrupt masked 10 rcfr 0: interrupt generated 1: interrupt masked 9 dbnb 0: interrupt generated 1: interrupt masked 8 rlor 0: interrupt generated 1: interrupt masked 7 rler 0: interrupt generated 1: interrupt masked 6 rcrce 0: interrupt generated 1: interrupt masked v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1465 of 1817 sep 19, 2011 (2/2) bit name description 5 rxer 0: interrupt generated 1: interrupt masked 4 ceps 0: interrupt generated 1: interrupt masked 3 reps 0: interrupt generated 1: interrupt masked 2 paig 0: interrupt generated 1: interrupt masked 1 txrx 0: interrupt generated 1: interrupt masked 0 dvcf 0: interrupt generated 1: interrupt masked v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1466 of 1817 sep 19, 2011 (20) txabtcnt: transmission abort counter this is a transmission abort counter. it counts the number of packets that have resulted in a mac transmission error (including an underrun). access this register can be read and written in 32-bit units. address 002e 0270h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?1?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 tabcnt15 tabcnt14 tabcnt13 tabcnt 12 tabcnt11 tabcnt10 tabcnt9 tabcnt8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tabcnt7 tabcnt6 tabcnt5 tabcnt 4 tabcnt3 tabcnt2 tabcnt1 tabcnt0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 0 tabcnt [15:0] transmission abort count these bits count the number of packets that have resulted in a mac transmission error (including an underrun). this counter is not incremented when mffcont.tabt is set to 1 to retransmit an aborted packet. if mffcont.txthrc = 1, retransmission is not executed when transmission has been aborted. in this case, the counter is incremented. packets are counted after 68 bytes have been tran sferred because they are not retransmitted by a retry request (usually, the mac does not i ssue a retry request after 64 bytes have been transferred). if the count value overflows, the value of these bits returns to 0 and the fstatus.tacof bit is set. these bits are not cleared by resetting the tran smission circuit (by setting tfrst and tfflsh). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1467 of 1817 sep 19, 2011 (21) rxabtcnt: reception abort counter this is a reception abort counter. it counts the number of receive packets that have been discarded because of the status of the receive packet, the st atus of the receive fifo, address filter ing by the mac, and reception of a control packet. access this register can be read and written in 32-bit units. address 002e 0274h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 16 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 tabcnt15 tabcnt14 tabcnt13 tabcnt 12 tabcnt11 tabcnt10 tabcnt9 tabcnt8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 tabcnt7 tabcnt6 tabcnt5 tabcnt 4 tabcnt3 tabcnt2 tabcnt1 tabcnt0 r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 0 tabcnt [15:0] reception abort count these bits count the number of receive packets th at have been discarded because of the status of the receive packet, the status of the receive fifo, address filtering by the mac, and reception of a control packet. if the count value overflows, the value of these bits returns to 0 and the fstatus.racof bit is set. these bits are not cleared by resetting the rec eption circuit (by setting rfrst and rfflsh). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1468 of 1817 sep 19, 2011 23.4.4 dmac control registers in ethernet controller (1) ethmode: core function control register this register is used to control reception and transmission. access this register can be read and written in 32-bit units. address 002e 0300h default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 19 and 16 to 0 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 rxs txs 0 r r r r r r/w r/w r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 r r r r r r r r bit name description 18 rxs this bit enables reception. this bit is aut omatically cleared after being set to 1. 17 txs this bit enables transmission. this bit is automatically cleared after being set to 1. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1469 of 1817 sep 19, 2011 (2) intms: interrupt register access this register can be read and written in 32-bit units. address 002e 0304h default value 0700 0700h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 27, 23 to 19, 15 to 11, and 7 to 3 to ?0?. remark the rbei, reci, rxi, tbei, teci, and txi bits of t he intms register are cleared when they are read. 31 30 29 28 27 26 25 24 0 0 0 0 0 rbemsk recmsk rxmsk r r r r r r/w r/w r/w 23 22 21 20 19 18 17 16 0 0 0 0 0 rbei reci rxi r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 tbemsk tecmsk txmsk r r r r r r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 0 0 tbei teci txi r r r r r r r r (1/2) bit name description 26 rbemsk this bit masks the rbei interrupt of bit 18. 0: interrupt enabled 1: interrupt masked 25 recmsk this bit masks the reci interrupt of bit 17. 0: interrupt enabled 1: interrupt masked 24 rxmsk this bit masks the rxi interrupt of bit 16. 0: interrupt enabled 1: interrupt masked 18 rbei this bit indicates the occurrence of the re ceive data buffer access erro r interrupt. it is cleared when read. 0: interrupt did not occur. 1: interrupt occurred. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1470 of 1817 sep 19, 2011 (2/2) bit name description 17 reci this bit indicates the occurrence of the recept ion (dma) end of chain interrupt. it is cleared when read. 0: interrupt did not occur. 1: interrupt occurred. 16 rxi this bit indicates the occurrence of the packet reception (dma) completion interrupt. it is cleared when read. 0: interrupt does not occur. 1: interrupt occurs. 10 tbemsk this bit masks the tebi interrupt of bit 2. 0: interrupt enabled 1: interrupt masked 9 tecmsk this bit masks the tbci interrupt of bit 1. 0: interrupt enabled 1: interrupt masked 8 txmsk this bit masks the txi interrupt of bit 0. 0: interrupt enabled 1: interrupt masked 2 tbei this bit indicates the occurrence of the transm it data buffer access error interrupt. it is cleared when read. 0: interrupt did not occur. 1: interrupt occurred. 1 teci this bit indicates the occurrence of the tran smission (dma) end of chain interrupt. it is cleared when read. 0: interrupt did not occur. 1: interrupt occurred. 0 txi this bit indicates the occurrence of the packet transmission (dma) completion interrupt. it is cleared when read. 0: interrupt did not occur. 1: interrupt occurred. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1471 of 1817 sep 19, 2011 (3) transctl: transmit control register this register is used to control transfer by the dmac in the ethernet controller. access this register can be read and written in 32-bit units. address 002e 0308h default value 0003 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 26, 23 to 18, and 15 to 1 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 rxen_sta txen_sta r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 rxen txen r r r r r r r/w r/w 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 rxchksm en r r r r r r r r/w bit name description 25 rxen_sta this bit indicates the reception status. 0: reception is not in progress (idle status). 1: reception is in progress. reception is stopped when the rbei or reci interrup t, which is controlled by the interrupt register (intms), has occurred. at this time, this bit is cleared (0). 24 txen_sta this bit indicate s the transmission status. 0: transmission is not in progress (idle status). 1: transmission is in progress. transmission is stopped when the tbei or teci in terrupt, which is controlled by the interrupt register (intms), has occurred. at this time, this bit is cleared to 0. 17 rxen this bit enables reception. 0: reception disable (dma reception is stopped) . 1: reception enable 16 txen this bit enables transmission. 0: transmission disable (dma transmission is stopped) . 1: transmission enable 0 rxchksmen this bit enables the receive checksum appending function. 0: disabled 1: enabled v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1472 of 1817 sep 19, 2011 (4) sftrst: software reset control register this register is used to set a software rese t for the dmac in the ethernet controller. access this register can be read and written in 32-bit units. address 002e 030ch default value 0000 0000h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 1 to ?0?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 sftrst r r r r r r r r/w bit name description 0 sftrst software reset when this bit is set to 1, the dmac in the ethernet controller is reset. the receive checksum unit is also reset. this bit is automatically cleared to 0 after 1 has been written to it. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1473 of 1817 sep 19, 2011 (5) dmacm: dmac mode control register access this register can be read and written in 32-bit units. address 002e 0310h default value 0000 0010h. this register is cleared to its default value by all types of resets. caution be sure to set bits 31 to 11, 7 to 5, 3 to 0 to ?0? and bit 4 to ?1?. 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 r r r r r r r r 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 burst2 burst1 burst0 r r r r r r/w r/w r/w 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 r r r r r r r r bit name description these bits specify the type of burst transfer. burst2 burst1 burs t0 type operation 0 0 0 single single transfer 0 1 1 incr4 4-beat increment burst 1 0 1 incr8 8-beat increment burst 1 1 1 incr16 16-beat increment burst other than above setting prohibited 10 to 8 burst [2:0] v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1474 of 1817 sep 19, 2011 (6) rxdp: receive descriptor pointer register this register is used to set the pointer position of the receive descriptor of the dmac in the ethernet controller. access this register can be read and written in 32-bit units. address 002e 0320h default value ffff fffch. this register is clear ed to its default value by all types of resets. 31 30 29 28 27 26 25 24 rxdp31 rxdp30 rxdp29 rxdp28 rxdp27 rxdp26 rxdp25 rxdp24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 rxdp23 rxdp22 rxdp21 rxdp20 rxdp19 rxdp18 rxdp17 rxdp16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 rxdp15 rxdp14 rxdp13 rxdp12 rxdp11 rxdp10 rxdp9 rxdp8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 rxdp7 rxdp6 rxdp5 rxdp4 rxdp3 rxdp2 rxdp1 rxdp0 r/w r/w r/w r/w r/w r/w r r bit name description 31 to 0 rxdp[31:0] these bits set the pointer position of the receive descriptor. specify the first address of the receive descriptor chain. bits 1 and 0 are fixed to 0, 0. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1475 of 1817 sep 19, 2011 (7) lstrxdp: last receive de scriptor pointer register this register indicates the last receive descripto r address of the dmac in the ethernet controller. access this register can be read-only, in 32-bit units. address 002e 0320h default value ffff fffch. this register is clear ed to its default value by all types of resets. 31 30 29 28 27 26 25 24 lstrxdp31 lstrxdp30 lstrxdp29 lstrxdp28 lstrxdp27 lstrxdp26 lstrxdp25 lstrxdp24 r r r r r r r r 23 22 21 20 19 18 17 16 lstrxdp23 lstrxdp22 lstrxdp21 lstrxdp20 lstrxdp19 lstrxdp18 lstrxdp17 lstrxdp16 r r r r r r r r 15 14 13 12 11 10 9 8 lstrxdp15 lstrxdp14 lstrxdp13 lstrxdp12 lstrxdp11 lstrxdp10 lstrxdp9 lstrxdp8 r r r r r r r r 7 6 5 4 3 2 1 0 lstrxdp7 lstrxdp6 lstrxdp5 lstrxdp4 lstrxdp3 lstrxdp2 lstrxdp1 lstrxdp0 r r r r r r r r bit name description 31 to 0 lstrxdp [31:0] these bits indicate the last receive descriptor pointer address. they hold the address information of the descriptor that was accessed last. bits 1 and 0 are fixed to 0, 0. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1476 of 1817 sep 19, 2011 (8) txdp: transmit descr iptor pointer register this register is used to set the pointer position of the transmit descriptor of the dmac in the ethernet controller. access this register can be read and written in 32-bit units. address 002e 0328h default value ffff fffch. this register is clear ed to its default value by all types of resets. 31 30 29 28 27 26 25 24 txdp31 txdp30 txdp29 txdp28 txdp27 txdp26 txdp25 txdp24 r/w r/w r/w r/w r/w r/w r/w r/w 23 22 21 20 19 18 17 16 txdp23 txdp22 txdp21 txdp20 txdp19 txdp18 txdp17 txdp16 r/w r/w r/w r/w r/w r/w r/w r/w 15 14 13 12 11 10 9 8 txdp15 txdp14 txdp13 txdp12 txdp11 txdp10 txdp9 txdp8 r/w r/w r/w r/w r/w r/w r/w r/w 7 6 5 4 3 2 1 0 txdp7 txdp6 txdp5 txdp4 txdp3 txdp2 txdp1 txdp0 r/w r/w r/w r/w r/w r/w r r bit name description 31 to 0 txdp[31:0] these bits set the pointer position of the transmit descrip tor. specify the first address of the transmit descriptor chain. bits 1 and 0 are fixed to 0, 0. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1477 of 1817 sep 19, 2011 (9) lsttxdp: last transmit descriptor pointer register this register indicates the last transmit descripto r address of the dmac in the ethernet controller. access this register can be read-only, in 32-bit units. address 002e 032ch default value ffff fffch. this register is clear ed to its default value by all types of resets. 31 30 29 28 27 26 25 24 lsttxdp31 lsttxdp30 lsttxdp29 lsttxdp28 lsttxdp27 lsttxdp26 lsttxdp25 lsttxdp24 r r r r r r r r 23 22 21 20 19 18 17 16 lsttxdp23 lsttxdp22 lsttxdp21 lsttxdp20 lsttxdp19 lsttxdp18 lsttxdp17 lsttxdp16 r r r r r r r r 15 14 13 12 11 10 9 8 lsttxdp15 lsttxdp14 lsttxdp13 lsttxdp12 lsttxdp11 lsttxdp10 lsttxdp9 lsttxdp8 r r r r r r r r 7 6 5 4 3 2 1 0 lsttxdp7 lsttxdp6 lsttxdp 5 lsttxdp4 lsttxdp3 lsttx dp2 lsttxdp1 lsttxdp0 r r r r r r r r bit name description 31 to 0 lsttxdp [31:0] these bits indicate the last transmit descriptor pointer address. they hold the address information of the descriptor that was accessed last. bits 1 and 0 are fixed to 0, 0. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1478 of 1817 sep 19, 2011 23.5 mac/fifo/dmac function 23.5.1 frame format with ethernet/ieee802.3, information is transmitted or received in the form of a packet or a frame. the ethernet controller supports the following three types of frames. ? basic frames ? vlan frames ? pause control frames (1) basic frames the basic frame used with ether net consists of a preamble, frame start delimiter (sfd), destination address (da), source address (sa), type/length field (type/len), dat a field (data), and frame check sequence (fcs). the packet size is defined to be 64 bytes minimum and 1,518 bytes maximum, excluding the preamble (pa) and frame start delimiter (sfd). figure 23-3. basic frame structure preamble 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 4 bytes 46 to 1,500 bytes sfd da type/ len data+pad sa fcs packet frame (a) preamble and frame start delimiter (sfd) the preamble and sfd consist of a repet ition of 10 for 62 bits following by 11 at the end, and indicate the header of each frame. (b) destination address (da) the destination address field indicates the destination ma c address. a unicast address, multicast address, or broadcast address is written to this field. (c) source address (sa) the source mac address is written to this field. (d) type/length field as an ethernet frame, this field is a type field that indicates a protocol type. as an ieee802.3 frame, this field is a length fiel d that indicates the length of the data field. (e) data field the data field size ranges from 46 bytes to 1,500 bytes. depending on the communication protocol, the data fi eld may be divided and special header information inserted. the ethernet controller us es the data in this field only for calculating the crc (cycle redundancy check) for the fcs and does not check its contents. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1479 of 1817 sep 19, 2011 (f) frame check sequence (fcs) the frame check sequence field is used to write 32-bit crc code to check the transfer data. the ethernet controller can automatically append a crc to a transmit frame. (2) vlan frames the structure of a vlan frame (qtag frame) is s lightly different from that of a basic frame. a 4-byte vlan header is inserted immediately after the s ource address field. as a result, the minimum packet length of a vlan frame is 64 bytes and the maximum packet length is 1,522 bytes. the ethernet controller has a vlan fram e detection function. if a transmit pa cket or a receive packet is identified as a vlan frame, packet processing is performed based on the receive packet length. figure 23-4. vlan frame structure preamble 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 4 bytes 46 to 1,500 bytes sfd da type/ len data+pad sa fcs 2 bytes tpid 2 bytes tci remark tpid: tag protocol id tci: tag control information tpid+tci: vlan header caution the ethernet controller recognizes the valu e set to the vltp.vltp[15:0] bits as a vlan frame (tpid). the default value is 0000h. for details , refer to 23.4.1 (10) vl tp: vlan type register. (3) pause control frames a pause control frame is a 64-byte packet with a dedicated format. the destination address field has a fixed value of 01-80-c2-00-00-01h. the type/length field has a value of 8808h, which indica tes a control frame, and the opcode has a value of 0001h, which indicates pause control. the parameter field has t he value specified by the pausetm register. the unused area following the parameter field is f illed with pad data consisting of zeros. figure 23-5. pause control frame structure preamble 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 4 bytes 42 bytes sfd da type pad (00h) sa 2 bytes op code 2 bytes para meter fcs remark da: fixed address (01-80-c2-00-00-01h) type/len: type of mac control frame (88-08h) opcode: pause op-code (00-01h) parameter: pause command paramet er (specified by pausetm register) pad: all bits are filled with zero (00h) v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1480 of 1817 sep 19, 2011 the ethernet controller can automatically transmit the pause control fr ame according to the quantity of the data remaining in the receive fifo. when a frame is received, the frame ty pe is identified by the da, type, and opcode fields as shown in table 23- 5. table 23-5. frame reception da type opcode frame identified 01-80-c2-00-00-01 8808h 0001h pause frame 01-80-c2-00-00-01 8808h other than 0001h not supported 01-80-c2-00-00-01 other than 8808h xxxx data frame unicast (stat. adr.) 8808h 0001h pause frame unicast (stat. adr.) 8808h other than 0001h not supported unicast (stat. adr.) other than 8808h xxxx data frame multicast 8808h xxxx not supported multicast other than 8808h xxxx data frame unicast (stat. adr.) 8808h xxxx not supported unicast (stat. adr.) other than 8808h xxxx data frame (4) pause control frames containing vlan tag the ethernet controller does not support a p ause control frame containing a vlan tag. it receives such a frame as an ordinary vlan packet, bu t the rbro and rlor flags of the reception status monitor register (rxstmoni) are set (t he rpcf and rfcr flags are not set). (5) envelope frames an envelope frame is a frame format that was added ieee802.3as (2005). because it is a frame for 1,000 mbps half-duplex communication, the ethernet controller does not support this type of frame. if an envelope frame containing an extension field is received, a crc error or length field mismatch occurs, or the receive fifo overflows. check the reception status and discard such a frame. the ethernet controller cannot transmit an enve lope frame containing an extension field. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1481 of 1817 sep 19, 2011 23.5.2 transmit function the ethernet controller ge nerates a transmit frame as defined by ieee802.3 from the transmit packe t data that is stored in the transmit fifo by the dmac in the ethernet controller via dma transfer, and outputs that transmit frame to a phy device. if a collision is detected, the frame is retransmitted by using a random back-off algor ithm. the status information of each transmit frame, such as excessive transmit delays and collisions exceeding the maximum number, is reflected in the txstatus register, and the number of times each event has occurred in all transmit frames is counted by statistics counters. (1) transmit frame the transmit frame defined by ieee802.3 consists of the following six fields (refer to figure 23-3 basic frame structure ). ? preamble ? frame start delimiter (sfd) ? destination address (da) ? source address (sa) ? length field (len) ? data and frame check sequence (fcs) for transmission, the ethernet controller generates the preamble, frame start delimiter, and fcs data. (2) transmission clock the ethernet controller operates in synchronization with the transmission clock (txclk) supplied by an external phy device. transmit packet data stored in the transmit fi fo by dma transfer is synchronized in the fifo with txclk and output to the phy device. ieee802.3 define s the frequency of txclk as 25 mhz100 ppm when the data rate is 100 mbps and 2.5 mhz100 ppm when the data rate is 10 mbps. (3) carrier sense signal (crs) during half-duplex communication, if a carrier is detecte d (crs = 1) after the ether net controller has stored transmit data in the fifo, and transmission is enabled, t he ethernet controller postpones transmission until the end of the carrier (crs = 0). after the carrier ends, trans mission is started when the inter-packet gap (ipg) count set by the ipgt register has been reached. if no carrier is detected (crs = 0) when transmission is enabled and if the ipg count is reached after the carrier immediately before has ended, transmission is started immediately. when a frame is transmitted from the source terminal, the carrier sense signal is looped back from the phy device and transmitted (received). if the carrier sense signal is masked during transmission from the source terminal by the system (phy) configured by the user , the ethernet controller detects a ca rrier sense error but this does not affect the transmission itself. (4) collision detection (c ol) and retransmission if the ethernet controller detects a co llision during half-duplex communication, it transmits jam data (an error crc) and stops transmission. if fewer than the maximum number of collisions (defau lt value: 15) are detected in the collision window, transmission is kept waiting by a random back-off algorithm and data in the transmit fifo is retransmitted (in this case, data is not captured into the fifo again by dma). if more than exceeding the maximum number of collisions are detected or if a late collision (collision detected outside the collision window) occurs, transmissi on is aborted and the transmit data is discarded. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1482 of 1817 sep 19, 2011 (5) inter-packet gap (ipg) the ipg is specified by the ipgt regist er if the source terminal successivel y transmits data; otherwise, it is be specified by the ipgr register. the ethernet controller starts counting the ipg when the sour ce or an other terminal has completed transmission. if a request for next transmission is issued from the fifo after transmission from the source terminal is executed and before the ipg count reaches the val ue of the ipgt register, it is assu med that the data is to be transmitted successively (back to back), and transmission is started as soon as counting is complete. when a packet is to be transmitted after transmission from an other terminal, the ipg c ount is controlled by the ipgr register. the ipgr register specifies the total time of the ipg in its ipgr2 field. the time during which a carrier is to be detected in the first half of the ipg is set in the ipgr1 field. if a carrier is detected during the time set in the ipgr1 field, the ethernet c ontroller waits for the end of the carrie r and then starts ipg counting from the beginning. if no carrier is detected during the time set in the ipgr1 field, transmission is started after the ipg period set in the ipgr2 field has elapsed. if transmission is not started before the time required to transmit 24,288 bits has elaps ed (2.43 ms when the data rate is 10 mbps and 243.88 s when the data rate is 100 mbps to have occurred) after the next transmission request has been received from the fifo, an excessive tr ansmission delay is assumed, transmission is aborted, and the transmit data is discarded. the set value of the ipgt and ipgr registers and the actual ipg period are calculated by the following expression. [when the data rate is 100 mbps] back-to-back transmission: ipg = (5 + ipgt) x 40 ns (default value: 960 ns) non back-to-back transmission: ipg = (5 + ipgr2) x 40 ns (default value: 960 ns) carrier sense time: (2 + ipgr1) x 40 ns (default value: 640 ns) [when the data rate is 10 mbps] back-to-back transmission: ipg = (5 + ipgt) x 400 ns (default value: 9.6 s) non back-to-back transmission: ipg = (5 + ipgr2) x 400 ns (default value: 9.6 s) carrier sense time: (2 + ipgr1) x 400 ns (default value: 6.4 s) caution because of the specification of ieee802.3, set the ipg to 960 ns or more when the data rate is 100 mbps and 9.6 s or more when the da ta rate is 10 mbps. the default value of the ipgt and ipgr register s is the minimum rated va lue and may be used as is. figure 23-6. ipg during back-to-back transmission ipg minimum gap = ipgt frame data frame data preamble sfd transmit packet time transmit packet v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1483 of 1817 sep 19, 2011 figure 23-7. ipg during non back-to-back transmission ipg minimum gap = ipgr2 carrier sense time = ipgr1 frame data frame data preamble sfd receive packet transmit packet time (6) preamble/crc/pad appending a 7-byte preamble and a 1-byte frame start delimiter (s fd) are appended to the beginning of the transmit packet supplied from the fifo. macc1.crce n operation 0 the end of the transmit packet must be a valid frame check sequence (fcs). the mac checks the fcs. if the fcs value is not correct, an error is reported by a transmission status interrupt (intetmts). 1 an internally generated frame check sequence (fcs) is appended to the end of the transmit packet. if the macc1.crcen bit is set to 1, a frame check se quence (fcs) that has been internally generated is appended to the end of the transmit packet. if the macc1.crcen bit is set to 0, the end of the trans mit packet must be a valid fcs. the ethernet controller can check the fcs. if the value of the fcs is not corre ct, an ethernet transmission status interrupt is generated. if the macc1.paden bit is set to 1, zeros (pad) are appe nded to a transmit packet shorter than 64 bytes (this is known as padding). in this case, the ethernet contro ller appends the correct fcs to the end of the frame, regardless of the setting of the crcen bit. if the macc2.apd or macc2.vpd bit is set to 1 when the macc1.paden bit is set to 1, pad is appended to a vlan frame. if the apd bit is set to 1, only a packet t hat matches the vlan type set by the vltp register is regarded as a vlan frame and is padded. if the vpd bit is set to 1, all packets are regarded as vlan frames and padded. a packet regarded as a vlan frame is padded to in crease the frame length to 68 bytes. the data that is appended as a pad is all 0. (7) aborting transmission the ethernet controller aborts trans mission under the following conditions. it does not abort transmission if the transmit fi fo underruns within the normal operating range. ? if more than the maximum number of collisions (max collision) occur ? if collision occurs outside the collision window (late collision) ? if there is an excessive transmission delay ? if a packet exceeding the frame length set by the lmax regist er is to be transmitted. (if the macc1.hugen bit is set to 1, however, the transmit frame length is not limited.) v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1484 of 1817 sep 19, 2011 (8) full-duplex operation a full-duplex operation is enabled when the macc1.fulld bit is set to 1. the ipg is always the value specified by the ipgt register. the fulld signal is asserted, when the macc1.fulld bit is set to 1 to report to the external circuit that a full-duplex operation has been specified. (9) flow control and ba ck pressure functions the ethernet controller has a fl ow control function (refer to 23.5.4 (1) flow control ) and a back pressure function (refer to 23.5.4 (2) back pressure ) associated with the receive fifo. thes e functions are automatically activated to prevent the fifo from overflowing when the va cant capacity of the receive fifo runs short. (10) timing of updating the transmission status the transmission status is updat ed at the following timing. figure 23-8. transmission status update timing phy interface fifo dma reception started dma transmission started dma transmission completed ? txinf1 updated transmission completed ? txstmoni1 updated ? txstmoni2 updated ? txfinf1 updated ? txfinf2 updated ? txstatus updated ? fstatus updated ? intetmts occurred ? intetmfs occurred transmit packet transmit packet transmit packet dmac for ethernet controller v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1485 of 1817 sep 19, 2011 23.5.3 receive function the ethernet controller generates a receive packet from a re ceive frame to be stored in the fifo, detects the sfd, checks the length field and fcs, and identifies whether the frame is a vlan frame. the status information of each receive packet is set to the reception stat us monitor register (rxstmoni) and the number of times each event has occurred in all re ceive frames is counted by statistics counters. (1) receive clock the ethernet controller receiv es data in synchronization with the reception clock (rxclk) supplied by an external (phy) device. ieee802.3 specifies the frequency of rxclk as 25 mhz100 ppm when the data rate is 100 mbps and 2.5 mhz100 ppm at 10 mbps. (2) reception of mii data the ethernet controller recognizes dat a synchronized with the p1rxdv[3:0] signal as receive frames while the p1rxdv signal is asserted, and recognizes the end of the frame when the p1rxdv signal is deasserted. (3) detecting preamble and sfd the ethernet controller detec ts the preamble and sfd at the beginning of a receive frame and recognizes the data that follows as a receive packet. (4) checking length field the ethernet controller count s the length of a receive packet and checks t he length of the data field, regarding the 2 bytes following the source address as a length field. the re sult of this check can be read as the reception status from the rxstmoni register. if the result of checking is a mismatch , an interrupt signal can be specified to be output. (5) crc the ethernet controller calc ulates the 4-byte frame check sequence (f cs) from a receive packet and compares it with the fcs data appended to the end of the receive packet. the result of the compar ison can be read from the rxstmoni register. if the two fcs data do not matc h, an interrupt signal can be specified to be output. (6) transmitting data to fifo the ethernet controller assume s that a packet of 6 bytes or more is valid and discards a packet of less than 6 bytes. (7) detection of huge packet if the macc1.hugen bit is set to 0, the ethernet controller receives on ly a packet shorter than the maximum frame length set by the lmax register (default value: 1, 536 bytes) and stops reception of a packet exceeding this length midway. for the length of receiv able packets, refer to table 23-14 restrictions on receive fifo . (8) detecting vlan frame the ethernet controller checks all the packets it has received to see whether they are a vlan frame. if the value of the tpid field (the 2 bytes following the sour ce address) of the received packet matches the value set to the vltp register, the packet is recognized as a vlan packet and the rxstmoni.vlan flag is set. in packets recognized as a vlan frame, the 2 bytes immediately after the vlan header (4 bytes following the source address) including the tpid field are regarded as the length field. (9) timing of updating the reception status the reception status is updat ed at the following timing. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1486 of 1817 sep 19, 2011 figure 23-9. reception status update timing phy interface fifo reception started reception completed ? rxstatus updated ? rxfinf2 updated ? intetmrs occurred ? intetmrq occurred dma reception completed ? rxstmoni updated ? rxfinf1 updated ? rxfinf2 updated ? intetmfs occurred receive packet receive packet receive packet dmac for ethernet controller dma reception started v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1487 of 1817 sep 19, 2011 23.5.4 mac control function (1) flow control the ethernet controller realizes flow control by usi ng a pause control frame defined by ?ieee802.3 annex 31?. the purpose of flow control is to decrease the frequency of frame transmission executed by an other terminal (link partner) connected point-to-point during full-duplex operation. the quantity of the data a syst em can receive and process is limited. if frames are received too frequently, processing by the system can no longer keep up. cons equently, the receive fifo may overflow. flow control is used to avoid this situation. when the ethernet controller receives a pause control frame, it loads the value of the parameter field in the control frame to the pause timer in the mac. if the value of the pause timer is not 0, the next transmission is started after the time set to the pause timer has elapsed. if the value of the parameter field in the received pause cont rol frame is 0 (a zero pause control frame), the value of the pause timer is cleared to 0 and transmission is resume d after the packet interval set by the ipgr register has elapsed. to suppress data transmission from the link partner, a reserved multicast address (01-80-c2-00-00-01), pause opcode (00-01), and the pause timer value of the pauset m register (pausetm_max) are transmitted as a pause control frame. starting transmission of a pause frame takes precedence over starting transmission of a basic frame. if a condition for transmitting a pause frame is satisfied while a basic fr ame is being transmitted, however, the pause frame is transmitted after transmission of t he basic frame has been completed. the ethernet controller performs flow c ontrol by setting mffcont.flowcnt to 1. the necessity of transmitting a pause control frame request is identified according to the quantity of data in the receive fifo. if mffcont.ivpause is set to 0 in the full-duplex communication mode, the ethernet controller monitors the quantity of data in the re ceive fifo during reception (refer to figure 23-10 (a) ). the pause control frame is transmitted as soon as t he quantity of data in the receive fifo exceeds the set value of flowthresh.flowthr (refer to figure 23-10 (b) ). if mffcont.ivpause is set to 1, the pause control frame is continually retransmitted at the interval indicated by the set value of pausetm.iptime as long as the quantity of data in the re ceive fifo exceeds the set value of flowthresh.flowthr. the ethernet controller monitors t he quantity of data in the receive fifo even while receive data is being transferred by dma (refer to figure 23-10 (c) ). if mffcont.zeropause is set to 1, a zero pause control frame is transmitted as soon as the quantity of data in the receive fifo falls below the set value of flowthresh.zpthr (refer to figure 23-10 (d) ). if mffcont.zeropause is set to 0, a zero pause control frame is not transmitted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1488 of 1817 sep 19, 2011 figure 23-10. flow control frame reception receive fifo zpthr flowthr dmac mac receive fifo zpthr flowthr dmac mac frame reception receive fifo zpthr flowthr dmac mac receive fifo zpthr flowthr dmac mac (a) when a frame is received, data is stored in the receive fifo. (b) when the amount of data in the receive fifo exceeds the value indicated by flowthr, a pause control frame is transmitted. (c) the data in the receive fifo is read by dma. (d) when the amount of data in the receive fifo falls below the value indicated by zpthr, a zero pause control frame is transm itted. the other terminal that has received the zero pause control frame stops pausing at that point and transmits the next frame. pause control frame request pause control frame reception zero pause control frame request zero pause control frame reception during this operation, the other terminal defers transmission of the next frame until the pause period has elapsed. remark the shaded part of the receive fifo in the above figures indicate s the quantity of the data in the receive fifo. if does not indicate how data is actually stored. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1489 of 1817 sep 19, 2011 (2) back pressure this function is available only during half-duplex operation. if the amount of data in the receive fifo exc eeds the set value of flowthresh.flowthr when mffcont.flowcnt is set to 1 and fulld is 0, the ethernet controller issues a back pressure request (refer to figure 23-11 (b) ). if the next frame is received in this status, a collisio n is intentionally generated by transmitting a dummy packet, prompting the other terminal to retransmit the frame (refer to figure 23-11 (c) ). a collision that occurrs in the back pressure status is not included in the number of collisions. the back pressure status is canceled when the amount of data in the receive fifo falls below the value of flowthr (refer to figure 23-11 (d) ). figure 23-11. back pressure control frame reception receive fifo flowthr dmac mac receive fifo flowthr dmac mac frame reception receive fifo back pressure request back pressure request flowthr frame reception dmac mac receive fifo flowthr dmac mac (a) when a frame is received, data is stored in the receive fifo. (b) a back pressure request is issued when the amount of data in the receive fifo exceeds the value indicated by flowthr. (c) back pressure is performed if the next frame is received in this status. (d) when the amount of data in the receive fifo falls below the value indicated by flowthr, the back pressure request is cance led. the other terminal detects a collision by back pressure and retransmits the frame by a random back-off algorithm. pause control frame reception v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1490 of 1817 sep 19, 2011 (3) operations related to vlan frame the ethernet controller detects a vlan frame by comparing the tpid field in a receive/transmit packet with the value of the vlan type register (vltp). operati ons related to the vlan frame are described next. (a) detection of vlan frame the ethernet controller const antly monitors the value of the 2-byte tpid field that follows the source address in a receive packet. during transmission, the value of the tpid field is checked when macc2.apd or vpd is 1. the ethernet controller recognizes a packet whose tpid field matches the value of the vlan type register (vltp) as a vlan frame. (b) reception of vlan frame if the value of the tpid field of a received packet ma tches the value of the vlan type register (vltp), all judgments concerning the frame size are made based on the vlan frame size (max: 1,522 bytes, min: 64 bytes). (c) transmission of vlan frame if a frame having a tpid field whose value matches the va lue of the vlan type register (vltp) is transmitted from an upper layer when the macc2.apd bit is 1, the fr ame is recognized as a vlan frame and is padded to increase the frame length to 68 bytes. when the macc2.vpd bit is 1, all frames are recogni zed as vlan frames and are padded to increase the frame length to 68 bytes. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1491 of 1817 sep 19, 2011 23.5.5 dedicated dmac the dedicated dma controller (dmac) enables a dma commun ication with the internal system bus of the ethernet controller. the dmac in the ethernet controller is used specifically for transmission and reception. all data to be transmitted and received is transfe rred by the dmac in the ethernet controller. (1) dma transfer mode the following settings can be made by using the dmacm register. transfer mode ? single transfer mode ? 4-beat incremental burst transfer mode ? 8-beat incremental burst transfer mode ? 16-beat incremental burst transfer mode after the transfer mode has been set to the register , it will be applied from the next dma transfer. cautions 1. a burst transfer mode of unde fined length cannot be set to the register. undefined length burst transfer is automati cally used by the ethern et controller to process fractional data. this mode cannot be intentionally u sed to transfer all transfer data. 2. the register that sets the transfer mode is not locked during dma transfer. if the setting of this register is changed during dma transfer , therefore, the curr ent dma cycle becomes illegal. do not change the set value of the re gister during dma transfer (when rxen_sta = 1 or txen_sta = 1). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1492 of 1817 sep 19, 2011 (2) areas accessible by dma transfer the areas subject to dma transfer are shown below. table 23-6. areas subject to transfer by dmac in ethernet controller internal rom internal ram data ram external memory on-chip peripheral i/o inaccessible inaccessible access ible accessible inaccessible (3) dma address boundary with the dmac of in the ethernet controller, the address boundary does not have to be considered when setting the start address of the data buffer and the number of transfer bytes. if there is fractional data during burst transfer, the fracti on is automatically processed before the data is transferred. however, because it is not possible to predict where the data to be received will end, the last transfer may be a dummy transfer when burst transfer is used. remark when the 4-, 8-, or 16-beat transfer mode is used, t he last data that falls s hort of a fixed length is automatically transferred in undefined length mode. byte access for byte alignment is always executed in the single transfer mode. (4) dma arbitration because the ethernet controller supports full-duplex transfer, dma transmission and dma reception may be executed together. if dma requests for transmission and reception are made at the same time, the request for reception takes precedence. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1493 of 1817 sep 19, 2011 23.5.6 serial management interface the ethernet controller has a pair of serial management interfaces which can be used to set a phy device, to read statuses, and for communicating with the phy device when auto-negotiation is used. set the the address of the phy device to be connected by ethernet controller to the ma dr register before using the serial management interface. (1) overview of serial management interface (a) mdc clock the management data clock (mdc) is generated by dividing the ethernet control clock (f ec ). the division ratio is set by the miic.clks bits. table 23-7. miic register: clks bits and f ec frequency miic.clks bits frequency range of f ec input bit 4 bit 3 bit 2 0 0 0 setting prohibited 0 0 1 33 mhz or less 0 1 0 50 mhz or less 0 1 1 setting prohibited 1 0 0 setting prohibited 1 0 1 setting prohibited 1 1 0 setting prohibited 1 1 1 setting prohibited if miic.physel is set to 0 (default value), mdc is output only when a management frame is transmitted or received. mdc is always output when miic.physel = 1. if communication with the phy device has failed wh en miic.physel = 0, se t miic.physel to 1. (b) serial management frame structure the ethernet controller gener ates the serial management frame shown below by writing a value to the mcmd or mwtd register. figure 23-12. serial management frame structure mdc pre (preamble) op (operation) phyad regad data (data) mdio ta (turnaround) st (start bit) v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1494 of 1817 sep 19, 2011 a 32-bit preamble, 2-bit start bit field, and 2-bit opcode, wh ich indicates whether a register in the phy device is read or written, are automatically appended to the serial management frame. phyad and regad indicate the address of the externally connected phy device and the add ress of a register in that phy device respectively. the values set to the madr.fiad and rgad bits are appended to phyad and regad, respectively. the ethernet controller serially out puts data from the preamble to regad, and after a 2-bit turnaround, the data set to the ctld bits of the mwtd register is output for a write access . for a read access, serial data is input by the mdi signal and written to the mrdd.prsd bit. while the mdo signal is being output, the mdoen signal is asserted to 1. figure 23-13. timing of mii manage ment interface signal (write access) mdc pre st op phyad regad ta data mdio remark setting conditions: phyad = 01h, regad = 01h, ctld = 0001h figure 23-14. timing of mii manage ment interface signal (read access) mdc pre st op phyad regad ta data mdio remark setting conditions: phyad = 01h, regad = 01h, ctld = 8001h (c) scan command the ethernet controller has a scan command to succ essively read a specific phy register. when the mcmd.scanc bit is set to 1, read accesses are gener ated one after another. by reading the mrdd.prsd bit, the specific phy regi ster can be polled. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1495 of 1817 sep 19, 2011 (2) procedure for transmitting or re ceiving a serial management frame serial management frames are transmitted or received as follows. first, the mind.scana bit is checked to see whether the scan command is under execution. if not, the mind.busy bit is checked to see whether the serial management frame is being accessed. if the busy bit is 1, the ethernet controller waits until it is cleared to 0. on the other hand, while the scan command is being executed, the mcmd.scanc bit is cleared to 0 and then t he ethernet controller waits until the busy bit is cleared to 0. next, the address of the external phy device to which t he frame is to be transmitted and the address of a register in the phy device are set to the madr.fiad and rgad bits, respectively. when a write access is to be made, writing is started by writing data to the mwtd.ctld bits. the busy bit is set to 1 when data has been written to the mwdt register and cleared to 0 when writing is complete. a read access is started by writing 1 to the mcmd.rstat bi t. when the rstat bit is set to 1, the busy bit is set to 1. the busy bit is cleared to 0 after completion of reading. the host system c an obtain the data of the phy register by confirming that the busy bit is 0 and then reading the mrdd.prsd bit. to execute the scan command, set the mcmd.scanc bit to 1. when this bit has been set to 1, reading is repeatedly executed. the mind.scana bit is set to 1 while the scan command is being executed. the mind.nvalid bit is set to 1 until the first read access is completed after the scan command has been executed. the mind.busy bit is set to 1 when the scan command is executed. if the scan command is disabled (by clearing the mcmd.scanc bit to 0), the mind.busy bit is cleared to 0 after the current read access is completed. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1496 of 1817 sep 19, 2011 figure 23-15. accessing a phy register phy write return set register address to madr.rgad bit. (a) writing to a phy register (b) reading from a phy register yes mind.busy bit = 1? set phy address to madr.fiad bit. set control data to mwtd.ctld[15:0] bits. no phy read yes mind.busy bit = 1? read value of mrdd.prsd[15:0] bits. return no yes mind.busy bit = 1? no set register address to madr.rgad bit. set phy address to madr.fiad bit. set mcmd.rstat (1). v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1497 of 1817 sep 19, 2011 23.5.7 address filtering (1) overview of address filtering the ethernet controller performs address filtering by using the destination address of a received packet and, based on the result of filtering, makes a decision as to whether to receive or discard the received packet. the filtering conditions can be specifi ed by the afr register. conditions c an be individually specified for unicast addresses, multicast addresses, and broadcast addresses, or conditions can be combined. (a) filtering of unicast addresses the address set to the lsa1 and lsa2 registers is co mpared with the destination addr ess of a received packet as a unicast address. a packet whose destination addr ess matches the set address of these registers is received and a packet whose destination address does not match is discarded. each receive packet is checked to see if its destination address matches the set unicast address. figure 23-16. image of filtering by unicast address during reception preamble sfd da type/ len lsa1 [15:0] lsa2 [31:0] data sa fcs compared received discarded (b) filtering of multicast addresses a multicast address is filtered in two ways. if the af r.prm bit is set to 1, all packets having a multicast address as the da are received. if the afr.amc bit is set to 1, only a packet having a multicast address that matches the hash table set to the ht1 and ht2 registers is received, and a packet whos e multicast address does not match is discarded. the hash table is used as follows for detecting of a match. the hash table is referenced by using bi ts [28:32] of the 32 bits of the crc calculation re sult of the received multicast address. the following polynom ial is used for calculating the crc. crc (x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 if 1 is set at the bit position indicated by the value re sulting from decoding the abov e 6 bits on the ht1 and ht2 registers, reception to that multicas t address is enabled. to set the hash table, it is necessary to execute a crc calculation on a multicast address defined in ad vance, and set the corresponding bits to 1. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1498 of 1817 sep 19, 2011 table 23-8. referencing the hash table (ht1, ht2) crc [25:23] crc [28:26] 111b 110b 101b 100b 011b 010b 001b 000b 111b ht1[31] ht1[30] ht1[29] ht1[28] ht1[27] ht1[26] ht1[25] ht1[24] 110b ht1[23] ht1[22] ht1[21] ht1[20] ht1[19] ht1[18] ht1[17] ht1[16] 101b ht1[15] ht1[14] ht1[13] ht1[12] ht1[11] ht1[10] ht1[9] ht1[8] 100b ht1[7] ht1[6] ht1[5] ht1[4] ht1[3] ht1[2] ht1[1] ht1[0] 011b ht2[31] ht2[30] ht2[29] ht2[28] ht2[27] ht2[26] ht2[25] ht2[24] 010b ht2[23] ht2[22] ht2[21] ht2[20] ht2[19] ht2[18] ht2[17] ht2[16] 001b ht2[15] ht2[14] ht2[13] ht2[12] ht2[11] ht2[10] ht2[9] ht2[8] 000b ht2[7] ht2[6] ht2[5] ht2[4] ht2[3] ht2[2] ht2[1] ht2[0] an example of a program that executes ha sh table calculations is shown below. where da = 12, 34, 56, 78, 9a, bc, for example, crc = d4, e8, 80, 56, crc[28:26] = 5, and crc[25:23] = 1. if ht1[9] in table 23-8 is set, a multic ast packet with the target da is rece ived. if the value of both the ht1 and ht2 registers is 00000000h, all packets are discarded. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1499 of 1817 sep 19, 2011 // calculate the set value of the hash table. #include v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1500 of 1817 sep 19, 2011 figure 23-17. image of filtering by referencing the hash table preamble sfd da type/ len crc[31:0] ht1[31:24] ht1[23:16] data sa fcs ht1[15:8] ht1[7:0] ht2[31:24] ht2[23:16] ht2[15:8] ht2[7:0] referencing the hash table received discarded (c) filtering of broadcast addresses when the afr.abc bit is set to 1, a packet having a broadcast address is received. (d) promiscuous mode when the afr.pro bit is set to 1, the promi scuous mode is set and all packets are received. if none of reception conditions (a) to (d) above is satisfied, the received packet is discarded. for the combinations of the above conditions, refer to table 23-9 . table 23-9. address filtering and receive packet setting of afr register receive packet pro prm amc abc lsa mismatch, unicast lsa match, unicast ht mismatch, multicast ht match, multicast broadcast packet 1 ? ? ? received 0 1 ? ? received 0 0 1 1 received 0 0 1 0 received discarded note 0 0 0 1 received 0 0 0 0 discarded received discarded discarded discarded note the broadcast packet can be received if the correspond ing bit of the hash table is set to 1 because the broadcast address is included in a multicast address. remark ? : any v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1501 of 1817 sep 19, 2011 (2) setting address f iltering conditions set address filtering as follows. first, clear the macc1.srxen bit to 0. when the srxen bit is set to 0, the receive data interface is disabled. next, set a terminal address to the lsa1 and lsa2 register s. a combination of the nece ssary filtering conditions to the afr register. to receive conditional multicast pac kets, a hash table must be set by using the ht1 and ht2 registers. after making the above setting, enable packe t reception by setting t he macc1.srxen bit to 1. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1502 of 1817 sep 19, 2011 23.5.8 statistics counters the ethernet controller has 39 statistics counters to check the communication quality of ci rcuits and other information. each time communication of one frame has been completed (or aborted), the communication status is checked and the corresponding statistics counter is updated. the statistics counters ca nnot be stopped. to not us e a statistics counter, set the corresponding bits of the cam1 and cam2 regist ers to 1 to mask the interrupt from that counter. the statistics counters can be read at any time even during communication. if a counter overflows, the corresponding bit of the car1 and ca r2 registers is set to 1, and, if the interrupt is not masked by the cam1 and cam2 registers, an ethernet mac interrupt is generated. the cam1 and cam2 registers can be used to specify whether to mask the overflow interrupt of each counter. to clear a statistics counter, write 0 to it. at this time, t he current communication does not have to be stopped. if there is a conflict between updating a statistics counter and writing it c ontend, updating takes prec edence. the counter is written after it has been updated. note that the statistics count ers cannot be stopped. to not use a statistics counter, mask the counter by setting the corresponding bit of carry mask registers 1 and 2 (cam1 and cam2) to prevent the intetmov interrupt from being generated. the statistics counters can be read and written in 32-bit units. cautions 1. the ethernet controller updates the statis tics counters by using the ethernet controller clock (f ec ). if the ethernet controller clock (f ec ) is considerably slower than the communication clock (txclk/rxclk), the counters may miscount statisti cs information. if the statistics information is miscounted, a status vector overrun occurs, the c2dv bit of carry register 2 (car2) is set to 1, and the intetmov inte rrupt is generated. 2. carry registers 1 and 2 (car1 and car2) are cleared when they are read. remark aside from the statistics counters, a transmission abort counter (txabtcnt) and a reception abort counter (rxabtcnt) are available for counting the number of times transmission/reception has been aborted. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1503 of 1817 sep 19, 2011 23.6 data transmission 23.6.1 buffer structure the buffers in the ethernet controlle r of the v850es/jx3-e are made up of a buffer descriptor and a data buffer. figure 23-18. buffer structure of ethernet controller(1/2) (a) at transmission status size size size size size size size data buffer buffer descriptor address pointer address pointer address pointer address pointer address pointer link pointer end of chain data data data data data status size status size status size status size status size remark when transmitting packets continuously, make t he area following the final buffer descriptor an end-of- chain. dma transmission will stop when the ethernet controller of the v850es/jx3-e detects an end-of- chain. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1504 of 1817 sep 19, 2011 figure 23-18. buffer structure of ethernet controller(2/2) (b) at reception size size size size size status size status size status size status size status size status size data buffer buffer descriptor address pointer address pointer address pointer address pointer address pointer link pointer data data data data data v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1505 of 1817 sep 19, 2011 23.6.2 descriptor mechanism the ethernet controller supports a descriptor mechanism to support a situation where the memory space that stores transmit data and receive data is not contiguous. the ethernet controller uses the following three types of descriptors. ? buffer descriptor ? link pointer ? end of chain each descriptor expands data aligned with 2 words (64 bits) on memory (refer to figure 23-29 example of configuration of descriptor ch ain (during packet reception) ). the ethernet controller c an consecutively process two or more descriptors in one dma transfer (refer to 23.6.2 (6) descriptor chain ). reception dma transfer or transmission dma transfer is start ed by setting the first address of a receive descriptor chain to rxdp or the first address of a transmit descrip tor chain to txdp, and setting the rxs or txs bit of the ethmode register. a descriptor chain must end with the descriptor of an end of chain. (1) format of buffer descriptor a buffer descriptor is configured of 2 words (64 bits). t he lower word consists of control bits. the higher word indicates the start address value of the dat a buffer indicated by the descriptor. figure 23-19. buffer descriptor format t(0) e status size buffer address pointer 31 63 30 29 28 27 26 25 16 15 0 32 ud so v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1506 of 1817 sep 19, 2011 table 23-10. buffer descriptor format (1/2) bit name description 63 to 32 bap this is an address pointer that indicates the start address of the data buffer. byte alignment can be specified for bap. 31 t descriptor type this bit indicates the type of the descriptor. if it is a buffer descriptor, this bit is set to 0. 30 e last buffer flag this is a control bit that indicates the end of packet data. 0: normal buffer data (not last data) 1: last buffer data of the current packet if this bit is set when data is to be transmitted, the txi interrupt is generated when transfer of the data of the corresponding data buffer has been completed, and then processing of the next descriptor is started. clear this bit during reception. when the last data of a frame has been written, this bit is set when the data is written back. after that, the rxi interrupt is generated, and processing of the next descriptor is started. 29 u used bit this bit indicates whether dma transfer has been comp leted or not (including transfer in progress). 0: transfer not completed (including transfer in progress) 1: transfer completed the cpu clears this bit when it creates or obtain s buffer data (a descriptor). when dma transfer to the buffer area indicated by this descriptor has been completed, the u bit is set by the ethernet controller. the ethernet controller issues the teci or reci interrupt and stops dma if it reads a descriptor whose u bit is set. if a bus error occurs, or an overflow error occurs during reception, the u bit of the descriptor at the start of the pa cket that caused the error is set. 28 d this bit indicates an access error in the data buffer. 0: no error 1: access error in the data buffer the cpu clears this bit when it creates or obtain s buffer data (a descriptor). if an access error occurs, the ethernet controller sets control bit d of the first descriptor that indicates the current packet, and control bit d of the descriptor t hat was responsible for the access error. 27 s note this bit indicates that reception status information has been written to the status field (only control bit s in the first descriptor of a received packet is valid). 0: status information is not included. 1: status information of the received packet is included. the cpu clears this bit when it creates or obtains buffer data (a descriptor). when a received packet is transferred by dma, the ethernet controller writ es a valid value to the status field of the first descriptor of the current packet and sets contro l bit s each time one packet has been transferred. note this bit is not used during transmission. set this bit to 0. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1507 of 1817 sep 19, 2011 table 23-10. buffer descriptor format (2/2) bit name description 26 o note this bit indicates occurrence of an overflow error during reception. 0: no overflow 1: overflow the cpu clears this bit when it cr eates or obtains buffer data (a descriptor). if an overflow error occurs during reception, the ethernet controller writes back 1 to the cont rol bit 0 of the first descriptor of the packet, and sets control bit e of the descriptor in which the overflow error occurred. no interrupt is generated. 25 to 16 status note this field indicates status inform ation during reception. if control bit s is 1, the value of the status field is valid. the cpu clears this bit when it cr eates or obtains buffer data (a descriptor). during dma transfer of a receive packet, the ethernet controlle r writes a valid value to the status field of the first descriptor of the current packet and sets cont rol bit s to 1 each time transfer of one packet has been completed,. the bits in the status field are shown below. the value of the reception status monitor (rxstmon1) is written to these bits. bit name 16 ceps 17 rcv 18 rcrcf 19 rlor 20 dbnb 21 rxok 23 to 25 ftyp[0:2] 000:rbro 001:rmul 010:usop 011:vlan 100:rpcf 101:rcfr 110:?nomal? 111:?reserved? 15 to 0 size this field indicates the size (in bytes) of the buffer data indi cated by this descriptor. during dma transfer of a receive packet, the ethernet controller writes the length of one transferred packet to the size field of the last descriptor of the current packet each time transfer of one packet has been completed. note these bits are not used during transmission. set these bit to 0. remark the size field is 16 bits. setting 0 to this field is prohibited. if 0 is set, an error interrupt is generated. if ffffh is set to this field, transfer of 64k ? 1 bytes is executed. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1508 of 1817 sep 19, 2011 (2) format of link pointer a link pointer consists of 2 words. the lower word consis ts of control bits. the higher word indicates the address value of the next descriptor. figure 23-20. link pointer format t(1) e(0) reserved (0) link pointer 31 63 30 29 0 32 table 23-11. link pointer data bit name description 63 to 32 link pointer this field indicates the addr ess of the next descriptor. the lower 2 bits are ignored (word aligned). 31 t this bit is set to 1. 30 e this bit is set to 0. 29 to 0 reserved this is a reserved field and must be set to 0. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1509 of 1817 sep 19, 2011 (3) format of end of chain an end of chain consists of 2 words. the lower word co nsists of control bits. the higher word indicates 0. when it detects the end of chai n, the ethernet controller, completes dma transfer and generates the reci or teci interrupt. figure 23-21. end of chain format t(1) e(1) reserved (0) 0 31 63 30 29 0 32 table 23-12. end of chain data bit name description 63 to 32 bap set null (all zero) to this field of an end of chain. 31 t this bit is set to 1. 30 e this bit is set to 1. 29 to 0 reserved this is a reserved field and must be set to 0. (4) writing back the status when dma reception is executed, the re ception status is written back to t he first descriptor of the packet, and the length of the packet transferred by dma is written back to t he last descriptor. the status is written back as shown below. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1510 of 1817 sep 19, 2011 (5) last descriptor report the current descriptor can be reported. two registers, lstrxdp and lsttxdp, hold the address information of the descriptors processed by the et hernet controller. the address inform ation of the descriptor that was processed immediately before can be asce rtained by reading these two registers. the timing of saving the address information of a descriptor to lstrxdp and lsttxdp is as follows. after the data of a descriptor has been transferred and th e descriptor has been written back, the address of the descriptor is copied to lstrxdp or lsttxdp. when the link pointer is read, the addr ess information of the next descrip tor can be read from the bap bit. therefore, the address of the link pointer is copied to lstrxdp or lsttxdp. figure 23-22. timing of copying the last descriptor reset value descriptor base address base address + 8 base address + 8 base address + 16 base address base address + 16 base address + 8 dma transfer dr dw descriptor 1 example of location address of descriptor descriptor chain current descriptor lstrxdp/lsttxdp register operation of ahb bus descriptor base address buffer address pointer dma transfer dr dw descriptor 2 buffer address pointer dma transfer dr dw descriptor 2 buffer address pointer dr t = 1, e = 0 link address pointer (new address) dr t = 1, e = 1 end of chain new address new address base address + 16 new address + 8 0000 0000h new address + 8 new address new address + 8 the descriptor base address is set to txdp/txdp register. remark dr: descriptor read dw: descriptor write-back v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1511 of 1817 sep 19, 2011 if a descriptor chain is stored in the ring buffer, the de scriptor can be updated by reading lstrxdp or lsttxdp, using the txi flag of the intetmtx interrupt (rxi flag of the intetmrx interrupt) as a trigger. figure 23-23. updating descriptor ch ain by using lstrxdp or lsttxdp txi interrupt return area indicated by buffer address pointer of descriptor indicated by lsttxdp is released. yes is descriptor indicated by lsttxdp link pointer? no buffer address pointer of new transmit packet is set to descriptor indicated by lsttxdp. new transmit packet is organized. rxi interrupt return yes is descriptor indicated by lsttxdp link pointer? no value of buffer address pointer of descriptor indicated by lsttxdp is transferred to higher socket. buffer address pointer of new receive packet is created for descriptor indicated by lsttxdp. new receive buffer is allocated. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1512 of 1817 sep 19, 2011 (6) descriptor chain a descriptor is used to indicate the data buffer (of an undefined length) in a chain structure. an image is as shown below. figure 23-24. overview of descriptor chain buffer descriptor [2] buffer descriptor [1] data buffer [1] data buffer [a] data buffer [2] data buffer [b-1] data buffer [b] : empty : packet buffer descriptor [a] link pointer (e bit = 0 indicates link to next descriptor) memory map memory map rxdp/txdp end of chain (e bit = 1 indicates end of chain) buffer descriptor [b] buffer descriptor [b-1] at the memory addresses following a buffer descriptor (a ddress + 8), either buffer descriptors are successively allocated or a link pointer is allocated. the link pointer indicates the location address of the next buffer descriptor. this combination makes up a descriptor chain. the descriptor chain ends when an end of chain is set. if an end of chain is detected before all receive packets are stored, the tbei (rbei) bit th at reports a buffer access error by using the intetmtx (intetmrx) interrupt is set to 1. two or more packets may be stored in one descriptor chain. a ring shaped descriptor chain may be configured by specifying the memory address of the first buffer descriptor by using the last link pointer. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1513 of 1817 sep 19, 2011 figure 23-25. overview of ring buff er formed by descriptor chain buffer descriptor [2] buffer descriptor [1] data buffer [a] data buffer [1] data buffer [a-1] data buffer [2] : empty : packet buffer descriptor [a] link pointer (e bit = 0 indicates link to next descriptor) buffer descriptor [a-1] memory map memory map rxdp/txdp ? ? ? when the beginning of a descriptor chain is specified by a link pointer, a ring buffer is configured. in the case of a ring buffer, the ethernet controller generates the reci or teci interrupt when a descriptor whose u bit is set is read in the same manner as it detec ts an end of chain, and stops dma. caution handling of u bit the u bit set to a transmit desc riptor indicates that transmission of the descriptor is completed, and the cpu can set a new descriptor by clearing the u bit. however, a receive descriptor may be updated later by status write back or error occurrence even if the u bit is set. therefore, a new d escriptor cannot be set unl ess completion of packet reception is confirmed. if the e bit is set, ho wever, it indicates that pa cket reception has been completed and therefore, that the descrip tor chain can be set as a new descriptor. (7) byte alignment and word boundary a descriptor must be word-aligned but the data buffer can be set at a byte-aligned address. the ethernet controller autom atically identifies an address, executes si ngle transfer up to a word boundary or transfer of a word of undefined length up to t he burst boundary, and then executes burst transfer. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1514 of 1817 sep 19, 2011 23.6.3 frame transmission the cpu prepares the transmission descriptor and transmission data in the data-only ram. after the transmission descriptor register (txdp) and the txs bit of the ethm ode register are set, the dedicated dmac fetches the transmission buffer descriptor from the address set in the de scriptor register, reads the transmission data from the data buffer, and transfers the data to the transmission fifo. the dat a transferred to the fifo is synchronized with txclk, and the preamble, sfd, and frame data are output to the phy in that order. if the crcen bit of the macc1 register is set, fcs is append ed to the end of the data. if the paden bit of the macc1 register is set, 0pad is automatically ap pended when a short frame is transmitted. if the current descriptor does not include an end-of-frame, t he next descriptor is read an d data is read from the data buffer indicated by this descriptor. at the end of transmission, the transmission status is written in the final descrip tor. the next transmission buffer descriptor is then fetched, and if the next data can be transmitted, transmission is carried out as described above. after all the buffer descriptors have been transmitted by dma, the txi interrupt is generated to indicate the end of dma transmission. if the following transmission buffer descriptor is an end-of-chain descriptor, the teci interrupt indicating an end-of-chain is generated and dma transmission stops. dma transmission can be restarted by setting the txdp register and the buffer descriptors again. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1515 of 1817 sep 19, 2011 here is an example of transmission procedure. figure 23-26. example of ethe rnet transmission procedure <1> initialization <3> setting transmit buffer descriptor register and enabling transmission <4> reading transmit data <6> interrupt request generated (dma transmission completed: per packet) wait for the cpu re-set txdp <5> transmitting preamble, sfd, data, and fcs yes no <8>the end-of-chain descriptor? initialization <2> preparing transmit data and transmit buffer descriptor <7> preparing data to be transmitted setting transmit descriptor address and enabling transmission interrupt ethernet controller cpu memory v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1516 of 1817 sep 19, 2011 <1> initializing the ethernet controller initialize the ethernet controller using t he procedure shown in 23.3 initialization. <2> creating buffer descriptors for the transmission and reception data create buffer descriptors for the transmission and reception data in the data-only ram. when creating the descriptors, set the bits of the transmission buffer descriptor as follows: set the e bit (to 1 to indicate the end of the packet data), set the t bit (to 0), set the u bit (to 0), and set the size bit. <3> setting the transmission buffer descrip tor register and enabling transmission set the transmission buffer descriptor address to the txdp r egister. then set the txs (tr ansmission enable) bit of the ethmode register. <4> reading the transmission data read the transmission data from the memory using dma. if the e bit of the transmission buffer descrip tor is 0, the next descriptor can be read. <5> transmitting packets transmit the packet including the preamble, sfd, data, and fcs. <6> reporting the end of dma transmission report the end of transmission to the cpu by generating the txi interrupt request. <7> preparing the next data the cpu checks the transmission stat us and prepares the next data. <8> reporting the end-of-chain descriptor report the arrival of the end-of-chain descriptor to the cpu by generating the teci interrupt request. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1517 of 1817 sep 19, 2011 how transmission works is described below usi ng an example of an actual descriptor chain. after the txs bit of the core function setti ng register (ethmode) is set to 1 by so ftware, the first descriptor is read from the address indicated by the transmission descriptor pointe r (txdp) (0028 0000h), and the transmission descriptor is analyzed. the buffer address pointer (0028 1000h) is set as t he dma transfer start address and the data in the buffer is transferred to the fifo. if the e bit of the transmission descriptor is 0, it indicates that the current data is not t he final data, so the next buffer descriptor (0028 0008h) is read. the buffer address pointer (0028 1800h) is set and the data in the buffer is transferred to the fifo. once the data in a buffer indicated by a buffer descriptor whose e bit is 1 is transmitted, the u bit of that descriptor is set and transmission ends. at this point t he txi interrupt is generated. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1518 of 1817 sep 19, 2011 figure 23-27. example of ethe rnet transmission procedure status (a) word (32 bits) word (32 bits) buffer a buffer b size (a) 0 0000 0 status (b) size (b) 0 0000 0 0 15 16 25 26 27 28 29 30 31 0028 0000h 0028 0004h 0028 0008h 0028 000c h 0028 0014h 0028 0010h 0028 0018h address 0028 0000h 0028 0004h 0028 0008h 0028 000c h 0028 0014h 0028 0010h 0028 0018h address 0028 1000h 0028 1800h address 11 bap (buffer address pointer) 0028 1000h bap (buffer address pointer) 0028 1800h end of chain reserved (0) reserved (0) status (a) word (32 bits) size (a) 0 1 0 1 0 0 status (b) size (b) 0 1 0 00 1 0 15 16 25 26 27 28 29 30 31 11 bap (buffer address pointer) 0028 1000h bap (buffer address pointer) 0028 1800h end of chain reserved (0) reserved (0) size (a) size (b) v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1519 of 1817 sep 19, 2011 23.6.4 frame reception once the srxen (reception enable) bit of the mac config uration register (macc1), the rxs (reception dma enable) bit of the ethmode register, and the rxdp bit of the reception descriptor pointer register are set and if there is data to be received, the mac begins reception frame processing. when data is received, the validity of its preamble and start-of-fra me delimiter (sfd) is checked. if the preamble and sfd are valid, t he received frame is processed. if a valid preamble and sfd cannot be found, the frame is ignored. if a frame collision occurs, or a frame is discarded due to addre ss filtering, the data is not wr itten to the reception buffer. a reception frame that is received normally and is not discar ded due to address filtering is transferred to the data buffer indicated by the reception buffer descriptor. during reception, the ethernet cont roller checks the whether the fram e is of an appropriate length. at the end of the frame, the fcs is che cked and written to the buffer descriptor. note that frames that are 64 bytes or shorter (short packets) are transferred by dma. when frame reception is complete, the e and u bits of the final descriptor are set to 1 and the number of data bytes transferred is written back to the descriptor?s size field. once all the packet data has been transferred, the u and s bits of the first descriptor are set to 1, and the reception status information is written back to the status fi eld. at this point the rxi interrupt is generated. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1520 of 1817 sep 19, 2011 here is an example of reception procedure. figure 23-28. example of ethe rnet transmission procedure <1> initialization yes no <6> data buffer full? <3> setting receive buffer descriptor register and enabling reception <5 > transferring receive data <6> using next descriptor <7> writing reception status and reading next descriptor <8> interrupt request generated (reception completed) <4> reading receive buffer descriptor initialization <2> preparing receive buffer descriptor <9> reading status check data and releasing data buffer setting receive descriptor address and enabling reception ethernet controller cpu memory memory memory interrupt v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1521 of 1817 sep 19, 2011 <1> initializing the ethernet controller initialize the ethernet controller using t he procedure shown in 23.3 initialization. <2> creating the recep tion buffer descriptor create the reception buffer descriptor in the memory. when creat ing the descriptor, set the bi ts of the reception buffer descriptor as follows: set the t bit (to 0), set the u bit (t o 0), and set the size bit (indicating the data buffer size). <3> setting the reception buffer descr iptor register and enabling reception set the reception buffer descriptor address to the rxdp register. then set the rxs bi t of the ethmode register. <4> reading the recep tion buffer descriptor read the reception buffer descriptor using dma. <5> transferring received packets transfer the data to the data-only ram using dma. <6> judging that the reception buffer is full when the current data buffer is full, read the next descriptor. <7> receiving packets repeat the process of reading the buffer descriptor and tran sferring the data. when an end-of-frame is received, 1 is written to the status bit (the e bit) of the final reception buffer descriptor and the number of bytes transferred is written to the size field. <8> reporting the end of reception report the end of reception to the cpu by generating the rxi interrupt request (assuming that the interrupt is not masked). <9> preparing the next data the cpu checks the reception stat us, releases the data buffer, and prepares the next data buffer. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1522 of 1817 sep 19, 2011 how reception works is described below using an example of an actual descriptor chain. after the rxs bit of the core function setting register (ethmode ) is set to 1 by software, the first descriptor is read from the address indicated by the reception descriptor pointer (rxd p) (0028 0000h), and the reception descriptor is analyzed. the first buffer address pointer (0028 1000h) is set as th e dma transfer start address and the reception data in the fifo is transferred to buffer a. when buffer a becomes full upon subsequent receptions, the next descriptor (0028 0008h) is read, the buffer address pointer (0028 1800h) is set as the dma start address, and the reception data in the fifo is transferred to buffer c. in the final reception, the e and u bits of the descriptor are set to 1, and the num ber of data bytes transferred is written back to the descriptor?s size field. once all the packet data has been transferred, the u and s bits of the first descriptor are set to 1, and the reception status information is written back to the status (a) field. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1523 of 1817 sep 19, 2011 figure 23-29. example of configuration of descriptor chain (during packet reception) status (a) word (32 bits) word (32 bits) buffer a buffer c size (a) 0 0000 0 status (c) size (c) 0 0000 0 0 15 16 25 26 27 28 29 30 31 0028 0000h 0028 0004h 0028 0008h 0028 000c h 0028 0014h 0028 0010h 0028 0018h address 0028 0000h 0028 0004h 0028 0008h 0028 000c h 0028 0014h 0028 0010h 0028 0018h address 0028 1000h 0028 1800h address 11 bap (buffer address pointer) 0028 1000h bap (buffer address pointer) 0028 1800h end of chain reserved (0) reserved (0) status (a) word (32 bits) size (a) 0 1 0 1 0 0 status (c) size (c) 0 1 0 00 1 0 15 16 25 26 27 28 29 30 31 11 bap (buffer address pointer) 0028 1000h bap (buffer address pointer) 0028 1800h end of chain reserved (0) reserved (0) size (a) size (c) v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1524 of 1817 sep 19, 2011 23.6.5 error occurrence (1) error write back if a bus error occurs when the data buffer is accessed during transmission or reception, an error interrupt is generated and dma is stopped. in addition, the u and d bits of the first descriptor of the packet are set to 1 (the u bit may have already been set to 1 in some cases). t he u, d, and e bits of the descriptor in which the error occurred are set also to 1. if an overflow occurs during reception, the u and o bits of the first descriptor of a packet are set (the u bit may have already been set in some cases). the u and e bits of the descriptor in which the overflow occurred are also set. (2) error interrupt the error interrupt is generated by an access error in the data buffer and also by the occurrence of as descriptor access error. the occurrence of the error interrupt can be confirmed by the setting of intms.rbei and intms.tbei. if a data buffer or descriptor access error occurs, the descr iptor chain containing the descriptor in which the error occurred must be reorganized. transmission if a descriptor or data buffer access error occurs, tbei is set to 1 and dma is stopped. transmission is not restarted until txs is next set to 1. reception if a descriptor or data buffer access error occurs, rbei is set and dma is stopped. reception is not performed until rxs is next set. at the same time, the packet being transferred from the fifo is discarded. if packet transfer has not been started, the packet is not discarded. even if a bus error occurs as a result of a reception overflow, the processing is the same as that when a descriptor access error occurs. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1525 of 1817 sep 19, 2011 23.7 receive checksum the ethernet controller has a receive chec ksum unit that can a receive checksum. receive checksum calculation is enabled and disabled by setting the rxchksmen bit of register. a checksum is appended to the end of receive data. because receive data has size of packet length + 2 bytes, a sufficient area must be allocated. while checksum calculation is enabled, all parts (payload) of a receive frame, except the mac header (first 14 bytes) and crc (last 4 bytes), are subject to checksum calculation. if the number of bytes subject to calculation is odd, 00h is added to the last byte. the minimum receive packet length subject to checksum calculation is 19 bytes (payload = 1 byte). if the receive packet length is 18 bytes (payload = 0 byte) or less, 0 is output as the checksum. however, the length information increases by 2 bytes. before changing the value of the rxchksmen bit, conf irm that transfer of the receive frame has stopped. 23.7.1 processing by software the first 14 bytes of a packet are treated as a mac header and are always excluded from checksum calculation. therefore, calculation starts from the 15th byte. if the mac header exceeds 14 bytes, such as in a vlan and huge frame, correction by software is necessary. figure 23-30. checksum calculation mac header note , 14 bytes crc 4 bytes payload tcp header ip header checksum 2 bytes + hardware (checksum calculated by ethernet controller) areas subject to calculation all areas except mac header and crc checksum checksum checksum dummy header checksum a dummy header checksum must be appended to the checksum calculated by ethernet controller by software. checksum of only ip header must be calculated by software. note the first 14 bytes are always exclude d from the checksum calculation. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1526 of 1817 sep 19, 2011 the minimum packet length is 64 bytes. when padding a short packet, many systems use 00h. some systems, however, use a specific code for padding. in this case, the checksum calculation is executed including the padding data. consequently, the calculation result and the checksum containe d in the header do not match. in this case, the checksum of the padding data must be corrected by software. caution according to rfc1071 if the checksum result is compared using the same endian format, the result can be compared regardless of whet her the data is in big endian or little endian format when the checksum is calculated. v850es/jh3-e, v850es/jj3-e chapter 23 ethernet controller r01uh0290ej0300 rev.3.00 page 1527 of 1817 sep 19, 2011 23.8 notes 23.8.1 notes on fifo note the following restrictions on the internal fifo buffers of the ethernet controller. table 23-13. restrictions on transmit fifo maximum fifo capacity dma transfer condition retry/abort condition of transmission to phy features note 2,044 bytes or less data in fifo is less than 1,536 bytes note . data is automatically retransmitted/ aborted in the case of collision detection. at least one packet is in the fifo data can be retransmitted without underrun the transmit packet length must be 1,536 bytes or less. note two or more packets may be stored in the fifo as l ong as its capacity is not exceeded. if the data in the transmit fifo reaches 1,536 bytes, however, dma tr ansmission stops, preventing the transmit fifo from overflowing. however, the ethernet controller starts transmission after data of one packet has been stored in fifo. consequently, if the length of one packet exceeds 1,536 bytes, the transmit fifo is locked. be sure to observe the rated size of one packet to be used (1,518 bytes or less for non-vlan frames and 1,522 bytes or less for vlan frames). table 23-14. restrictions on receive fifo maximum fifo capacity dma transfer condition transmission condition of pause control frame note features notes 2,036 bytes or less at least one packet is in the fifo ? transmission of pause control frame: data in the fifo is greater than the size set by flowthr ? transmission of zero pause control frame: data in fifo is less than the size set by zpthr all error packets can be discarded. the receive packet length is limited to 2,036 bytes or less. note control by a pause control frame does not completely prev ent overflow of the receive fifo. if the receive fifo overflows, packets that could not be received are discarded. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1528 of 1817 sep 19, 2011 chapter 24 dma function (dma controller) the v850es/jh3-e and v850es/jj3-e include a direct memory access (dma) controller (dmac) that executes and controls dma transfer. the dmac controls data transfer between memory and i/o, between memo ries, or between i/os based on dma requests issued by the on-chip peripheral i/o (serial interface, timer/counter, and a/d converter), inte rrupts from external input pins, or software triggers (memory refe rs to internal ram or external memory). 24.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? transfer type: two-cycle transfer ? transfer mode: single transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (serial interface, timer/counter, a/d converter) or interrupts from external input pin ? requests by software trigger ? transfer targets ? internal ram ? peripheral i/o ? peripheral i/o ? peripheral i/o ? internal ram ? external memory ? external memory ? peripheral i/o ? external memory ? external memory v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1529 of 1817 sep 19, 2011 24.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850es/jh3-e, v850es/jj3-e bus interface external bus external ram external rom external i/o dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) external dma request enable register n (exdrqn) udmarqm udmaakm remark n = 0 to 3 m = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1530 of 1817 sep 19, 2011 24.3 registers (1) dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma source addresse s (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram ir 0 1 specification of dma transfer source set the address (a25 to a16) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa25 to sa16 set the address (a15 to a0) of the dma transfer source (default value is undefined). during dma transfer, the next dma transfer source address is held. when dma transfer is completed, the dma address set first is held. sa15 to sa0 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah, dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h dsanl (n = 0 to 3) sa15 sa14 sa13 sa12 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa7 sa8 sa9 sa10 sa11 dsanh (n = 0 to 3) ir 000 sa22 sa21 sa20 sa19 sa18 sa17 sa16 sa23 sa24 sa25 0 0 cautions 1. be sure to clear bits 14 to 10 of the dsanh register to 0. 2. set the dsanh and dsanl registers at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the dsan register is read, two 16-bit re gisters, dsanh and dsanl, are read. if reading and updating conflict, the value being updated may be read (see 24.13 cautions). 4. following reset, set the dsanh, dsa nl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1531 of 1817 sep 19, 2011 (2) dma destination address regi sters 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dma destination address (26 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, ddanh and ddanl. these registers can be read or written in 16-bit units. external memory or on-chip peripheral i/o internal ram ir 0 1 specification of dma transfer destination set an address (a25 to a16) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da25 to da16 set an address (a15 to a0) of dma transfer destination (default value is undefined). during dma transfer, the next dma transfer destination address is held. when dma transfer is completed, the dma transfer source address set first is held. da15 to da0 after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, da2h fffff096h, dda3h fffff09eh, dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch ddanl (n = 0 to 3) da15 da14 da13 da12 da6 da5 da4 da3 da2 da1 da0 da7 da8 da9 da10 da11 ddanh (n = 0 to 3) ir 000 da22 da21 da20 da19 da18 da17 da16 da23 da24 da25 0 0 cautions 1. be sure to clear bits 14 to 10 of the ddanh register to 0. 2. set the ddanh and ddanl registers at the following timing when dm a transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. when the value of the ddan register is read, two 16-bit registers, ddanh and ddanl, are read. if reading and updating conflict, a va lue being updated may be read (see 24.13 cautions). 4. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1532 of 1817 sep 19, 2011 (3) dma transfer count regi sters 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bit registers that set the transfer count for dma channel n (n = 0 to 3). these registers hold the remaining transfer count during dma transfer. these registers are decremented by 1 per transfer regardless of the transfer data unit (8/16 bits), and the transfer is terminated if a borrow occurs. these registers can be read or written in 16-bit units. transfer count of 1st transfer or remaining transfer count transfer count of 2nd transfer or remaining transfer count : transfer count of 65,536 (2 16 )th transfer or remaining transfer count bc15 to bc0 0000h 0001h : ffffh transfer count setting or remaining transfer count during dma transfer after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h dbcn (n = 0 to 3) 15 bc15 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 bc0 the number of transfer data set first is held when dma transfer is complete. cautions 1. set the dbcn register at the followi ng timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. following reset, set the dsanh, dsanl, ddanh, ddanl, and dbcn registers before starting dma transfer. if these registers are not set, the operation when dma transfer is started is not guaranteed. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1533 of 1817 sep 19, 2011 (4) dma addressing control registers 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-b it registers that control the dma tr ansfer mode for dma channel n (n = 0 to 3). these registers can be read or written in 16-bit units. reset sets these registers to 0000h. dadcn (n = 0 to 3) 8 bits 16 bits ds0 0 1 setting of transfer data size increment decrement fixed setting prohibited sad1 0 0 1 1 sad0 0 1 0 1 setting of count direction of the transfer source address increment decrement fixed setting prohibited dad1 0 0 1 1 dad0 0 1 0 1 setting of count direction of the destination address after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h sad1 sad0 dad1 dad0 0 0 0 0 0ds000 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 cautions 1. be sure to clear bits 15, 13 to 8, and 3 to 0 of the dadcn register to 0. 2. set the dadcn register at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 3. the ds0 bit specifies the size of the transfer data, and does not control bus sizing. if 8-bit data (ds0 bit = 0) is set, therefore, the lower data bus is not always used. 4. if the transfer data size is set to 16 bits (ds0 bit = 1), transfer cannot be started from an odd address. transfer is always started from an address with the first bit of the lower address aligned to 0. 5. if dma transfer is executed on an on-chip pe ripheral i/o register (as the transfer source or destination), be sure to specify the same transfer size as the re gister size. for example, to execute dma transfer on an 8-bit register , be sure to specify 8-bit transfer. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1534 of 1817 sep 19, 2011 (5) dma channel control registers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bi t registers that control the dma transfer operating mode for dma channel n. these registers can be read or written in 8-bit or 1-bit un its. (however, bit 7 is read-only and bits 1 and 2 are write- only. if bit 1 or 2 is read, the read value is always 0.) reset sets these registers to 00h. dchcn (n = 0 to 3) dma transfer had not completed. dma transfer had completed. it is set to 1 on the last dma transfer and cleared to 0 when it is read. tcn note 1 0 1 status flag indicates whether dma transfer through dma channel n has completed or not dma transfer disabled dma transfer enabled dma transfer is enabled when the enn bit is set to 1. when dma transfer is completed (when a terminal count is generated), this bit is automatically cleared to 0. to abort dma transfer, clear the enn bit to 0 by software. to resume, set the enn bit to 1 again. when aborting or resuming dma transfer, however, be sure to observe the procedure described in 24.13 cautions . enn 0 1 setting of whether dma transfer through dma channel n is to be enabled or disabled this is a software startup trigger of dma transfer. if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. stgn note 2 after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h tcn note 1 0 0 0 0 initn note 2 stgn note 2 enn <0> <1> <2> 3 4 5 6 <7> initn note 2 if the initn bit is set to 1 with dma transfer disabled (enn bit = 0), the dma transfer status can be initialized. when re-setting the dma transfer status (re-setting the ddanh, ddanl, dsanh, dsanl, dbcn, and dadcn registers) before dma transfer is completed (before the tcn bit is set to 1), be sure to initialize the dma channel. when initializing the dma controller, however, be sure to observe the procedure described in 24.13 cautions . notes 1. the tcn bit is read-only. 2. the initn and stgn bits are write-only. cautions 1. be sure to clear bits 6 to 3 of the dchcn register to 0. 2. when dma transfer is completed (when a terminal count is generated), the enn bit is cleared to 0 and then the tcn bit is set to 1. if the dchcn regist er is read while its bits are being updated, a value indicating ?transfer not co mpleted and transfer is disabled? (tcn bit = 0 and enn bit = 0) may be read. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1535 of 1817 sep 19, 2011 (6) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that c ontrol the dma transfer start trigger via interrupt request signals from on-chip peripheral i/o. the interrupt request signals set by these re gisters serve as dma transfer start factors. these registers can be read or written in 8-bit units. however, dfn bit can be read or written in 1-bit units. reset sets these registers to 00h. dtfrn (n = 0 to 3) no dma transfer request dma transfer request dfn note 0 1 dma transfer request status flag after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 0 1 2 3 4 5 6 <7> note do not set the dfn bit to 1 by software. write 0 to this bit to clear a dma transfer request if an interrupt that is specified as the dma transfer start fa ctor occurs while dma transfer is disabled. cautions 1. set the ifcn5 to if cn0 bits at the following timing when dma transfer is disabled (dchcn.enn bit = 0). ? period from after reset to start of first dma transfer ? period from after channel initialization by dchcn.initn bit to start of dma transfer ? period from after completion of dma transfer (dchcn.tcn bit = 1) to start of the next dma transfer 2. an interrupt request that is generated in the standby mode (idel1, idle2, stop, or sub- idle mode) does not start the dma transfer cycle (nor is the dfn bit set to 1). 3. if a dma start factor is selected by the ifcn 5 to ifcn0 bits, the dfn bi t is set to 1 when an interrupt occurs from the selected on-chip pe ripheral i/o, regardless of whether the dma transfer is enabled or disable d. if dma is enabled in this status, dma transfer is immediately started. 4. be sure to follow the steps below when changing the dtfrn register settings. ? when the values to be set to bits ifcn5 to ifcn0 are not set to bits ifcm5 to ifcm0 of another channel (n = 0 to 3, m = 0 to 3, n m) <1> stop the dman operation of the cha nnel to be rewritten (dchcn.enn bit = 0). <2> change the dtfrn register settings. (be sure to set dfn bit = 0 and change the settings in the 8-bit manipulation.) <3> confirm that dfn bit = 0. (stop the interrupt generation source operation beforehand.) <4> enable the dman operation (enn bit = 1). ? when the values to be set to bits ifcn5 to ifcn0 are set to bits ifcm5 to ifcm0 of another channel (n = 0 to 3, m = 0 to 3, n m) <1> stop the dman operation of the cha nnel to be rewritten (dchcn.enn bit = 0). <2> stop the dmam operation of the channel where the same values are set to bits ifcm5 to ifcm0 as the values to be used to rewrite bits ifcn5 to ifcn0 (dchcm.emm bit = 0). <3> change the dtfrn register settings. (be sure to set dfn bit = 0 and change the settings in the 8-bit manipulation.) <4> confirm that bits dfn and dfm = 0. (s top the interrupt generation source operation beforehand.) <5> enable the dman operation (bits enn and emm = 1). remark for the ifcn5 to ifcn0 bits, see table 24-1 dma start factors . v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1536 of 1817 sep 19, 2011 table 24-1. dma start factors (1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request by interrupt disabled 0 0 0 0 0 1 intp01 0 0 0 0 1 0 intp02 0 0 0 0 1 1 intp05 0 0 0 1 0 0 intp06 0 0 0 1 0 1 intp13 0 0 0 1 1 0 intp17 0 0 0 1 1 1 inttab0ov 0 0 1 0 0 0 inttab0cc0 0 0 1 0 0 1 inttab0cc1 0 0 1 0 1 0 inttab0cc2 0 0 1 0 1 1 inttab0cc3 0 0 1 1 0 0 inttab1ov_base note 0 0 1 1 0 1 inttab1ov 0 0 1 1 1 0 inttab1cc0_base note 0 0 1 1 1 1 inttab1cc0 0 1 0 0 0 0 inttab1cc1 0 1 0 0 0 1 inttab1cc2 0 1 0 0 1 0 inttab1cc3 0 1 0 0 1 1 inttt0ov 0 1 0 1 0 0 inttt0cc0 0 1 0 1 0 1 inttt0cc1 0 1 0 1 1 0 inttaa0ov 0 1 0 1 1 1 inttaa0cc0 0 1 1 0 0 0 inttaa0cc1 0 1 1 0 0 1 inttaa1ov 0 1 1 0 1 0 inttaa1cc0 0 1 1 0 1 1 inttaa1cc1 0 1 1 1 0 0 inttaa2cc0 0 1 1 1 0 1 inttaa2cc1 0 1 1 1 1 0 inttaa3cc0 0 1 1 1 1 1 inttaa3cc1 1 0 0 0 0 0 inttaa4cc0 1 0 0 0 0 1 inttaa4cc1 1 0 0 0 1 0 inttaa5cc0 1 0 0 0 1 1 inttaa5cc1 1 0 0 1 0 0 inttm0eq0 1 0 0 1 0 1 inttm1eq0 1 0 0 1 1 0 inttm2eq0 1 0 0 1 1 1 inttm3eq0 1 0 1 0 0 0 intce0t/intuc4r 1 0 1 0 0 1 intce0tiof/intuc4t note inttab1ov_base and inttab1cc0_base are the interrupt signals before culling by tabop. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1537 of 1817 sep 19, 2011 table 24-1. dma start factors (2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 1 0 1 0 intce1t/intuc5r/intiic3 1 0 1 0 1 1 intce1tiof/intuc5t 1 0 1 1 0 0 intcf0r/intuc3r/intiic1 1 0 1 1 0 1 intcf0t/intuc3t 1 0 1 1 1 0 intcf1r/intuc1r/intiic0 1 0 1 1 1 1 intcf1t/intuc1t 1 1 0 0 0 0 intcf2r/intuc0r 1 1 0 0 0 1 intcf2t/intuc0t 1 1 0 0 1 0 intcf3r/intub1tir 1 1 0 0 1 1 intcf3t/intub1tit 1 1 0 1 0 0 intcf4r/intub0tir 1 1 0 1 0 1 intcf4t/intub0tit 1 1 0 1 1 0 intcf5r/intuc6r 1 1 0 1 1 1 intcf5t/intuc6t 1 1 1 0 0 0 intcf6r/intuc7r 1 1 1 0 0 1 intcf6t/intuc7t 1 1 1 0 1 0 intuc2r/intiic2 1 1 1 0 1 1 intuc2t 1 1 1 1 0 0 intiic4 1 1 1 1 0 1 intad 1 1 1 1 1 0 intkr 1 1 1 1 1 1 intrtc1 remark n = 0 to 3 v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1538 of 1817 sep 19, 2011 (7) external dma request enable register (exdrqen) the exdrqen register sets the dma request to each dma channel when connecting the external usb device by using the udmarqm/udmaakm pin (m = 0, 1). this register can be read or written in 8-bit units. reset sets this register to 00h. rq3ex1e rqnex1e 0 1 assignment of dma channel n (n = 0 to 3) does not assign dma channel n to udmarq1/udmaak1 pin assigns dma channel n to udmarq1/udmaak1 pin exdrqen rq2ex1e rq1ex1e rq0ex1e rq3ex0e rq2ex0e rq1ex0e rq0ex0e 65 4 3 21 7 0 rqnex0e 0 1 assignment of dma channel n (n = 0 to 3) does not assign dma channel n to udmarq0/udmaak0 pin assigns dma channel n to udmarq0/udmaak0 pin after reset: 00h r/w address: ffffff60h cautions 1. assigning multiple dma channels to the udmarq1/udmaak1 pin is prohibited (setting the rq3ex1e, rq2ex1e, rq1ex1e, and rq 0ex1e bits to the udmarq1/udmaak1 pin at the same time is prohibited). 2. assigning multiple dma channels to the udmarq0/udmaak0 pin is prohibited (setting the rq3ex0e, rq2ex0e, rq1ex0e, and rq 0ex0e bits to the udmarq0/udmaak0 pin at the same time is prohibited). 3. assigning both the udmarq1/udmaak1 pin and the udmarq0/udmaak0 pin to the same dma channel is prohibited (setti ng the rq3ex1e and rq 3ex0e, rq2ex1e and rq2ex0e, rq1ex1e and rq1ex0e, and rq0 ex1e and rq0ex0e bits respectively at the same time is prohibited). 4. when using a dma request from an exte rnal source by setting the exdrqen register, set the dtfrn.ifcn5-ifcn0 bi t to 000000 (to prohibit a dma request via an interrupt). for details, see 24.3 (6) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3). v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1539 of 1817 sep 19, 2011 24.4 transfer targets table 24-2 shows the relationship between the transfer targets ( : transfer enabled, : transfer disabled). table 24-2. relationship between transfer targets transfer destination internal rom on-chip peripheral i/o internal ram external memory on-chip peripheral i/o internal ram external memory source internal rom caution the operation is not guaranteed for combinati ons of transfer destination and source marked with ? ? in table 24-2. 24.5 transfer modes single transfer is supported as the transfer mode. in single transfer mode, the bus is released at each byte /halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher priority dma transfer request is issued, the higher priority dma request always takes precedence. if a new transfer request of the same channel and a transf er request of another channel with a lower priority are generated in a transfer cycle, dma transfer of the channel with the lower priority is executed after the bus is released to the cpu (the new transfer request of the same channel is ignored in the transfer cycle). v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1540 of 1817 sep 19, 2011 24.6 transfer types as a transfer type, the 2-cycle transfer is supported. in two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle. in the read cycle, the transfer source ad dress is output and reading is performed from the source to the dmac. in the write cycle, the transfer destination addr ess is output and writing is performed from the dmac to the destination. an idle cycle of one clock is always inserted between a read cycle and a write cycle. if the data bus width differs between the transfer source and destination for dma transfe r of two cycles, the operation is performed as follows. <16-bit data transfer> <1> transfer from 32-bit bus 16-bit bus a read cycle (the higher 16 bits are in a high-impedance state) is generated, follow ed by generation of a write cycle (16 bits). <2> transfer from 16-/32-bit bus to 8-bit bus a 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice. <3> transfer from 8-bit bus to 16-/32-bit bus an 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once. <4> transfer between 16-bit bus and 32-bit bus a 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once. for dma transfer executed to an on-chip peripheral i/o regist er (transfer source/destinati on), be sure to specify the same transfer size as the register size. for example, for dm a transfer to an 8-bit register, be sure to specify byte (8-bit) transfer. remark the bus width of each transfer target (tr ansfer source/destination) is as follows. ? on-chip peripheral i/o: 16-bit bus width ? internal ram: 32-bit bus width ? external memory: 8-bit or 16-bit bus width v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1541 of 1817 sep 19, 2011 24.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 the priorities are checked for every transfer cycle. 24.8 time related to dma transfer the time required to respond to a dma request, and the mi nimum number of clocks required for dma transfer are shown below. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note 1 + transfer destination memory access (<2>) dma cycle minimum number of execution clocks <1> dma request response time 4 clocks (min.) + noise elimination time note 2 external memory access depends on connected memory. internal ram access 2 clocks note 3 peripheral i/o register access 3 clocks + number of wait cycles specified by vswc register note 4 usb register access 4 clocks note 5 <2> memory access data-only ram access 4 clocks note 5 notes 1. one clock is always inserted between a read cycle and a write cycle in dma transfer. 2. if an external interrupt (intpn) is specified as the tr igger to start dma transfer, noise elimination time is added (n = 00 to 20: v850es/jh3-e, n = 00 to 25: v850es/jj3-e). 3. two clocks are required for a dma cycle. 4. more wait cycles are necessary for accessing a specific peripheral i/o register (for details, see 3.4.9 (2) ). 5. this is the number of clocks required when the following wait specifications have been made: 1 data wait (set by the dwc0 register), 0 address waits (set by the awc register), and 0 idle waits (s et by the bcc register). v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1542 of 1817 sep 19, 2011 24.9 dma transfer start factors there are two types of dma transfe r start factors, as shown below. (1) request by software if the stgn bit is set to 1 while the dchcn.tcn bit = 1 and enn bit = 1 (dma transfer enabled), dma transfer is started. to request the next dma transfer cycle i mmediately after that, confirm, by using the dbcn re gister, that the preceding dma transfer cycle has been completed, and set the stgn bit to 1 again (n = 0 to 3). tcn bit = 0, enn bit = 1 stgn bit = 1 ? starts the first dma transfer. confirm that the contents of the dbcn register have been updated. stgn bit = 1 ? starts the second dma transfer. : generation of terminal count ? enn bit = 0, tc n bit = 1, and intdman signal is generated. (2) request by on-chip peripheral i/o if an interrupt request is generated from the on-chip peripheral i/o set by the dtfrn register when the dchcn.tcn bit = 0 and enn bit = 1 (dma transf er enabled), dma transfer is started. cautions 1. two start factors (software trigger and hard ware trigger) cannot be u sed for one dma channel. if two start factors are simultaneously generate d for one dma channel, only one of them is valid. the start factor that is valid cannot be identified. 2. a new transfer request that is generate d after the preceding dma transfer request was generated or in the preceding dma tran sfer cycle is ignored (cleared). 3. the transfer request interval of the same dm a channel varies depending on the setting of bus wait in the dma transfer cycle, the start status of the other channels, or the external bus hold request. in particular, as described in caution 2, a new transfer request that is generated for the same channel before the dma transfer cycle or during the dma transfer cycle is ignored. therefore, the transfer request intervals fo r the same dma channel must be sufficiently separated by the system. when the software trigger is used, completion of the dma transfer cycle that was generated before can be checked by updating the dbcn register. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1543 of 1817 sep 19, 2011 24.10 dma abort factors dma transfer is aborted if a bus hold occurs. the same applies if transfer is exec uted between the internal memory/on-chip peripheral i/o and internal memory/on- chip peripheral i/o. when the bus hold is cleared, dma transfer is resumed. 24.11 end of dma transfer when dma transfer has been completed the number of times set to the dbcn register and when the dchcn.enn bit is cleared to 0 and tcn bit is set to 1, a dma transfer end in terrupt request signal (intdman) is generated for the interrupt controller (intc) (n = 0 to 3). the v850es/jh3-e and v850es/jj3-e do not output a terminal co unt signal to external devices. therefore, confirm completion of dma transfer by using the dma transfer end interrupt or polling the tcn bit. 24.12 operation timing figures 24-1 to 24-4 show dma operation timing. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1544 of 1817 sep 19, 2011 figure 24-1. priority of dma (1) preparation for transfer read write idle end processing dma2 processing cpu processing dma1 processing cpu processing cpu processing dma0 processing dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit preparation for transfer read write idle end processing preparation for transfer read remarks 1. transfer in the order of dma0 dma1 dma2 2. in the case of transfer between external memory spaces (multiplexed bus, no wait) v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1545 of 1817 sep 19, 2011 figure 24-2. priority of dma (2) preparation for transfer read write idle dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit cpu processing dma0 processing cpu processing dma1 processing cpu processing dma0 processing read write idle end processing read preparation for transfer preparation for transfer end processing remarks 1. transfer in the order of dma0 dma1 dma0 (dma2 is held pending.) 2. in the case of transfer between external memory spaces (multiplexed bus, no wait) v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1546 of 1817 sep 19, 2011 figure 24-3. period in which dma transfer request is ignored (1) preparation for transfer read cycle write cycle idle end processing dma transfer mode of processing dfn bit system clock transfer request generated after this can be acknowledged dma0 processing cpu processing cpu processing note 2 note 2 dman transfer request note 1 note 2 notes 1. interrupt from on-chip peripheral i/o , or software trigger (stgn bit) 2. new dma request of the same channel is ignor ed between when the first request is generated and the end processing is complete. remark in the case of transfer between external memory spaces (multiplexed bus, no wait) v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1547 of 1817 sep 19, 2011 figure 24-4. period in which dma transfer request is ignored (2) preparation for transfer read write idle end processing write end processing preparation for transfer read idle <1> <2> <3> <4> cpu processing dma0 processing cpu processing dma1 processing cpu processing preparation for transfer read dma0 transfer request system clock dma1 transfer request dma2 transfer request dma transfer mode of processing df0 bit df1 bit df2 bit dma0 processing <1> dma0 transfer request <2> new dma0 transfer request is generated during dma0 transfer. a dma transfer request of the same channel is ignored during dma transfer. <3> requests for dma0 and dma1 are generated at the same time. dma0 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma1 request is acknowledged. <4> requests for dma0, dma1, and dma2 are generated at the same time. dma1 request is ignored (a dma transfer request of the same channel during transfer is ignored). dma0 request is acknowledged according to priority. dma2 request is held pending (transfer of dma2 occurs next). 24.13 cautions v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1548 of 1817 sep 19, 2011 (1) caution for vswc register when using the dmac, be sure to set an appropriate value, in accordance with the operating frequency, to the vswc register. when the default value (77h) of the vswc r egister is used, or if an inappropriate value is set to the vswc register, the operation is not correctly performed (for details of the vswc register, see 3.4.9 (1) (a) system wait control register (vswc) ). (2) caution for reading dchcn .tcn bit (n = 0 to 3) the tcn bit is cleared to 0 when it is read, but it is not aut omatically cleared even if it is read at a specific timing. to accurately clear the tcn bit, add the following processing. (a) when waiting for completion of dma transfer by polling tcn bit confirm that the tcn bit has been set to 1 (after tcn bi t = 1 is read), and then read the tcn bit three more times. (b) when reading tcn bit in interrupt servicing routine execute reading the tcn bit three times. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1549 of 1817 sep 19, 2011 (3) dma transfer initialization pr ocedure (setting dchcn.initn bit to 1) even if the initn bit is set to 1 when the channel execut ing dma transfer is to be initialized, the channel may not be initialized. to accurately initialize the chann el, execute either of the following two procedures. (a) temporarily stop transf er of all dma channels initialize the channel executing dma transfer using the procedure in <1> to <7> below. note, however, that tcn bit is cleared to 0 when step <5 > is executed. make sure that the other processing programs do not expect that the tcn bit is 1. <1> disable interrupts (di). <2> read the dchcn.enn bit of dma channels other than the one to be forcibly terminated, and transfer the value to a general-purpose register. <3> clear the enn bit of the dma channe ls used (including the channel to be forcibly terminated) to 0. to clear the enn bit of the last dma channel, execute the cl ear instruction twice. if the target of dma transfer (transfer source/destination) is the internal ram, execute the instruction three times. example: execute instructions in the following order if channels 0, 1, and 2 are used (if the target of transfer is not the internal ram). ? clear dchc0.e00 bit to 0. ? clear dchc1.e11 bit to 0. ? clear dchc2.e22 bit to 0. ? clear dchc2.e22 bit to 0 again. <4> set the initn bit of the channel to be forcibly terminated to 1. <5> read the tcn bit of each channel not to be forcibly terminated. if both the tcn bit and the enn bit read in <2> are 1 (logical product (and) is 1), clear the saved enn bit to 0. <6> after the operation in <5>, write the enn bit value to the dchcn register. <7> enable interrupts (ei). caution be sure to execute step <5> above to prevent illegal setting of the enn bit of the channels whose dma transfer has been normally completed between <2> and <3>. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1550 of 1817 sep 19, 2011 (b) repeatedly execute setting initn bit until transfer is forcibly terminated correctly <1> suppress a request from the dma request source of t he channel to be forcibly terminated (stop operation of the on-chip peripheral i/o). <2> check that the dma transfer request of the channel to be forcibly terminated is not held pending, by using the dtfrn.dfn bit. if a dma transfer request is held pe nding, wait until executi on of the pending request is completed. <3> when it has been confirmed that t he dma request of the channel to be forcibly terminated is not held pending, clear the enn bit to 0. <4> again, clear the enn bit of the channel to be forcibly terminated. if the target of transfer for the channel to be forcibly terminated (transfer source/des tination) is the internal ram, execute this operation once more. <5> copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose register. <6> set the initn bit of the channel to be forcibly terminated to 1. <7> read the value of the dbcn register of the channel to be forcibly terminated, and compare it with the value copied in <5>. if the two values do not match, repeat operations <6> and <7>. remarks 1. when the value of the dbcn regist er is read in <7>, the initial number of transfers is read if forced termination has been correctly completed. if not, the remaining number of transfers is read. 2. note that method (b) may take a long time if the application frequently uses dma transfer for a channel other than the dma channel to be forcibly terminated. (4) procedure of temporarily stoppi ng dma transfer (clearing enn bit) stop and resume the dma transfer under ex ecution using the following procedure. <1> suppress a transfer request from the dma request source (stop the operation of t he on-chip peripheral i/o). <2> check the dma transfer request is not held pending , by using the dfn bit (check if the dfn bit = 0). if a request is pending, wait until execution of the pending dma transfer request is completed. <3> if it has been confirmed that no dma transfer request is held pending, clear the enn bit to 0 (this operation stops dma transfer). <4> set the enn bit to 1 to resume dma transfer. <5> resume the operation of the dma request source t hat has been stopped (start t he operation of the on-chip peripheral i/o). (5) memory boundary the operation is not guaranteed if the address of the transfer source or destination exceeds the area of the dma target (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (6) transferring misaligned data dma transfer of misaligned data with a 16-bit bus width is not supported. if an odd address is specified as the transfe r source or destination, the least signi ficant bit of the address is forcibly assumed to be 0. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1551 of 1817 sep 19, 2011 (7) bus arbitration for cpu because the dma controller has a higher priority bus mastership than the cpu, a cpu access that takes place during dma transfer is held pe nding until the dma transfer cycle is comple ted and the bus is re leased to the cpu. however, the cpu can access the external memory, inte rnal peripheral i/o, and internal ram for which dma transfer is not being executed. ? the cpu can access the internal rom and internal ram when dma transfer is being executed between the external memory and on-chip peripheral i/o. ? the cpu can access the internal rom, and internal peripheral i/o when dma transfer is being executed between external memories. (8) registers/bits that must not be rewritten during dma operation set the following registers at the following ti ming when a dma operation is not under execution. [registers] ? dsanh, dsanl, ddanh, ddanl, dbcn, and dadcn registers ? dtfrn.ifcn5 to dtfrn.ifcn0 bits [settable timing] ? period from after reset to start of the first dma transfer ? time after channel initialization to start of dma transfer ? period from after completion of dma transfer (tcn bit = 1) to start of the next dma transfer (9) be sure to set the following register bits to 0. ? bits 14 to 10 of dsanh register ? bits 14 to 10 of ddanh register ? bits 15, 13 to 8, and 3 to 0 of dadcn register ? bits 6 to 3 of dchcn register (10) dma start factor do not start two or more dma channels with the same st art factor. if two or more channels are started with the same factor, dma for which a channel has already been se t may be started or a dma channel with a lower priority may be acknowledged earlier than a dma channel with a higher priority. the operat ion cannot be guaranteed. v850es/jh3-e, v850es/jj3-e chapter 24 dma function (dma controller) r01uh0290ej0300 rev.3.00 page 1552 of 1817 sep 19, 2011 (11) read values of dsan and ddan registers values in the middle of updating may be read from the ds an and ddan registers during dma transfer (n = 0 to 3). for example, if the dsanh register and then the dsanl register are read when the dma transfer source address (dsan register) is 0000ffffh and the co unt direction is incremental (da dcn.sad1 and dadcn.sad0 bits = 00), the value of the dsan register differs as follows, depending on whether dma transfe r is executed immediately after the dsanh register is read. (a) if dma transfer does not occu r while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> read value of dsanl register: dsanl = ffffh (b) if dma transfer occurs while dsan register is read <1> read value of dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register: dsan = 00100000h <4> read value of dsanl register: dsanl = 0000h v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1553 of 1817 sep 19, 2011 chapter 25 interrupt/except ion processing function the v850es/jh3-e and v850es/jj3-e are prov ided with a dedicated interrupt controll er (intc) for interrupt servicing and can process a total of 100 to 115 interrupt requests. an interrupt is an event that occurs independently of program execution, and an e xception is an event whose occurrence is dependent on program execution. the v850es/jh3-e and v850es/jj3-e can process interrupt r equest signals from the on-chip peripheral hardware and external sources. moreover, exception processing can be st arted by the trap instruction (software exception) or by generation of an exception event (i.e. fetc hing of an illegal opcode) (exception trap). 25.1 features interrupts table 25-1. interrupts of v850es/jh3-e and v850es/jj3-e internal external non-maskable maskable total n on-maskable maskable total pd70f3778 1 77 78 1 21 22 pd70f3779 1 77 78 1 21 22 pd70f3780 1 77 78 1 21 22 pd70f3781 1 77 78 1 21 22 pd70f3782 1 77 78 1 21 22 v850es/jh3-e pd70f3783 1 81 82 1 21 22 pd70f3784 1 83 84 1 26 27 pd70f3785 1 83 84 1 26 27 v850es/jj3-e pd70f3786 1 87 88 1 26 27 ? 8 levels of programmable priorities (maskable interrupts) ? multiple interrupt control according to priority ? masks can be specified for eac h maskable interrupt request. ? noise elimination, edge detection, and valid edge specification for external interrupt request signals. exceptions ? software exceptions: 32 sources ? exception trap: 2 sources (illegal opcode exception) interrupt/exception sources of the v850e s/jh3-e and v850es/jj3-e are listed in tables 25-2 and 25-3 , respectively. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1554 of 1817 sep 19, 2011 table 25-2. v850es/jh3-e interrupt/exception sources (1/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register reset interrupt ? reset reset pin input/reset input by internal source reset 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt2 wdt2 over flow wdt2 0020h 00000020h note 1 ? ? trap0n (n = 0 to fh) trap instruction ? 004nh 00000040h nextpc ? software exception exception ? trap1n (n = 0 to fh) trap instruction ? 005nh 00000050h nextpc ? exception trap exception ? ilgop/dbg0 illegal opcode/dbtrap instruction ? 006nh 00000060h nextpc ? 0 intlvi note 2 low voltage detection note 2 poclvi 0080h 00000080h nextpc lviic note 2 1 intp00 external interrupt pin input edge detection (intp00) pin 0090h 00000090h nextpc pic00 2 intp01 external interrupt pin input edge detection (intp01) pin 00a0h 000000a0h nextpc pic01 3 intp02 external interrupt pin input edge detection (intp02) pin 00b0h 000000b0h nextpc pic02 4 intp03 external interrupt pin input edge detection (intp03) pin 00c0h 000000c0h nextpc pic03 5 intp04 external interrupt pin input edge detection (intp04) pin 00d0h 000000d0h nextpc pic04 6 intp05 external interrupt pin input edge detection (intp05) pin 00e0h 000000e0h nextpc pic05 7 intp06 external interrupt pin input edge detection (intp06) pin 00f0h 000000f0h nextpc pic06 8 intp07 external interrupt pin input edge detection (intp07) pin 0100h 00000100h nextpc pic07 9 intp08 external interrupt pin input edge detection (intp08) pin 0110h 00000110h nextpc pic08 10 intp09 external interrupt pin input edge detection (intp09) pin 0120h 00000120h nextpc pic09 11 intp10 external interrupt pin input edge detection (intp10) pin 0130h 00000130h nextpc pic10 12 intp11 external interrupt pin input edge detection (intp11) pin 0140h 00000140h nextpc pic11 13 intp12 external interrupt pin input edge detection (intp12) pin 0150h 00000150h nextpc pic12 14 intp13 external interrupt pin input edge detection (intp13) pin 0160h 00000160h nextpc pic13 maskable interrupt 15 intp14 external interrupt pin input edge detection (intp14) pin 0170h 00000170h nextpc pic14 notes 1. for restoring in the case of intwdt2, see 25.2.2 (2) from intwdt2 signal . 2. when mii is used, the use of intlvi is prohibited. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1555 of 1817 sep 19, 2011 table 25-2. v850es/jh3-e interrupt/exception sources (2/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 16 intp15 external interrupt pin input edge detection (intp15) pin 0180h 00000180h nextpc pic15 17 intp16 external interrupt pin input edge detection (intp16) pin 0190h 00000190h nextpc pic16 18 intp17 external interrupt pin input edge detection (intp17) pin 01a0h 000001a0h nextpc pic17 19 intp18 external interrupt pin input edge detection (intp18) pin 01b0h 000001b0h nextpc pic18 20 intp19 external interrupt pin input edge detection (intp19) pin 01c0h 000001c0h nextpc pic19 21 intp20 external interrupt pin input edge detection (intp20) pin 01d0h 000001d0h nextpc pic20 27 inttab0ov tab0 overflow tab0 0230h 00000230h nextpc tab0ovic 28 inttab0cc0 tab0 capture 0/ compare 0 match tab0 0240h 00000240h ne xtpc tab0ccic0 29 inttab0cc1 tab0 capture 1/ compare 1 match tab0 0250h 00000250h ne xtpc tab0ccic1 30 inttab0cc2 tab0 capture 2/ compare 2 match tab0 0260h 00000260h ne xtpc tab0ccic2 32 inttab1ov note 1 tab1 overflow note 1 tab1 0280h 00000280h nextpc tab1ovic note 1 33 inttab1cc0 note 2 tab1 capture 0/ compare 0 match note 2 tab1 0290h 00000290h nextpc tab1ccic0 note 2 34 inttab1cc1 tab1 capture 1/ compare 1 match tab1 02a0h 000002a0h nextpc tab1ccic1 35 inttab1cc2 tab1 capture 2/ compare 2 match tab1 02b0h 000002b0h nextpc tab1ccic2 36 inttab1cc3 tab1 capture 3/ compare 3 match tab1 02c0h 000002c0h nextpc tab1ccic3 37 inttt0ov tmt0 overflow tmt0 02d0h 000002d0h nextpc tt0ovic 38 inttt0cc0 tmt0 capture 0/ compare 0 match tmt0 02e0h 000002e0h nextpc tt0ccic0 39 inttt0cc1 tmt0 capture 1/ compare 1 match tmt0 02f0h 000002f0h nextpc tt0ccic1 40 inttt0ec tmt0 encoder input tmt0 0300h 00000300h nextpc tt0ecic 41 inttaa0ov taa0 overflow taa0 0310h 00000310h nextpc taa0ovic 42 inttaa0cc0 taa0 capture 0/ compare 0 match taa0 0320h 00000320h ne xtpc taa0ccic0 maskable interrupt 43 inttaa0cc1 taa0 capture 1/ compare 1 match taa0 0330h 00000330h ne xtpc taa0ccic1 notes 1. when using tab1 in the 6-phase pw m output mode, functions as the zero match interrupt (tab1tiod) request from tabop. 2. when using tab1 in the 6-phase pwm output mode, f unctions as the compare match interrupt (tab1ticd0) request from tabop. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1556 of 1817 sep 19, 2011 table 25-2. v850es/jh3-e interrupt/exception sources (3/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 44 inttaa1ov taa1 overflow taa1 0340h 00000340h nextpc taa1ovic 45 inttaa1cc0 taa1 capture 0/ compare 0 match taa1 0350h 00000350h nextpc taa1ccic0 46 inttaa1cc1 taa1 capture 1/ compare 1 match taa1 0360h 00000360h nextpc taa1ccic1 47 inttaa2ov taa2 overflow taa2 0370h 00000370h nextpc taa2ovic 48 inttaa2cc0 taa2 capture 0/ compare 0 match taa2 0380h 00000380h nextpc taa2ccic0 49 inttaa2cc1 taa2 capture 1/ compare 1 match taa2 0390h 00000390h nextpc taa2ccic1 50 inttaa3ov taa3 overflow taa3 03a0h 000003a0h nextpc taa3ovic 51 inttaa3cc0 taa3 capture 0/ compare 0 match taa3 03b0h 000003b0h nextpc taa3ccic0 52 inttaa3cc1 taa3 capture 1/ compare 1 match taa3 03c0h 000003c0h nextpc taa3ccic1 53 inttaa4ov taa4 overflow taa4 03d0h 000003d0h nextpc taa4ovic 54 inttaa4cc0 taa4 capture 0/ compare 0 match taa4 03e0h 000003e0h nextpc taa4ccic0 55 inttaa4cc1 taa4 capture 1/ compare 1 match taa4 03f0h 000003f0h nextpc taa4ccic1 56 inttaa5ov taa5 overflow taa5 0400h 00000400h nextpc taa5ovic 57 inttaa5cc0 taa5 capture 0/ compare 0 match taa5 0410h 00000410h nextpc taa5ccic0 58 inttaa5cc1 taa5 capture 1/ compare 1 match taa5 0420h 00000420h nextpc taa5ccic1 59 inttm0eq0 tmm0 compare match t mm0 0430h 00000430h nextpc tm0eqic0 60 inttm1eq0 tmm1 compare match t mm1 0440h 00000440h nextpc tm1eqic0 61 inttm2eq0 tmm2 compare match t mm2 0450h 00000450h nextpc tm2eqic0 62 inttm3eq0 tmm3 compare match t mm3 0460h 00000460h nextpc tm3eqic0 63 intce0t/ intuc4r csie0 transfer completion/ uartc4 reception error csie0/ uartc4 0470h 00000470h nextpc ce0tic/ uc4ric 64 intce0tiof/ intuc4t csie0 buffer overflow/ uartc4 consecutive transmission write enable csie0/ uartc4 0480h 00000480h nextpc ce0tiofic/ uc4tic 65 intce1t/ intuc5r/ intiic3 csie1 transfer completion/ uartc5 reception error/ iic2 transfer completion csie1/ uartc5/ iic3 0490h 00000490h nextpc ce1tic/ uc5ric/ iicic3 66 intce1tiof/ intuc5t csie1 buffer overflow/ uartc5 consecutive transmission write enable csie1/ uartc5 04a0h 000004a0h nextpc ce1tiofic/ uc5tic 67 intcf0r/ intuc3r/ intiic1 csif0 transfer completion/ uartc3 reception completion/uartc3 reception error/iic1 transfer completion csif0/ uartc3/ iic1 04b0h 000004b0h nextpc ce0ric/ uc3ric/ iicic1 maskable interrupt 68 intcf0t/ intuc3t csif0 consecutive transmission write enable/ uartc3 consecutive transmission write enable csif0/ uartc3 04c0h 000004c0h nex tpc cf0tic/ uc3tic v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1557 of 1817 sep 19, 2011 table 25-2. v850es/jh3-e interrupt/exception sources (4/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 69 intcf1r/ intuc1r/ intiic0 csif1 reception completion/csif1 reception error/uartc1 reception completion/uartc1 reception error/iic0 transfer completion csif1/ uartc1/ iic0 04d0h 000004d0h nextpc cf1ric/ uc1ric/ iicic0 70 intcf1t/ intuc1t csif1 consecutive transmission write enable/uartc1 consecutive transmission write enable csif1 uartc1 04e0h 000004e0h nextpc cf1tic/ uc1tic 71 intcf2r/ intuc0r csif2 reception completion/ csif2 reception error/ uartc0 reception completion/ uartc0 reception error csif2/ uartc0 04f0h 000004f0h nex tpc cf2ric/ uc0ric 72 intcf2t/ intuc0t csif2 consecutive transmission write enable/ uartc0 consecutive transmission write enable csif2/ uartc0 0500h 00000500h nextpc cf2tic/ uc0tic 73 intcf3r/ intub1tir csif3 reception completion/ csif3 reception error/ uartb1 reception completion csif3/ uartb1 0510h 00000510h nextpc cf3ric/ ub1tiric 74 intcf3t/ intub1tit csif3 consecutive transmission write enable/ uartb1 transfer completion csif3/ uartb1 0520h 00000520h nextpc cf3tic/ ub1titic 75 intub1tif uartb1fifo transfer completion uartb1 0530h 00000530h nextpc ub1tific 76 intub1tire uartb1 reception erro r uartb1 0540h 00000540h nextpc ub1tireic 77 intub1tito uartb1 reception tim eout uartb1 0550h 00000550h nextpc ub1titoic 78 intcf4r/ intub0tir csif4 reception completion/ csif4 reception error/ uartb0 reception completion csif4/ uartb0 0560h 00000560h nextpc cf4ric/ ub0tiric 79 intcf4t/ intub0tit csif4 consecutive transmission write enable/ uartb0 transfer completion csif4/ uartb0 0570h 00000570h nextpc cf4tic/ ub0titic 80 intub0tif uartb0 fifo transfer completion uartb0 0580h 00000580h nextpc ub0tific 81 intub0tire uartb0 reception erro r uartb0 0590h 00000590h nextpc ub0tireic 82 intub0tito uartb0 reception timeout uartb0 05a0h 000005a0h nextpc ub0titoic 87 intuc2r/ intiic2 uartc2 reception completion/ uartc2 reception error/ iic2 transfer completion uartc2/ iic2 05f0h 000005f0h nex tpc uc2ric/ iicic2 88 intuc2t uartc2 consecutive transmission write enable uartc2 0600h 00000600h nextpc uc2tic 90 intad a/d conversion comple tion a/d 0620h 00000620h nextpc adic 91 intdma0 dma0 transfer completi on dma 0630h 00000630h nextpc dmaic0 92 intdma1 dma1 transfer completi on dma 0640h 00000640h nextpc dmaic1 93 intdma2 dma2 transfer completi on dma 0650h 00000650h nextpc dmaic2 94 intdma3 dma3 transfer completi on dma 0660h 00000660h nextpc dmaic3 95 intkr key return interrupt kr 0670h 00000670h nextpc kric maskable interrupt 96 intrtc0 rtc constant cycle signal rtc 0680h 00000680h nextpc rtc0ic v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1558 of 1817 sep 19, 2011 table 25-2. v850es/jh3-e interrupt/exception sources (5/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 97 intrtc1 rtc alarm match rt c 0690h 00000690h nextpc rtc1ic 98 intrtc2 rtc interval signal rtc 06a0h 000006a0h nextpc rtc2ic 99 intusbf0 usbf inte rrupt usbf 06b0h 000006b0h nextpc ufic0 100 intusbf1 usbf resume interrupt usbf 06c0h 000006c0h nextpc ufic1 101 intetmrx packet reception ether net 06d0h 000006d0h nextpc etmrxic 102 intetmtx packet transmission ether net 06e0h 000006e0h nextpc etmtxic 103 intetmrq reception packet read request ethernet 06f0h 000006f0h nextpc etmrqic 104 intetmfs fifo status ether net 0700h 00000700h nextpc etmfsic 105 intetmts transmission status et hernet 0710h 00000710h nextpc etmtsic 106 intetmrs reception status et hernet 0720h 00000720h nextpc etmrsic 107 intetmov statistics c ounter overflow ethernet 0730h 00000730h nextpc etmovic 108 intetber error interrupt et hernet 0740h 00000740h nextpc etberic 110 intc0err note can0 error note can0 0760h 00000760h nextpc erric0 note 111 intc0wup1 note can0 wakeup note can0 0770h 00000770h nextpc wupic0 note 112 intc0rec note can0 reception note can0 0780h 00000780h nextpc recic0 note maskable interrupt 113 intc0trx note can0 transmission note can0 0790h 00000790h nextpc trxic0 note note pd70f3783 only remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. the priority order of non-maskable interrupt is intwdt2 > nmi. restored pc: the value of the program counter (pc) saved to eipc, fepc, or dbpc when interrupt servicing is started. note, however, t hat the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the proc essing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1559 of 1817 sep 19, 2011 table 25-3. v850es/jj3-e interrupt/exception sources (1/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register reset interrupt ? reset reset pin input/reset input by internal source reset 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt2 wdt2 over flow wdt2 0020h 00000020h note 1 v ? trap0n (n = 0 to fh) trap instruction ? 004nh 00000040h nextpc ? software exception exception ? trap1n (n = 0 to fh) trap instruction ? 005nh 00000050h nextpc ? exception trap exception ? ilgop/dbg0 illegal opcode/dbtrap instruction ? 006nh 00000060h nextpc ? 0 intlvi note 2 low voltage detection note 2 poclvi 0080h 00000080h nextpc lviic note 2 1 intp00 external interrupt pin input edge detection (intp00) pin 0090h 00000090h nextpc pic00 2 intp01 external interrupt pin input edge detection (intp01) pin 00a0h 000000a0h nextpc pic01 3 intp02 external interrupt pin input edge detection (intp02) pin 00b0h 000000b0h nextpc pic02 4 intp03 external interrupt pin input edge detection (intp03) pin 00c0h 000000c0h nextpc pic03 5 intp04 external interrupt pin input edge detection (intp04) pin 00d0h 000000d0h nextpc pic04 6 intp05 external interrupt pin input edge detection (intp05) pin 00e0h 000000e0h nextpc pic05 7 intp06 external interrupt pin input edge detection (intp06) pin 00f0h 000000f0h nextpc pic06 8 intp07 external interrupt pin input edge detection (intp07) pin 0100h 00000100h nextpc pic07 9 intp08 external interrupt pin input edge detection (intp08) pin 0110h 00000110h nextpc pic08 10 intp09 external interrupt pin input edge detection (intp09) pin 0120h 00000120h nextpc pic09 11 intp10 external interrupt pin input edge detection (intp10) pin 0130h 00000130h nextpc pic10 12 intp11 external interrupt pin input edge detection (intp11) pin 0140h 00000140h nextpc pic11 13 intp12 external interrupt pin input edge detection (intp12) pin 0150h 00000150h nextpc pic12 14 intp13 external interrupt pin input edge detection (intp13) pin 0160h 00000160h nextpc pic13 maskable interrupt 15 intp14 external interrupt pin input edge detection (intp14) pin 0170h 00000170h nextpc pic14 notes 1. for restoring in the case of intwdt2, see 25.2.2 (2) from intwdt2 signal . 2. when mii is used, the use of intlvi is prohibited. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1560 of 1817 sep 19, 2011 table 25-3. v850es/jj3-e interrupt/exception sources (2/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 16 intp15 external interrupt pin input edge detection (intp15) pin 0180h 00000180h nextpc pic15 17 intp16 external interrupt pin input edge detection (intp16) pin 0190h 00000190h nextpc pic16 18 intp17 external interrupt pin input edge detection (intp17) pin 01a0h 000001a0h nextpc pic17 19 intp18 external interrupt pin input edge detection (intp18) pin 01b0h 000001b0h nextpc pic18 20 intp19 external interrupt pin input edge detection (intp19) pin 01c0h 000001c0h nextpc pic19 21 intp20 external interrupt pin input edge detection (intp20) pin 01d0h 000001d0h nextpc pic20 22 intp21 external interrupt pin input edge detection (intp21) pin 01e0h 000001e0h nextpc pic21 23 intp22 external interrupt pin input edge detection (intp22) pin 01f0h 000001f0h nextpc pic22 24 intp23 external interrupt pin input edge detection (intp23) pin 0200h 00000200h nextpc pic23 25 intp24 external interrupt pin input edge detection (intp24) pin 0210h 00000210h nextpc pic24 26 intp25 external interrupt pin input edge detection (intp25) pin 0220h 00000220h nextpc pic25 27 inttab0ov tab0 overflow t ab0 0230h 00000230h nextpc tab0ovic 28 inttab0cc0 tab0 capture 0/ compare 0 match tab0 0240h 00000240h nextpc tab0ccic0 29 inttab0cc1 tab0 capture 1/ compare 1 match tab0 0250h 00000250h nextpc tab0ccic1 30 inttab0cc2 tab0 capture 2/ compare 2 match tab0 0260h 00000260h nextpc tab0ccic2 31 inttab0cc3 tab0 capture 3/ compare 3 match tab0 0270h 00000270h nextpc tab0ccic3 32 inttab1ov note 1 tab1 overflow note 1 tab1 0280h 00000280h nextpc tab1ovic note 1 33 inttab1cc0 note 2 tab1 capture 0/ compare 0 match note 2 tab1 0290h 00000290h nextpc tab1ccic0 note 2 34 inttab1cc1 tab1 capture 1/ compare 1 match tab1 02a0h 000002a0h nextpc tab1ccic1 35 inttab1cc2 tab1 capture 2/ compare 2 match tab1 02b0h 000002b0h nextpc tab1ccic2 maskable interrupt 36 inttab1cc3 tab1 capture 3/ compare 3 match tab1 02c0h 000002c0h nextpc tab1ccic3 notes 1. when using tab1 in the 6-phase pw m output mode, functions as the zero match interrupt (tab1tiod) request from tabop. 2. when using tab1 in the 6-phase pwm output mode, f unctions as the compare match interrupt (tab1ticd0) request from tabop. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1561 of 1817 sep 19, 2011 table 25-3. v850es/jj3-e interrupt/exception sources (3/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 37 inttt0ov tmt0 overflow tmt0 02d0h 000002d0h nextpc tt0ovic 38 inttt0cc0 tmt0 capture 0/ compare 0 match tmt0 02e0h 000002e0h nextpc tt0ccic0 39 inttt0cc1 tmt0 capture 1/ compare 1 match tmt0 02f0h 000002f0h nextpc tt0ccic1 40 inttt0ec tmt0 encoder input tmt0 0300h 00000300h nextpc tt0ecic 41 inttaa0ov taa0 overflow t aa0 0310h 00000310h nextpc taa0ovic 42 inttaa0cc0 taa0 capture 0/ compare 0 match taa0 0320h 00000320h nex tpc taa0ccic0 43 inttaa0cc1 taa0 capture 1/ compare 1 match taa0 0330h 00000330h nex tpc taa0ccic1 44 inttaa1ov taa1 overflow t aa1 0340h 00000340h nextpc taa1ovic 45 inttaa1cc0 taa1 capture 0/ compare 0 match taa1 0350h 00000350h nex tpc taa1ccic0 46 inttaa1cc1 taa1 capture 1/ compare 1 match taa1 0360h 00000360h nex tpc taa1ccic1 47 inttaa2ov taa2 overflow t aa2 0370h 00000370h nextpc taa2ovic 48 inttaa2cc0 taa2 capture 0/ compare 0 match taa2 0380h 00000380h nex tpc taa2ccic0 49 inttaa2cc1 taa2 capture 1/ compare 1 match taa2 0390h 00000390h nex tpc taa2ccic1 50 inttaa3ov taa3 overflow taa3 03a0h 000003a0h nextpc taa3ovic 51 inttaa3cc0 taa3 capture 0/ compare 0 match taa3 03b0h 000003b0h nextpc taa3ccic0 52 inttaa3cc1 taa3 capture 1/ compare 1 match taa3 03c0h 000003c0h nextpc taa3ccic1 53 inttaa4ov taa4 overflow taa4 03d0h 000003d0h nex tpc taa4ovic 54 inttaa4cc0 taa4 capture 0/ compare 0 match taa4 03e0h 000003e0h nextpc taa4ccic0 55 inttaa4cc1 taa4 capture 1/ compare 1 match taa4 03f0h 000003f0h nextpc taa4ccic1 56 inttaa5ov taa5 overflow t aa5 0400h 00000400h nextpc taa5ovic 57 inttaa5cc0 taa5 capture 0/ compare 0 match taa5 0410h 00000410h nex tpc taa5ccic0 58 inttaa5cc1 taa5 capture 1/ compare 1 match taa5 0420h 00000420h nex tpc taa5ccic1 59 inttm0eq0 tmm0 compare match tmm0 0430h 00000430h nextpc tm0eqic0 60 inttm1eq0 tmm1 compare match tmm1 0440h 00000440h nextpc tm1eqic0 61 inttm2eq0 tmm2 compare match tmm2 0450h 00000450h nextpc tm2eqic0 62 inttm3eq0 tmm3 compare match tmm3 0460h 00000460h nextpc tm3eqic0 63 intce0t/ intuc4r csie0 transfer completion/ uartc4 reception error csie0/ uartc4 0470h 00000470h nextpc ce0tic/ uc4ric maskable interrupt 64 intce0tiof/ intuc4t csie0 buffer overflow/ uartc4 consecutive transmission write enable csie0/ uartc4 0480h 00000480h nextpc ce0tiofic/ uc4tic v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1562 of 1817 sep 19, 2011 table 25-3. v850es/jj3-e interrupt/exception sources (4/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 65 intce1t/ intuc5r/ intiic3 csie1 transfer completion/ uartc5 reception error/ iic2 transfer completion csie1/ uartc5/ iic3 0490h 00000490h nextpc ce1tic/ uc5ric/ iicic3 66 intce1tiof/ intuc5t csie1 buffer overflow/ uartc5 consecutive transmission write enable csie1/ uartc5 04a0h 000004a0h nextpc ce1tiofic/ uc5tic 67 intcf0r/ intuc3r/ intiic1 csif0 transfer completion/ uartc3 reception completion/ uartc3 reception error/ iic1 transfer completion csif0/ uartc3/ iic1 04b0h 000004b0h nextpc ce0ric/ uc3ric/ iicic1 68 intcf0t/ intuc3t csif0 consecutive transmission write enable/ uartc3 consecutive transmission write enable csif0/ uartc3 04c0h 000004c0h ne xtpc cf0tic/ uc3tic 69 intcf1r/ intuc1r/ intiic0 csif1 reception completion/ csif1 reception error/ uartc1 reception completion/ uartc1 reception error/ iic0 transfer completion csif1/ uartc1/ iic0 04d0h 000004d0h ne xtpc cf1ric/ uc1ric/ iicic0 70 intcf1t/ intuc1t csif1 consecutive transmission write enable/ uartc1 consecutive transmission write enable csif1 uartc1 04e0h 000004e0h nextpc cf1tic/ uc1tic 71 intcf2r/ intuc0r csif2 reception completion/ csif2 reception error/ uartc0 reception completion/ uartc0 reception error csif2/ uartc0 04f0h 000004f0h ne xtpc cf2ric/ uc0ric 72 intcf2t/ intuc0t csif2 consecutive transmission write enable/ uartc0 consecutive transmission write enable csif2/ uartc0 0500h 00000500h nextpc cf2tic/ uc0tic 73 intcf3r/ intub1tir csif3 reception completion/ csif3 reception error/ uartb1 reception completion csif3/ uartb1 0510h 00000510h nextpc cf3ric/ ub1tiric 74 intcf3t/ intub1tit csif3 consecutive transmission write enable/ uartb1 transfer completion csif3/ uartb1 0520h 00000520h nextpc cf3tic/ ub1titic 75 intub1tif uartb1fifo transfer completion uartb1 0530h 00000530h nextpc ub1tific 76 intub1tire uartb1 reception error uartb1 0540h 00000540h nextpc ub1tireic 77 intub1tito uartb1 reception timeout uartb1 0550h 00000550h nextpc ub1titoic 78 intcf4r/ intub0tir csif4 reception completion/ csif4 reception error/ uartb0 reception completion csif4/ uartb0 0560h 00000560h nextpc cf4ric/ ub0tiric 79 intcf4t/ intub0tit csif4 consecutive transmission write enable/ uartb0 transfer completion csif4/ uartb0 0570h 00000570h nextpc cf4tic/ ub0titic 80 intub0tif uartb0fifo transfer completion uartb0 0580h 00000580h nextpc ub0tific 81 intub0tire uartb0 reception error uartb0 0590h 00000590h nextpc ub0tireic 82 intub0tito uartb0 reception timeout uartb0 05a0h 000005a0h nextpc ub0titoic maskable interrupt 83 intcf5r/ intuc6r csif5 reception completion/ csif5 reception error/ uartc6 reception completion/ uartc6 reception error csif5/ uartc6 05b0h 000005b0h nextpc cf5ric/ uc6ric v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1563 of 1817 sep 19, 2011 table 25-3. v850es/jj3-e interrupt/exception sources (5/5) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 84 intcf5t/ intuc6t csif5 consecutive transmission write enable/ uartc6 consecutive transmission write enable csif5/ uartc6 05c0h 000005c0h ne xtpc cf5tic/ uc6tic 85 intcf6r/ intuc7r csif6 reception completion/ csif6 reception error/ uartc7 reception completion/ uartc7 reception error csif6/ uartc7 05d0h 000005d0h ne xtpc cf6ric/ uc7ric 86 intcf6t/ intuc7t csif6 consecutive transmission write enable/ uartc7 consecutive transmission write enable csif6/ uartc7 05e0h 000005e0h nextpc cf6tic/ uc7tic 87 intuc2r/ intiic2 uartc2 reception completion/ uartc2 reception error/ iic2 transfer completion uartc2/ iic2 05f0h 000005f0h nextpc uc2ric/ iicic2 88 intuc2t uartc2 consecutive transmission write enable uartc2 0600h 00000600h nextpc uc2tic 89 intiic4 iic4 transfer completi on iic4 0610h 00000610h nextpc iicic4 90 intad a/d conversion completi on a/d 0620h 00000620h nextpc adic 91 intdma0 dma0 transfer completi on dma 0630h 00000630h nextpc dmaic0 92 intdma1 dma1 transfer completi on dma 0640h 00000640h nextpc dmaic1 93 intdma2 dma2 transfer completi on dma 0650h 00000650h nextpc dmaic2 94 intdma3 dma3 transfer completi on dma 0660h 00000660h nextpc dmaic3 95 intkr key return interrupt kr 0670h 00000670h nextpc kric 96 intrtc0 rtc constant cycle signal rtc 0680h 00000680h nextpc rtc0ic 97 intrtc1 rtc alarm match rt c 0690h 00000690h nextpc rtc1ic 98 intrtc2 rtc interval signal rt c 06a0h 000006a0h nextpc rtc2ic 99 intusbf0 usbf inte rrupt usbf 06b0h 000 006b0h nextpc ufic0 100 intusbf1 usbf resume interrupt usbf 06c0h 000006c0h nextpc ufic1 101 intetmrx packet reception etherne t 06d0h 000006d0h nextpc etmrxic 102 intetmtx packet transmission etherne t 06e0h 000006e0h nextpc etmtxic 103 intetmrq reception packet read request ethernet 06f0h 000006f0h nextpc etmrqic 104 intetmfs fifo status ether net 0700h 00000700h nextpc etmfsic 105 intetmts transmission status et hernet 0710h 00000710h nextpc etmtsic 106 intetmrs reception status et hernet 0720h 00000720h nextpc etmrsic 107 intetmov statistics count er overflow ethernet 0730h 00000730h nextpc etmovic 108 intetber error interrupt ether net 0740h 00000740h ne xtpc etberic 110 intc0err note can0 error note can0 0760h 00000760h nextpc erric0 note 111 intc0wup1 note can0 wakeup note can0 0770h 00000770h nextpc wupic0 note 112 intc0rec note can0 reception note can0 0780h 00000780h nextpc recic0 note maskable interrupt 113 intc0trx note can0 transmission note can0 0790h 00000790h nextpc trxic0 note note pd70f3786 only v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1564 of 1817 sep 19, 2011 remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. the priority order of non-maskable interrupt is intwdt2 > nmi. restored pc: the value of the program counter (pc) saved to eipc, fepc, or dbpc when interrupt servicing is started. note, however, t hat the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the proc essing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4). v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1565 of 1817 sep 19, 2011 25.2 non-maskable interrupts a non-maskable interrupt request signal is acknowledged unc onditionally, even when interr upts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupt request signals. this product has the following two non-maskable interrupt request signals. ? nmi pin input (nmi) ? non-maskable interrupt request signal generated by overflow of watchdog timer (intwdt2) the valid edge of the nmi pin can be se lected from four types: ?rising edge?, ?falling edge?, ?both edges?, and ?no edge detection?. the non-maskable interrupt request signal generated by over flow of watchdog timer 2 (intwdt2) functions when the wdtm2.wdm21 and wdtm2.wdm20 bits are set to ?01?. if two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt request signal with the lower priority is ignored). intwdt2 > nmi if a new nmi or intwdt2 request signal is issued while an nmi is being serviced, it is serviced as follows. (1) if new nmi request signal is i ssued while nmi is being serviced the new nmi request signal is held pending, regardless of the value of the psw.np bit. the pending nmi request signal is acknowledged after the nmi currently under exec ution has been serviced (after the reti instruction has been executed). (2) if intwdt2 request signal is issued while nmi is being serviced the intwdt2 request signal is held pending if the np bit remains set (1) while the nmi is being serviced. the pending intwdt2 request signal is acknowledged after the nmi currently under execution has been serviced (after the reti instruction has been executed). if the np bit is cleared (0) while the nmi is being se rviced, the newly generated intwdt2 request signal is executed (the nmi servicing is stopped). caution for the non-maskable interrupt servicing ex ecuted by the non-maskable interrupt request signal (intwdt2), see 25.2.2 (2) from intwdt2 signal. figure 25-1. non-maskable interrupt requ est signal acknowledgment operation (1/2) (a) nmi and intwdt2 request signa ls generated at the same time main routine system reset nmi and intwd t2 requests (generated simultaneously) intwd t2 servicing v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1566 of 1817 sep 19, 2011 figure 25-1. non-maskable interrupt requ est signal acknowledgment operation (2/2) (b) non-maskable interrupt request signal ge nerated during non-maskab le interrupt servicing non-maskable interrupt being serviced non-maskable interrupt request signal generated during non-maskable interrupt servicing nmi intwdt2 nmi ? nmi request generated during nmi servicing ? intwdt2 request generated during nmi servicing (np bit = 1 retained before intwdt2 request) main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request main routine system reset nmi request nmi servicing (held pending) intwdt2 servicing intwdt2 request ? intwdt2 request generated during nmi servicing (np bit = 0 set before intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing intwdt2 request np = 0 ? intwdt2 request generated during nmi servicing (np = 0 set after intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing np = 0 ? intwdt2 request generated during intwdt2 servicing main routine system reset intwdt2 request intwdt2 servicing (invalid) ? nmi request generated during intwdt2 servicing intwdt2 main routine system reset intwdt2 request intwdt2 servicing (invalid) nmi request (held pending) intwdt2 request intwdt2 request v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1567 of 1817 sep 19, 2011 25.2.1 operation if a non-maskable interrupt request signal is generated, t he cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code (0010h, 0020h) to the higher halfword (fecc) of ecr. <4> sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. <5> sets the handler address (00000010h, 00000020h) corr esponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non- maskable interrupt is shown below. figure 25-2. servicing configurat ion of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h, 0020h 1 0 1 00000010h, 00000020h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1568 of 1817 sep 19, 2011 25.2.2 restore (1) from nmi pin input execution is restored from the nmi se rvicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following processing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from fepc and fepsw, respectively, because the psw.ep bit is 0 and the psw.np bit is 1. <2> transfers control back to the address of the restored pc and psw. the processing of the reti in struction is shown below. figure 25-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the ep and np bits are changed by the ldsr instruction duri ng non-maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 0 and the np bit back to 1 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1569 of 1817 sep 19, 2011 (2) from intwdt2 signal restoring from non-maskable interrupt servicing execut ed by the non-maskable interrupt request (intwdt2) by using the reti instruction is disabled. ex ecute the following software reset processing. figure 25-4. software reset processing intwdt2 occurs. fepc software reset processing address fepsw value that sets np bit = 1, ep bit = 0 reti reti 10 times (fepc and fepsw note must be set.) psw psw default value setting initialization processing intwdt2 servicing routine software reset processing routine note fepsw value that sets np bit = 1, ep bit = 0 25.2.3 np flag the np flag is a status flag that indicates that non -maskable interrupt servicing is under execution. this flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. 0 np ep id sat cy ov s z psw no nmi interrupt servicing nmi interrupt currently being serviced np 0 1 nmi interrupt servicing status after reset: 00000020h v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1570 of 1817 sep 19, 2011 25.3 maskable interrupts maskable interrupt request signals can be masked by interrupt control registers. t he v850es/jh3-e and v850es/jj3- e have 98 to 113 maskable interrupt sources. if two or more maskable interrupt request signals are generat ed at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). when an interrupt request signal has been acknowledged, the acknowledgment of othe r maskable interrupt request signals is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt service routine, the interr upt enabled (ei) status is set, which enables servicing of interrupts having a higher priority t han the interrupt request signal in progress (specified by the interrupt control register). note that only interrupts with a higher priority will have this capability; interrupts with the s ame priority level cannot be nested. to enable multiple interrupts, however, save eipc an d eipsw to memory or general-purpose registers before executing the ei instruction, and execute the di instruction bef ore the reti instruction to re store the original values of eipc and eipsw. 25.3.1 operation if a maskable interrupt occurs, the cpu performs the following processing, and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the psw. id bit to 1 and clears the psw. ep bit to 0. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal generated while another interrupt is being serviced (while the psw.np bit = 1 or the psw.id bit = 1) are held pending inside intc. in this case, servicing a new maskable interrupt is started in acco rdance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or the np and id bits are set to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1571 of 1817 sep 19, 2011 figure 25-5. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc acknowledged yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address interrupt requested? note for the ispr register, see 25.3.6 in-service priority register (ispr) . v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1572 of 1817 sep 19, 2011 25.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is executed, t he cpu performs the following processing , and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and eipsw because the psw.ep bit is 0 and the psw.np bit is 0. <2> transfers control back to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 25-6. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 25.3.6 in-service priority register (ispr) . caution when the ep and np bits are changed by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 0 and the np bit back to 0 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1573 of 1817 sep 19, 2011 25.3.3 priorities of maskable interrupts the intc performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are spec ified by the interrupt priority level spec ification bit (xxprn) of the interrupt cont rol register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, see table 25-2 and table 25-3 . the programmable priority control customizes in terrupt request signals into eight levels by setting the priority level specificatio n flag. note that when an interrupt request signal is acknowledged, t he psw.id flag is automatically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (see table 25-4 interrupt control register (xxicn) ) n: peripheral unit number (see table 25-4 interrupt control register (xxicn) ). v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1574 of 1817 sep 19, 2011 figure 25-7. example of processing in which another interrupt request signal is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1575 of 1817 sep 19, 2011 figure 25-7. example of processing in which another interrupt request signal is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1576 of 1817 sep 19, 2011 figure 25-8. example of servicing interrupt request signals simu ltaneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, th e values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1577 of 1817 sep 19, 2011 25.3.4 interrupt control register (xxicn) the xxicn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 47h. caution disable interrupts (di) or mask the interrupt to read the xxicn.xxifn bi t. if the xxifn bit is read while interrupts are enabled (ei) or while the interrupt is unmasked, the correct value may not be read when acknowledging an interrupt and reading the bit conflict. xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff112h to fffff184h <6> <7> note the flag xxlfn is reset automatically by the hardwa re if an interrupt request signal is acknowledged. remark xx: identification name of each peripheral unit (see table 25-4 interrupt control register (xxicn) ) n: peripheral unit number (see table 25-4 interrupt control register (xxicn) ). the addresses and bits of the interrupt control registers are as follows. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1578 of 1817 sep 19, 2011 table 25-4. interrupt control register (xxicn) (1/4) bit address register <7> <6> 5 4 3 2 1 0 fffff110h lviic lviif lvimk 0 0 0 lvipr2 lvipr1 lvipr0 fffff112h pic00 pif00 pmk 00 0 0 0 ppr002 ppr001 ppr000 fffff114h pic01 pif01 pmk 01 0 0 0 ppr012 ppr011 ppr010 fffff116h pic02 pif02 pmk 02 0 0 0 ppr022 ppr021 ppr020 fffff118h pic03 pif03 pmk 03 0 0 0 ppr032 ppr031 ppr030 fffff11ah pic04 pif04 pmk04 0 0 0 ppr042 ppr041 ppr040 fffff11ch pic05 pif05 pmk05 0 0 0 ppr052 ppr051 ppr050 fffff11eh pic06 pif06 pmk06 0 0 0 ppr062 ppr061 ppr060 fffff120h pic07 pif07 pmk 07 0 0 0 ppr072 ppr071 ppr070 fffff122h pic08 pif08 pmk 08 0 0 0 ppr082 ppr081 ppr080 fffff124h pic09 pif09 pmk 09 0 0 0 ppr092 ppr091 ppr090 fffff126h pic10 pif10 pmk 10 0 0 0 ppr102 ppr101 ppr100 fffff128h pic11 pif11 pmk 11 0 0 0 ppr112 ppr111 ppr110 fffff12ah pic12 pif12 pmk12 0 0 0 ppr122 ppr121 ppr120 fffff12ch pic13 pif13 pmk13 0 0 0 ppr132 ppr131 ppr130 fffff12eh pic14 pif14 pmk14 0 0 0 ppr142 ppr141 ppr140 fffff130h pic15 pif15 pmk 15 0 0 0 ppr152 ppr151 ppr150 fffff132h pic16 pif16 pmk 16 0 0 0 ppr162 ppr161 ppr160 fffff134h pic17 pif17 pmk 17 0 0 0 ppr172 ppr171 ppr170 fffff136h pic18 pif18 pmk 18 0 0 0 ppr182 ppr181 ppr180 fffff138h pic19 pif19 pmk 19 0 0 0 ppr192 ppr191 ppr190 fffff13ah pic20 pif20 pmk20 0 0 0 ppr202 ppr201 ppr200 fffff13ch pic21 note pif21 pmk21 0 0 0 ppr212 ppr211 ppr210 fffff13eh pic22 note pif22 pmk22 0 0 0 ppr222 ppr221 ppr220 fffff140h pic23 note pif23 pmk23 0 0 0 ppr232 ppr231 ppr230 fffff142h pic24 note pif24 pmk24 0 0 0 ppr242 ppr241 ppr240 fffff144h pic25 note pif25 pmk25 0 0 0 ppr252 ppr251 ppr250 fffff146h tab0ovic tab0ovif tab0ovmk 0 0 0 tab0ovpr2 tab0ovpr1 tab0ovpr0 fffff148h tab0ccic0 tab0ccif0 tab0ccmk 0 0 0 0 tab0ccpr02 tab0ccpr01 tab0ccpr00 fffff14ah tab0ccic1 tab0ccif1 tab0ccmk 1 0 0 0 tab0ccpr12 tab0ccpr11 tab0ccpr10 fffff14ch tab0ccic2 tab0ccif2 tab0ccmk 2 0 0 0 tab0ccpr22 tab0ccpr21 tab0ccpr20 fffff14eh tab0ccic3 tab0ccif3 tab0ccmk 3 0 0 0 tab0ccpr32 tab0ccpr31 tab0ccpr30 fffff150h tab1ovic tab1ovif tab1ovmk 0 0 0 tab1ovpr2 tab1ovpr1 tab1ovpr0 fffff152h tab1ccic0 tab1ccif0 tab1ccmk 0 0 0 0 tab1ccpr02 tab1ccpr01 tab1ccpr00 fffff154h tab1ccic1 tab1ccif1 tab1ccmk 1 0 0 0 tab1ccpr12 tab1ccpr11 tab1ccpr10 fffff156h tab1ccic2 tab1ccif2 tab1ccmk 2 0 0 0 tab1ccpr22 tab1ccpr21 tab1ccpr20 fffff158h tab1ccic3 tab1ccif3 tab1ccmk 3 0 0 0 tab1ccpr32 tab1ccpr31 tab1ccpr30 fffff15ah tt0ovic tt0ovif tt0ovmk 0 0 0 tt0ovpr2 tt0ovpr1 tt0ovpr0 fffff15ch tt0ccic0 tt0ccif0 tt0ccmk0 0 0 0 tt0ccpr02 tt0ccpr01 tt0ccpr00 fffff15eh tt0ccic1 tt0ccif1 tt0ccmk1 0 0 0 tt0ccpr12 tt0ccpr11 tt0ccpr10 fffff160h tt0iecic tt0iecif tt0iecmk 0 0 0 tt0iecpr2 tt0iecpr1 tt0iecpr0 fffff162h taa0ovic taa0ovif taa0ovmk 0 0 0 taa0ovpr2 taa0ovpr1 taa0ovpr0 note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1579 of 1817 sep 19, 2011 table 25-4. interrupt control register (xxicn) (2/4) bit address register <7> <6> 5 4 3 2 1 0 fffff164h taa0ccic0 taa0ccif0 taa0ccmk0 0 0 0 taa0ccpr02 taa0ccpr01 taa0ccpr00 fffff166h taa0ccic1 taa0ccif1 taa0ccmk1 0 0 0 taa0ccpr12 taa0ccpr11 taa0ccpr10 fffff168h taa1ovic taa1ovif taa1ovmk 0 0 0 taa1ovpr2 taa1ovpr1 taa1ovpr0 fffff16ah taa1ccic0 taa1ccif0 taa1ccmk0 0 0 0 taa1ccpr02 taa1ccpr01 taa1ccpr00 fffff16ch taa1ccic1 taa1ccif1 taa1ccmk1 0 0 0 taa1ccpr12 taa1ccpr11 taa1ccpr10 fffff16eh taa2ovic taa2ovif taa2ovmk 0 0 0 taa2ovpr2 taa2ovpr1 taa2ovpr0 fffff170h taa2ccic0 taa2ccif0 taa2ccmk0 0 0 0 taa2ccpr02 taa2ccpr01 taa2ccpr00 fffff172h taa2ccic1 taa2ccif1 taa2ccmk1 0 0 0 taa2ccpr12 taa2ccpr11 taa2ccpr10 fffff174h taa3ovic taa3ovif taa3ovmk 0 0 0 taa3ovpr2 taa3ovpr1 taa3ovpr0 fffff176h taa3ccic0 taa3ccif0 taa3ccmk0 0 0 0 taa3ccpr02 taa3ccpr01 taa3ccpr00 fffff178h taa3ccic1 taa3ccif1 taa3ccmk1 0 0 0 taa3ccpr12 taa3ccpr11 taa3ccpr10 fffff17ah taa4ovic taa4ovif taa4ovmk 0 0 0 taa4ovpr2 taa4ovpr1 taa4ovpr0 fffff17ch taa4ccic0 taa4ccif0 taa4ccmk0 0 0 0 taa4ccpr02 taa4ccpr01 taa4ccpr00 fffff17eh taa4ccic1 taa4ccif1 taa4ccmk1 0 0 0 taa4ccpr12 taa4ccpr11 taa4ccpr10 fffff180h taa5ovic taa5ovif taa5ovmk 0 0 0 taa5ovpr2 taa5ovpr1 taa5ovpr0 fffff182h taa5ccic0 taa5ccif0 taa5ccmk0 0 0 0 taa5ccpr02 taa5ccpr01 taa5ccpr00 fffff184h taa5ccic1 taa5ccif1 taa5ccmk1 0 0 0 taa5ccpr12 taa5ccpr11 taa5ccpr10 fffff186h tm0eqic0 tm0eqif0 tm0eqmk0 0 0 0 tm0eqpr02 tm0eqpr01 tm0eqpr00 fffff188h tm1eqic0 tm1eqif0 tm1eqmk0 0 0 0 tm1eqpr02 tm1eqpr01 tm1eqpr00 fffff18ah tm2eqic0 tm2eqif0 tm2eqmk0 0 0 0 tm2eqpr02 tm2eqpr01 tm2eqpr00 fffff18ch tm3eqic0 tm3eqif0 tm3eqmk0 0 0 0 tm3eqpr02 tm3eqpr01 tm3eqpr00 fffff18eh ce0tic/ uc4ric ce0tif/ uc4rif ce0tmk/ uc4rmk 000ce0tpr2/ uc4rpr2 ce0tpr1/ uc4rpr1 ce0tpr0/ uc4rpr0 fffff190h ce0tiofic/ uc4tic ce0tiofif/ uc4tif ce0tiofmk/ uc4tmk 0 0 0 ce0tiofpr2/ uc4tpr2 ce0tiofpr1/ uc4tpr1 ce0tiofpr0/ uc4tpr0 fffff192h ce1tic/ uc5ric/ iicic3 ce1tif/ uc5rif/ iicif3 ce1tmk/ uc5rmk/ iicmk3 000ce1tpr2/ uc5rpr2/ iicpr32 ce1tpr1/ uc5rpr1/ iicpr31 ce1tpr0/ uc5rpr0/ iicpr30 fffff194h ce1tiofic/ uc5tic ce1tiofif/ uc5tif ce1tiofmk/ uc5tmk 0 0 0 ce1tiofpr2/ uc5tpr2 ce1tiofpr1/ uc5tpr1 ce1tiofpr0/ uc5tpr0 fffff196h cf0ric/ uc3ric/ iicic1 cf0rif/ uc3rif/ iicif1 cf0rmk/ uc3rmk/ iicmk1 000cf0rpr2/ uc3rpr2/ iicpr12 cf0rpr1/ uc3rpr1/ iicpr11 cf0rpr0/ uc3rpr0/ iicpr10 fffff198h cf0tic/ uc3tic cf0tif/ uc3tif cf0tmk/ uc3tmk 0 0 0 cf0tpr2/ uc3tpr2 cf0tpr1/ uc3tpr1 cf0tpr0/ uc3tpr0 fffff19ah cf1ric/ uc1ric/ iicic0 cf1rif/ uc1rif/ iicif0 cf1rmk/ uc1rmk/ iicmk0 000cf1rpr2/ uc1rpr2/ iicpr02 cf1rpr1/ uc1rpr1/ iicpr01 cf1rpr0/ uc1rpr0/ iicpr00 fffff19ch cf1tic/ uc1tic cf1tif/ uc1tif cf1tmk/ uc1tmk 0 0 0 cf1tpr2/ uc1tpr2 cf1tpr1/ uc1tpr1 cf1tpr0/ uc1tpr0 fffff19eh cf2ric/ uc0ric cf2rif/ uc0rif cf2rmk/ uc0rmk 000cf2rpr2/ uc0rpr2 cf2rpr1/ uc0rpr1 cf2rpr0/ uc0rpr0 v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1580 of 1817 sep 19, 2011 table 25-4. interrupt control register (xxicn) (3/4) bit address register <7> <6> 5 4 3 2 1 0 fffff1a0h cf2tic/ uc0tic cf2tif/ uc0tif cf2tmk/ uc0tmk 0 0 0 cf2tpr2/ uc0tpr2 cf2tpr1/ uc0tpr1 cf2tpr0/ uc0tpr0 fffff1a2h cf3ric/ ub1tiric cf3rif/ ub1tirif cf3rmk/ ub1tirmk 000cf3rpr2/ ub1tirpr2 cf3rpr1/ ub1tirpr1 cf3rpr0/ ub1tirpr0 fffff1a4h cf3tic/ ub1titic cf3tif/ ub1titif cf3tmk/ ub1titmk 0 0 0 cf3tpr2/ ub1titpr2 cf3tpr1/ ub1titpr1 cf3tpr0/ ub1titpr0 fffff1a6h ub1tific ub1tifif ub1tifmk 0 0 0 ub1tifpr2 ub1tifpr1 ub1tifpr0 fffff1a8h ub1tireic ub1tireif ub1tiremk 0 0 0 ub1tirepr2 ub1tirepr1 ub1tirepr0 fffff1aah ub1titoic ub1titoif ub1titomk 0 0 0 ub1titopr2 ub1titopr1 ub1titopr0 fffff1ach cf4ric/ ub0tiric cf4rif/ ub0tirif cf4rmk/ ub0tirmk 000cf4rpr2/ ub0tirpr2 cf4rpr1/ ub0tirpr1 cf4rpr0/ ub0tirpr0 fffff1aeh cf4tic/ ub0titic cf4tif/ ub0titif cf4tmk/ ub0titmk 0 0 0 cf4tpr2/ ub0titpr2 cf4tpr1/ ub0titpr1 cf4tpr0/ ub0titpr0 fffff1b0h ub0tific ub0tifif ub0tifmk 0 0 0 ub0tifpr2 ub0tifpr1 ub0tifpr0 fffff1b2h ub0tireic ub0tireif ub0tiremk 0 0 0 ub0tirepr2 ub0tirepr1 ub0tirepr0 fffff1b4h ub0titoic ub0titoif ub0titomk 0 0 0 ub0titopr2 ub0titopr1 ub0titopr0 fffff1b6h cf5ric/ uc6ric note cf5rif/ uc6rif cf5rmk/ uc6rmk 000cf5rpr2/ uc6rpr2 cf5rpr1/ uc6rpr1 cf5rpr0/ uc6rpr0 fffff1b8h cf5tic/ uc6tic note cf5tif/ uc6tif cf5tmk/ uc6tmk 0 0 0 cf5tpr2/ uc6tpr2 cf5tpr1/ uc6tpr1 cf5tpr0/ uc6tpr0 fffff1bah cf6ric/ uc7ric note cf6rif/ uc7rif cf6rmk/ uc7rmk 000cf6rpr2/ uc7rpr2 cf6rpr1/ uc7rpr1 cf6rpr0/ uc7rpr0 fffff1bch cf6tic/ uc7tic note cf6tif/ uc7tif cf6tmk/ uc7tmk 0 0 0 cf6tpr2/ uc7tpr2 cf6tpr1/ uc7tpr1 cf6tpr0/ uc7tpr0 fffff1beh uc2ric/ iicic2 uc2rif/ iicif2 uc2rmk/ iicmk2 0 0 0 uc2rpr2/ iicpr22 uc2rpr1/ iicpr21 uc2rpr0/ iicpr20 fffff1c0h uc2tic uc2tif uc2tmk 0 0 0 uc2tpr2 uc2tpr1 uc2tpr0 fffff1c2h iicic4 note iicif4 iicmk4 0 0 0 iicpr42 iicpr41 iicpr40 fffff1c4h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff1c6h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff1c8h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff1cah dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff1cch dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff1ceh kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff1d0h rtc0ic rtc0if rtc0mk 0 0 0 rtc0pr2 rtc0pr1 rtc0pr0 fffff1d2h rtc1ic rtc1if rtc1mk 0 0 0 rtc1pr2 rtc1pr1 rtc1pr0 fffff1d4h rtc2ic rtc2if rtc2mk 0 0 0 rtc2pr2 rtc2pr1 rtc2pr0 fffff1d6h ufic0 ufif0 ufmk0 0 0 0 ufpr02 ufpr01 ufpr00 fffff1d8h ufic1 ufif1 ufmk1 0 0 0 ufpr12 ufpr11 ufpr10 fffff1dah etmrxic etmrxif etmrxmk 0 0 0 etmrxpr2 etmrxpr1 etmrxpr0 fffff1dch etmtxic etmtxif etmtxmk 0 0 0 etmtxpr2 etmtxpr1 etmtxpr0 fffff1deh etmrqic etmrqif etmrqmk 0 0 0 etmrqpr2 etmrqpr1 etmrqpr0 note v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1581 of 1817 sep 19, 2011 table 25-4. interrupt control register (xxicn) (4/4) bit address register <7> <6> 5 4 3 2 1 0 fffff1e0h etmfsic etmfsif etmfsmk 0 0 0 etmfspr2 etmfspr1 etmfspr0 fffff1e2h etmtsic etmtsif etmtsmk 0 0 0 etmtspr2 etmtspr1 etmtspr0 fffff1e4h etmrsic etmrsif etmrsmk 0 0 0 etmrspr2 etmrspr1 etmrspr0 fffff1e6h etmovic etmovif etmovmk 0 0 0 etmovpr2 etmovpr1 etmovpr0 fffff1e8h etberic etberif etbermk 0 0 0 etberpr2 et berpr1 etberpr0 fffff1ech erric0 note errif0 errmk0 0 0 0 errpr02 errpr01 errpr00 fffff1eeh wupic0 note wupif0 wupmk0 0 0 0 w uppr02 wuppr01 wuppr00 fffff1f0h recic0 note recif0 recmk0 0 0 0 recpr02 recpr01 recpr00 fffff1f2h trxic0 note trxif0 trxmk0 0 0 0 t rxpr02 trxpr01 trxpr00 note pd70f3783, 70f3786 only v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1582 of 1817 sep 19, 2011 25.3.5 interrupt mask register s 0 to 7 (imr0 to imr7) the imr0 to imr5 registers set the in terrupt mask state for the maskable interr upts. the xxmkn bit of the imr0 to imr7 registers is equivalent to the xxicn.xxmkn bit. the imrm register can be read or written in 16-bit units. if the higher 8 bits of the imrm regi ster are used as an imrmh register and th e lower 8 bits as an imrml register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 7). reset sets these registers to ffffh. caution the device file defines the xxicn.xxmkn bit as a reser ved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). (1/2) after reset: ffffh r/w address: imr4 fffff108h, after reset: ffffh r/w address: imr5 fffff10ah, cf4tmk/ ub0titmk imr4 (imr4h note 2 ) cf4rmk/ ub0tirmk ub1tiremk cf3tmk/ ub1titmk cf3rmk/ ub1tirmk krmk ub0tifmk imr5 (imr5h note 2 ) dmamk3 dmamk1 cf5rmk/ uc6rmk note 3 ub0titomk admk dmamk2 dmamk0 iicmk4 note 3 ub0tiremk imr5l imr4l 8 9 10 11 12 13 14 15 1 ce1tmk/ uc5rmk/ iicmk3 2 3 4 5 6 7 0 8 9 10 11 12 14 13 15 1 2 3 4 5 6 7 0 imr5l fffff10ah, imr5h fffff10bh imr4l fffff108h, imr4h fffff109h cf2tmk/ uc0tmk cf0tmk/ uc3tmk cf6rmk/ uc7rmk note 3 cf6tmk/ uc7tmk note 3 uc2rmk/ iicmk2 uc2tmk ce1ti0fmk/ uc5tmk ce0ti0fmk/ uc4tmk cf0rmk/ uc3rmk/ iicmk1 cf1rmk/ uc1rmk/ iicmk0 cf1tmk/ uc1tmk cf2rmk/ uc0rmk ub1titomk ub1tifmk cf5tmk/ uc6tmk note 3 imr6 (imr6h note 2 ) after reset: ffffh r/w address: imr6 fffff10ch, after reset: 1fh r/w address: fffff10eh recmk0 note 1 imr7l 11 trxmk0 note 1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 imr6l 1 2 3 4 5 6 7 0 imr6l fffff10ch, imr6h fffff10dh rtc0mk etmfsmk 0 0 01 wupmk0 note 1 errmk0 note 1 etphymk etbermk etmovmk etmrsmk etmtsmk etmrqmk etmtxmk etmrxmk ufmk1 ufmk0 rtc2mk rtc1mk notes 1. pd70f3783, 70f3786 only 2. to read bits 8 to 15 of the imr6 to imr4 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of imr6h to imr4h registers. 3. v850es/jj3-e only cautions 1. set bits 7 to 5 of the imr7 register to ?0? and bits 4 to 2 to ?1?. if the setting of these bits is changed, the operati on is not guaranteed. 2. do not read or write the imr7 register in 16-bit units. remark xx: identification name of each peripheral unit (see table 25-4 interrupt control register (xxicn) ). n: peripheral unit number (see table 25-4 interrupt control register (xxicn) ) v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1583 of 1817 sep 19, 2011 (2/2) pmk14 pmk06 imr0 (imr0h note 1 ) pmk13 pmk05 pmk12 pmk04 pmk11 pmk03 pmk10 pmk02 pmk09 pmk01 pmk08 pmk00 pmk07 lvimk after reset: ffffh r/w address: imr0 fffff100h, after reset: ffffh r/w address: imr1 fffff102h, after reset: ffffh r/w address: imr2 fffff104h, tab0ccmk3 pmk22 note 2 imr1 (imr1h note 1 ) tab0ccmk2 pmk21 note 2 tab0ccmk1 pmk20 tab0ccmk0 pmk19 tab0ovmk pmk18 pmk25 note 2 pmk17 pmk24 note 2 pmk16 pmk23 note 2 pmk15 taa2ovmk tt0ccmk1 tt0iecmk tab1ovmk xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled imr2 (imr2h note 1 ) taa1ccmk1 tt0ccmk0 tt0ovmk taa1ovmk tab1ccmk3 tab1ccmk2 tab1ccmk1 taa0ccmk0 taa1ccmk0 taa0ccmk1 taa0ovmk tab1ccmk0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 imr2l imr1l imr0l 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 setting of interrupt mask flag 14 13 15 1 2 3 4 5 6 7 0 imr2l fffff104h, imr2h fffff105h imr1l fffff102h, imr1h fffff103h imr0l fffff100h, imr0h fffff101h ce0tmk/ uc4rmk taa4ccmk1 imr3 (imr3h note 1 ) tm3eqmk0 taa4ccmk0 tm2eqmk0 taa4ovmk tm1eqmk0 taa3ccmk1 tm0eqmk0 taa3ccmk0 taa5ccmk1 taa3ovmk taa5ccmk0 taa2ccmk1 after reset: ffffh r/w address: imr3 fffff106h, 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 imr3l imr3l fffff106h, imr3h fffff107h taa2ccmk0 aa5ovmk notes 1. to read bits 8 to 15 of the imr0 to imr3 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of imr0h to imr3h registers. 2. v850es/jj3-e only remark xx: identification name of each peripheral unit (see table 25-4 interrupt control register (xxicn) ). n: peripheral unit number (see table 25-4 interrupt control register (xxicn) ) v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1584 of 1817 sep 19, 2011 25.3.6 in-service priority register (ispr) the ispr register holds the priority level of the maskable interrupt currentl y acknowledged. when an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that in terrupt request signal is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, t he bit corresponding to the interrupt request signal having the highest priority is automatically reset to 0 by hardware. ho wever, it is not reset to 0 when execut ion is returned from non-maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after the bits of the register have been set by acknowledging the interrupt may be read. to accurately read the valu e of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di). ispr7 interrupt request signal with priority n not acknowledged interrupt request signal with priority n acknowledged isprn 0 1 priority of interrupt currently acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah <7> <6> <5> <4> <3> <2> <1> <0> remark n = 0 to 7 (priority level) v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1585 of 1817 sep 19, 2011 25.3.7 id flag this flag controls the maskable interrupt?s operating stat e, and stores control information regarding enabling or disabling of interrupt request signals. an inte rrupt disable flag (id) is assigned to the psw. reset sets this flag to 00000020h. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled id 0 1 specification of maskable interrupt servicing note after reset: 00000020h note interrupt disable flag (id) function this bit is set to 1 by the di instruction and cleared to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instru ction when referencing the psw. non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. when a maskable interrupt request signal is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request signal generated during the acknowledgment disabled period (id flag = 1) is acknowledged when the xxicn.xxifn bit is set to 1, and the id flag is cleared to 0. 25.3.8 watchdog timer mode register 2 (wdtm2) this register can be read or writt en in 8-bit units (for details, see chapter 13 functions of watchdog timer 2 ). reset sets this register to 67h. 0 wdtm2 wdm21 wdm20 0 0 0 0 0 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode reset mode (initial value) wdm21 0 0 1 wdm20 0 1 selection of watchdog timer operation mode v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1586 of 1817 sep 19, 2011 25.4 software exception a software exception is generated when the cpu executes the trap instructi on, and can always be acknowledged. 25.4.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1. <5> sets the handler address (00000040h or 00000050h) corresponding to the software exception to the pc, and transfers control. the processing of a software exception is shown below. figure 25-9. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (t he vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if t he vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1587 of 1817 sep 19, 2011 25.4.2 restore restoration from software exception processing is carried out by the reti instruction. by executing the reti instruct ion, the cpu carries out the following processi ng and shifts control to the restored pc?s address. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 25-10. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the ep and np bits are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set the ep bit back to 1 and the np bit back to 0 using the ldsr instruction immediately befo re the reti instruction. remark the solid line shows the cpu processing flow. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1588 of 1817 sep 19, 2011 25.4.3 ep flag the ep flag is a status flag used to indi cate that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress. exception processing in progress. ep 0 1 exception processing status after reset: 00000020h v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1589 of 1817 sep 19, 2011 25.5 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850es/jh3-e and v850es/jj3-e, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 25.5.1 illegal opcode an illegal opcode is defined as an instruction with instruct ion opcode (bits 10 to 5) = 111111b, sub-opcode (bits 26 to 23) = 0111b to 1111b, and sub-opcode (bit 16) = 0b. when su ch an instruction is exec uted, an exception trap is generated. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution it is recommended not to u se an illegal opcode because instruct ions may newly be assigned in the future. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. the processing of the exc eption trap is shown below. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1590 of 1817 sep 19, 2011 figure 25-11. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restoration restoration from an exception trap is ca rried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. caution dbpc and dbpsw can be accessed only during th e interval between the execution of an illegal opcode and dbret instruction. processing for restoring from an exception trap is shown below. figure 25-12. processing for restoring from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1591 of 1817 sep 19, 2011 25.5.2 debug trap a debug trap is an exception that is generated when the db trap instruction is executed and is always acknowledged. (1) operation upon occurrence of a debug trap, the cpu performs the following processing. <1> saves restored pc to dbpc. <2> saves current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets handler address (00000060h) for debug trap to pc and transfers control. the debug trap processing format is shown below. figure 25-13. debug trap processing format dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1592 of 1817 sep 19, 2011 (2) restoration restoration from a debug trap is exec uted with the dbret instruction. with the dbret instruction, the cpu performs the follo wing steps and transfers cont rol to the address of the restored pc. <1> the restored pc and psw are read from dbpc and dbpsw. <2> control is transferred to the fetc hed address of the restored pc and psw. caution dbpc and dbpsw can be accessed only duri ng the interval between the execution of the dbtrap instruction and dbret instruction. the processing format for restoration from a debug trap is shown below. figure 25-14. processing format of restoration from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1593 of 1817 sep 19, 2011 25.6 external interrupt request input pins (nmi and intp00 to intp25) 25.6.1 noise elimination (1) eliminating noise on nmi pin the nmi pin has an internal noise eliminat ion circuit that uses analog delay. therefore, the input level of the nmi pin is not detected as an edge unless it is maintained for a specific time or longer. therefore, an edge is detected after specific time. the nmi pin can be used to release the stop mode. in the stop mode, noise is not eliminated by using the system clock because the internal system clock is stopped. (2) eliminating noise on intp00 to intp25 pins the intp00 to intp25 pins have an internal noise eliminati on circuit that uses analog de lay. therefore, the input level of the nmi pin is not detected as an edge unless it is maintained for a specific time or longer. therefore, an edge is detected after specific time. (3) eliminating noise on intp02 the intp02 pin has an internal noise elimination circuit that uses analog delay and an internal digital noise elimination circuit. either can be selected by using the noise elimination contro l register (intnfc) (see 25.6.2 (7) ). 25.6.2 edge detection the valid edge of each of the nmi and intp00 to intp 25 pins can be selected from the following four. ? rising edge ? falling edge ? both rising and falling edges ? no edge detected the edge of the nmi pin is not detected after reset. therefore, the interr upt request signal is not acknowledged unless a valid edge is enabled by using the intf0 and intr0 re gister (the nmi pin functions as a normal port pin). remark intp21 to intp25: v850es/jj3-e only v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1594 of 1817 sep 19, 2011 (1) external interrupt fallin g, rising edge specification register 0 (intf0, intr0) the intf0 and intr0 registers are 8-bi t registers that specify detection of the falling and rising edges of the nmi pin via bit 2 and the external interrupt pin (intp00) via bit 3. these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the external interrupt functi on (alternate function) to the port function, an edge may be detected. therefore, set the intf0n and intr0n bits to 00, and then set the port mode. 0 intf0 0 0 0 intf03 intf02 nmi 00 after reset: 00h r/w address: intf0 fffffc00h, intr0 fffffc20h 0 intr0 0 0 0 intr03 intr02 0 0 intp00 nmi intp00 76543210 76543210 remark for how to specify a valid edge, see table 25-5 . table 25-5. valid edge specification intf0n intr0n valid edge specification (n = 2, 3) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to set the intf0n and intr0n bits to 00 when these register s are not used as the nmi and intp00 pins. remark n = 2: control of the nmi pin n = 3: control of the intp00 pin v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1595 of 1817 sep 19, 2011 (2) external interrupt fallin g, rising edge specification register 2 (intf2, intr2) the intf2 and intr2 registers are 8-bit r egisters in which bits 0, 2 to 4, 6, and 7 are used to specify detection of the falling and rising edges of the external interrupt pins (intp01 to intp05 and intp21). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the external interrupt functi on (alternate function) to the port function, an edge may be detected. therefore, set the intf2n and intr2n bits to 00, and then set the port mode. intf27 note intf2 intf26 0 intf24 intf23 intf22 0 intf20 after reset: 00h r/w address: intf2 fffffc04h, intr2 fffffc24h intr27 note intr2 intr26 0 intr24 intr23 intr22 0 intr20 intp04 intp03 intp02 intp01 intp05 intp21 note intp04 intp03 intp02 intp01 intp05 intp21 note 76543210 76543210 note v850es/jj3-e only remark for how to specify a valid edge, see table 25-6 . table 25-6. valid edge specification intf3n intr3n valid edge specification (n = 0, 2 to 4, 6, 7) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to set the intf 2n and intr2n bits to 00 when these registers are not used as the intp01 to intp05 and intp21 pins. remark n = 0: control of intp01 pin n = 2 to 4: control of intp02 to intp04 pins n = 6: control of intp05 pin n = 7: control of intp21 pin v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1596 of 1817 sep 19, 2011 (3) external interrupt fallin g, rising edge specification register 3 (intf3, intr3) the intf3 and intr3 registers are 8-bit registers in which bi t 5 is used to specify detection of the falling and rising edges of the external interrupt pin (intp06). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the external interrupt functi on (alternate function) to the port function, an edge may be detected. therefore, set the intf35 and intr35 bits to 00, and then set the port mode. 0 intf3 0 intf35 0 0 0 0 0 after reset: 00h r/w address: intf3 fffffc06h, intr3 fffffc26h 0 intr3 0 intr35 0 0 0 0 0 intp06 intp06 76543210 76543210 remark for how to specify a valid edge, see table 25-7 . table 25-7. valid edge specification intf35 intr35 valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to set the intf35 and intr35 bits to 00 when these regist ers are not used as the intp06 pin. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1597 of 1817 sep 19, 2011 (4) external interrupt falling, rising edge specification registers 4 (intf4, intr4) (v850es/jj3-e only) the intf4 and intr4 registers are 8-bit registers in which bi t 0 is used to specify detection of the falling and rising edges of the external interrupt pin (intp22). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 00h. caution when the function is changed from the external interrupt functi on (alternate function) to the port function, an edge may be detected. therefore, set the intf48 and intr48 bits to 00, and then set the port mode. 0 intf4 000000 intf48 after reset: 00h r/w address: intf4 fffffc08h, intr4 fffffc28h 0 intr4 000000 intr48 intp22 intp22 76543210 76543210 remark for the valid edge specification combinations, see table 25-8 . table 25-8. valid edge specification intf48 intr48 valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to set the intf48 and intr48 bits to 00 if the corresponding pin is not used as the intp22 pin. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1598 of 1817 sep 19, 2011 (5) external interrupt fallin g, rising edge specification registers 5 (intf5, intr5) the intf5 and intr5 registers are 16-bit or 8-bit registers in which bits 0 to 6 and 9 are used to specify detection of the falling and rising edges of the external interrupt pins (intp07 to intp11 and intp23 to intp25). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 0000h/00h. caution when the function is changed from the external interrupt functi on (alternate function) to the port function, an edge may be detected. therefore, set the intf5n and intr5n bits to 00, and then set the port mode. 0 intf5 (intf5h note 1 ) 00000 intf59 note 2 0 after reset: 0000h r/w address: intf5 fffffc0ah, intf5l fffffc0ah, intf5h fffffc0bh 0 (intf5l) intf56 note 2 intf55 note 2 intf54 intf53 intf52 intf51 intf50 intp25 note 2 intp24 note 2 intp23 note 2 intp11 intp10 intp9 intp8 intp7 15 14 13 12 11 10 9 8 76543210 0 intr5 (intr5h note 1 ) 00000 intr59 note 2 0 after reset: 0000h r/w address: intr5 fffffc2ah, intr5l fffffc2ah, intr5h fffffc2bh 0 (intr5l) intr56 note 2 intr55 note 2 intr54 intr53 intr52 intr51 intr50 intp25 note 2 intp24 note 2 intp23 note 2 intp11 intp10 intp9 intp8 intp7 15 14 13 12 11 10 9 8 76543210 notes 1. to read or write bits 8 to 15 of the intf5 and intr5 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of the intf5h and intr5h registers. 2. v850es/jj3-e only remark for the valid edge specification combinations, see table 25-9 . table 25-9. valid edge specification intf5n intr5n valid edge specification (n = 0 to 6, 9) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to set the intf5 n and intr5n bits to 00 if the corresponding pin is not used as the intp07 to intp11 and intp23 to intp25 pins. remark n = 0 to 6: control of the intp07 to intp11, intp23, and intp24 pins n = 9: control of the intp25 pin v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1599 of 1817 sep 19, 2011 (6) external interrupt fallin g, rising edge specification register 9 (intf9, intr9) the intf9h and intr9h registers are 16-bit or 8-bit register s in which bits 0, 2 to 5, 8, and 12 to 14 are used to specify detection of the falling and rising edges of the external interrupt pins (intp12 to intp20). these registers can be read or written in 8-bit or 1-bit units. reset sets these registers to 0000h/00h. caution when the function is changed from the external interrupt functi on (alternate function) to the port function, an edge may be detected. therefore, cl ear the intf9n and intr9n bits to 0, and then set the port mode. 0 intf9 (intf9h note ) intf914 intf913 intf912 0 0 0 intf98 after reset: 0000h r/w address: intf9 fffffc12h, intf9l fffffc12h, intf9h fffffc13h 0 (intf9l) 0 intf95 intf94 intf93 intf92 0 intf90 intp20 intp19 intp18 intp17 intp16 intp15 intp14 intp13 intp12 15 14 13 12 11 10 9 8 76543210 0 intr9 (intr9h note ) intr914 intr913 intr912 0 0 0 intr98 after reset: 0000h r/w address: intr9 fffffc32h, intr9l fffffc32h, intr9h fffffc33h 0 (intr9l) 0 intr95 intr94 intr93 intr92 0 intr90 intp20 intp19 intp18 intp17 intp16 intp15 intp14 intp13 intp12 15 14 13 12 11 10 9 8 76543210 note to read or write bits 8 to 15 of the intf9 and intr9 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of the intf9h and intr9h registers. remark for how to specify a valid edge, see table 25-10 . table 25-10. valid edge specification intf9n intr9n valid edge specification (n = 0, 2 to 5, 8, 12 to 14) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf9n and intr9n bi ts to 00 when these regist ers are not used as the intp12 to intp20 pins. remark n = 0, 2 to 5, 8, 12-14: control of intp12 to intp20 pins v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1600 of 1817 sep 19, 2011 (7) noise elimination control register (intnfc) analog noise elimination and digital noise elimination can be selected for the intp02 pin. the noise elimination settings are performed using the intnfc register. when analog noise elimination is selected, the input level of the pin is detected as an edge by maintaining it for a specific time or longer. when digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, and f xt . sampling is performed 3 times. even when digital noise elimination is selected, using f xt as the sampling clock makes it possible to use the intp02 interrupt request signal to release the idle1, idle2, and stop modes. this register can be read or written in 8-bit units. reset sets this register to 00h. caution after the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital noise eliminator. therefore, if an intp02 valid edge is input within these 3 sampling clocks after the sampling clock has been changed, an interrupt request signal may be generated. therefore, be careful about the following points when using the interrupt and dma functions. ? when using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts after the interrupt request flag (p ic2.pif2 bit) has been cleared. ? when using the dma function (started by in tp02), enable dma after 3 sampling clocks have elapsed. intnfen intnfc 0 0 0 0 intnfc2 intnfc1 intnfc0 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xt (subclock) intnfc2 0 0 0 0 1 1 digital sampling clock setting prohibited intnfc1 0 0 1 1 0 0 intnfc0 0 1 0 1 0 1 after reset: 00h r/w address: fffff728h analog noise elimination (60 ns (typ.)) digital noise elimination intnfen 0 1 settings of intp02 pin noise elimination other than above remarks 1. since sampling is performed 3 times, the reliably eliminated noise width is 2 sampling clocks. 2. in the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input. v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1601 of 1817 sep 19, 2011 25.7 interrupt acknowledge time of cpu except the following cases, the interrupt acknowledge time of the cpu is 4 clo cks minimum. to input interrupt request signals successively, input the next interrupt request sig nal at least 5 clocks after the preceding interrupt. ? in idle1/idle2/stop mode ? when the external bus is accessed ? when interrupt request non-sampling instructions are successively executed (see 25.8 periods in which interrupts are not acknowledged by cpu .) ? when the interrupt control register is accessed figure 25-15. pipeline operation at interr upt request signal acknowledgment (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clocks (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clocks remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt acknowledge time (internal system clock) internal interrupt external interrupt condition minimum 4 4 + analog delay time maximum 6 6 + analog delay time the following cases are exceptions. ? in idle1/idle2/stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register v850es/jh3-e, v850es/jj3-e chapter 25 interrupt/exception pr ocessing function r01uh0290ej0300 rev.3.00 page 1602 of 1817 sep 19, 2011 25.8 periods in which interrupts are not acknowledged by cpu an interrupt is acknowledged by the cpu while an instru ction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instructi on and the next instruction (int errupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the prcmd register ? the store, set1, not1, or clr1 inst ructions for the following registers. ? interrupt-related registers: interrupt control register (xxicn), interr upt mask registers 0 to 7 (imr0 to imr7) ? power save control register (psc) ? on-chip debug mode register (ocdm) remark xx: identification name of each peripheral unit (see table 25-4 interrupt control register (xxicn) ) n: peripheral unit number (see table 25-4 interrupt control register (xxicn) ). 25.9 cautions the nmi pin alternately functions as t he p02 pin, and functions as a normal port pin after being reset. to enable the nmi pin, validate the nmi pin with the pmc0 register. the initial setting of the nm i pin is ?no edge detected?. select the nmi pin valid edge using the intf0 and intr0 registers. v850es/jh3-e, v850es/jj3-e chapter 26 key interrupt function r01uh0290ej0300 rev.3.00 page 1603 of 1817 sep 19, 2011 chapter 26 key interrupt function 26.1 function a key interrupt request signal (intkr) can be generated by inpu tting a falling edge to the eight key input pins (kr0 to kr7) by setting the krm register. table 26-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 26-1. key re turn block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 v850es/jh3-e, v850es/jj3-e chapter 26 key interrupt function r01uh0290ej0300 rev.3.00 page 1604 of 1817 sep 19, 2011 26.2 register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or writt en in 8-bit or 1-bit units. reset sets this register to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 control of key return mode krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution rewrite the krm register afte r once setting the krm register to 00h. remark for the alternate-function pin settings, see table 4-18 using port pin as alternate- function pin . 26.3 cautions (1) if a low level is input to any of the kr0 to kr7 pins, the intkr signal is not generat ed even if the falling edge of another pin is input. (2) if the krm register is changed, an interrupt request si gnal (intkr) may be generated. to prevent this, change the krm register after disabling interrupts (di) or masking, th en clear the interrupt request flag (kric.krif bit) to 0, and enable interrupts (ei) or clear the mask. (3) to use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation with the krm register. to switch from the key return pin to the port pin, disable the operat ion with the krm register and then set the port pin. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1605 of 1817 sep 19, 2011 chapter 27 standby function 27.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available stan dby modes are listed in table 27-1. table 27-1. standby modes mode functional outline halt mode mode in which only the operating clock of the cpu is stopped idle1 mode mode in which all the operations of the internal circuits except the oscillator, pll note , and flash memory are stopped idle2 mode mode in which all the operations of internal circuits except the oscillator are stopped stop mode mode in which all the operations of internal circuits except the subclock oscillator are stopped subclock operation mode mode in which the subclock is used as the internal system clock sub-idle mode mode in which all the operations of internal circuits except the oscillator are stopped, in the subclock operation mode note the pll holds the prev ious operating status. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1606 of 1817 sep 19, 2011 figure 27-1. status transition reset subclock operation mode (fx operates, pll operates) subclock operation mode (fx stops, pll stops) sub-idle mode (fx operates, pll operates) sub-idle mode (fx stops, pll stops) stop mode (fx stops, pll stops) idle2 mode (fx operates, pll stops) idle1 mode (fx operates, pll operates) idle1 mode (fx operates, pll stops) halt mode (fx operates, pll stops) halt mode (fx operates, pll operates) normal operation mode oscillation stabilization wait clock through mode (pll operates) clock through mode (pll stops) pll mode (pll operates) internal oscillation clock operation wdt overflow oscillation stabilization wait note pll lockup time wait oscillation stabilization wait note oscillation stabilization wait note note if a wdt overflow occurs during an oscillation stabilization time, the cpu operates on the internal oscillation clock. remark f x : main clock oscillation frequency v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1607 of 1817 sep 19, 2011 27.2 registers (1) power save control register (psc) the psc register is an 8-bit register t hat controls the standby f unction. the stp bit of this register is used to specify the standby mode. this regist er is a special register that can be written onl y by the special sequence combinations (see 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 psc nmi1m nmi0m intm 0 0 stp 0 releasing standby mode by intwdt2 signal enabled releasing standby mode by intwdt2 signal disabled nmi1m 0 1 control of releasing standby mode by intwdt2 signal releasing standby mode by nmi pin input enabled releasing standby mode by nmi pin input disabled nmi0m 0 1 control of releasing standby mode by nmi pin input releasing standby mode by maskable interrupt request signals enabled releasing standby mode by maskable interrupt request signals disabled intm 0 1 control of releasing standby mode by maskable interrupt request signals normal mode standby mode stp 0 1 standby mode note setting after reset: 00h r/w address: fffff1feh < > < > < > < > note standby mode set by stp bit: idle1, idle2, stop, or sub-idle mode cautions 1. before setting the idle1, idle2, stop, or sub-idle mode, set the psmr.psm1 and psmr.psm0 bits and then set the stp bit. 2. settings of the nmi1m, nmi0m, and in tm bits are invalid when halt mode is released. 3. if the nmi1m, nmi0m, or intm bit is set to 1 at the same ti me the stp bit is set to 1, the setting of nmi1m, nmi0m, or in tm bit becomes invalid. if there is an unmasked interrupt request signal being held pending when the idle1/idle2/stop mode is set, set the bit corresponding to the interrupt request signal (nmi1m, nmi0m, or intm) to 1, and then set the stp bit to 1. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1608 of 1817 sep 19, 2011 (2) power save mode register (psmr) the psmr register is an 8-bit register that controls the operation status in the power save mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 idle1, sub-idle modes stop mode idle2, sub-idle modes stop mode psm1 0 0 1 1 specification of operation in software standby mode psmr 0 0 0 0 0 psm1 psm0 after reset: 00h r/w address: fffff820h psm0 0 1 0 1 < > < > cautions 1. be sure to set bits 2 to 7 to ?0?. 2. the psm0 and psm1 bits are valid only when the psc.stp bit is 1. remark idle1: in this mode, all operations except the oscillator operation and some other circuits (flash memory and pll) are stopped. after the idle1 mode is released, the norma l operation mode is restored without needing to secure the oscillation stabilization time, like the halt mode. idle2: in this mode, all operations ex cept the oscillator operation are stopped. after the idle2 mode is released, the nor mal operation mode is restored following the lapse of the setup time specified by t he osts register (flash memory and pll). stop: in this mode, all operations except the subclock oscillator operation are stopped. after the stop mode is released, the normal operation mode is restored following the lapse of the oscillation stabilization time specified by the osts register. sub-idle: in this mode, all other operations are halte d except for the oscillator. after the idle mode has been released by the interrupt request signal, the subclock operation mode will be restored after 12 cycles of the subclock have been secured. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1609 of 1817 sep 19, 2011 (3) oscillation stabilization time select register (osts) the wait time until the oscillation stabiliz es after the stop mode is released or the wait time until the on-chip flash memory stabilizes after the idle2 mode is released is controlled by the osts register. this register can be read or written in 8-bit units. reset sets this register to 06h. 0 osts 0 0 0 0 osts2 osts1 osts0 osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time/setup time note osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 after reset: 06h r/w address: fffff6c0h 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x f x setting prohibited 6.25 mhz 0.164 ms 0.328 ms 0.655 ms 1.311 ms 2.621 ms 5.243 ms 10.49 ms 6 mhz 0.171 ms 0.341 ms 0.683 ms 1.365 ms 2.731 ms 5.461 ms 10.92 ms note the oscillation stabilization time and setu p time are required when the stop mode and idle2 mode are released, respectively. cautions 1. the wait time following release of the stop mode does not include the time until the clock oscillation starts ("a" in the figure below) following release of the stop mode, regardless of whether th e stop mode is released by reset or the occurrence of an in terrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to set bits 3 to 7 to ?0?. 3. the oscillation stabilization ti me following reset release is 2 16 /f x (because the initial value of the osts register = 06h). remark f x = main clock oscillation frequency v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1610 of 1817 sep 19, 2011 27.3 halt mode 27.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock o scillator continues operating. only clock supply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the internal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction proce ssing by the cpu continue operating. table 27-3 shows the operating status in the halt mode. the average current consumpt ion of the system can be reduced by usi ng the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed while an unmasked interrupt request signal is being held pending, the status shifts to halt mode, but the halt mode is then released immediately by the pending interrupt request. 27.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt r equest signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intpn pin input), unmasked internal interrupt request signal from a peripheral function operable in the halt mode, or reset signal (reset by reset pin input, wdt2res signal, low- voltage detector (lvi), or clock monitor (clm)). after the halt mode has been released, the normal operation mode is restored. remark n = 00 to 20: v850es/jh3-e n = 00 to 25: v850es/jj3-e (1) releasing halt mode by non-m askable interrupt request signal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priori ty of the interrupt request signal. if the halt mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the halt mode is released, bu t that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signa l), the halt mode is re leased and that interrupt request signal is acknowledged. table 27-2. operation after releasing ha lt mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1611 of 1817 sep 19, 2011 (2) releasing halt mode by reset the same operation as the normal reset operation is performed. table 27-3. operating status in halt mode operating status setting of halt mode item when subclock is not used when subclock is used main clock oscillator (f x ) oscillation enabled subclock oscillator (f xt ) ? oscillation enabled internal oscillator (f r ) oscillation enabled pll operable cpu stops operation dma controller operable interrupt controller operable taa0 to taa5 operable tab0, tab1 operable tmm0 to tmm3 operable when a clock other than f xt is selected as the count clock operable timer tmt0 operable real-time counter (rtc) operable when f x (divided brg) is selected as the count clock operable watchdog timer (wdt2) operable when a clock other than f xt is selected as the count clock operable csifn operable (n = 0 to 4: v850es/jh3-e, n = 0 to 6: v850es/jj3-e) csie0, csie1 operable i 2 c0m operable (m = 0 to 3: v850es/jh3-e, m = 0 to 4: v850es/jj3-e) uartcx operable (x = 0 to 5: v850es/jh3-e, x = 0 to 7: v850es/jj3-e) serial interface uartb0, uartb1 operable a/d converter operable real-time output function (rto) operable key interrupt function (kr) operable crc operation circuit operable (no data input to the crcin register because the cpu is stopped) external bus interface see chapter 5 bus control function . port function retains status before halt mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. can note operable usb function operable ethernet controller operable note pd70f3783, 70f3786 only v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1612 of 1817 sep 19, 2011 27.4 idle1 mode 27.4.1 setting and operation status the idle1 mode is set by setting the psmr.psm1 and psmr.psm 0 bits to 00 and setting the psc.stp bit to 1 in the normal operation mode. in the idle1 mode, the clock oscillator , pll, and flash memory continue operating but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle1 mode was set are retained. the cpu and other on-chip peripheral func tions stop operating. however, the on-chip peripheral functions that can operate with the subclock or an exte rnal clock continue operating. table 27-5 shows the operating status in the idle1 mode. the idle1 mode can reduce the power consumption more t han the halt mode because it stops the operation of the on-chip peripheral functions. the main clock oscillator does not stop, so the normal operat ion mode can be restored without waiting for the oscillation stabilization time after t he idle1 mode has been released, in the same manner as when the halt mode is released. cautions 1. insert five or more nop in structions after the instruction that stores data in the psc register to set the idle1 mode. 2. if the idle1 mode is set while an unmasked in terrupt request signal is being held pending, the idle1 mode is released immediatel y by the pending interrupt request. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1613 of 1817 sep 19, 2011 27.4.2 releasing idle1 mode the idle1 mode is released by a non-maskable interrupt r equest signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intpn pin input), unmasked internal interrupt request signal from a peripheral function operable in the idle1 mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). after the idle1 mode has been released, the normal operation mode is restored. (1) releasing idle1 mode by non- maskable interrupt request signal or unmasked maskable interrupt request signal the idle1 mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle1 mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is processed as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the idle1 mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal ), the idle1 mode is rel eased and that interrupt request signal is acknowledged. caution an interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle1 mode is not released. remar k n = 00 to 20: v850es/jh3-e n = 00 to 25: v850es/jj3-e table 27-4. operation after releasing id le1 mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the prescribed setup time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the prescribed setup time. the next instruction is executed after securing the prescribed setup time. (2) releasing idle1 mode by reset the same operation as the normal reset operation is performed. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1614 of 1817 sep 19, 2011 table 27-5. operating status in idle1 mode operating status setting of idle1 mode item when subclock is not used when subclock is used main clock oscillator (f x ) oscillation enabled subclock oscillator (f xt ) ? oscillation enabled internal oscillator (f r ) oscillation enabled pll operable cpu stops operation dma controller stops operation interrupt controller stops operation (but standby mode release is possible) taa0 to taa5 stops operation tab0, tab1 stops operation tmm0 to tmm3 operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock timer tmt0 stops operation real-time counter (rtc) operable when f x (divided brg) is selected as the count clock operable watchdog timer (wdt2) operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock csifn operable when the sckfn input clock is selected as the count clock (n = 0 to 4: v850es/jh3-e, n = 0 to 6: v850es/jj3-e) csie0, csie1 operable when the scke0 or scke1 input clock is selected as the count clock i 2 c0m stops operation (m = 0 to 3: v850es/jh3-e, m = 0 to 4: v850es/jj3-e) uartcx stops operation (but uartc0 is operable when the asckc0 input clock is selected) (x = 0 to 5: v850es/jh3-e, x = 0 to 7: v850es/jj3-e) serial interface uartb0, uartb1 stops operation a/d converter holds operation (conversion result held) note 1 real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see chapter 5 bus control function . port function retains status before idle1 mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle1 mode was set. can note 2 stops operation usb function operable when the uclk input clock is selected as the count clock or the pll is operating note 1 ethernet controller stops operation note 1 notes 1. to realize low power consumption, stop the a/d co nverter, usb function, and ethernet controller before shifting to the idle1 mode. 2. pd70f3783, 70f3786 only v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1615 of 1817 sep 19, 2011 27.5 idle2 mode 27.5.1 setting and operation status the idle2 mode is set by setting the psmr.psm1 and psmr.psm 0 bits to 10 and setting the psc.stp bit to 1 in the normal operation mode. in the idle2 mode, the clock oscillator continues operation but clock supply to the cpu, pll, flash memory, and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle2 mode was set are retained. the cpu, pll, and other on-chip peripheral functions stop operating. however, t he on-chip peripheral functions that can operate with the subclock or an exte rnal clock continue operating. table 27-7 shows the operating status in the idle2 mode. the idle2 mode can reduce the power cons umption more than the idle1 mode becaus e it stops the op erations of the on-chip peripheral functions, pll, and flash memory. howeve r, because the pll and flash memory are stopped, a setup time for the pll and flash memory is required when idle2 mode is released. cautions 1. insert five or more nop in structions after the instruction that stores data in the psc register to set the idle2 mode. 2. if the idle2 mode is set while an unmasked in terrupt request signal is being held pending, the idle2 mode is released immediatel y by the pending interrupt request. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1616 of 1817 sep 19, 2011 27.5.2 releasing idle2 mode the idle2 mode is released by a non-maskable interrupt r equest signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intpn pi n input), unmasked internal interrupt requ est signal from the peripheral functions operable in the idle2 mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). the pll returns to the operati ng status it was in before the idle2 mode was set. after the idle2 mode has been released, the normal operation mode is restored. (1) releasing idle2 mode by non- maskable interrupt request signal or unmasked maskable interrupt request signal the idle2 mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle2 mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is processed as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the idle2 mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal ), the idle2 mode is re leased and that interrupt request signal is acknowledged. caution the interrupt request signal that is di sabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and idle2 mode is not released. remark n = 00 to 20: v850es/jh3-e n = 00 to 25: v850es/jj3-e table 27-6. operation after releasing id le2 mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the prescribed setup time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the prescribed setup time. the next instruction is executed after securing the prescribed setup time. (2) releasing idle2 mode by reset the same operation as the normal reset operation is performed. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1617 of 1817 sep 19, 2011 table 27-7. operating status in idle2 mode operating status setting of idle2 mode item when subclock is not used when subclock is used main clock oscillator (f x ) oscillation enabled subclock oscillator (f xt ) ? oscillation enabled internal oscillator (f r ) oscillation enabled pll stops operation cpu stops operation dma controller stops operation interrupt controller stops operation taa0 to taa5 stops operation tab0, tab1 stops operation tmm0 to tmm3 operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock timer tmt0 stops operation real-time counter (rtc) operable when f x (divided brg) is selected as the count clock operable watchdog timer (wdt2) operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock serial interface csifn operable when the sckf n input clock is selected as the count clock (n = 0 to 4: v850es/jh3-e, n = 0 to 6: v850es/jj3-e) csie0, csie1 operable when the scke0 or scke1 input clock is selected as the count clock i 2 c0m stops operation (m = 0 to 3: v850es/jh3-e, m = 0 to 4: v850es/jj3-e) uartcx stops operation (but uartc0 is operable when the asckc0 input clock is selected) (x = 0 to 5: v850es/jh3-e, x = 0 to 7: v850es/jj3-e) uartb0, uartb1 stops operation a/d converter holds operation (conversion result held) note 1 real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see chapter 5 bus control function . port function retains status before idle2 mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle2 mode was set. can note 2 stops operation usb function operable when the uclk input clock is selected as the count clock or the pll is operating note 1 ethernet controller stops operation note 1 notes 1. to realize low power consumption, stop the a/d co nverter, usb function, and ethernet controller before shifting to the idle2 mode. 2. pd70f3783, 70f3786 only v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1618 of 1817 sep 19, 2011 27.5.3 securing setup time when releasing idle2 mode secure the setup time for the flash me mory after releasing the idle2 mode bec ause the operation of the blocks other than the main clock oscillator stops after the idle2 mode is set. (1) releasing idle2 mode by non- maskable interrupt request signal or unmasked maskable interrupt request signal secure the specified setup time by setting the osts register. when the releasing source is generated, the dedicated internal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillated waveform rom circuit stopped setup time count main clock idle mode status interrupt request (2) release by reset (reset pin input, wdt2r es generation) this operation is the same as that of a normal reset. the oscillation stabilization time is the initial value of the osts register, 2 16 /f x . v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1619 of 1817 sep 19, 2011 27.6 stop mode 27.6.1 setting and operation status the stop mode is set by setting t he psmr.psm1 and psmr.psm0 bits to 01 or 11 and setting the psc.stp bit to 1 in the normal operation mode. in the stop mode, the subclock oscillato r continues operating but the main clo ck oscillator stops. clock supply to the cpu and the on-chip peripher al functions is stopped. as a result, program execution stops , and the contents of the internal ram before the stop mode was set are retained. the on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. table 27-9 shows the operating status in the stop mode. because the stop mode stops operation of the main clock oscillator, it reduc es the power consumption to a level lower than the idle2 mode. if the subclock oscillator, inte rnal oscillator, and external clock are not used, the power consumption can be minimized with only leakage current flowing. cautions 1. insert five or more nop in structions after the instruction that stores data in the psc register to set the stop mode. 2. if the stop mode is set while an unmasked interrupt request signal is being held pending, the stop mode is released immediatel y by the pending interrupt request. 27.6.2 releasing stop mode the stop mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intpn pi n input), unmasked internal interrupt requ est signal from the peripheral functions operable in the stop mode, or reset signal (reset by reset pin input, wdt2res signal, or low-voltage detector (lvi)). after the stop mode has been released, the normal operati on mode is restored after the oscillation stabilization time has been secured. (1) releasing stop mode by non-m askable interrupt request signal or unmasked maskable interrupt request signal the stop mode is released by a non-maskable interr upt request signal or an unmasked maskable interrupt request signal, regardless of the priori ty of the interrupt request signal. if the stop mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the stop mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal ), the stop mode is rele ased and that interrupt request signal is acknowledged. caution the interrupt request that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and stop mode is not released. remark n = 00 to 20: v850es/jh3-e n = 00 to 25: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1620 of 1817 sep 19, 2011 table 27-8. operation after releasing st op mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the oscillation stabilization time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the oscillation stabilization time. the next instruction is executed after securing the oscillation stabilization time. (2) releasing stop mode by reset the same operation as the normal reset operation is performed. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1621 of 1817 sep 19, 2011 table 27-9. operating status in stop mode setting of stop mode operating status item when subclock is not used when subclock is used main clock oscillator (f x ) stops oscillation subclock oscillator (f xt ) ? oscillation enabled internal oscillator (f r ) oscillation enabled pll stops operation cpu stops operation dma controller stops operation interrupt controller stops operation taa0 to taa5 stops operation tab0, tab1 stops operation tmm0 to tmm3 operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock timer tmt0 stops operation real-time counter (rtc) stops operation operable when f xt is selected as the count clock watchdog timer (wdt2) operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock csifn operable when the sckfn input clock is selected as the count clock (n = 0 to 4: v850es/jh3-e, n = 0 to 6: v850es/jj3-e) csie0, csie1 operable when the scke0 or scke1 input clock is selected as the count clock i 2 c0m stops operation (m = 0 to 3: v850es/jh3-e, m = 0 to 4: v850es/jj3-e) uartcx stops operation (but uartc0 is operable when the asckc0 input clock is selected) (x = 0 to 5: v850es/jh3-e, x = 0 to 7: v850es/jj3-e) serial interface uartb0, uartb1 stops operation a/d converter stops operation (conversion result undefined) notes 1, 2 real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see chapter 5 bus control function . port function retains status before stop mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the stop mode was set. can note 5 stops operation usb function stops operation note 4 ethernet controller stops operation note 4 notes 1. if the stop mode is set while the a/d converter is operating, the a/d converter is automatically stopped and starts operating again after the stop mode is released. however, in that case, the a/d conversion results after the stop mode is released are invalid. all the a/ d conversion results before the stop mode is set are invalid. 2. even if the stop mode is set while the a/d converte r is operating, the power consumption is reduced equivalently to when the a/d converter is stopped before the stop mode is set. 3. pd70f3783, 70f3786 only 4. to realize low power consumption, stop the usb function and ethernet cont roller before shifting to the stop mode. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1622 of 1817 sep 19, 2011 27.6.3 securing oscillation stabilizati on time when releasing stop mode secure the oscillation stabilization time for the main clo ck oscillator after releasing the stop mode because the operation of the main clock oscillator stops after stop mode is set. (1) releasing stop mode by non-m askable interrupt request signal or unmasked maskable interrupt request signal secure the oscillation stabilization time by setting the osts register. when the releasing source is generated, the dedicated internal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillated waveform rom circuit stopped setup time count main clock stop status interrupt request (2) release by reset this operation is the same as that of a normal reset. the oscillation stabilization time is the initial value of the osts register, 2 16 /f x . v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1623 of 1817 sep 19, 2011 27.7 subclock operation mode 27.7.1 setting and operation status the subclock operation mode is set by setting the pcc.ck3 bit to 1 in the normal operation mode. when the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. check whether the clock has been s witched by using the pcc.cls bit. when the pcc.mck bit is set to 1, the operation of the main clock oscillator is stopped. as a result, the system operates only on the subclock. in the subclock operation mode, the pow er consumption can be reduced to a le vel lower than in the normal operation mode because the subclock is used as the internal system clock. in addition , the power consumption can be further reduced to the level of the stop mode by stoppi ng the operation of the main clock oscillator. table 27-10 shows the operating st atus in subclock operation mode. cautions 1. when manipulating the ck3 bit, do not ch ange the set values of the pcc.ck2 to pcc.ck0 bits (using a bit manipulation instruction to manipulat e the bit is recommended). for details of the pcc register, see 6.3 (1) processor clock control register (pcc). 2. if the following conditions are not satisfied, ch ange the ck2 to ck0 bits so that the conditions are satisfied and set the subclock operation mode. internal system clock (f clk ) > subclock (f xt = 32.768 khz) 4 remark internal system clock (f clk ): clock generated from main clock (f xx ) in accordance with the settings of the ck2 to ck0 bits 27.7.2 releasing subc lock operation mode the subclock operation mode is released by a reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)) when the ck3 bit is set to 0. if the main clock is stopped (mck bit = 1), set the mck bit to 1, secure the oscillation st abilization time of the main clock by software, and set the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1 ) processor clock control register (pcc). v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1624 of 1817 sep 19, 2011 table 27-10. operating status in subclock operation mode operating status setting of subclock operation mode item when main clock is oscillating when main clock is stopped subclock oscillator (f xt ) oscillation enabled internal oscillator (f r ) oscillation enabled pll operable stops operation note 1 cpu operable dma controller operable interrupt controller operable taa0 to taa5 operable stops operation tab0, tab1 operable stops operation tmm0 to tmm3 operable operable when f r /8 or f xt is selected as the count clock timer tmt0 real-time counter (rtc) operable operable when f xt is selected as the count clock watchdog timer (wdt2) operable operable when f r or f xt is selected as the count clock csifn (n = 0 to 4: v850es/jh3-e, n = 0 to 6: v850es/jj3-e) operable operable when the sckfn input clock is selected as the count clock csie0, csie1 operable operable when the scke0 and scke1 input clock is selected as the count clock i 2 cm (m = 0 to 3: v850es/jh3-e, m = 0 to 4: v850es/jj3-e) operable stops operation uartcx (x = 0 to 5: v850es/jh3-e, x = 0 to 7: v850es/jj3-e) operable stops operation (but uartc0 is operable when the asckc0 input clock is selected) serial interface uartb0, uartb1 operable a/d converter operable stops operation real-time output function (rto) oper able stops operation (output held) key interrupt function (kr) operable crc operation circuit operable external bus interface see chapter 5 bus control function . port function settable internal data settable can note 2 operable stops operation usb function operable stops operation ethernet controller stops operation note 3 notes 1, be sure to stop the pll (pllctl.pllon bi t = 0) before stopping the main clock. 2. pd70f3783, 70f3786 only 3. to realize low power consumption, stop the ethernet controller before shifting to the subclock mode. caution when the cpu is operating on the subclock and main clock oscillation is stopped, accessing a register in which a wait occurs is disabled. if a wait is generated, it can be released only by reset (see 3.4.9 (2)). v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1625 of 1817 sep 19, 2011 27.8 sub-idle mode 27.8.1 setting and operation status the sub-idle mode is set by setting the psmr.psm1 and psmr.psm0 bits to 00 or 10 and setting the psc.stp bit to 1 in the subclock operation mode. in this mode, the clock oscillator continues operating but cl ock supply to the cpu, flash memory, and the other on-chip peripheral functions is stopped. as a result, program execution stops and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and the other on-chip pe ripheral functions are stopped. however, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. because the sub-idle mode stops operat ion of the cpu, flash memory, and other on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. if the sub-idle mode is set after the main clock has been stopped, the current consumpt ion can be reduced to a level as low as that in the stop mode. table 27-12 shows the operating status in the sub-idle mode. cautions 1. following the store instruction to the psc register for setting the sub- idle mode, insert the five or more nop instructions. 2. if the sub-idle mode is set while an unmasked interrupt request signal is being held pending, the sub-idle mode is then released immedi ately by the pending interrupt request. 27.8.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable inte rrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intpn pin in put), unmasked internal interrupt request signal from the peripheral functions operable in the su b-idle mode, or reset signal (reset by reset pin input, wdt2res signal, low- voltage detector (lvi), or clock monitor (clm)). the pll re turns to the operating status it was in before the sub-idle mode was set. when the sub-idle mode is released by an interrupt request signal, the subclock operation mode is set. (1) releasing sub-idle mo de by non-maskable interrupt request si gnal or unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable interru pt request signal or an unmasked maskable interrupt request signal, regardless of the priori ty of the interrupt request signal. if the sub-idle mode is set in an interrupt servicing routi ne, however, an interrupt request signal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, the sub-idle mode is released, but that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal ), the sub-idle mode is released and that interrupt request signal is acknowledged. cautions 1. the interrupt request signal that is disabled by setting the psc.nmi1m, psc.nmi0m, and psc.intm bits to 1 becomes invalid and sub-idle mode is not released. 2. when the sub-idle mode is rele ased, 12 cycles of the subclock (about 366 s) elapse from when the interrupt request signa l that releases the sub-idle mo de is generated to when the mode is released. remark n = 00 to 20: v850es/jh3-e n = 00 to 25: v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1626 of 1817 sep 19, 2011 table 27-11. operation after releasing sub- idle mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed. v850es/jh3-e, v850es/jj3-e chapt er 27 standby function r01uh0290ej0300 rev.3.00 page 1627 of 1817 sep 19, 2011 (2) releasing sub-idle mode by reset the same operation as the normal reset operation is performed. table 27-12. operating status in sub-idle mode operating status setting of sub-idle mode item when main clock is oscillating when main clock is stopped subclock oscillator (f xt ) oscillation enabled internal oscillator (f r ) oscillation enabled pll operable stops operation note 1 cpu stops operation dma controller stops operation interrupt controller stops operation taa0 to taa5 stops operation tab0, tab1 stops operation tmm0 to tmm3 operable when f r /8 or f xt is selected as the count clock timer tmt0 stops operation real-time counter (rtc) operable operable when f xt is selected as the count clock watchdog timer (wdt2) operable when f r or f xt is selected as the count clock csifn operable when the sckfn input clock is selected as the count clock (n = 0 to 4: v850es/jh3-e, n = 0 to 6: v850es/jj3-e) csie0, csie1 operable when the scke0 or scke1 input clock is selected as the count clock i 2 c0m stops operation (m = 0 to 3: v850es/jh3-e, m = 0 to 4: v850es/jj3-e) uartcx stops operation (but uartc0 is operable when the asckc0 input clock is selected) (x = 0 to 5: v850es/jh3-e, x = 0 to 7: v850es/jj3-e) serial interface uartb0, uartb1 stops operation a/d converter holds operation (conversion result held) note 2 real-time output function (rto) stops operation (output held) key interrupt function (kr) operable crc operation circuit stops operation external bus interface see chapter 5 bus control function . (same operation status as idle mode). port function retains status before sub-idle mode was set internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they we re before the sub-idle mode was set. can note 3 stops operation usb function stops operation ethernet controller stops operation note 2 notes 1. be sure to stop the pll (pllctl.pllon bi t = 0) before stopping the main clock. 2. to realize low power consumption, stop the a/d converter and ethernet c ontroller before shifting to the sub- idle mode. 3. pd70f3770, 70f3771 only remark perform the settings described in notes 1 and 2 when shifting from the normal operation mode to the subclock operation mode, rather than when shifting from the subclock operation mode to the sub-idle mode. v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1628 of 1817 sep 19, 2011 chapter 28 reset functions 28.1 overview the following reset functions are available. (1) four kinds of reset sources ? external reset input via the reset pin ? reset via the watchdog timer 2 (wdt2) overflow (wdt2res) ? system reset via the comparison of the low-volt age detector (lvi) supply voltage and detected voltage ? system reset via the detecting clock monitor (clm) oscillation stop after a reset is released, the source of the reset can be confirmed with the reset source flag register (resf). (2) emergency operation mode if the wdt2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock oscillation anomaly is judged and the cpu starts operating on the internal oscillation clock. caution in emergency operation mode , do not access on-chip peripheral i/o registers other than registers used for interrupts, port function, wdt2, or timer m, each of wh ich can operate with the internal oscillation clock. in a ddition, operation of csif0 to csif4 and uartc0 using the externally input clock is also prohibited in this mode. figure 28-1. block di agram of reset function clmrf lvirf wdt2rf reset source flag register (resf) internal bus wdt2 reset signal clm reset signal reset lvi reset signal reset signal reset signal reset signal to lvim register clear set set clear clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remark lvim: low-voltage detection register v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1629 of 1817 sep 19, 2011 28.2 registers to check reset source the v850es/jh3-e and v850es/jj3-e have four kinds of reset sources. after a reset has been released, the source of the reset that occurred can be checked wit h the reset source flag register (resf). (1) reset source flag register (resf) the resf register is a special regist er that can be written only by a co mbination of specific sequences (see 3.4.8 special registers ). the resf register indicates the source from which a reset signal is generated. this register can be read or written in 8-bit or 1-bit units. reset pin input sets this register to 00h. the initial val ue differs if the source of re set is other than the reset pin signal. 0 wdt2rf 0 1 not generated generated resf 0 0 wdt2rf 0 0 clmrf lvirf after reset: 00h note r/w address: fffff888h reset signal from wdt2 lvirf 0 1 not generated generated reset signal from lvi clmrf 0 1 not generated generated reset signal from clm note the value of the resf register is set to 00h when a reset is executed via the reset pin. when a reset is executed by the watchdog timer 2 (wdt2), low-vo ltage detector (lvi), or clock monitor (clm), the reset flags of this register (wdt2rf bit, clmrf bit, and lvirf bit) are set. however, other sources are retained. caution only "0" can be written to ea ch bit of this register. if writin g "0" conflicts with setting the flag (occurrence of reset), setting the flag takes precedence. v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1630 of 1817 sep 19, 2011 28.3 operation 28.3.1 reset operation via reset pin when a low level is input to the reset pin, the syst em is reset, and each hardware unit is initialized. when the level of the reset pin is changed from low to high, the reset status is released. table 28-1. hardware status on reset pin input item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues internal oscillator (f r ) oscillation stops oscillation starts peripheral clock (f x to f x /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to fxx/8) cpu initialized program execution starts after securing oscillation stabilization time watchdog timer 2 operation stops (initialized to 0) counts up from 0 with internal oscillation clock as source clock. internal ram undefined if power-on reset or cpu access and reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained. i/o lines (ports/alternate-function pins) high impedance note on-chip peripheral i/o registers initialized to sp ecified status, ocdm register is set (01h). other on-chip peripheral functions operation stops operation can be started after securing oscillation stabilization time note when the power is turned on, the following pin may output an undefined level temporarily, even during reset. ? p51/intp8/ddo caution the ocdm register is initialized by the reset pin input. therefore, note with caution that, if a high level is input to the p54/intp11/drst pin after a re set release before the o cdm.ocdm0 bit is cleared, the on-chip debug mode is entered. for details, see chapter 4 port functions. v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1631 of 1817 sep 19, 2011 figure 28-2. timing of reset operation by reset pin input counting of oscillation stabilization time initialized to f xx /8 operation oscillation stabilization timer overflows internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay figure 28-3. timing of power-on reset operation oscillation stabilization time count must be on-chip regulator stabilization time (1 ms (max.)) or longer. initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal reset f x v dd f clk analog delay v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1632 of 1817 sep 19, 2011 28.3.2 reset operation by watchdog timer 2 when watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (wdt2res signal generation), a system reset is executed and the hardware is initialized to the initial status. following watchdog timer 2 overflow, the reset status is en tered and lasts the predetermined time (analog delay), and the reset status is then aut omatically released. the main clock oscillator is stopped during the reset period. table 28-2. hardware status during watchdog timer 2 reset operation item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues internal oscillator (f r ) oscillation stops oscillation starts peripheral clock (f xx to f xx /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu initialized program execution after securing oscillation stabilization time watch dog timer 2 operation stops (initialized to 0) counts up from 0 with internal oscillation clock as source clock. internal ram undefined if power-on reset or cpu access a nd reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained. i/o lines (ports/alternate- function pins) high impedance on-chip peripheral i/o register initialized to spec ified status, ocdm register retains its value. on-chip peripheral functions other than above operation stops operation can be started after securing oscillation stabilization time. v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1633 of 1817 sep 19, 2011 figure 28-4. timing of reset oper ation by wdt2res signal generation counting of oscillation stabilization time initialized to f xx /8 operation oscillation stabilization timer overflow internal system reset signal wdt2res f x f clk analog delay v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1634 of 1817 sep 19, 2011 28.3.3 reset by clock monitor when the clock monitor is enabled, it samples the main cloc k by using the internal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. after reset is canceled, the cpu operates using the internal oscillation clock. once the clm.clme bit is set to 1 (to enable the clock monitor), it can only be cleared by a reset signal. the clock monitor automatically stops under the following conditions. ? when the oscillation stabilization time after shifting to stop mode is being counted ? when the main clock is stopped (after setting the pcc.mck bit to 1 when the system is operating on the subclock and before setting the pcc.cls bit to 0 when the system is operating on the main clock) ? when the sampling clock (internal oscillation clock) is stopped ? when the cpu is operating on the internal oscillation clock table 28-3. hardware status during and after reset triggered by clock monitor item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues internal oscillator (f r ) oscillation stops oscillation starts peripheral clock (f xx to f xx /1,024) operation stops operation starts after oscillation stabilization time has elapsed internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after oscillation stabilization time (initialized to f xx /8) has elapsed cpu initialized program execution starts after oscillation stabilization time has elapsed wdt2 operation stops (initialized to 0) counts up from 0 with internal oscillation clock as source clock internal ram undefined i/o lines (port pins/alternat e-function pins) high impedance on-chip peripheral i/o registers initialized to the specif ied status. the ocdm register retains its value. on-chip peripheral functions other than above operation stops operation can be started after oscillation stabilization time has elapsed remark for the timing of a reset triggered by the clock monitor, see chapter 29 clock monitor . v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1635 of 1817 sep 19, 2011 28.3.4 reset operation by low-voltage detector if the supply voltage falls below the vo ltage detected by the low- voltage detector when lvi operation is enabled, a system reset is executed (when the lvim.lvimd bit is set to 1), and the hardware is initia lized to the initial status. the reset status lasts from when a s upply voltage drop has been detected until t he supply voltage rises above the lvi detection voltage. the main clock oscillator is stopped during the reset period. when the lvimd bit = 0, an interrupt request signal (i ntlvi) is generated if a low voltage is detected. table 28-4. hardware status during reset operation by low-voltage detector item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues internal oscillator (f r ) oscillation stops oscillation starts peripheral clock (f xx to f xx /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu initialized program execution starts after securing oscillation stabilization time wdt2 operation stops (initialized to 0) counts up from 0 with internal oscillation clock as source clock. internal ram undefined if power-on reset or cpu access a nd reset input conflict (data is damaged). otherwise value imm ediately after reset input is retained. i/o lines (ports/alternate-function pins) high impedance on-chip peripheral i/o register initialized to spec ified status, ocdm register retains its value. lvi setting retains on-chip peripheral functions other than above operation stops operation can be started after securing oscillation stabilization time. remark for the reset timing of the low-voltage detector, see chapter 30 low-voltage detector (lvi) . v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1636 of 1817 sep 19, 2011 28.3.5 operation after reset release after the reset is released, the main clock starts oscillatio n and oscillation stabilization time (osts register initial value: 2 16 /f x ) is secured, and the cpu st arts program execution. wdt2 immediately begins to operate after a reset has been released using the internal oscillation clock as a source clock. figure 28-5. operation after reset release main clock reset counting of oscillation stabilization time normal operation (f cpu = main clock) operation stops operation in progress operation stops operation in progress clock monitor internal oscillation clock v850es/jh3-e, v850es/jj3-e wdt2 (1) emergent operation mode if an anomaly occurs in the main clock before oscillatio n stabilization time is secured, wdt2 overflows before executing the cpu program. at this ti me, the cpu starts program execution by using the internal oscillation clock as the source clock. figure 28-6. operation after reset release main clock reset counting of oscillation stabilization time wdt overflows emergency mode (f cpu = internal oscillation clock) operation stops operation in progress operation in progress (re-count) operation stops clock monitor internal oscillation clock v850es/jh3-e, v850es/jj3-e wdt2 the cpu operation clock states c an be checked with the cpu operation clock status register (ccls). v850es/jh3-e, v850es/jj3-e chapt er 28 reset functions r01uh0290ej0300 rev.3.00 page 1637 of 1817 sep 19, 2011 28.3.6 reset function operation flow start (reset source occurs) main clock oscillation stabilization time secured? no ccls.cclsf bit = 1? yes no (in normal operation mode) no (in emergent operation mode) reset source generated? yes no yes (in normal operation mode) wdt2 overflow? no yes (in emergent operation mode) set resf register note 1 reset occurs reset release emergent operation software processing normal operation cpu operation starts from reset address (f cpu = f x /8, f r ) firmware operation f cpu = f x f cpu = f r note 2 ccls.cclsf bit 1 wdt2 restart internal oscillation and main clock oscillation start, wdt2 count up starts (reset mode) notes 1. bit to be set differs depending on the reset source. reset source wdt2rf bit crmrf bit lvirf bit reset pin 0 0 0 wdt2 1 value before reset is retained. value before reset is retained. clm value before reset is retained. 1 value before reset is retained. lvi value before reset is retained. value before reset is retained. 1 2. the internal oscillator cannot be stopped. v850es/jh3-e, v850es/jj3-e ch apter 29 clock monitor r01uh0290ej0300 rev.3.00 page 1638 of 1817 sep 19, 2011 chapter 29 clock monitor 29.1 functions the clock monitor samples the main clock by using the inte rnal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset. when a reset by the clock monitor occurs, the resf.clmrf bit is set. for details on the resf register, see 28.2 registers to check reset source . the clock monitor automatically stops under the following conditions. ? during oscillation stabilization time after stop mode is released ? when the main clock is stopped (from when the pcc.mck bi t = 1 during subclock operation, until the pcc.cls bit = 0 during main clock operation) ? when the sampling clock (internal oscillation clock) is stopped ? when the cpu operates with the internal oscillation clock 29.2 configuration the clock monitor includes the following hardware. table 29-1. configuration of clock monitor item configuration control register clock monitor mode register (clm) figure 29-1. timing of reset via reset pin input main clock internal oscillation clock internal reset signal enable/disable clme clock monitor mode register (clm) v850es/jh3-e, v850es/jj3-e ch apter 29 clock monitor r01uh0290ej0300 rev.3.00 page 1639 of 1817 sep 19, 2011 29.3 register the clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) the clm register is a special regist er. this can be written only in a special combination of sequences (see 3.4.8 special registers ). this register is used to set the operation mode of the clock monitor. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. after reset: 00h r/w address: fffff870h 7 6 5 4 3 2 1 <0> clm 0 0 0 0 0 0 0 clme clme clock monitor operation enable or disable 0 disable clock monitor operation. 1 enable clock monitor operation. cautions 1. once the clme bit h as been set to 1, it cannot be cleared to 0 by any means other than reset. 2. when a reset by the clock monitor occu rs, the clme bit is cleared to 0 and the resf.clmrf bit is set to 1. 3. be sure to set bits 7 to 1 to ?0?. v850es/jh3-e, v850es/jj3-e ch apter 29 clock monitor r01uh0290ej0300 rev.3.00 page 1640 of 1817 sep 19, 2011 29.4 operation this section explains the functions of the clock m onitor. the start and stop conditions are as follows. v850es/jh3-e, v850es/jj3-e ch apter 29 clock monitor r01uh0290ej0300 rev.3.00 page 1641 of 1817 sep 19, 2011 (1) operation when main clock osc illation is stopped (clme bit = 1) if oscillation of the main clock is stopped when the clme bi t = 1, an internal reset signal is generated as shown in figure 29-2. figure 29-2. reset period due to that oscillation of main clock is stopped four internal oscillation clocks main clock internal oscillation clock internal reset signal clm.clme bit resf.clmrf bit (2) clock monitor status after reset input reset input clears the clm.clme bit to 0 and stops the cl ock monitor operation. when clme bit is set to 1 by software at the end of the oscillati on stabilization time of the main clock, monitoring is started. figure 29-3. clock monitor status after reset input (clm.clme bit = 1 is set after reset input and at the end of main clock oscillation stabilization time) cpu operation clock monitor status clme reset internal oscillation clock main clock reset oscillation stabilization time normal operation clock supply stopped normal operation monitoring monitoring stopped monitoring set to 1 by software v850es/jh3-e, v850es/jj3-e ch apter 29 clock monitor r01uh0290ej0300 rev.3.00 page 1642 of 1817 sep 19, 2011 (3) operation in stop mode or after stop mode is released if the stop mode is set with the clm.cl me bit = 1, the monitor operation is stopped in the stop mode and while the oscillation stabilization time is bei ng counted. after the oscillation stabilization time, the monitor operation is automatically started. figure 29-4. operation in stop mode or after stop mode is released clock monitor status during monitor monitor stops during monitor clme internal oscillation clock main clock cpu operation normal operation stop oscillation stabilization time normal operation oscillation stops oscillation stabilization time (set by osts register) (4) operation when main clock is stopped (arbitrary) during subclock operation (pcc.cls bit = 1) or when the main clock is stopped by setting the pcc.mck bit to 1, the monitor operation is stopped until the main clock operat ion is started (pcc.cls bit = 0). the monitor operation is automatically started when the ma in clock operation is started. figure 29-5. operation when main clock is stopped (arbitrary) clock monitor status during monitor monitor stops monitor stops during monitor clme internal oscillation clock main clock cpu operation oscillation stops subclock operation main clock operation oscillation stabilization time (set by osts register) oscillation stabilization time count by software pcc.mck bit = 1 (5) operation while cpu is operating on inte rnal oscillation clock (ccls.cclsf bit = 1) the monitor operation is not stopped when the cclsf bi t is 1, even if the clme bit is set to 1. v850es/jh3-e, v850es/jj3-e chapter 30 low-voltage detector (lvi) r01uh0290ej0300 rev.3.00 page 1643 of 1817 sep 19, 2011 chapter 30 low-voltage detector (lvi) 30.1 functions the low-voltage detector (lvi) has the following functions. ? if the interrupt occurrence at low voltage detection is se lected, the low-voltage detecto r continuously compares the supply voltage (v dd ) and the detected voltage (v lvi ), and generates an internal interrupt signal when the supply voltage drops or rises ac ross the detected voltage. ? if the reset occurrence at low voltage detection is sele cted, the low-voltage detector generates an interrupt reset signal when the supply voltage (v dd ) drops across the detected voltage (v lvi ). ? interrupt or reset signal c an be selected by software. ? can operate in stop mode. if the low-voltage detector is used to generate a reset signal, the resf.lvirf bit is set to 1 when the reset signal is generated. for details of resf register, see 28.2 registers to check reset source . 30.2 configuration the block diagram of the low-vo ltage detector is shown below. figure 30-1. block diagram of low-voltage detector lvion detected voltage source (v lvi ) v dd v dd intlvi internal bus n-ch low-voltage detection register (lvim) lvimd lvif internal reset signal selector low- voltage detection level selector ? + v850es/jh3-e, v850es/jj3-e chapter 30 low-voltage detector (lvi) r01uh0290ej0300 rev.3.00 page 1644 of 1817 sep 19, 2011 30.3 registers the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? internal ram data status register (rams) (1) low-voltage detection register (lvim) the lvim register is a special register . this can be written only in the spec ial combination of the sequences (see 3.4.8 special registers ). the lvim register is used to enable or disable low-volt age detection, and to set the operation mode of the low- voltage detector. this register can be read or written in 8-bit or 1- bit units. however, the lvif bit is read-only. after reset: 00h note 1 r/w address: fffff890h <7> 6 5 4 3 2 <1> <0> lvim lvion 0 0 0 0 0 lvimd lvif lvion low-voltage detection operation enable or disable 0 disable operation. 1 enable operation. lvimd selection of operation mode of low-voltage detection 0 generates interrupt signal intlvi when the supply voltage drops or rises across the detection voltage value. 1 generates internal reset signal lvires when the supply voltage drops across the detected voltage value. lv i f note 2 low-voltage detection flag 0 when supply voltage > detected voltage, or when operation is disabled 1 supply voltage of connected power supply < detected voltage notes 1. reset by low-voltage detection: 82h reset due to other source: 00h 2. after the lvi operation has started (lvion bi t = 1) or when intlvi has occurred, confirm the supply voltage state using the lvif bit. cautions 1. when the lvion and lvimd bits to 1, the low-voltage detector cannot be stopped until the reset request due to other than th e low-voltage detection is generated. 2. when the lvion bit is set to 1, the comparator in the lvi circuit starts operating. wait 0.2 ms or longer by software before checking the voltage at the lvif bit after the lvion bit is set. 3. be sure to set bits 6 to 2 to ?0?. v850es/jh3-e, v850es/jj3-e chapter 30 low-voltage detector (lvi) r01uh0290ej0300 rev.3.00 page 1645 of 1817 sep 19, 2011 (2) internal ram data status register (rams) the rams register is a special regi ster. this can be written only in a special combination of sequences (see 3.4.8 special registers ). this register is a flag register that indica tes whether the internal ram is valid or not. this register can be read or written in 8-bit or 1-bit units. the set/clear conditions for the ramf bit are shown below. ? setting conditions: detection of voltage lower than specified level set by instruction ? clearing condition: writing of 0 in specific sequence after reset: 01h note r/w address: fffff892h 7 6 5 4 3 2 1 <0> rams 0 0 0 0 0 0 0 ramf ramf internal ram voltage detection 0 voltage lower than ram retention voltage is not detected. 1 voltage lower than ram retention voltage is detected. note this register is reset only when a voltage dr op below the ram retention voltage is detected. v850es/jh3-e, v850es/jj3-e chapter 30 low-voltage detector (lvi) r01uh0290ej0300 rev.3.00 page 1646 of 1817 sep 19, 2011 30.4 operation depending on the setting of the lvim.vimd bit, an interrupt si gnal (intlvi) or an internal reset signal is generated. how to specify each operation is described below, together with timing charts. 30.4.1 to use for inte rnal reset signal v850es/jh3-e, v850es/jj3-e chapter 30 low-voltage detector (lvi) r01uh0290ej0300 rev.3.00 page 1647 of 1817 sep 19, 2011 30.4.2 to use for interrupt v850es/jh3-e, v850es/jj3-e chapter 30 low-voltage detector (lvi) r01uh0290ej0300 rev.3.00 page 1648 of 1817 sep 19, 2011 30.5 ram retention voltage detection operation the supply voltage and detected voltage are compared. when the supply volt age drops below the detected voltage (including on power application), the rams.ramf bit is set to 1. figure 30-4. operation timing of ram retention voltage detection function supply voltage (v dd ) 2.0 v (minimum ram retention voltage) reset pin rams.ramf bit initialize ram (ramf bit is also cleared) when power application, ramf bit is set ram data is not retained ramf bit = 0 is retained regardless of reset pin if v dd > 2.0 v initialize ram (ramf bit is also cleared) v dd < 2.0 v detected set ramf bit ram data is not retained remarks 1. the ramf bit is set to 1 if the supply volt age drops under the minimum ram retention voltage (2.0 v (typ.)). 2. the ramf bit operates regardl ess of the reset pin status. v850es/jh3-e, v850es/jj3-e chapter 31 crc function r01uh0290ej0300 rev.3.00 page 1649 of 1817 sep 19, 2011 chapter 31 crc function 31.1 functions ? crc operation circuit for detection of data block errors ? generation of 16-bit crc code using a crc-ccitt (x 16 + x 12 + x 5 + 1) generation polynomial for blocks of data of any length in 8-bit units ? crc code is set to the crcd data register each time 1-byte data is transferred to the crcin register, after the initial value is set to the crcd register. 31.2 configuration the crc function includes the following hardware. table 31-1. crc configuration item configuration control registers crc input register (crcin) crc data register (crcd) figure 31-1. block diagram of crc register crc data register (crcd) (16 bits) crc input register (crcin) (8 bits) internal bus internal bus crc code generator v850es/jh3-e, v850es/jj3-e chapter 31 crc function r01uh0290ej0300 rev.3.00 page 1650 of 1817 sep 19, 2011 31.3 registers (1) crc input register (crcin) the crcin register is an 8-bi t register for setting data. this register can be read or written in 8-bit units. reset sets this register to 00h. crcin 654321 after reset: 00h r/w address: fffff310h 7 0 (2) crc data register (crcd) the crcd register is a 16-bit register t hat stores the crc-ccitt operation results. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the crcd register is prohibited in th e following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock and the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock crcd 12 10 8 6 4 2 after reset: 0000h r/w address: fffff312h 14 0 13 11 9 7 5 3 15 1 v850es/jh3-e, v850es/jj3-e chapter 31 crc function r01uh0290ej0300 rev.3.00 page 1651 of 1817 sep 19, 2011 31.4 operation an example of the crc operation circuit is shown below. figure 31-2. crc operation circui t operation example (lsb first) (1) setting of crcin = 01h 1189h b15 b0 b0 b7 crc code is stored (2) crcd register read the code when 01h is sent lsb first is (1000 0000). therefore, the crc code from generation polynomial x 16 + x 12 + x 5 + 1 becomes the remainder when (1000 0000) x 16 is divided by (1 0001 0000 0010 0001) using the modulo-2 operation formula. the modulo-2 operation is performed based on the following formula. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 ? 1 = 1 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb lsb msb msb therefore, the crc code becomes . since lsb first is used, this corresponds to 1189h in hexadecimal notation. 1001 9811 0001 1000 1000 v850es/jh3-e, v850es/jj3-e chapter 31 crc function r01uh0290ej0300 rev.3.00 page 1652 of 1817 sep 19, 2011 31.5 usage method how to use the crc logic circuit is described below. figure 31-3. crc operation flow start write of 0000h to crcd register crcd register read crcin register write yes no input data exists? end [basic usage method] <1> write 0000h to the crcd register. <2> write the required quantity of data to the crcin register. <3> read the crcd register. v850es/jh3-e, v850es/jj3-e chapter 31 crc function r01uh0290ej0300 rev.3.00 page 1653 of 1817 sep 19, 2011 communication errors can easily be detected if the c rc code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. the following is an illustration using the transmission of 12345678h (0001 0010 0011 0100 0101 0110 0111 1000b) lsb-first as an example. figure 31-4. crc transmission example 78 transmit/receive data (12345678h) crc code (08f6h) 56 34 12 f6 08 setting procedure on transmitting side <1> write the initial value 0000h to the crcd register. <2> write the 1 byte of data to be transmitted first to the trans mit buffer register. (at this time, also write the same data to the crcin register.) <3> when transmitting several bytes of data, write the sa me data to the crcin register each time transmit data is written to the transmit buffer register. <4> after all the data has been transmitted, write the cont ents of the crcd register (crc code) to the transmit buffer register and transmit them. (since this is lsb first, transmit the data starting from the lower bytes, then the higher bytes.) setting procedure on receiving side <1> write the initial value 0000h to the crcd register. <2> when reception of the first 1 byte of data is co mplete, write that receive data to the crcin register. <3> if receiving several bytes of data, write the rece ive data to the crcin register upon every reception completion. (in the case of normal reception, w hen all the receive data has been written to the crcin register, the contents of the crcd r egister on the receiving side and t he contents of the crcd register on the transmitting side are the same.) <4> next, the crc code is transmitted from the transmitting si de, so write this data to the crcin register similarly to receive data. <5> when reception of all the data, including the crc co de, has been completed, reception was normal if the contents of the crcd register are 0000h. if the content s of the crcd register ar e other than 0000h, this indicates a communication error, so transmi t a resend request to the transmitting side. v850es/jh3-e, v850es/jj3-e chapter 32 regulator r01uh0290ej0300 rev.3.00 page 1654 of 1817 sep 19, 2011 chapter 32 regulator 32.1 overview the v850es/jh3-e and v850es/jj3-e include a regul ator to reduce power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits (except the a/d converter, d/a converter, and output buffers). figure 32-1. regulator ev dd regc flmd0 v dd ev dd ev dd regc v dd usb av ref0 uv dd main oscillator internal digital circuits 2.5 v (typ.) bidirectional level shifter ev dd i/o buffer a/d converter flash memory regulator ev dd i/o buffer regulator sub oscillator caution be sure to use in v dd = uv dd = ev dd = av ref0 . v850es/jh3-e, v850es/jj3-e chapter 32 regulator r01uh0290ej0300 rev.3.00 page 1655 of 1817 sep 19, 2011 32.2 operation the regulators of the v850e s/jh3-e and v850es/jj3-e always operate in any mode (normal operation mode, halt mode, idle1 mode, idle2 mode, stop mode, subclock operation mode, s ub idle mode, or during reset). be sure to connect a capacitor (4.7 f (recommend value)) to the regc pin note to stabilize the regulator output. a diagram of the regulator pin connection method is shown below. note there are two regc pins. figure 32-2. regc pin connection reg v dd v ss regc input voltage 2.85 to 3.6 v voltage supply to oscillator/internal logic 4.7 f (recommend) caution the v850es/jh3-e and v850es/jj3-e have two regulators. therefore, connect each of the two regc pins to a capacitor. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1656 of 1817 sep 19, 2011 chapter 33 flash memory the v850es/jh3-e and v850es/jj3-e incorporate a flash memory. ? pd70f3778: 256 kb flash memory ? pd70f3779, 70f3781: 384 kb flash memory ? pd70f3780, 70f3782, 70f3783, 70f3784, 70f3785, 70f3786: 512 kb flash memory flash memory versions offer the following advantages for development environments and mass production applications. { for altering software after the v850es/jh3-e and v850es/jj3-e are soldered onto the target system. { for data adjustment when starting mass production. { for differentiating software according to the specif ication in small scale production of various models. { for facilitating inventory management. { for updating software after shipment. 33.1 features { 4-byte/1-clock access (when instruction is fetched) { capacity: 256/384/512 kb { rewrite voltage: erase/write with a single power supply { rewriting method ? rewriting by communication with dedicated flash pr ogrammer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { flash memory rewrite prohibit func tion supported (security function) { safe rewriting of entire flash memory area by self programming using boot swap function { interrupts can be acknowledged during self programming. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1657 of 1817 sep 19, 2011 33.2 memory configuration the internal flash memory area of the v850es/jh3-e and v850es/jj3-e is divided into 64, 96 or 128 blocks and can be programmed/erased in block units. all the blocks can also be erased at once. when the boot swap function is used, the physical memory lo cated at the addresses of blocks 0 to 15 is replaced by the physical memory located at the addresses of blocks 16 to 31. for details of the boot swap function, see 33.5 rewriting by self programming . figure 33-1. flash memory mapping : : : pd70f3778 (256 kb) : : : : pd70f3780, 70f3782, 70f3783, 70f3784, 70f3785, 70f3786 (512 kb) : : : : : pd70f3779,70f3781 (384 kb) 00000000h 00000fffh 00001000h 00001fffh 00002000h 0000efffh 0000f000h 0000ffffh 00010000h 00010fffh 00011000h 00011fffh 00012000h 0001efffh 0001f000h 0001ffffh 00020000h 00020fffh 00021000h 0003efffh 0003f000h 0003ffffh 00040000h 00040fffh 00041000h 0005efffh 0005f000h 0005ffffh 00060000h 00060fffh 00061000h 0007efffh 0007f000h 0007ffffh 00080000h block 0 (4 kb) block 1 (4 kb) block 15 (4 kb) block 17 (4 kb) block 31 (4 kb) block 32 (4 kb) block 16 (4 kb) block 63 (4 kb) block 95 (4 kb) block 127 (4 kb) block 96 (4 kb) block 0 (4 kb) block 1 (4 kb) block 15 (4 kb) block 17 (4 kb) block 31 (4 kb) block 32 (4 kb) block 16 (4 kb) block 63 (4 kb) block 64 (4 kb) block 0 (4 kb) block 1 (4 kb) block 15 (4 kb) block 17 (4 kb) block 31 (4 kb) block 32 (4 kb) block 16 (4 kb) block 63 (4 kb) block 95 (4 kb) block 64 (4 kb) note 1 note 2 notes 1. area to be replaced with the boot area by the boot swap function 2. boot area v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1658 of 1817 sep 19, 2011 33.3 functional overview the internal flash memory of the v850es/jh3-e and v850es/ jj3-e can be rewritten by us ing the rewrite function of the dedicated flash programmer, regardless of whether th e v850es/jh3-e and v850es/jj3-e have already been mounted on the target system or not (off-board/on-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programming) is ideal for an application w here it is assumed that the program is changed after production/shipment of the target system. a boot swap function that rewrites the entire flash memory area safely is also supported. in addition, interrup t servicing is supported during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. table 33-1. rewrite method rewrite method functional overview operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of off-board/on- board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance). normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1659 of 1817 sep 19, 2011 table 33-2. basic functions support ( : supported, : not supported) function functional outline on-board/off-board programming self programming block erasure the contents of specified memory blocks are erased. chip erasure the contents of the entire memory area are erased all at once. write writing to specified addresses, and a verify check to see if write level is secured are performed. verify/checksum data read from the flash memory is compared with data transferred from the flash programmer. (can be read by user program) blank check the erasure status of the entire memory is checked. security setting use of the block erase command, chip erase command, program command, and read command is prohibited, and rewriting of the boot area is prohibited. (supported only when setting is changed from enable to disable) the following table lists the security functions. the bloc k erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default a fter shipment, and security can be set by rewriting via on- board/off-board programming. each security function can be used in combination with the others at the same time. table 33-3. security functions function function outline block erase command prohibit execution of a block erase command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. chip erase command prohibit execution of block erase and chip erase commands on all the blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. program command prohibit execution of program and block erase commands on all the blocks is prohibited. setting of prohibition can be initialized by execution of the chip erase command. read command prohibit execution of a read command on all of the blocks is prohibited. setting of the prohibition can be initialized by execution of a chip erase command. boot area rewrite prohibit execution of write, block erase, and chip erase commands on the boot area is prohibited. setting of the prohibition of rewriting the boot ar ea cannot be initialized after it is once set. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1660 of 1817 sep 19, 2011 table 33-4. security setting erase, write, read operations when each security is set ( : executable, : not executable, ? : not supported) notes on security setting function on-board/ off-board programming self programming on-board/ off-board programming self programming block erase command prohibit block erase command: chip erase command: program command: read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. chip erase command prohibit block erase command: chip erase command: program command: note 1 read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition cannot be initialized. program command prohibit block erase command: chip erase command: program command: read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. read command prohibit block erase command: chip erase command: program command: read command: block erasure (flashblockerase): chip erasure: ? write (flashwordwrite): read (flashwordread): setting of prohibition can be initialized by chip erase command. supported only when setting is changed from enable to prohibit boot area rewrite prohibit block erase command: note 2 chip erase command: program command: note 2 read command: block erasure (flashblockerase): note 2 chip erasure: ? write (flashwordwrite): note 2 read (flashwordread): setting of prohibition cannot be initialized. supported only when setting is changed from enable to prohibit note 3 notes 1. in this case, since the erase command is invalid, data different from the data alr eady written in the flash memory cannot be written. 2. executable except in boot area. 3. the boot area rewrite proh ibit function becomes effective after the reset input. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1661 of 1817 sep 19, 2011 33.4 rewriting by dedicated flash programmer the flash memory can be rewritten by using a dedicated flash programmer after the v850es/jh3-e and v850es/jj3-e are mounted on the target syst em (on-board programming). the flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (fa series). 33.4.1 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850es/jh3-e and v850es/jj3-e. figure 33-2. environment required for writing programs to flash memory host machine rs-232c usb dedicated flash programmer flmd1 note flmd0 v dd v ss reset uartc0/csif0/csif3 v850es/jh3-e, v850es/jj3-e note connect the flmd1 pin to the flash programmer or con nect to gnd via a pull-down resistor on the board. a host machine is required for controlling the dedicated flash programmer. uartc0, csif0, or csif3 is used fo r the interface between the dedicated flash programmer and the v850es/jh3-e and v850es/jj3-e to perform writing, erasi ng, etc. a dedicated program adapter (f a series) required for off-board writing. remark the fa series is a product of naito densei machida mfg. co., ltd. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1662 of 1817 sep 19, 2011 33.4.2 communication mode communication between the dedicated flash programmer and the v850es/jh3-e or v850es/jj3-e is performed by serial communication using the uartc0, csif0, or cs if3 interface of the v850 es/jh3-e or v850es/jj3-e. (1) uartc0 transfer rate: 9,600 to 153,600 bps figure 33-3. communication with dedicated flash programmer (uartc0) v dd v ss reset txdc0 rxdc0 flmd1 flmd1 note flmd0 flmd0 v dd gnd reset rxd txd dedicated flash programmer v850es/jh3-e, v850es/jj3-e note connect the flmd1 pin to the flash programmer or con nect to gnd via a pull-down resistor on the board. (2) csif0, csif3 serial clock: 8 mhz or less: csif0 (msb first) 5 mhz or less: csif3 (msb first) figure 33-4. communication with dedica ted flash programmer (csif0, csif3) flmd1 note v dd v ss reset sof0, sof3 sif0, sif3 sckf0, sckf3 flmd1 flmd0 flmd0 v dd gnd reset si so sck dedicated flash programmer v850es/jh3-e, v850es/jj3-e note connect the flmd1 pin to the flash programmer or con nect to gnd via a pull-down resistor on the board. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1663 of 1817 sep 19, 2011 (3) csif0 + hs, csif3 + hs serial clock: 8 mhz or less: csif0 (msb first) 5 mhz or less: csif3 (msb first) figure 33-5. communication with dedicated flash programmer (csif0 + hs, csif3 + hs) v dd v ss reset sof0, sof3 sif0, sif3 sckf0, sckf3 p20 v dd flmd1 flmd1 note flmd0 flmd0 gnd reset si so sck hs dedicated flash programmer v850es/jh3-e, v850es/jj3-e note connect the flmd1 pin to the flash programmer or con nect to gnd via a pull-down resistor on the board. the dedicated flash programmer output s the transfer clock, and the v850es/ jh3-e and v850es/jj3-e operate as a slave. when the pg-fp5 is used as the dedicated flash programmer, it generates the following signals to the v850es/jh3-e and v850es/jj3-e. for details, refer to the pg-fp5 user?s manual (r20ut0008e) . v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1664 of 1817 sep 19, 2011 table 33-5. signal connections of dedicated flash programmer (pg-fp5) pg-fp5 v850es/jh3-e, v850es/jj3-e processing for connection signal name i/o pin function pin name uartc0 csif0, csif3 csif0 + hs, csif3 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/jh3-e and v850es/jj3-e x1, x2 note 2 note 2 note 2 reset output reset signal reset si/rxd input receive signal sof0, sof3/ txdc0 so/txd output transmit signal sif0, sif3/ rxdc0 sck output transfer clock sckf0, sckf3 hs input handshake signal for csif0 + hs, csif3 + hs communication p20 notes 1. wire these pins as shown in figures 33-6 and 33-7, or connect then to gnd via pull-down resistor on board. 2. clock cannot be supplied via the clk pin of the flas h programmer. create an oscillator on board and supply the clock. remark : must be connected. : does not have to be connected. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1665 of 1817 sep 19, 2011 table 33-6. wiring of v850es/jh3-e flash writing adapters (fa-128gf-gat-b) (1/2) flash programmer (fg-fp5) connection pin csif0 + hs used csif0 used uartc0 used signal name i/o pin function name of fa board pin pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal si p41/sof0 4 p41/sof0 4 p30/txdc0 25 so/txd output transmit signal so p 40/sif0 3 p40/sif0 3 p31/rxdc0 26 sck output transfer clock sck p42/sckf0 5 p42/sckf0 5 not needed ? x1 not needed ? not needed ? not needed ? clk output clock to v850es/jh3-e x2 not needed ? not needed ? not needed ? /reset output reset signal /reset reset 18 reset 18 reset 18 flmd0 output write voltage flmd0 flmd0 12 flmd0 12 flmd0 12 flmd1 output write voltage flmd1 pdl5/ad5/ flmd1 92 pdl5/ad5/ flmd1 92 pdl5/ad5/ flmd1 92 hs input handshake signal for csi0 + hs communication reserve/ hs p20 38 not needed ? not needed ? v dd 13, 82 v dd 13, 82 v dd 13, 82 ev dd 35, 61, 85, 102, 118 ev dd 35, 61, 85, 102, 118 ev dd 35, 61, 85, 102, 118 uv dd 11 uv dd 11 uv dd 11 vdd ? vdd voltage generation/ voltage monitor vdd av ref0 1 av ref0 1 av ref0 1 v ss 15, 34, 60, 84, 101, 117 v ss 15, 34, 60, 84, 101, 117 v ss 15, 34, 60, 84, 101, 117 gnd ? ground gnd av ss 2 av ss 2 av ss 2 cautions 1. be sure to connect the regc pin to gnd via 4.7 f (recommend value) capacitor. 2. clock cannot be supplied from th e clk pin of the flash programmer. create an oscillator on the board and supply clock. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1666 of 1817 sep 19, 2011 table 33-6. wiring of v850es/jh3-e flash writing adapters (fa-128gf-gat-b) (2/2) flash programmer (fg-fp5) connection pin csif3 + hs used csif3 used signal name i/o pin function name of fa board pin pin name pin no. pin name pin no. si/rxd input receive signal si p914/sof3 79 p914/sof3 79 so/txd output transmit signal so p913/sif3 78 p913/sif3 78 sck output transfer clock sck p915/sckf3 80 p915/sckf3 80 x1 not needed ? not needed ? clk output clock to v850es/jh3-e x2 not needed ? not needed ? /reset output reset signal /reset reset 18 reset 18 flmd0 output write voltage flmd0 flmd0 12 flmd0 12 flmd1 output write voltage flmd1 pdl5/ad5/flmd1 92 pdl5/ad5/flmd1 92 hs input handshake signal for csi0 + hs communication reserve/hs p20 38 not needed ? v dd 13, 82 v dd 13, 82 ev dd 35, 61, 85, 102, 118 ev dd 35, 61, 85, 102, 118 uv dd 11 uv dd 11 vdd ? vdd voltage generation/ voltage monitor vdd av ref0 1 av ref0 1 v ss 15, 34, 60, 84, 101, 117 v ss 15, 34, 60, 84, 101, 117 gnd ? ground gnd av ss 2 av ss 2 cautions 1. be sure to connect the regc pin to gnd via 4.7 f (recommend value) capacitor. 2. clock cannot be supplied from th e clk pin of the flash programmer. create an oscillator on the board and supply clock. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1667 of 1817 sep 19, 2011 figure 33-6. wiring example of v850es/jh3- e flash writing adapter (fa-128gf-gat-b) (in csif0 + hs mode) (1/2) rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs clkout vdd gnd gnd vdd gnd vdd vdd gnd 1 5 10 15 20 25 38 30 35 95 90 100 102 85 80 75 70 65 39 40 45 50 55 60 64 120 125 128 115 110 105 103 v850es/jh 3-e 4.7 f connect this pin to vdd. connect this pin to gnd. note 3 note 2 note 1 note 4 4.7 f v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1668 of 1817 sep 19, 2011 figure 33-6. wiring example of v850es/jh3- e flash writing adapter (fa-128gf-gat-b) (in csif0 + hs mode) (2/2) notes 1. corresponding pins when csif3 is used. 2. wire the flmd1 pin as shown below, or connect it to gnd on board via a pull-down resistor. 3. create an oscillator on the flash writing adapte r (shown in broken lines) and supply a clock. here is an example of the oscillator. example: x1 x2 4. corresponding pins when uartc0 is used. caution do not input a high level to the drst pin. remarks 1. process the pins not shown in accordan ce with the handling of unused pins (see 2.3 pin i/o circuit types, i/o buffer power supplies, and connection of unused pins ). 2. this adapter is for the 128-pin plastic lqfp package. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1669 of 1817 sep 19, 2011 table 33-7. wiring of v850es/jj3-e flash wr iting adapters (fa-144gj-gae-b) (1/2) flash programmer (fg-fp5) connection pin csif0 + hs used csif0 used uartc0 used signal name i/o pin function name of fa board pin pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal si p41/sof0 4 p41/sof0 4 p30/txdc0 28 so/txd output transmit signal so p40/sif0 3 p40/sif0 3 p31/rxdc0 29 sck output transfer clock sck p42/sckf0 5 p42/sckf0 5 not needed ? x1 not needed ? not needed ? not needed ? clk output clock to v850es/jj3-e x2 not needed ? not needed ? not needed ? /reset output reset signal /reset reset 18 reset 18 reset 18 flmd0 output write voltage flmd0 flmd0 12 flmd0 12 flmd0 12 flmd1 output write voltage flmd1 pdl5/ad5/ flmd1 98 pdl5/ad5/ flmd1 98 pdl5/ad5/ flmd1 98 hs input handshake signal for csi0 + hs communication reserve/ hs p20 38 not needed ? not needed ? v dd 13, 88 v dd 13, 88 v dd 13, 88 ev dd 35, 67, 91, 108, 132 ev dd 35, 67, 91, 108, 132 ev dd 35, 67, 91, 108, 132 uv dd 11 uv dd 11 uv dd 11 vdd ? vdd voltage generation/ voltage monitor vdd av ref0 1 av ref0 1 av ref0 1 v ss 15, 34, 66, 90, 107, 131 v ss 15, 34, 66, 90, 107, 131 v ss 15, 34, 66, 90, 107, 131 gnd ? ground gnd av ss 2 av ss 2 av ss 2 cautions 1. be sure to connect the regc pin to gnd via 4.7 f (recommend value) capacitor. 2. clock cannot be supplied from th e clk pin of the flash programmer. create an oscillator on the board and supply clock. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1670 of 1817 sep 19, 2011 table 33-7. wiring of v850es/jj3-e flash wr iting adapters (fa-144gj-gae-b) (2/2) flash programmer (fg-fp5) connection pin csif3 + hs used csif3 used signal name i/o pin function name of fa board pin pin name pin no. pin name pin no. si/rxd input receive signal si p914/sof3 85 p914/sof3 85 so/txd output transmit signal so p913/sif3 84 p913/sif3 84 sck output transfer clock sck p915/sckf3 86 p915/sckf3 86 x1 not needed ? not needed ? clk output clock to v850es/jj3-e x2 not needed ? not needed ? /reset output reset signal /reset reset 18 reset 18 flmd0 output write voltage flmd0 flmd0 12 flmd0 12 flmd1 output write voltage flmd1 pdl5/ad5/flmd1 98 pdl5/ad5/flmd1 98 hs input handshake signal for csi0 + hs communication reserve/hs p20 38 not needed ? v dd 13, 88 v dd 13, 88 ev dd 35, 67, 91, 108, 132 ev dd 35, 67, 91, 108, 132 uv dd 11 uv dd 11 vdd ? vdd voltage generation/ voltage monitor vdd av ref0 1 av ref0 1 v ss 15, 34, 66, 90, 107, 131 v ss 15, 34, 66, 90, 107, 131 gnd ? ground gnd av ss 2 av ss 2 cautions 1. be sure to connect the regc pin to gnd via 4.7 f (recommend value) capacitor. 2. clock cannot be supplied from th e clk pin of the flash programmer. create an oscillator on the board and supply clock. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1671 of 1817 sep 19, 2011 figure 33-7. wiring example of v850es/jj3- e flash writing adapter (fa-144gj-gae-b) (in csif0 + hs mode) (1/2) v850es/jj3-e vdd gnd gnd vdd gnd vdd vdd gnd 25 30 20 15 75 80 85 90 95 100 105 35 40 45 50 55 60 65 70 110 115 120 125 130 135 140 10 rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 si so sck /reset v pp reserve/hs clkout note 2 connect this pin to vdd. connect this pin to gnd. note 3 note 4 note 1 note 2 4.7 f (recommend value) 4.7 f (recommend value) v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1672 of 1817 sep 19, 2011 figure 33-7. wiring example of v850es/jj3- e flash writing adapter (fa-144gj-gae-b) (in csif0 + hs mode) (2/2) notes 1 . corresponding pins when csif3 is used. 2. wire the flmd1 pin as shown below, or connect it to gnd on board via a pull-down resistor. 3. create an oscillator on the flash writing adapte r (shown in broken lines) and supply a clock. here is an example of the oscillator. example: x1 x2 4. corresponding pins when uartc0 is used. caution do not input a high level to the drst pin. remarks 1. process the pins not shown in accord ance with the handling of unused pins (see 2.3 pin i/o circuit types, i/o buffer power supplies, and connection of unused pins ). 2. this adapter is for the 144-pin plastic lqfp package. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1673 of 1817 sep 19, 2011 33.4.3 flash memory control the following shows the procedure for manipulating the flash memory. figure 33-8. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies flmd0 pulse no end switch to flash memory programming mode v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1674 of 1817 sep 19, 2011 33.4.4 selection of communication mode in the v850es/jh3-e and v850es/jj3-e, the communication mode is selected by inputting pulses (12 pulses max.) to the flmd0 pin after switching to the flash memory programm ing mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. figure 33-9. selection of communication mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxdc0 (input) txdc0 (output) v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset released note the number of clocks is as follows depending on the communication mode. flmd0 pulse communication mode remarks 0 uartc0 communication rate: 9,600 bps (after reset), lsb first 8 csif0 v850es/jx3-e performs slave operation, msb first 9 csif3 v850es/jx3-e performs slave operation, msb first 11 csif0 + hs v850es/jx3-e performs slave operation, msb first 12 csif3 + hs v850es/jx3-e performs slave operation, msb first other rfu setting prohibited caution when uartc0 is selected , the receive clock is calculate d based on the reset command sent from the dedicated flash programme r after receiving the flmd0 pulse. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1675 of 1817 sep 19, 2011 33.4.5 communication commands the v850es/jh3-e and v850es/jj3-e communicate with the dedicated flash programmer by means of commands. the signals sent from the dedicated flash programmer to the v850es/jh3-e and v850es/jj3-e are called ?commands?. the response signals sent from the v850es/jh3-e and v 850es/jj3-e to the dedicated flash programmer are called ?response commands?. figure 33-10. communication commands command response command dedicated flash programmer v850es/jh3-e, v850es/jj3-e the following shows the commands for flash memory control in the v850es/jh3-e and v850 es/jj3-e. all of these commands are issued from the dedicated flash program mer, and the v850es/jh3-e and v850es/jj3-e perform the processing corresponding to the commands. table 33-7. flash memory control commands support classification command name csif0, csif3 csif0 + hs, csif3 + hs uartc0 function blank check block blank check command checks if the contents of the memory in the specified block have been correctly erased. chip erase command erases the contents of the entire memory. erase block erase command erases the contents of the memory of the specified block. write program command writes the specified address range, and executes a contents verify check. verify command compares the contents of memory in the specified address range with data transferred from the flash programmer. verify checksum command reads the checksum in the specified address range. silicon signature command reads silicon signature information. system setting, control security setting command prohibits the chip erase command, block erase command, program command, read command, and boot area rewrite. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1676 of 1817 sep 19, 2011 33.4.6 pin connection when performing on-board writing, mount a connector on t he target system to connect to the dedicated flash programmer. also, incorporate a function on-board to s witch from the normal operation mode to the flash memory programming mode. in the flash memory programming mode, all the pins not us ed for flash memory programming become the same status as that immediately after reset. theref ore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mode, input a voltage of v ss level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, see 33.5.5 (1) flmd0 pin . figure 33-11. flmd0 pin connection example flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 ) v850es/jh3-e, v850es/jj3-e (2) flmd1 pin when 0 v is input to the flmd0 pin, t he flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v mu st be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 33-12. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/jh3-e, v850es/jj3-e caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1677 of 1817 sep 19, 2011 table 33-8. relationship between flmd0 and flmd1 pi ns and operation mode wh en reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited (3) serial interface pin the following shows the pins used by each serial interface. table 33-9. pins used by serial interfaces serial interface pins used uartc0 txdc0, rxdc0 csif0 sof0, sif0, sckf0 csif3 sof3, sif3, sckf3 csif0 + hs sof0, sif0, sckf0, p20 csif3 + hs sof3, sif3, sckf3, p20 when connecting a dedicated flash programmer to a serial interface pin that is co nnected to another device on- board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) conflict of signals when the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other devi ce to the output high-impedance status. figure 33-13. conflict of signals (serial interface input pin) input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side. v850es/jh3-e, v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1678 of 1817 sep 19, 2011 (b) malfunction of other device when the dedicated flash programmer (outpu t or input) is connected to a seri al interface pin (input or output) that is connected to another device (i nput), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 33-14. malfunction of other device pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal that the v850es/jh3-e and v850es/jj3-e output affects the other device, isolate the signal on the other device side. pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal that the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. v850es/jh3-e, v850es/jj3-e v850es/jh3-e, v850es/jj3-e v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1679 of 1817 sep 19, 2011 (4) reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of si gnals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals ot her than the reset signals from the dedicated flash programmer. figure 33-15. conflict of signals (reset pin) reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal that the reset signal generator outputs conflicts with the signal that the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. v850es/jh3-e, v850es/jj3-e (5) port pins (including nmi) when the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. if the ex ternal device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to v dd via a resistor or connecting to v ss via a resistor. (6) other signal pins connect x1, x2, xt1, xt2, and regc in the same status as that in t he normal operation mode. during flash memory programming, input a low level to t he drst pin or leave it open. do not input a high level. (7) power supply supply the same power (v dd , v ss , ev dd , uv dd , av ref0 , av ss ) as in normal operation mode. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1680 of 1817 sep 19, 2011 33.5 rewriting by self programming 33.5.1 overview the v850es/jh3-e and v850es/jj3-e support a flash macro se rvice that allows the user program to rewrite the internal flash memory by itself. by using this interface a nd a self programming library that is used to rewrite the flash memory with a user application program, t he flash memory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, the user program can be upgraded and constant data note can be rewritten in the field. note be sure not to allocate the program code to the block wh ere the constant data of rewrit ing target is allocated. see 33.2 memory configuration for the block configuration. figure 33-16. concept of self programming application program self programming library flash macro service flash memory flash function execution flash information erase, write v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1681 of 1817 sep 19, 2011 33.5.2 features (1) secure self programming (boot swap function) the v850es/jh3-e and v850es/jj3-e support a boot swap f unction that can exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. by writing the start program to be rewritten to blocks 16 to 31 in advance and then swapping the physical memo ry, the entire area can be safely rewritten even if a power failure occurs during rewriting because the corre ct user program always exists in blocks 0 to 15. figure 33-17. rewriting entire memory area (boot swap) block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block block 0 block 1 : block 15 block 16 block 17 : block 31 block 32 : last block boot swap rewriting blocks 16 to 31 (2) interrupt support instructions cannot be fetched from the flash memory during self-programming. consequently, a user handler written to the flash memory could not be used even if an interrupt has occurred. therefore, in the v850es/jh3-e and v850es/jj3-e, to use an interrupt during self-programming, processing transits to the specific address note in the internal ram. allocate the jump instruction that transits processing to the user interrupt servicing at the specific address note in the internal ram. note nmi interrupt: start address of internal ram maskable interrupt: start address of internal ram + 4 addresses v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1682 of 1817 sep 19, 2011 33.5.3 standard self programming flow the entire processing to rewrite the flash memory by flash self programming is illustrated below. figure 33-18. standard self programming flow flash environment initialization processing erase processing write processing internal verify processing flash memory manipulation flash environment end processing end of processing all blocks end? ? disable accessing flash area ? disable stopping clock ? disable setting of an standby mode other than the halt mode ? disable dma transfer yes no v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1683 of 1817 sep 19, 2011 33.5.4 flash functions table 33-10. flash function list function name outline support flashinit self-programming library initialization flashenv flash environment start/end flashflmdcheck flmd pin check flashstatuscheck hardware proc essing execution status check flashblockerase block erase flashwordwrite data write flashblockiverify internal verification of block flashblockblankcheck blank check of block flashsetinfo flash information setting flashgetinfo flash information acquisition flashbootswap boot swap execution 33.5.5 pin processing (1) flmd0 pin the flmd0 pin is used to set the operation mode when rese t is released and to protect the flash memory from being written during self rewriting. it is therefore necessary to keep the voltage applied to the flmd0 pin at 0 v when reset is released and a normal operation is execut ed. it is also necessary to apply a voltage of v dd level to the flmd0 pin during the self programming mode period via port control before the memory is rewritten. when self programming has been completed, the volt age on the flmd0 pin must be returned to 0 v. figure 33-19. mode change timing reset signal flmd0 pin v dd 0 v v dd 0 v self programming mode normal operation mode normal operation mode caution make sure that the flmd0 pin is at 0 v when reset is released. v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1684 of 1817 sep 19, 2011 33.5.6 internal resources used the following table lists the internal resources used for self programming. these internal resources can also be used freely for purposes other than self programming. table 33-11. internal resources used resource name description stack area an extension of the stack used by the user is used by the library (can be used in both the internal ram and external ram). library code note program entity of library (can be used anywhere other than the flash memory block to be manipulated). application program executed as user application. calls flash functions. maskable interrupt can be used in the user application execution status or self-programming status. to use this interrupt in the self-programming status , since the processing transits to the address of the internal ram start address + 4 addresses, allocate the jump instruction that transits the processing to the user interrupt servicing at the address of the internal ram start address + 4 addresses in advance. nmi interrupt can be used in the user application execution status or self-programming status. to use this interrupt in the self-programming status , since the processing transits to the address of the internal ram start address, allocate the jump instruction that transits the processing to the user interrupt servicing at the internal ram start address in advance. note about resources used, refer to the flash memory self-progra mming library user?s manual . v850es/jh3-e, v850es/jj3-e chapter 33 flash memory r01uh0290ej0300 rev.3.00 page 1685 of 1817 sep 19, 2011 33.6 creating rom code to place order for previously written product before placing an order with renesas electronics for a previ ously written product, the rom code for the order must be created. to create the rom code, use the hex co nsolidation utility (hereafter abbrevia ted to hcu) on the finished programs (hex files) and optional data (such as security settings for flash memory programs). the hcu is a software tool that includes functions required for creating rom code. the hcu can be downloaded at t he renesas electronics website. (1) website http://www2.renesas.com/micro/en/ods/ click version-up service. (2) downloading the hcu to download the hcu, click software for previ ously written flash products and then hcu_gui. remark for details about how to install and use the hcu, s ee the materials (the user?s manual) that comes with the hcu at the above website. 33.6.1 procedure for using rom code to place an order use the hcu to create the rom code by following the pr ocedure below, and then place your order with renesas electronics. for details, see the rom code ordering method information (c10302j). customer renesas electronics decide which product to order. renesas electronics processes the product name and number and creates a record of the transaction. create the rom code note check the rom order details and generate the required data. renesas electronics processes the rom code. note use the hcu to create the rom code for the order. send the order information. renesas electronics sends the order number and other order-related information. send the data required for the rom order. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1686 of 1817 sep 19, 2011 chapter 34 on-chip debug function the on-chip debug function of the v850es/jh3-e and v850es/jj3-e can be implemented by the following two methods. ? using the dcu (debug control unit) on-chip debug function is implemented by the on-chip dcu in the v850es/jh3-e and v850es/jj3-e, with using the drst, dck, dms, ddi, and ddo pins as the debug interface pins. ? not using the dcu on-chip debug function is implemented by minicube2 or t he like, using the user res ources, instead of the dcu. the following table shows the features of the two on-chip debug functions. table 34-1. on-chip debug function features debugging using dcu debugging without using dcu debug interface pins drst, dck, dms, ddi, ddo ? when uartc0 is used rxdc0, txdc0 ? when csif0 is used sif0, sof0, sckf0, hs (p20) ? when csif3 is used sif3, sof3, sckf3, hs (p20) securement of user resources not required required hardware break function 2 points 2 points internal rom area 4 points 4 points software break function internal ram area 2000 points 2000 points real-time ram monitor function note 1 available available dynamic memory modification (dmm) function note 2 available available mask function reset, nmi, intwdt2, hldrq, wait reset pin rom security function 10-byte id code aut hentication 10-byte id code authentication hardware used ninicube, etc. ninicube2, etc. trace function not supported. not supported. debug interrupt interface function (dbint) not supported. not supported. notes 1. this is a function which reads out memo ry contents during program execution. 2. this is a function which rewrites ra m contents during program execution. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1687 of 1817 sep 19, 2011 34.1 debugging with dcu programs can be debugged using the debug interface pins (drst, dck, dms, ddi, and ddo) to connect the on-chip debug emulator (minicube). 34.1.1 connection circuit example figure 34-1. circuit connection example when debu g interface pins are used for communication interface minicube v850es/jh3-e, v850es/jj3-e vdd dck dms ddi ddo drst reset flmd0 gnd ev dd dck dms ddi ddo drst note 2 reset flmd0 note 3 flmd1/pdl5 v ss note 1 status target power notes 1. example of pin connection wh en minicube is not connected 2. a pull-down resistor is provided on chip. 3. for flash memory rewriting 34.1.2 interface signals the interface signals are described below. (1) drst this is a reset input signal for the on-chip debug unit. it is a negative-logic signal that asynchronously initializes the debug control unit. minicube raises the drst signal when it detects v dd of the target system after the integrated d ebugger is started, and starts the on-chip debug unit of the device. when the drst signal goes high, a reset signal is also generated in the cpu. when starting debugging by starti ng the integrated debugger, a cpu reset is always generated. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1688 of 1817 sep 19, 2011 (2) dck this is a clock input signal. it supplies a 20 mhz or 10 mhz clock from minicube. in the on-chip debug unit, the dms and ddi signals are sampled at t he rising edge of the dck signal, and t he data ddo is output at its falling edge. (3) dms this is a transfer mode select signal. the transfer stat us in the debug unit changes depending on the level of the dms signal. (4) ddi this is a data input signal. it is sampled in the on-chip debug unit at the rising edge of dck. (5) ddo this is a data output signal. it is output from the on- chip debug unit at the falling edge of the dck signal. (6) ev dd this signal is used to detect vdd of the target system. if vdd from the tar get system is not det ected, the signals output from minicube (drst, dck, dms, ddi, flmd 0, and reset) go into a high-impedance state. (7) flmd0 the flash self programming function is used for the f unction to download data to the flash memory via the integrated debugger. during flash self programming, the flmd0 pin must be kept high. in addition, connect a pull-down resistor to the flmd0 pin. the flmd0 pin can be controlled in either of the following two ways. <1> to control from minicube connect the flmd0 signal of minicube to the flmd0 pin. in the normal mode, nothing is dr iven by minicube (high impedance). during a break, minicube raises the flmd0 pin to the high level when the download function of the integrated debugger is executed. <2> to control from port connect any port of the device to the flmd0 pin. the same port as the one used by t he user program to realize the flas h self programming function may be used. on the console of the int egrated debugger, make a setting to raise the port pin to high level before executing the download function, or lower the port pi n after executing the download function. for details, refer to the id850qb ver. 3.40 integrated debugge r operation user's manual (u18604e) . (8) reset this is a system reset input pin. if the drst pin is made in valid by the value of th e ocdm0 bit of the ocdm register set by the user program, on-chip debugging cannot be executed. therefore, reset is effected by minicube, using the reset pin, to make the drst pin valid (initialization). v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1689 of 1817 sep 19, 2011 34.1.3 maskable functions reset, nmi, intwdt2, wait, and hldrq signals can be masked. the maskable functions with the de bugger (id850qb) and the correspondi ng v850es/jh3-e and v850es/jj3-e functions are listed below. table 34-2. maskable functions maskable functions with id850qb correspondi ng v850es/jh3-e and v850es/jj3-e functions nmi0 nmi pin input nmi2 non-maskable interrupt request signal (intwdt2) generation stop ? hold hldrq pin input reset reset signal generation by reset pin input, low-voltage detector, clock monitor, or wa tchdog timer (wdt2) overflow wait wait pin input 34.1.4 register (1) on-chip debug mode register (ocdm) the ocdm register is used to select the normal operation mode or on-chip debug mode. this register is a special register and can be written only in a combination of specific sequences (see 3.4.8 special registers ). this register is also used to specify whether a pin provided with an on-chip debug func tion is used as an on-chip debug pin or as an ordinary port/peripheral function pin. it also is used to disconnect the internal pull-down resistor of the p54/intp11/drst pin. the ocdm register can be written only while a low level is input to the drst pin. this register can be read or written in 8-bit or 1-bit units. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1690 of 1817 sep 19, 2011 0 ocdm0 0 1 operation mode ocdm 0 0 0 0 0 0 ocdm0 after reset: 01h note r/w address: fffff9fch when drst pin is low: normal operation mode (in which a pin that functions alternately as an on-chip debug function pin is used as a port/peripheral function pin) when drst pin is high: on-chip debug mode (in which a pin that functions alternately as an on-chip debug function pin is used as an on-chip debug mode pin) selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the p54/intp11/drst pin. < > note reset input sets this register to 01h. after rese t by the wdt2res signal, clock monitor (clm), or low- voltage detector (lvi), however, the valu e of the ocdm register is retained. cautions 1. when using the ddi, ddo, dck, and dms pins not as on-chip debug pins but as port pins after external reset, any of the following actions must be taken. ? input a low level to the p54/intp11/drst pin. ? set the ocdm0 bit. in this case, take the following actions. <1> clear the ocdm0 bit to 0. <2> fix the p54/intp11/drst pin to low level until <1> is completed. 2. the drst pin has an on-chip pull-down resi stor. this resistor is disconnected when the ocdm0 flag is set to 0. ocdm0 flag (1: pull-down on, 0: pull-down off) 10 to 100 k (30 k (typ.)) drst v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1691 of 1817 sep 19, 2011 34.1.5 operation the on-chip debug function is made invalid under the conditions shown in the table below. when this function is not used, keep the drst pin low until the ocdm.ocdm0 flag is cleared to 0. ocdm0 flag drst pin 0 1 l invalid invalid h invalid valid remark l: low-level input h: high-level input figure 34-2. timing when on-chip debug function is not used low-level input after ocdm0 bit is cleared, high level can be input/output. clearing ocdm0 bit releasing reset reset ocdm0 p54/intp11/drst 34.1.6 cautions (1) if a reset signal is input (from the target system or a reset signal from an internal reset source) during run (program execution), the break function may malfunction. (2) even if the reset signal is masked by the mask function, the i/o buffer (port pin) may be reset if a reset signal is input from a pin. (3) pin reset during a break is masked a nd the cpu and peripheral i/o are not reset. if pin reset or internal reset is generated as soon as the flash memory is rewritten by dmm or read by the ram monitor function while the user program is being executed, the cpu and peripheral i/o may not be correctly reset. (4) in the on-chip debug mode, the ddo pin is forcibly set to the high-level output. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1692 of 1817 sep 19, 2011 34.2 debugging without using dcu the following describes how to implement an on-chip debu g function using minicube2 wit h pins for uartc0 (rxdc0 and txdc0), pins for csif0 (sif0, sof0, sckf0, and hs (p20 )), or pins for csif3 (sif3, sof3, sckf3, and hs (p20)) as debug interfaces, without using the dcu. 34.2.1 circuit connection examples figure 34-3. circuit connection example when uart c0/csif0/csif3 is used for communication interface qb-mini2 v850es/jh3-e, v850es/jj3-e gnd v dd v dd reset_out rxd/si note 1 vdd txd/so note 1 sck hs clk note 2 flmd1 note 3 flmd0 note 3 reset_in note 4 v ss txdc0/sof0/sof3 v dd rxdc0/sif0/sif3 sckf0/sckf3 flmd1 reset circuit flmd0 port x 100 10 k 1 to 10 k 1 k reset signal 10 k 1 to 10 k 1 to 10 k 3 to 10 k 1 to 10 k v dd note 5 v dd v dd hs (p20) reset m in ic u b e 2 m in ic u b e 2 notes 1. connect txdc0/sof0/sof3 (transmit side) of the v850es/jh3-e or v850es/jj3-e to rxd/si (receive side) of the target connector, and txd/so (transmit side) of the target connector to rxdc0/sif0/sif3 (receive side) of the v850es/jh3-e or v850es/jj3-e. 2. this pin may be used to supply a clock from minicube2 during flash memory programming. for details, refer to chapter 33 flash memory . 3. because this pin is an (unused) input during debuggi ng, its alternate function can be used. note that, within minicube2, a 100 k pull-down resistor is connected. 4. this connection is designed assuming that the reset signal is output from the n-ch open-drain buffer (output resistance: 100 or less). 5. the circuit enclosed by a dashed line is designed for flash self programming, which controls the flmd0 pin via ports. use the port for inputting or outputting the high level. when flash self programming is not performed, a pull-down resistance for the flmd0 pin can be within 1 to 10 k . remark refer to table 34-3 for pins used when uartc0, csif0, or csif3 is used for communication interface. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1693 of 1817 sep 19, 2011 table 34-3. wiring between v850es/jh3-e and minicube2 pin configuration of minicube2 (qb-mini2) wi th csif0-hs with csif3-hs with uartc0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input pin to receive commands and data from v850es/jh3-e p41/sof0 4 p914/sof3 79 p30/txdc0 28 so/txd output pin to transmit commands and data to v850es/jh3-e p40/sif0 3 p913/sif3 78 p31/rxdc0 29 sck output clock output pin for 3-wire serial communication p42/sckf0 5 p915/sckf3 80 not needed ? clk note output clock output pin to v850es/jh3-e not needed note ? not needed note ? not needed note ? reset_out output reset output pin to v850es/jh3-e reset 18 reset 18 reset 18 flmd0 output output pin to set v850es/jh3-e to debug mode or programming mode flmd0 12 flmd0 12 flmd0 12 flmd1 output output pin to set programming mode pdl5/ad5/ flmd1 92 pdl5/ad5 flmd1 92 pdl5/ad5/ flmd1 92 hs input handshake signal for csi0 + hs communication p20 38 p20 38 not needed ? v ss 15, 34, 60, 84, 101, 117 v ss 15, 34, 60, 84, 101, 117 v ss 15, 34, 60, 84, 101, 117 gnd ? ground av ss 2 av ss 2 av ss 2 reset_in input reset input pin on the target system note it is used as the clock output of the flash programmer for minicube2. for details, refer to chapter 33 flash memory . v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1694 of 1817 sep 19, 2011 table 34-4. wiring between v850es/jj3-e and minicube2 pin configuration of minicube2 (qb-mini2) wi th csif0-hs with csif3-hs with uartc0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input pin to receive commands and data from v850es/jj3-e p41/sof0 4 p914/sof3 67 p30/txdc0 28 so/txd output pin to transmit commands and data to v850es/jj3-e p40/sif0 3 p913/sif3 66 p31/rxdc0 29 sck output clock output pin for 3-wire serial communication p42/sckf0 5 p915/sckf3 68 not needed ? clk note output clock output pin to v850es/jj3-e not needed note ? not needed note ? not needed note ? reset_out output reset output pin to v850es/jj3-e reset 18 reset 18 reset 18 flmd0 output output pin to set v850es/jj3-e to debug mode or programming mode flmd0 12 flmd0 12 flmd0 12 flmd1 output output pin to set programming mode pdl5/ad5/ flmd1 98 pdl5/ad5/ flmd1 98 pdl5/ad5/ flmd1 98 hs input handshake signal for csi0 + hs communication p20 38 p20 38 not needed ? v ss 15, 34, 66, 90, 107, 131 v ss 15, 34, 66, 90, 107, 131 v ss 15, 34, 66, 90, 107, 131 gnd ? ground av ss 2 av ss 2 av ss 2 reset_in input reset input pin on the target system note it is used as the clock output of the flash programmer for minicube2. for details, refer to chapter 33 flash memory . v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1695 of 1817 sep 19, 2011 34.2.2 maskable functions only reset signals can be masked. the functions that can be masked in the debugger (id850qb) and the correspon ding functions of the v850es/jh3-e and v850es/jj3-e are listed below. table 34-5. maskable functions functions maskable in id850qb corresponding functions of v850es/jh3-e and v850es/jj3-e nmi0 ? nmi1 ? nmi2 ? stop ? hold ? reset reset signal generation by reset pin input wait ? v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1696 of 1817 sep 19, 2011 34.2.3 securement of user resources the user must prepare the following to perform communi cation between minicube2 and the target device and implement each debug function. these it ems need to be set in the user program or using the compiler options. (1) securement of memory space the shaded portions in figure 34-4 are the areas rese rved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces. these spaces must be secured so as not to be used by the user program. (2) security id setting the id code must be embedded in the area between 0 000070h and 0000079h in figure 34-4, to prevent the memory from being read by an unauthorized person. for details, refer to 34.3 rom security function . v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1697 of 1817 sep 19, 2011 figure 34-4. memory spaces where de bug monitor programs are allocated csi/uart receive interrupt vector (4 bytes) reset vector (4 bytes) interrupt vector for debugging (4 bytes) (2 kb) security id area (10 bytes) : debugging area note 1 0000060h 00004b0h note 2 0000070h 0000000h internal rom (16 bytes) 3ffefffh 3ffeff0h access-prohibited area internal ram internal rom area internal ram area 3ff0000h notes 1. address values vary depending on the product. internal rom size address value pd70f3778 256 kb 003f800h to 003ffffh pd70f3779, 70f3781 384 kb 005f800h to 005ffffh pd70f3780, 70f3782, 70f3783, 70f3784, 70f3785, 70f3786, 512 kb 007f800h to 007ffffh 2. this is the address when csif0 is used. it starts at 0000510h when csif3 is used, and at 00004f0h when uartc0 is used. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1698 of 1817 sep 19, 2011 (3) reset vector a reset vector includes the jump in struction for the debug monitor program. [how to secure areas] it is not necessary to secure this area intentionally. when downloading a program, howe ver, the debugger rewrites the reset vector in accordance with the following cases. if the rewritten pattern does not match the following cases, the debugger generates an error (f 0c34 when using the id850qb). (a) when two nop instructions ar e placed in succession from address 0 before rewriting after rewriting 0x0 nop jumps to debug monitor program at 0x0 0x2 nop 0x4 xxxx 0x4 xxxx (b) when two 0xffff are successively placed fr om address 0 (alread y erased device) before rewriting after rewriting 0x0 0xffff jumps to debug monitor program at 0x0 0x2 0xffff 0x4 xxxx 0x4 xxxx (c) the jr instruction is placed at address 0 (when using ca850) before rewriting after rewriting 0x0 jr disp22 jumps to debug monitor program at 0x0 0x4 jr disp22 - 4 (d) mov32 and jmp are placed in succession from address 0 (when using iar compiler iccv850) before rewriting after rewriting 0x0 mov imm32,reg1 jumps to debug monitor program at 0x0 0x6 jmp [reg1] 0x4 mov imm32,reg1 0xa jmp [reg1] (e) the jump instruction for the debug monitor program is placed at address 0 before rewriting after rewriting jumps to debug monitor program at 0x0 no change v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1699 of 1817 sep 19, 2011 (4) securement of area for debug monitor program the shaded portions in figure 34-4 are the areas wher e the debug monitor program is allocated. the monitor program performs initialization processing for debug communi cation interface and run or break processing for the cpu. the internal rom area must be filled with 0xff. this area must no t be rewritten by the user program. [how to secure areas] it is not necessarily required to secure this area if the user program does not use this area. to avoid problems that may occur during the debugger start up, however, it is recommended to secure this area in advance, using the compiler. the following shows examples for securing the area, us ing the renesas electronics compiler ca850. add the assemble source file and link directive code, as shown below. ? assemble source (add the following code as an assemble source file.) -- secures 2 kb space for monitor rom section .section "monitorrom", const .space 0x800, 0xff -- secures interrupt vector for debugging .section "dbg0" .space 4, 0xff -- secures interrupt vector for serial communication -- change the section name according to the serial communication mode used .section "intcf0r" .space 4, 0xff -- secures 16-byte space for monitor ram section .section "monitorram", bss .lcomm monitorramsym, 16, 4 -- defines symbol monitorramsym ? link directive (add the following code to the link directive file.) the following shows an example when the internal rom has 512 kb (end address is 007ffffh) and internal ram has 60 kb (end address is 3ffefffh). mromseg : !load ?r v0x07f800{ monitorrom = $progbits ?a monitorrom; }; mramseg : !load ?rw v0x03ffeff0{ monitorram = $nobits ?aw monitorram; }; v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1700 of 1817 sep 19, 2011 (5) securement of communication serial interface uartc0, csif0, or csif3 is used for communication between minicube2 and the target system. the settings related to the serial interface modes are performed by th e debug monitor program, but if the setting is changed by the user program, a communication error may occur. to prevent such a problem from occurring, communication serial interface must be secured in the user program. [how to secure communica tion serial interface] ? on-chip debug mode register (ocdm) for the on-chip debug function using th e uartc0, csif0, or csif3, set the ocdm register functions to normal mode. be sure to set as follows. ? input low level to the p56/intp05/drst pin. ? set the ocdm0 bit as shown below. <1> clear the ocdm0 bit to 0. <2> fix the p56/intp05/drst pin input to low leve l until the processing of <1> is complete. ? serial interface registers do not set the registers related to csif0, csif3, or uartc0 in the user program. ? interrupt mask register when csif0 is used, do not mask the transfer end interru pt (intcf0r). when csif 3 is used, do not mask the transfer end interrupt (intcf3r). when uartc0 is used, do not mask t he reception completion interrupt (intuc0r). (a) when csif0 is used cf0ric 0 6543210 7 (b) when csif3 is used cf3ric 0 6543210 7 (c) when uartc0 is used uc0ric 0 6543210 7 remark : don?t care v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1701 of 1817 sep 19, 2011 ? port registers when uartc0 is used when uartc0 is used, port registers are set to make the txdc0 and rxdc0 pins valid by the debug monitor program. do not change the following register setti ngs with the user program during debugging. (the same value can be overwritten.) pfc3 00 6543210 7 pfce3 00 6543210 7 pmc3 11 6543210 7 remark : don?t care ? port registers when csif0 is used when csif0 is used, port registers are set to make the sif0, sof0, sckf0, and hs (p20) pins valid by the debug monitor program. do not change the following regi ster settings with the user program during debugging. (the same value can be overwritten.) (a) sif0, sof0, and sckf0 settings pmc4 111 6543210 7 pfc4 0 00 6543210 7 pfce4 000 6543210 7 (b) hs (p20 pin) settings pm2 0 14 13 12 11 10 9 8 15 p2 note 14 13 12 11 10 9 8 15 note writing to this bit is prohibited. the port values corresponding to the hs pin are changed by the monitor program according to the debugger status. to perform port register settings in 8-bit units, the user program can usually use read-modify-write. if an interrupt fo r debugging occurs before writing, however, an unexpected operation may be performed. remark : don?t care v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1702 of 1817 sep 19, 2011 ? port registers when csif3 is used when csif3 is used for communication, port registers are set to make the sif3, sof3, sckf3, and hs (p20) pins valid by the debug monitor program. do not chan ge the following register setti ngs with the user program during debugging. (the same value can be overwritten.) (a) sif3, sof3, and sckf3 settings pmc9h 1 11 14 13 12 11 10 9 8 15 pfc9h 00 14 13 12 11 10 9 8 15 0 pfce9h 00 14 13 12 11 10 9 8 15 0 (b) hs (p20 pin) settings pm2 0 14 13 12 11 10 9 8 15 p2 note 14 13 12 11 10 9 8 15 note writing to this bit is prohibited. the port values corresponding to the hs pin are changed by the monitor program according to the debugger status. to perform port register settings in 8-bit units, the user program can usually use read-modify-write. if an interrupt fo r debugging occurs before writing, however, an unexpected operation may be performed. remark : don?t care v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1703 of 1817 sep 19, 2011 34.2.4 cautions (1) handling of device that was used for debugging do not mount a device that was us ed for debugging on a mass-produced product, because the flash memory was rewritten during debugging and the numbe r of rewrites of the flash memory cannot be guaranteed. moreover, do not embed the debug monitor program into mass-produced products. (2) when breaks cannot be executed forced breaks cannot be executed if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, which is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between minicube2 and the target device is uartc0, and the main clock has been stopped (3) when pseudo real-ti me ram monitor (rrm) function and dmm function do not operate the pseudo rrm function and dmm function do not operat e if one of the following conditions is satisfied. ? interrupts are disabled (di) ? interrupts issued for the serial interface, which is used for communication between minicube2 and the target device, are masked ? standby mode is entered while standby releas e by a maskable interrupt is prohibited ? mode for communication between minicube2 and the target device is uartc0, and the main clock has been stopped ? mode for communication between minicube2 and the target device is uartc0, and a clock different from the one specified in the debugger is used for communication (4) standby release with pseudo rrm and dmm functions enabled the standby mode is released by the pseudo rrm function and dmm function if one of the following conditions is satisfied. ? mode for communication between minicube2 and the target device is csif0 or csif3 ? mode for communication between minicube2 and the target device is uartc0, and the main clock has been supplied. (5) rewriting to peripheral i/o registers that re quires a specific sequenc e, using dmm function peripheral i/o registers that requires a specific sequence cannot be rewritt en with the dmm function. (6) flash self programming if a space where the debug monitor program is allocated is rewritten by flash self programming, the debugger can no longer operate normally. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1704 of 1817 sep 19, 2011 34.3 rom security function 34.3.1 security id the flash memory versions of the v850es/jh3-e and v850es/jj3-e perform authent ication using a 10-byte id code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on- chip debug emulator. set the id code in the 10-byte on-chip flash memory ar ea from 0000070h to 0000079h to allow the debugger perform id authentication. if the ids match, the security is released and reading flash memory and using the on-chip debug emulator are enabled. ? set the 10-byte id code to 0000070h to 0000079h. ? bit 7 of 0000079h is the on-chip debug emulator enable flag. (0: disable, 1: enable) ? when the on-chip debug emulator is started, the debugger requ ests id input. when the id code input on the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if the on-chip debug emul ator enable flag is 0, even if the id codes match. figure 34-5. security id area 0000079h 0000070h 0000000h security id (10 bytes) caution after the flash memory is erased , 1 is written to the entire area. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1705 of 1817 sep 19, 2011 34.3.2 setting the following shows how to set the id code as shown in table 34-6. when the id code is set as shown in t able 34-6, the id code input in the conf iguration dialog box of the id850qb is ?123456789abcdef123d4? (the id code is case-insensitive). table 34-6. id code address value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9a 0x75 0xbc 0x76 0xde 0x77 0xf1 0x78 0x23 0x79 0xd4 the id code can be specified for the devic e file that supports ca850 ver. 3.10 or later and the security id using the pm+ compiler common option setting. v850es/jh3-e, v850es/jj3-e chapter 34 on-chip debug function r01uh0290ej0300 rev.3.00 page 1706 of 1817 sep 19, 2011 [program example (when usi ng ca850 ver. 3.10 or later)] #-------------------------------------- # securityid #-------------------------------------- .section "security_id" --interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xf1debc9a --4-7 byte code .hword 0xd423 --8-9 byte code remark add the above program example to the startup files. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1707 of 1817 sep 19, 2011 chapter 35 electrical specifications 35.1 absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = uv dd = av ref0 ? 0.5 to +4.6 v ev dd v dd = ev dd = uv dd = av ref0 ? 0.5 to +4.6 v uv dd v dd = ev dd = uv dd = av ref0 ? 0.5 to +4.6 v av ref0 v dd = ev dd = uv dd = av ref0 ? 0.5 to +4.6 v v ss v ss = av ss ? 0.5 to +0.5 v supply voltage av ss v ss = av ss ? 0.5 to +0.5 v v i1 p40 to p45, pcm0 to pcm3, pcs0, pcs2, pcs3, pct0, pct1, pct4, pct6 pdl0 to pdl15, pdh0 to pdh7, reset, flmd0 ? 0.5 to ev dd + 0.5 note 1 v v i2 udmf, udpf ? 0.5 to uv dd + 0.5 note 1 v v i3 x1, x2, xt1, xt2 ? 0.5 to v ro note 2 + 0.5 note 1 v input voltage v i5 p02, p03, p10, p20 to p27, p30 to p37, p46 to p48 p50 to p59, p90 t p915 ? 0.5 to +6.0 v analog input voltage v ian p70 to p711 ? 0.5 to av ref0 + 0.5 note 1 v notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. on-chip regulator output voltage (2.5 v (typ.)) cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product a nd an external circuit is possible, if the output pins can be set to the high-impedance state and th e output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at which the product is on the verge of suffering physical damage. therefore the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. the ratings and cond itions indicated for dc characteristi cs and ac characteristics represent the quality assurance range during normal operation. remark unless specified otherwise, the characteristics of alter nate-function pins are the sa me as those of port pins. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1708 of 1817 sep 19, 2011 (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin 4 ma p02, p03, p20 to p27, p30 to p37 p40 to p48, p50 to p59, p90 to p915 total of all pins 50 ma per pin 4 ma pcm0 to pcm3, pcs0, pcs2, pcs3 pct0, pct1, pct4, pct6 pdl0 to pdl15, pdh0 to pdh7 total of all pins 50 ma per pin 4 ma udmf, udpf total of all pins 8 ma per pin 4 ma output current, low i ol p70 to p711 total of all pins 20 ma per pin ? 4 ma p02, p03, p20 to p27, p30 to p37 p40 to p48, p50 to p59, p90 to p915 total of all pins ? 50 ma per pin ? 4 pcm0 to pcm3, pcs0, pcs2, pcs3 pct0, pct1, pct4, pct6 pdl0 to pdl15, pdh0 to pdh7 total of all pins ? 8 per pin ? 4 ma udmf, udpf total of all pins ? 8 ma per pin ? 4 ma output current, high i oh p70 to p711 total of all pins ? 20 ma in normal operation ? 40 to +85 c operating ambient temperature t a in flash memory programming ? 40 to +85 c storage temperature t stg ? 40 to +125 c cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product a nd an external circuit is possible, if the output pins can be set to the high-impedance state and th e output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute m aximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at which the product is on the verge of suffering physical damage. therefore the product must be used under conditions that ensure that the absolute maxi mum ratings are not exceeded. the ratings and cond itions indicated for dc characteristi cs and ac characteristics represent the quality assurance range during normal operation. remark unless specified otherwise, the characteristics of alter nate-function pins are the sa me as those of port pins. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1709 of 1817 sep 19, 2011 35.2 capacitance (t a = 25 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i/o capacitance c io f x = 1 mhz measured pins returned to 0 v 10 pf 35.3 operating conditions (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) supply voltage internal system clock frequency conditions v dd ev dd uv dd av ref0 unit c = 4.7 f, a/d converter stopped, ethernet stopped, usb stopped 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 v f xx = 3 to 6.25 mhz (during clock- through operation) f xx = 24 to 50 mhz (during pll operation) c = 4.7 f, a/d converter operating, ethernet operating, usb operating 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v f xt = 32.768 khz c = 4.7 f, note 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 2.85 to 3.6 v note when the system is operat ing on the subclock (f xt = 32.768 khz), the a/d converter, d/a converter, and usb controller do not operate. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1710 of 1817 sep 19, 2011 35.4 oscillator characteristics 35.4.1 main clock oscillator characteristics (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) resonator circuit example paramete r conditions min. typ. max. unit oscillation frequency (f x ) note 1 3 6.25 mhz after reset is released 2 16 /f x s after stop mode is released note 3 ms ceramic resonator/ crystal resonator x2 x1 oscillation stabilization time note 2 after idle2 mode is released note 3 s notes 1. the oscillation frequency shown above indicates only os cillator characteristics. use the v850es/jh3-e and v850es/jj3-e so that the internal operation c onditions do not exceed the ratings shown in ac characteristics and dc characteristics . 2. time required from start of oscillation until the resonator stabilizes. 3. the value varies depending on the setting of the osts register. cautions 1. when using the usb controller, be sure to use a ceramic resonator or crystal resonator with an accuracy of 6 mhz 500 ppm or less when using the internal clock as the usb clock. when using the external clock input by the uclk pin, be sure to supply a clock with an accuracy of 48 mhz 500 ppm or less. if the usb clock accuracy drops, the tran smission/reception data cannot satisfy the usb specification. 2. when using the main clock oscillator, wire as foll ows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 3. when the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1711 of 1817 sep 19, 2011 35.4.2 subclock oscillator characteristics (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) resonator circuit example parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator xt2 xt1 oscillation stabilization time note 2 10 s notes 1. the oscillation frequency shown above indicates only oscillator characteristics. use the v850es/jh3-e and v850es/jj3-e so that the internal operation c onditions do not exceed the ratings shown in ac characteristics and dc characteristics . 2. time required from when v dd reaches the oscillation voltage range (2.8 5 v (min.)) to when the crystal resonator stabilizes. cautions 1. when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-am plitude circuit for reduci ng power consumption, and is more prone to malfunction due to noise than the ma in clock oscillator. particular care is therefore required with the wiring method when the subclock is used. 3. for the resonator selection and oscillator constant, customers are re quested to either evaluate the oscillation themselves or apply to the r esonator manufacturer for evaluation. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1712 of 1817 sep 19, 2011 35.4.3 pll characteristics (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit input frequency f x 3 6.25 mhz clock-through mode 3 6.25 mhz output frequency f xx pll mode ( 8) 24 50 mhz lock time t pll 800 s 35.4.4 internal oscill ator characteristics (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit output frequency f r 100 220 400 khz v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1713 of 1817 sep 19, 2011 35.5 dc characteristics 35.5.1 i/o level (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit v ih1 reset, flmd0, p40 to p43, p45 pdh0, pdh2 to pdh5 0.8ev dd ev dd v v ih2 p02, p03,p20 to p27, p30 to p37 p46 to p48, p50 to p59, p90 to p915 0.8ev dd 5.5 v v ih3 p44, pdl0 to pdl15, pdh1 to pdh6, pdh7, pcm0 to pcm3, pcs0, pcs2, pcs3, pct0, pct1, pct4, pct6 0.7ev dd ev dd v v ih4 udpf, udmf 2.0 uv dd v input voltage, high v ih5 p70 to p711 0.7av ref0 av ref0 v v il1 reset, flmd0, p40 to p43, p45 pdh0, pdh2 to pdh5 v ss 0.2ev dd v v il2 p02, p03,p20 to p27, p30 to p37 p46 to p48, p50 to p59, p90 to p915 v ss 0.2ev dd v v il3 p44, pdl0 to pdl15, pdh1 to pdh6, pdh7, pcm0 to pcm3, pcs0, pcs2, pcs3, pct0, pct1, pct4, pct6 v ss 0.3ev dd v v il4 udpf, udmf v ss 0.8 v input voltage, low v il5 p70 to p711 av ss 0.3av ref0 v input leakage current, high i lih v i = v dd = ev dd = uv dd = av ref0 5 a input leakage current, low i lil v i = 0 v ? 5 a output leakage current, high i loh v o = v dd = ev dd = uv dd = av ref0 5 a output leakage current, low i lol v o = 0 v ? 5 a remark unless specified otherwise, the characteristics of alter nate-function pins are the sa me as those of port pins. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1714 of 1817 sep 19, 2011 (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit per pin i oh = ? 1.0 ma ev dd ? 1.0 ev dd v v oh1 note per pin i oh = ? 100 a ev dd ? 0.5 ev dd v per pin i oh = ? 0.4 ma av ref0 ? 1.0 av ref0 v v oh2 p70 to p711 per pin i oh = ? 100 a av ref0 ? 0.5 av ref0 v output voltage, high v oh4 udpf, udmf r l = 15 k (connect to v ss ) 2.8 v v ol1 note per pin i ol = 1.0 ma 0 0.4 v v ol2 p70 to p711 per pin i ol = 1.0 ma 0 0.4 v output voltage, low v ol3 udpf, udmf r l = 1.5 k (connect to uv dd ) 0 0.3 v software pull-down resistor r 1 p54 v i = v dd 10 30 100 k note p02, p03, p20 to p27, p30 to p37, p40 to p48, p50 to p59, p90 to p9 15, pcm0 to pcm3, pcs0, pcs2, pcs3, pct0, pct1, pct4, pct6, pdh0 to pdh7, pdl0 to pdl15 remarks 1. unless specified otherwise, the characteristics of alter nate-function pins are the sa me as those of port pins. 2. when the i oh and i ol conditions are not satisfied for one pin but the total value of all pins is satisfied, only that pin is deemed to not satisfy the dc characteristics. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1715 of 1817 sep 19, 2011 35.5.2 supply current (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit f xx = 50 mhz (f x = 6.25 mhz) peripheral function operating 137 ma i dd1 normal operation f xx = 50 mhz (f x = 6.25 mhz) usbf operating 57 ma i dd2 halt mode f xx = 50 mhz (f x = 6.25 mhz) peripheral function operating 84 ma i dd3 idle1 mode f xx = 50 mhz (f x = 6.25 mhz), pll on 4.3 10 ma i dd4 idle2 mode f xx = 6.25 mhz (f x = 6.25 mhz), pll off 0.5 1 ma i dd5 subclock operation mode f xt = 32.768 khz, main clock stopped, internal oscillator stopped 120 600 a ? 40 t a +25 c 13 25 a i dd6 sub-idle mode f xt = 32.768 khz, main clock stopped, internal oscillator stopped 25 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1717 of 1817 sep 19, 2011 35.7 ac characteristics (1) ac test input measurement points (v dd , av ref0 , ev dd ) v dd 0 v v ih v il v ih v il measurement points (2) ac test output measurement points v oh v ol v oh v ol measurement points (3) load conditions dut (device under measurement) c l = 50 pf caution if the load cap acitance exceeds 50 pf due to the circuit configur ation, bring the load capacitance of the device to 50 pf or less by in serting a buffer or by some other means. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1718 of 1817 sep 19, 2011 35.7.1 clkout output timing (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <1> 20 ns 31.25 s high-level width t wkh <2> t cyk /2 ? 6 ns low-level width t wkl <3> t cyk /2 ? 6 ns rise time t kr <4> 6 ns fall time t kf <5> 6 ns clock timing clkout (output) <1> <2> <3> <4> <5> v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1719 of 1817 sep 19, 2011 35.7.2 bus timing (1) in multiplexed bus mode/separate bus mode (a) read/write cycle (clkout asynchronous) (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t dast <6> (0.5 + t asw )t ? 9 ns address hold time (from astb ) t hsta <7> (0.5 + t ahw )t ? 8 ns delay time from rd to address float t frda <8> 5 ns data input setup time from address t daid <9> (2 + n + t asw + t ahw )t ? 25 ns data input setup time from rd t drdid2 <10> (1 + n)t ? 15 ns delay time from astb to rd t dstrd delay time from astb to wrm t dstwr <11> (0.5 + t ahw )t ? 4 ns data input hold time (from rd ) t hrdid <12> 0 ns address output delay time from rd t drdod <13> (1 + i)t ? 3 ns delay time from rd to astb t drdst delay time from wrm to astb t dwrst <14> 0.5t ? 5 ns delay time from rd to astb t drdst <15> (1.5 + i + t asw )t ? 4 ns rd low-level width t wrdl wrm low-level width t wwrl <16> (1 + n)t ? 10 ns astb high-level width t wsth <17> (1 + i + t asw )t ? 10 ns data output delay time from wrm t dwrod <18> 9 ns data output delay time (from wrm ) t dodwr <19> (1 + n)t ? 11 ns data output hold time (from wrm ) t hwrod <20> t ? 3 ns t sawt1 <21> n 1 (1.5 + t asw + t ahw )t ? 25 ns wait setup time (to address) t sawt2 <22> (1.5 + n + t asw + t ahw )t ? 25 ns t hawt1 <23> n 1 (0.5 + n + t asw + t ahw )t ns wait hold time (from address) t hawt2 <24> (1.5 + n + t asw + t ahw )t ns t sstwt1 <25> n 1 (1 + t ahw )t ? 15 ns wait setup time (to astb ) t sstwt2 <26> (1 + n + t ahw )t ? 15 ns t hstwt1 <27> n 1 (n + t ahw )t ns wait hold time (from astb ) t hstwt2 <28> (1 + n + t ahw )t ns address hold time from rd t hrda2 <29> (1 + i)t ? 5 ns address hold time from wrm t hwra2 <30> t ? 5 ns hold time from rd to csn t hrdc2 <31> i 1 t ? 5 ns hold time from wrm to csn t hwrc2 <32> t ? 5 ns remarks 1. t asw : number of address setup wait clocks t ahw : number of address hold wait clocks 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: number of idle states inserted after a read cycle (0 or 1) 6. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1720 of 1817 sep 19, 2011 read cycle (clkout asynchronous): in mu ltiplexed bus mode/separate bus mode clkout (output) a0 to a23 (output) note2 ad0 to ad15 (i/o) astb (output) cs0, cs2, cs3 (output) note1 rd (output) wait (input) t1 t2 tw t3 ti t1 data address hi-z <6> <7> <17> <9> <31> <12> <14> <10> <11> <25> <27> <26> <28> <21> <23> <22> <24> <16> <8> <13> <29> <15> notes1. v850es/jj3-e only, v850es/jh3-e is cs0, cs2 2. v850es/jj3-e only, v850es/jh3-e is a0 to a21 remark wr0 and wr1 are high level. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1721 of 1817 sep 19, 2011 write cycle (clkout asynchronous): in mu ltiplexed bus mode/separate bus mode clkout (output) ad0 to ad15 (i/o) astb (output) cs0, cs2 cs3 (output) note1 wr0, wr1 (output) wait (input) t1 t2 tw t3 t1 data address <25> <27> <26> <28> <21> <23> <22> <24> <6> <17> <7> <14> <32> <30> <20> <19> <16> <11> <18> a0 to a23 (output) note2 notes1. v850es/jj3-e only, v850es/jh3-e is cs0, cs2 2. v850es/jj3-e only, v850es/jh3-e is a0 to a21 remark rd is high level. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1722 of 1817 sep 19, 2011 (b) read/write cycle (clkout synchronous): in multiplexed bus mode/separate bus mode (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <33> 0 17 ns delay time from clkout to address float t fka <34> 0 15 ns delay time from clkout to astb t dkst <35> 0 12 ns delay time from clkout to rd, wrm t dkrdwr <36> 0 12 ns data input setup time (to clkout ) t sidk <37> 16 ns data input hold time (from clkout ) t hkid <38> 0 ns data output delay time from clkout t dkod <39> 17 ns wait setup time (to clkout ) t swtk <40> 16 ns wait hold time (from clkout ) t hkwt <41> 0 ns address hold time from clkout t hka2 <42> 0 ns data output hold time from clkout t hkod2 <43> 0 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. read cycle (clkout synchronous): in mult iplexed bus mode/separate bus mode clkout (output) a0 to a23 (output) note2 ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 ti t1 data address hi-z <33> <35> <36> <34> <42> <35> <42> <36> <40> <40> <41> <41> <37> <38> cs0, cs2, cs3 (output) note1 notes1. v850es/jj3-e only, v850es/jh3-e is cs0, cs2 2. v850es/jj3-e only, v850es/jh3-e is a0 to a21 remark wr0 and wr1 are high level. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1723 of 1817 sep 19, 2011 write cycle (clkout synchronous): in mult iplexed bus mode/separate bus mode clkout (output) ad0 to ad15 (i/o) astb (output) cs0, cs2, cs3 (output) note1 wr0, wr1 (output) wait (input) t1 t2 tw t3 t1 data address <33> <35> <36> <36> <41> <41> <40> <40> <35> <43> <42> <33> <39> a0 to a23 (output) note2 notes1. v850es/jj3-e only, v850es/jh3-e is cs0, cs2 2. v850es/jj3-e only, v850es/jh3-e is a0 to a21 remark rd is high level. v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1724 of 1817 sep 19, 2011 (2) during bus hold (a) clkout asynchronous (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq high-level width t whqh <44> t + 16 ns hldak low-level width t whal <45> t ? 10 ns delay time from hldak to bus output t dhac <46> ? 7 ns delay time from hldrq to hldak t dhqha1 <47> 2.5t ns delay time from hldrq to hldak t dhqha2 <48> 0.5t + 17 1.5t + 31 ns delay time from bus float to hldak t dfha <49> 0 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. bus hold (clkout asynchronous) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th ti ti hi-z cs0, cs2, cs3 (output) note hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <44> <48> <45> <49> <46> <47> note. v850es/jj3-e only, v850es/jh3-e is cs0, cs2 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1725 of 1817 sep 19, 2011 (b) clkout synchronous (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit hldrq setup time (to clkout ) t shqk <50> 16 ns hldrq hold time (from clkout ) t hkhq <51> 0 ns delay time from clkout to bus float t dkf <52> 15 ns delay time from clkout to hldak t dkha1 <53> 1 15 ns delay time from clkout to hldak t dkha2 <54> 1 15 ns delay time from clkout to data output t dkbo <55> 1 17 ns remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. bus hold (clkout synchronous) clkout (output) hldrq (input) hldak (output) address bus (output) data bus (i/o) th th th t2 t3 ti ti hi-z hi-z astb (output) rd (output), wr0, wr1 (output) hi-z hi-z <50> <50> <54> <55> <53> <51> <52> cs0, cs2, cs3 (output) note note. v850es/jj3-e only, v850es/jh3-e is cs0, cs2 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1726 of 1817 sep 19, 2011 35.8 basic operation (1) power on/power off/reset timing (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit time from ev dd, uv dd to v dd t rel <56> 0 ns time from ev dd , uv dd to av ref0 t rea <57> 0 t rel ns time from v dd to reset t rer <58> 500 + t reg note ns analog noise elimination (during flash erase/writing) 500 ns reset low-level width t wrsl <59> analog noise elimination 500 ns time from reset to v dd t fre <60> 500 ns time from v dd to ev dd , uv dd t fel <61> 0 ns time from av ref0 to ev dd , uv dd t fea <62> 0 t fel ns note depends on the on-chip regulator characteristics. v dd ev dd , uv dd v i v i v i v i av ref0 reset (input) <56> <58> <60> <59> <57> <61> <62> v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1727 of 1817 sep 19, 2011 (2) reset, interrupt timing (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit reset input low-level width t wrsl 500 ns nmi high-level width t wnih analog noise elimination 500 ns nmi low-level width t wnil analog noise elimination 500 ns n = 0 to 18 (analog noise elimination) 500 ns intpn high-level width t with n = 2 (digital noise elimination) 3t smp + 20 ns n = 0 to 18 (analog noise elimination) 500 ns intpn low-level width t witl n = 2 (digital noise elimination) 3t smp + 20 ns remark t smp : set by the noise elimination control r egister (intnfc). selectable from f xx /64, f xx /128, f xx /256, f xx /512, and f xx /1024. (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit krn high-level width t wkrh analog noise elimination 500 ns krn low-level width t wkrl analog noise elimination 500 ns remark n = 0 to 7 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1728 of 1817 sep 19, 2011 (3) timer timing (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit tab00 to tab03,tab10 to tab13, evtab1, trgab1 12t + 20 ns ti high-level width t tih tiaa00, tiaa01, tiaa10, tiaa11, tiaa20, tiaa21, tiaa30, tiaa31, tiaa40, tiaa41,tiaa50, tiaa51 3t smp1 + 20 ns tab00 to tab03, tab10 to tab13, evtab1, trgab1 12t + 20 ns ti low-level width t til tiaa00, tiaa01, tiaa10, tiaa11, tiaa20, tiaa21, tiaa30, tiaa31, tiaa40, tiaa41,tiaa50, tiaa51 3t smp1 + 20 ns tencn high-level width t wenchn n = 0, 1 3t smp2 + 20 ns tencn low-level width t wencln n = 0, 1 3t smp2 + 20 ns tecr0 high-level width t wcrh0 3t smp2 + 20 ns tecr0 low-level width t wcrl0 3t smp2 + 20 ns titn high-level width t wtithn n = 0, 1 3t smp2 + 20 ns titn low-level width t wtitln n = 0, 1 3t smp2 + 20 ns evtt0 high-level width t wtith0 3t smp2 + 20 ns evtt0 low-level width t wtitl0 3t smp2 + 20 ns tencn input time difference t phud n = 0, 1 3t smp2 + 20 ns remarks 1. t = 1/f xx 2. t smp1 : set by the noise elimination control register (tanfc). selectable from f xx and f xx /4. 3. t smp2 : set by the noise elimination control register (ttnfc). selectable from f xx , f xx /4, f xx /8, f xx /16, f xx /32, and f xx /64. 4. the specifications above show the pul se widths that can be accurately detected as valid edges. therefore, even if a pulse width less than the above specificat ions is input, it may be detected as a valid edge. tin (input) v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1729 of 1817 sep 19, 2011 (4) uartb timing (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate 3.125 mbps (5) uartc timing (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate 3.125 mbps asck0 cycle time 10 mhz v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1730 of 1817 sep 19, 2011 (6) csie timing (a) master mode [when using csie0 to csie1 (port dh pins) (8.33 mbps)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit scken cycle time t kcy1 <63> 120 ns scken high-level width t kh1 t kcy1 /2 ? 8 ns scken low-level width t kl1 <64> t kcy1 /2 ? 8 ns sien setup time (to scken ) 26 ns sien setup time (to scken ) t sik1 <65> 26 ns sien hold time (from scken ) 26 ns sien hold time (from scken ) t ksi1 <66> 26 ns soen output delay time (from scken ) 26 ns soen output delay time (from scken ) t kso1 <67> 26 ns soen output hold time (from scken ) t kcy1 /2 ? 10 ns soen output hold time (from scken ) t hso1 <68> t kcy1 /2 ? 10 ns remark n = 0, 1 [when using csie1 (port 9 pin) (5 mbps)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit scke1 cycle time t kcym <63> 200 ns scke1 high-level width t kcym /2 ? 8 ns scke1 low-level width t khm <64> t kcym /2 ? 8 ns sie1 setup time (to scke1 ) 46 ns sie1 setup time (to scke1 ) t sikm <65> 46 ns sie1 hold time (from scke1 ) 46 ns sie1 hold time (from scke1 ) t ksim <66> 46 ns soe1 output delay time (from scke1 ) 46 ns soe1 output delay time (from scke1 ) t ksom <67> 46 ns soe1 output hold time (from scke1 ) t kcym /2 ? 10 ns soe1 output hold time (from scke1 ) t hsom <68> t kcym /2 ? 10 ns v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1731 of 1817 sep 19, 2011 (b) slave mode [when using csie0 to csie1 (port dh pin) (8.33 mbps)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit scken cycle time t kcy2 <63> 120 ns scken high-level width t kh2 t kcyn /2 ? 8 ns scken low-level width t kl2 <64> t kcyn /2 ? 8 ns 33.3 mhz f xx 50 mhz 26 ns sien setup time (to scken ) 24 mhz f xx 33.3 mhz 14 33.3 mhz f xx 50 mhz 26 ns sien setup time (from scken ) t sik2 <65> 24 mhz f xx 33.3 mhz 14 33.3 mhz f xx 50 mhz t kcyn /2 ? 8 ns sien hold time (to scken ) 24 mhz f xx 33.3 mhz 33.3 mhz f xx 50 mhz t kcyn /2 ? 8 ns sien hold time (from scken ) t ksi2 <66> 24 mhz f xx 33.3 mhz soen output delay time (to scken ) 26 ns soen output delay time (from scken ) t kso2 <67> 26 ns soen output delay time (to scken ) t kcyn /2 ? 10 ns soen output delay time (from scken ) t hso2 <68> t kcyn /2 ? 10 ns remark n = 0, 1 [when using csie1 (port 9 pin) (5 mbps)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit scke1 cycle time t kcy2 <63> 200 ns scke1 high-level width t kcym /2 ? 8 ns scke1 low-level width t kh2 <64> t kcym /2 ? 8 ns sie1 setup time (to scke1 ) 46 ns sie1 setup time (to scke1 ) t sik2 <65> 46 ns sie1 hold time (from scke1 ) t kcym /2 ? 8 ns sie1 hold time (from scke1 ) t ksi2 <66> t kcym /2 ? 8 ns soe1 output delay time (from scke1 ) 46 ns soe1 output delay time (from scke1 ) t kso2 <67> 46 ns soe1 output hold time (from scke1 ) t kcym /2 ? 10 ns soe1 output hold time (from scke1 ) t hso2 <68> t kcym /2 ? 10 ns v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1732 of 1817 sep 19, 2011 (a) cenctl1.cenckp, cendap bits = 00 or 11 soen(output) input data output data sien(input) scken(i/o) <63> <64> <64> <65> <66> <68> <67> (b) cenctl1.cenckp, cendap bits = 10 or 01 <63> <64> <64> <65> <66> <68> <67> input data output data soen(output) sien(input) scken(i/o) remark n = 0, 1 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1733 of 1817 sep 19, 2011 (7) csif timing (a) master mode [when using csif3, csif4 (port dh pins), csif5, csif6 (8.33 mhz)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l =30 pf) parameter symbol conditions min. max. unit sckfn cycle time t kcy1 <69> 120 ns sckfn high-level width t kh1 t kcy1 /2 ? 8 ns sckfn low-level width t kl1 <70> t kcy1 /2 ? 8 ns sifn setup time (to sckfn ) 26 ns sifn setup time (to sckfn ) t sik1 <71> 26 ns sifn hold time (from sckfn ) 26 ns sifn hold time (from sckfn ) t ksi1 <72> 26 ns sofn output delay time (from sckfn ) 26 ns sofn output delay time (from sckfn ) t kso1 <73> 26 ns sofn output hold time (from sckfn ) t kcy1 /2 ? 10 ns sofn output hold time (from sckfn ) t hso1 <74> t kcy1 /2 ? 10 ns remark n = 3 to 6 [when using csi4 (port dh pins side) (12.5 mhz)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit sckf4 cycle time t kcym <69> 80 ns sckf4 high-level width t kcym /2 ? 8 ns sckf4 low-level width t khm <70> t kcym /2 ? 8 ns sif4 setup time (to sckf4 ) 19 ns sif4 setup time (to sckf4 ) t sikm <71> 19 ns sif4 hold time (from sckf4 ) 13 ns sif4 hold time (from sckf4 ) t ksim <72> 13 ns sof4 output delay time (from sckf4 ) 13 ns sof4 output delay time (from sckf4 ) t ksom <73> 13 ns sof4 output hold time (from sckf4 ) t kcym /2 ? 10 ns sof3 output hold time (from sckf4 ) t hsom <74> t kcym /2 ? 10 ns v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1734 of 1817 sep 19, 2011 [when using csif0 to csif2, csif4 (port 3 pin side)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit sckfn cycle time t kcy1 <69> 200 ns sckfn high-level width t kh1 t kcy1 /2 ? 8 ns sckfn low-level width t kl1 <70> t kcy1 /2 ? 8 ns sifn setup time (to sckfn ) 46 ns sifn setup time (to sckfn ) t sik1 <71> 46 ns sifn hold time (from sckfn ) 46 ns sifn hold time (from sckfn ) t ksi1 <72> 46 ns sofn output delay time (from sckfn ) 46 ns sofn output delay time (from sckfn ) t kso1 <73> 46 ns sofn output hold time (from sckfn ) t kcy1 /2 ? 10 ns sofn output hold time (from sckfn ) t hso1 <74> t kcy1 /2 ? 10 ns remark n = 0 to 2, 4 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1735 of 1817 sep 19, 2011 (b) slave mode [when using csif3, csif4 (port dh pin side), csif5, csif6 (8.33 mhz)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit sckfn cycle time t kcy2 <69> 120 ns sckfn high-level width t kh2 t kcy1 /2 ? 8 ns sckfn low-level width t kl2 <70> t kcy1 /2 ? 8 ns sifn setup time (to sckfn ) 26 ns sifn setup time (to sckfn ) t sik2 <71> 26 ns sifn hold time (from sckfn ) 26 ns sifn hold time (from sckfn ) t ksi2 <72> 26 ns sofn output delay time (from sckfn ) 26 ns sofn output delay time (from sckfn ) t kso2 <73> 26 ns sofn output hold time (from sckfn ) t kcy1 /2 ? 10 ns sofn output hold time (from sckfn ) t hso2 <74> t kcy1 /2 ? 10 ns remark n = 3 to 6 [when using csif0 to csif2, csif4 (port 3 pin side) (5 mhz)] (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit sckfn cycle time t kcy1 <69> 200 ns sckfn high-level width t kh1 t kcy1 /2 ? 8 ns sckfn low-level width t kl1 <70> t kcy1 /2 ? 8 ns sifn setup time (to sckfn ) 46 ns sifn setup time (to sckfn ) t sik1 <71> 46 ns sifn hold time (from sckfn ) 46 ns sifn hold time (from sckfn ) t ksi1 <72> 46 ns sofn output delay time (from sckfn ) 46 ns sofn output delay time (from sckfn ) t kso1 <73> 46 ns sofn output hold time (from sckfn ) t kcy1 /2 ? 10 ns sofn output hold time (from sckfn ) t hso1 <74> t kcy1 /2 ? 10 ns remark n = 0 to 2, 4 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1736 of 1817 sep 19, 2011 (a) cfnctl1.cfnckp, cfndap bits = 00 or 11 sofn ( output) input data output data sifn ( input) sckfn (i/o) <69> <70> <70> <71> <72> <74> <73> (b) cfnctl1.cfnckp, cfndap bits = 10 or 01 <69> <70> <70> <71> <72> <74> <73> sofn ( output) input data output data sifn ( input) sckfn (i/o) remark n = 0 to 6 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1737 of 1817 sep 19, 2011 (8) i 2 c bus mode (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scl0n clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <75> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <76> 4.0 ? 0.6 ? s scl0n clock low-level width t low <77> 4.7 ? 1.3 ? s scl0n clock high-level width t high <78> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <79> 4.7 ? 0.6 ? s cbus compatible master 5.0 ? ? ? s data hold time i 2 c mode t hd:dat <80> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <81> 250 ? 100 note 4 ? ns sda0n and scl0n signal rise time t r <82> ? 1000 20 + 0.1cb note 5 300 ns sda0n and scl0n signal fall time t f <83> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <84> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <85> ? ? 0 50 ns capacitive load of each bus line cb ? 400 ? 400 pf notes 1. when the start condition is satisfied, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda0n signal (at v ihmin. of the scl0n signal) in order to occupy the undefined area at the falling edge of scl0n. 3. if the system does not extend the scl0n signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in a normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl0n signal low hold time: t su:dat 250 ns ? if the system extends the scl0n signal low hold time: output the next data bit to the sda0n line before the scl0n line is released (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0 to 4 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1738 of 1817 sep 19, 2011 stop condition start condition restart condition stop condition scl0n (i/o) sda0n (i/o) <77> <83> <83> <82> <82> <80> <81> <79> <76> <75> <76> <85> <84> <78> remark n = 0 to 4 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1739 of 1817 sep 19, 2011 (9) can timing (can controller versions only) (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate 1 mbps internal delay time t node 100 ns can internal clock (f can ) ctxd0 pin (transmit data) crxd0 pin (receive data) t output t intput remark can internal clock (f can ): can baud rate clock internal delay time (t node ) = internal transm ission delay time (t output ) + internal reception delay time (t input ) can controller v850es/jh3-e, v850es/jj3-e internal transmission delay time (t output ) ctxd0 pin crxd0 pin internal reception delay time (t input ) v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1740 of 1817 sep 19, 2011 (10) mii interface (ethernet controller) (a) transmission interface (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit txd[3:0] delay time t dtktd <86> 0 25 ns txen, txer delay time t dtkte <87> 0 25 ns txclk clock width t cytk <88> 40 ns txclk high-level width t tkh <89> 0.4 t cykt 0.6 t cykt ns txclk low-level width t tkl <90> 0.4 t cykt 0.6 t cykt ns txclk txd[3:0] txen txer <88> <89> <90> <87> <87> <86> v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1741 of 1817 sep 19, 2011 (b) reception interface (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit rxd[3:0] hold time t hrkrd <91> 5 ns rxd[3:0] hold time t srdrk <92> 5 ns rxdv hold time t hrkrv <93> 5 ns rxdv set up time t srvrk <94> 5 ns txclk clock width t cyrk <95> 40 ns txclk high-level width t rkh <96> 0.4 t cyrk 0.6 t cyrk ns txclk low-level width t rkl <97> 0.4 t cyrk 0.6 t cyrk ns rxclk rxd[3:0] rxdv rxer <97> <96> <94> <93> <95> <92> <91> v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1742 of 1817 sep 19, 2011 (c) management interface (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 30 pf) parameter symbol conditions min. max. unit mdc cycle time t cymdc <98> 400 ns mdc to mod delay time t dmcmd <99> 0 300 ns mdc to mdoen delay time t dmcme <100> 0 300 ns mdi to mdc set up time t smdmc <101> 50 ns mdi from mdc hold time t hmcmd <102> 50 ns mdc mdo mdc mdi mdoen <102> <101> <100> <99> <98> <98> v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1743 of 1817 sep 19, 2011 (11) high-impedance control timing (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit time from oscillator stop to timer output high impedance t clm clock monitor operating 65 s time from toab1off input timer output high impedance t htqn 300 ns time from toaa1off input timer output high impedance t htp2 300 ns (12) a/d converter (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , 3.0 v av ref0 3.6 v, v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 3.0 av ref0 3.6 v 0.6 %fsr conversion time t conv 2.17 10 s zero scale error 0.5 %fsr full scale error 0.5 %fsr non-linearity error 4.0 lsb differential linearity error 4.0 lsb analog input voltage v ian av ss av ref0 v reference voltage av ref0 3.0 3.6 v normal conversion mode 3 6.5 ma high-speed conversion mode 4 10 ma av ref0 current ai ref0 when a/d converter unused 5 a note excluding quantization error ( 0.05 %fsr). caution do not set (read/write) alternate-function por ts during a/d conversion; otherwise the conversion resolution may be degraded. remark lsb: least significant bit fsr: full scale range v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1744 of 1817 sep 19, 2011 (13) lvi circuit characteristics (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit detection voltage v lvi0 2.85 2.95 3.05 v response time note t ld after v dd reaches v lvi0 (max.), or after v dd has dropped to v lvi0 (max.) 0.2 2.0 ms minimum pulse width t lw 0.2 ms reference voltage stabilization wait time t lwait after v dd reaches 2.85 v(min.) 0.1 0.2 ms note time required to detect the detection volt age and output an interrupt or reset signal. supply voltage (v dd ) time detection voltage (min.) operating voltage (min.) detection voltage (typ.) detection voltage (max.) t lwait t lw t ld t ld lvion bit = 0 1 v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1745 of 1817 sep 19, 2011 (14) ram retention detection (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit detection voltage v ramh 1.9 2.0 2.1 v supply voltage rise time t ramhth v dd = 0 to 2.85 v 0.002 ms response time note t ramhd after v dd reaches 2.1 v 0.2 3.0 ms minimum pulse width t ramhw 0.2 ms note time required to detect the detection voltage and set the rams.ramf bit. supply voltage (v dd ) time detection voltage (min.) rams.ramf bit cleared by instruction operating voltage (min.) detection voltage (typ.) detection voltage (max.) t ramhw t ramhd t ramhd t ramhth v850es/jh3-e, v850es/jj3-e chapter 35 electrical specifications r01uh0290ej0300 rev.3.00 page 1746 of 1817 sep 19, 2011 35.9 flash memory programming characteristics (t a = ? 40 to +85 c, v dd = ev dd = uv dd = av ref0 , v ss = av ss = 0 v, c l = 50 pf) (1) basic characteristics parameter symbol conditions min. typ. max. unit operating frequency f cpu 24 48 mhz supply voltage v dd 2.85 3.6 v number of rewrites c wrt 1000 times programming temperature t prg ? 40 +85 c (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit flmd0, flmd1 setup time t mdset 2 3000 ms flmd0 count start time from reset t rfcf f x = 3 to 6 mhz 800 s flmd0 counter high-level width/ low-level width t ch /t cl 10 100 s flmd0 counter rise time/fall time t r /t f 1 s flash write mode setup timing v dd flmd1 0 v v dd reset (input) 0 v v dd flmd0 0 v t rfcf t mdset t cl t f t r t ch v850es/jh3-e, v850es/jj3-e chapter 36 package drawings r01uh0290ej0300 rev.3.00 page 1747 of 1817 sep 19, 2011 chapter 36 package drawings s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 p128gf-50-gat detail of lead end b 38 64 1 128 39 65 102 103 128-pin plastic lqfp (fine pitch) (14x20) note each lead centerline is located within 0.08 mm of its true position at maximum material condition. 0.20 + 0.07 ? 0.03 3 + 5 ? 3 + 0.075 ? 0.025 v850es/jh3-e, v850es/jj3-e chapter 36 package drawings r01uh0290ej0300 rev.3.00 page 1748 of 1817 sep 19, 2011 144-pin plastic lqfp (fine pitch) (20x20) s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 (unit:mm) item dimensions d e hd he a a1 a2 a3 20.00 0.20 20.00 0.20 22.00 0.20 22.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p144gj-50-gae-2 3 detail of lead end 0.20 b 36 72 1 144 37 73 108 109 + 0.07 0.03 + 0.075 0.025 + 3 4 v850es/jh3-e, v850es/jj3-e chapter 37 recommended soldering conditions r01uh0290ej0300 rev.3.00 page 1749 of 1817 sep 19, 2011 chapter 37 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those re commended below, please contact a renesas electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.renesas.com/prod/package/index.html) remark evaluation of the soldering conditions for the (a) st andard products is incomplete because these products are under development. table 37-1. surface mounting type solderi ng conditions pd70f3778gf-gat-ax: 128-pin plastic lqfp (fine pitch) (14 20 mm) pd70f3779gf-gat-ax: 128-pin plastic lqfp (fine pitch) (14 20 mm) pd70f3780gf-gat-ax: 128-pin plastic lqfp (fine pitch) (14 20 mm) pd70f3781gf-gat-ax: 128-pin plastic lqfp (fine pitch) (14 20 mm) pd70f3782gf-gat-ax: 128-pin plastic lqfp (fine pitch) (14 20 mm) pd70f3783gf-gat-ax: 128-pin plastic lqfp (fine pitch) (14 20 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remarks 1. products with ?ax at the end of t he part number are lead-free products. 2. for soldering methods and conditions other th an those recommended, please contact a renesas electronics sales representative. v850es/jh3-e, v850es/jj3-e chapter 37 recommended soldering conditions r01uh0290ej0300 rev.3.00 page 1750 of 1817 sep 19, 2011 table 37-1. surface mounting ty pe soldering conditions pd70f3784gj-gae-ax: 144-pin plastic lqfp (fine pitch) (20 20 mm) pd70f3785gj-gae-ax: 144-pin plastic lqfp (fine pitch) (20 20 mm) pd70f3786gj-gae-ax: 144-pin plastic lqfp (fine pitch) (20 20 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). remarks 1. products with ?ax at the end of t he part number are lead-free products. 2. for soldering methods and conditions other th an those recommended, please contact a renesas electronics sales representative. v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1751 of 1817 sep 19, 2011 appendix a development tools the following developm ent tools are available for t he development of systems that employ the v850es/jh3-e or v850es/jj3-e. figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, pr oducts supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computers, re fer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98, 2000 ? windows me ? windows xp ? windows nt tm ver. 4.0 v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1752 of 1817 sep 19, 2011 figure a-1. development tool configuration flash memory write environment debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter note 2 in-circuit emulator (qb-v850esjx3e) notes 5 ? project manager (windows only) note 1 software package conversion socket or conversion adapter target system control software embedded software ? real-time os ? network library ? file system on-chip debug emulator (qb-v850mini) note 3 (qb-mini2) note 4 flash memory write adapter flash programmer flash memory language processing software ? c compiler package ? device file notes 1. project manager pm+ is included in the c compiler package. pm+ is only used in windows. 2. the qb-v850mini, qb-mini2, and qb-v850esj x3e support the usb interface only. 3. the qb-v850mini is supplied with the id850qb, usb interface cable, ocd cable, self-check board, kel adapter, and kel connector. all other products are optional. 4. the qb-mini2 is supplied with usb interface cable, 16- pin target cable, 10-pin target cable, and 78k0- ocd board (integrated debugger is not supp lied.) all other products are optional. 5. the qb-v850esjx3e is supplied with the id850qb, flash memory programmer (minicube2), power supply unit, and usb interface adapter. all other products are optional. v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1753 of 1817 sep 19, 2011 a.1 software package development tools (software) commonly us ed with v850 microcontrollers are included this package. sp850 software package for v850 microcontrollers part number: s sp850 remark in the part number differs depending on the host machine and os used. s sp850 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this compiler converts programs written in c into object codes executable with a microcontroller. this compiler is started from project manager pm+. ca850 c compiler package part number: s ca703000 df703786 device file this file contains informat ion peculiar to the device. this device file should be used in combi nation with a tool (ca850 or id850qb). the corresponding os and host machine di ffer depending on the tool to be used. remark in the part number differs depending on the host machine and os used. s ca703000 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) cd-rom a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from pm+. v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1754 of 1817 sep 19, 2011 a.4 debugging tools (hardware) a.4.1 when using iecube qb-v850esjx3e the system configuration when connec ting the qb-v850esjx3e to the host machine (pc-9821 series, pc/at compatible) is shown below. even if optional prod ucts are not prepared, connection is possible. figure a-2. system configurat ion (when using qb-v850esjx3e) <13> mount adapter for device mounting <14> target connector for mounting on target system <9> exchange adapter exchanges pins among different microcontroller types <10> check pin adapter (s type only) enables signal monitoring <11> space adapter each adapter can adjust height by 5.6 mm. <15> target system <7> extension probe flexible type (s and t types) <13> mount adapter for device mounting <14> target connector for mounting on target system <12> yq connector connector for connecting to emulator <9> exchange adapter exchanges pins among different microcontroller types <11> space adapter each adapter can adjust height by 3.2 mm. <6> check pin adapter (under development) enables signal monitoring (s and t types) <5> iecube <1> s-type socket configuration optional required <4> power supply <2> cd-rom <3> usb cable simple flash programmer <15> target system t-type socket configuration system configuration accessories <8> extension probe coaxial type (s and t types) device feature <1> host machine pc-9821 series, ibm-pc/at compatibles <2> cd-rom debugger, usb driver, manuals (id850qb disk, accessory disk note ) <3> usb interface cable cable to connect the host machine and the qb-v850esjx3e. <4> ac adapter 100 to 240 v can be supported by replacing the ac plug. <5> in-circuit emulator (qb-v850esjx3e) the in-circuit emulator serves to debug hardwar e and software when developing application systems using the v850es/jh3-e or v850es/jj3-e. it su pports the integrated debugger id850qb. this emulator should be used in combination with a powe r supply unit and emulation probe. use the usb interface cable to connect this emulator to the host machine. <9> exchange adapter adapter to perform pin conversion. <10> check pin adapter adapter used in wavefo rm monitoring using the oscilloscope, etc. <11> space adapter adapter to adjust the height. <12> yq connector conversion adapter to c onnect target connector and exchange adapter <13> mount adapter adapter to mount the v850es/jh3-e or v850es/jj3-e on a socket. <14> target connector connector to solder on the target system. note download the device file from the renesas electronics website. http://www2.renesas.com/micro/en/ods/index.html v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1755 of 1817 sep 19, 2011 table a-1. system configur ation (when using qb-v850esjx3e note 1 ) target device v850es/jh3-e 128-pin plastic lqfp v850es/jj3-e 144-pin plastic lqfp <5> in-circuit emulator qb-v850esjx3e note 1 s type <6> check pin adapter t type qb-144-ca-01 note 2 (optional) s type <7> extension probe (flexible type) t type qb-144-ep-02s (optional) s type <8> extension probe (coaxial type) t type qb-144-ep-01s (optional) s type qb-128gf-ea-01s qb-144gj-ea-01s <9> exchange adapter note 3 t type qb-128gf-ea-02t qb-144gj-ea-01t <10> check pin adapter note 4 s type qb-128-ca-01s (optional ) qb-144-ca-01s (optional) s type qb-144-sa-01s (optional ) qb-144-sa-01s (optional) <11> space adapter note 4 t type qb-128gf-ys-01t (opti onal) qb-144gj-01t (optional) <12> yq connector note 3 t type qb-128gf-yq-01t qb-144gj-yq-01t s type qb-128gf-ma-01s qb-144gj-ma-01s <13> mount adapter t type qb-128gf-hq-01t qb-144gj-hq-01t s type qb-128gf-tc-01s qb-144gj-tc-01s <14> target connector note 3 t type qb-128gf-nq-01t qb-144gj-nq-01t <15> target system notes 1. the qb-v850esjx3e (under development) is supplied wit h a power supply unit, usb interface cable, and flash memory programmer (minicube2). it is also supplied with integrated debugger id850qb as control software. 2. under development 3. supplied with the device depending on the ordering number. ? when qb-v850esjx3e-zzz is ordered: the excha nge adapter and the tar get connector are not supplied. ? when qb-v850esjx3e-s128gf is ordered: the qb-128gf-ea-01s and qb-128gf-tc-01s are supplied. ? when qb-v850esjx3e-t128gf is ordered: the qb-128gf-ea-02t, qb-128gf-yq-01t, and qb- 128gf-nq-01t are supplied. ? when qb-v850esjx3e-s144gj is ordered: t he qb-144gj-ea-01s and qb-144gj-tc-01s are supplied. ? when qb-v850esjx3e-t144gj is ordered: the qb-144gj-ea-01t, qb -144gj-yq-01t, and qb- 144gj-nq-01t are supplied. 4. when using both <9> and <10>, the order between <9> and <10> is not cared. remark the numbers in the angle brackets correspond to the numbers in figure a-2. v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1756 of 1817 sep 19, 2011 a.4.2 when using minicube qb-v850mini note 1 (1) on-chip emulation using minicube the system configuration when connec ting minicube to the host machine (pc-9821 series, pc/at compatible) is shown below. figure a-3. on-chip emulation system configuration <7> <6> target system v850es/jh3-e, v850es/jj3-e <1> <4> <3> <5> <2> s t a t u s t a r g e t p o w e r <1> host machine pc with usb ports <2> cd-rom note 2 contents such as integrated debugger id850qb note 1 , n-wire checker, device driver, and documents are included in cd-rom. it is supplied with minicube. <3> usb interface cable usb cable to connect the host machine and minicube. it is supplied with minicube. the cable length is approximately 2 m. <4> minicube on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using t he v850es/jh3-e or v850es/jj3-e. it supports integrated debugger id850qb note 1 . <5> ocd cable cable to connect minicube and the target system. it is supplied with minicube. the cable length is approximately 20 cm. <6> connector conversion board kel adapter this conversion board is supplied with minicube. <7> minicube connector kel connector note 3 8830e-026-170s (supplied with minicube) 8830e-026-170l (sold separately) notes 1. under development 2. download the device file from the renesas electronics website. http://www2.renesas.com/micro/en/ods/index.html 3. product of kel corporation remark the numbers in the angular brackets correspond to the numbers in figure a-3. v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1757 of 1817 sep 19, 2011 a.4.3 when using minicube2 qb-mini2 note the system configurati on when connecting mi nicube2 to the host machine (pc-9 821 series, pc/at compatible) is shown below. figure a-4. system configuration of on-chip emulation system <6> <5> target system v850es/jh3-e, v850es/jj3-e <1> <2> software <4> <3> minicube2 <1> host machine pc with usb ports <2> software the integrated debugger id850qb note , device file, etc. download the device file from the renesas electronics website. http://www2.renesas.com/micro/en/ods/index.html <3> usb interface cable usb cable to connect the host machine and minicube. it is supplied with minicube. the cable length is approximately 2 m. <4> minicube2 on-chip debug emulator this on-chip debug emulator serves to debug hardware and software when developing application systems using t he v850es/jh3-e or v850es/jj3-e. it supports integrated debugger id850qb note . <5> 16-pin target cable cable to connect minicube2 and the target system. it is supplied with minicube. the cable length is approximately 15 cm. <6> target connector (sold separately) use a 16- pin general-purpose connector with 2.54 mm pitch. note under development remark the numbers in the angular brackets correspond to the numbers in figure a-4. v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1758 of 1817 sep 19, 2011 a.5 debugging tools (software) this debugger supports the in-circuit emul ators for v850 microcontrollers. the id850qb is windows-based software. it has improved c-compatible debugging func tions and can display the results of tracing with the source program using a wi ndow integration function that associates the source program, disassemble display, and memory display with the trace result. it should be used in combinat ion with the device file. id850qb (under development) integrated debugger part number: s id703000-qb (id850qb) remark in the part number differs depending on the host machine and os used. s id703000-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom v850es/jh3-e, v850es/jj3-e appendi x a development tools r01uh0290ej0300 rev.3.00 page 1759 of 1817 sep 19, 2011 a.6 embedded software the rx850 and rx850 pro are real-time oss conforming to itron 3.0 specifications. a tool (configurator) for generating multip le information tables is supplied. rx850 pro has more functions than the rx850. rx850, rx850 pro (under development) real-time os part number: s rx703000- ??? (rx850) s rx703100- ??? (rx850 pro) rx-fs850 (file system) this is a fat file system function. it is a file system that supports the cd-rom file system function. this file system is used with the real-time os rx850 pro. caution to purchase the rx850 or rx850 pro, first fill in the purchase applicati on form and sign the license agreement. remark and ??? in the part number differ depending on the host machine and os used. s rx703000- ??? s rx703100- ??? ??? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k 0.1 million units 001m 1 million units 010m mass-production object 10 million units s01 source program object source program for mass production host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3k17 sparcstation solaris (rel. 2.5.1) cd-rom a.7 flash memory writing tools flashpro v (part number: pg-fp5 note ) flash programmer flash programmer dedicated to microcontro llers with internal flash memory. qb-mini2 note (minicube2) on-chip debug emulator with programming function. fa-128gf-gat-b fa-144gf-gae-b flash memory writing adapter flash memory writing adapter (not wire d) used by connecting to the flashpro iv, flashpro v, etc. ? fa-128gf-gat-b: 128-pin plastic lqfp (gf-gat type) ? fa-144gj-gae-b: 144-pin pl astic lqfp (gj-gae type) note under development remark fa-128gf-gat-b and fa-144gf-gae-b are products of naito densei machida mfg. co., ltd. tel: +81-42-750-4172 v850es/jh3-e, v850es/jj3-e appendix b major differences between v850es/jx3-e and v850es/jx3-h r01uh0290ej0300 rev.3.00 page 1760 of 1817 sep 19, 2011 appendix b major differences betw een v850es/jx3-e and v850es/jx3-h table b-1. major differences be tween v850es/jx3-e and v850es/jx3-h major difference v850es/jx3-e v850es/jx3-h minimum instruction execution time 20 ns ( 50 mhz operation) 20.8 ns (48 mhz operation) maximum ram size 60 kb + 64 kb note 48 kb + 8 kb note d/a controller none available ethernet controller available none uartc: 6/8 ch uartc: 5 ch asynchronous serial interface uartb(uart with fifo function): 2 ch none clocked serial interface csie (csi with fifo function): 2 ch none i 2 c 4/5 ch 3 ch package 128-pin lqfp 144-pin lqfp 100-pin lqfp 128-pin lqfp note data-only ram v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1761 of 1817 sep 19, 2011 appendix c register index (1/43) symbol name unit page ada0cr0 a/d conversion result register 0 adc 709 ada0cr0h a/d conversion result register 0h adc 709 ada0cr1 a/d conversion result register 1 adc 709 ada0cr10 a/d conversion result register 10 adc 709 ada0cr10h a/d conversion result register 10h adc 709 ada0cr11 a/d conversion result register 11 adc 709 ada0cr11h a/d conversion result register 11h adc 709 ada0cr1h a/d conversion result register 1h adc 709 ada0cr2 a/d conversion result register 2 adc 709 ada0cr2h a/d conversion result register 2h adc 709 ada0cr3 a/d conversion result register 3 adc 709 ada0cr3h a/d conversion result register 3h adc 709 ada0cr4 a/d conversion result register 4 adc 709 ada0cr4h a/d conversion result register 4h adc 709 ada0cr5 a/d conversion result register 5 adc 709 ada0cr5h a/d conversion result register 5h adc 709 ada0cr6 a/d conversion result register 6 adc 709 ada0cr6h a/d conversion result register 6h adc 709 ada0cr7 a/d conversion result register 7 adc 709 ada0cr7h a/d conversion result register 7h adc 709 ada0cr8 a/d conversion result register 8 adc 709 ada0cr8h a/d conversion result register 8h adc 709 ada0cr9 a/d conversion result register 9 adc 709 ada0cr9h a/d conversion result register 9h adc 709 ada0m0 a/d converter mode register 0 adc 702 ada0m1 a/d converter mode register 1 adc 704 ada0m2 a/d converter mode register 2 adc 707 ada0pfm power-fail compare mode register adc 711 ada0pft power-fail compare threshold value register adc 712 ada0s a/d converter channel specification register adc 708 adic interrupt control register adc 1577 afr address filter register ethernet 1389 awc address wait control register bcu 211 bcc bus cycle control register bcu 212 bpc peripheral i/o area select control register bcu 99 brginte bridge interrupt enable register usbf 1301 brgintt bridge interrupt control register usbf 1300 bsc bus size configuration register bcu 200 c0brp can0 module bit rate prescaler register can 1095 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1762 of 1817 sep 19, 2011 (2/43) symbol name unit page c0ctrl can0 module control register can 1085 c0erc can0 module error counter register can 1091 c0gmabt can0 global automatic bl ock transmission register can 1080 c0gmabtd can0 global automatic block transmission delay register can 1082 c0gmcs can0 global clock selection register can 1079 c0gmctrl can0 global control register can 1077 c0ie can0 module interrupt enable register can 1092 c0info can0 module information register can 1090 c0ints can0 module interrupt status register can 1094 c0lec can0 module last error code register can 1089 c0lipt can0 module last in-pointer register can 1098 c0lopt can0 module last out-pointer register can 1100 c0mask1h can0 module mask 1 register can 1083 c0mask1l can0 module mask 1 register can 1083 c0mask2h can0 module mask 2 register can 1083 c0mask2l can0 module mask 2 register can 1083 c0mask3h can0 module mask 3 register can 1083 c0mask3l can0 module mask 3 register can 1083 c0mask4h can0 module mask 4 register can 1083 c0mask4l can0 module mask 4 register can 1083 c0mconf00 can0 message configuration register 00 can 1107 c0mconf01 can0 message configuration register 01 can 1107 c0mconf02 can0 message configuration register 02 can 1107 c0mconf03 can0 message configuration register 03 can 1107 c0mconf04 can0 message configuration register 04 can 1107 c0mconf05 can0 message configuration register 05 can 1107 c0mconf06 can0 message configuration register 06 can 1107 c0mconf07 can0 message configuration register 07 can 1107 c0mconf08 can0 message configuration register 08 can 1107 c0mconf09 can0 message configuration register 09 can 1107 c0mconf10 can0 message configuration register 10 can 1107 c0mconf12 can0 message configuration register 12 can 1107 c0mconf13 can0 message configuration register 13 can 1107 c0mconf14 can0 message configuration register 14 can 1107 c0mconf15 can0 message configuration register 15 can 1107 c0mconf16 can0 message configuration register 16 can 1107 c0mconf17 can0 message configuration register 17 can 1107 c0mconf18 can0 message configuration register 18 can 1107 c0mconf19 can0 message configuration register 19 can 1107 c0mconf20 can0 message configuration register 20 can 1107 c0mconf21 can0 message configuration register 21 can 1107 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1763 of 1817 sep 19, 2011 (3/43) symbol name unit page c0mconf22 can0 message configuration register 22 can 1107 c0mconf23 can0 message configuration register 23 can 1107 c0mconf24 can0 message configuration register 24 can 1107 c0mconf25 can0 message configuration register 25 can 1107 c0mconf26 can0 message configuration register 26 can 1107 c0mconf27 can0 message configuration register 27 can 1107 c0mconf28 can0 message configuration register 28 can 1107 c0mconf29 can0 message configuration register 29 can 1107 c0mconf30 can0 message configuration register 30 can 1107 c0mconf31 can0 message configuration register 31 can 1107 c0mctrl00 can0 message control register 00 can 1109 c0mctrl01 can0 message control register 01 can 1109 c0mctrl02 can0 message control register 02 can 1109 c0mctrl03 can0 message control register 03 can 1109 c0mctrl04 can0 message control register 04 can 1109 c0mctrl05 can0 message control register 05 can 1109 c0mctrl06 can0 message control register 06 can 1109 c0mctrl07 can0 message control register 07 can 1109 c0mctrl08 can0 message control register 08 can 1109 c0mctrl09 can0 message control register 09 can 1109 c0mctrl10 can0 message control register 10 can 1109 c0mctrl11 can0 message control register 11 can 1109 c0mctrl12 can0 message control register 12 can 1109 c0mctrl13 can0 message control register 13 can 1109 c0mctrl14 can0 message control register 14 can 1109 c0mctrl15 can0 message control register 15 can 1109 c0mctrl16 can0 message control register 16 can 1109 c0mctrl17 can0 message control register 17 can 1109 c0mctrl18 can0 message control register 18 can 1109 c0mctrl19 can0 message control register 19 can 1109 c0mctrl20 can0 message control register 20 can 1109 c0mctrl21 can0 message control register 21 can 1109 c0mctrl22 can0 message icontrol register 22 can 1109 c0mctrl23 can0 message control register 23 can 1109 c0mctrl24 can0 message control register 24 can 1109 c0mctrl25 can0 message control register 25 can 1109 c0mctrl26 can0 message control register 26 can 1109 c0mctrl27 can0 message control register 27 can 1109 c0mctrl28 can0 message control register 28 can 1109 c0mctrl29 can0 message control register 29 can 1109 c0mctrl30 can0 message control register 30 can 1109 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1764 of 1817 sep 19, 2011 (4/43) symbol name unit page c0mctrl31 can0 message control register 31 can 1109 c0mdata000 can0 message data byte 0 register 00 can 1104 c0mdata001 can0 message data byte 0 register 01 can 1104 c0mdata002 can0 message data byte 0 register 02 can 1104 c0mdata003 can0 message data byte 0 register 03 can 1104 c0mdata004 can0 message data byte 0 register 04 can 1104 c0mdata005 can0 message data byte 0 register 05 can 1104 c0mdata006 can0 message data byte 0 register 06 can 1104 c0mdata007 can0 message data byte 0 register 07 can 1104 c0mdata008 can0 message data byte 0 register 08 can 1104 c0mdata009 can0 message data byte 0 register 09 can 1104 c0mdata010 can0 message data byte 0 register 10 can 1104 c0mdata0100 can0 message data byte 01 register 00 can 1104 c0mdata0101 can0 message data byte 01 register 01 can 1104 c0mdata0102 can0 message data byte 01 register 02 can 1104 c0mdata0103 can0 message data byte 01 register 03 can 1104 c0mdata0104 can0 message data byte 01 register 04 can 1104 c0mdata0105 can0 message data byte 01 register 05 can 1104 c0mdata0106 can0 message data byte 01 register 06 can 1104 c0mdata0107 can0 message data byte 01 register 07 can 1104 c0mdata0108 can0 message data byte 01 register 08 can 1104 c0mdata0109 can0 message data byte 01 register 09 can 1104 c0mdata011 can0 message data byte 0 register 11 can 1104 c0mdata0110 can0 message data byte 01 register 10 can 1104 c0mdata0111 can0 message data byte 01 register 11 can 1104 c0mdata0112 can0 message data byte 01 register 12 can 1104 c0mdata0113 can0 message data byte 01 register 13 can 1104 c0mdata0114 can0 message data byte 01 register 14 can 1104 c0mdata0115 can0 message data byte 01 register 15 can 1104 c0mdata0116 can0 message data byte 01 register 16 can 1104 c0mdata0117 can0 message data byte 01 register 17 can 1104 c0mdata0118 can0 message data byte 01 register 18 can 1104 c0mdata0119 can0 message data byte 01 register 19 can 1104 c0mdata012 can0 message data byte 0 register 12 can 1104 c0mdata0120 can0 message data byte 01 register 20 can 1104 c0mdata0121 can0 message data byte 01 register 21 can 1104 c0mdata0122 can0 message data byte 01 register 22 can 1104 c0mdata0123 can0 message data byte 01 register 23 can 1104 c0mdata0124 can0 message data byte 01 register 24 can 1104 c0mdata0125 can0 message data byte 01 register 25 can 1104 c0mdata0126 can0 message data byte 01 register 26 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1765 of 1817 sep 19, 2011 (5/43) symbol name unit page c0mdata0127 can0 message data byte 01 register 27 can 1104 c0mdata0128 can0 message data byte 01 register 28 can 1104 c0mdata0129 can0 message data byte 01 register 29 can 1104 c0mdata013 can0 message data byte 0 register 13 can 1104 c0mdata0130 can0 message data byte 01 register 30 can 1104 c0mdata0131 can0 message data byte 01 register 31 can 1104 c0mdata014 can0 message data byte 0 register 14 can 1104 c0mdata015 can0 message data byte 0 register 15 can 1104 c0mdata016 can0 message data byte 0 register 16 can 1104 c0mdata017 can0 message data byte 0 register 17 can 1104 c0mdata018 can0 message data byte 0 register 18 can 1104 c0mdata019 can0 message data byte 0 register 19 can 1104 c0mdata020 can0 message data byte 0 register 20 can 1104 c0mdata021 can0 message data byte 0 register 21 can 1104 c0mdata022 can0 message data byte 0 register 22 can 1104 c0mdata023 can0 message data byte 0 register 23 can 1104 c0mdata024 can0 message data byte 0 register 24 can 1104 c0mdata025 can0 message data byte 0 register 25 can 1104 c0mdata026 can0 message data byte 0 register 26 can 1104 c0mdata027 can0 message data byte 0 register 27 can 1104 c0mdata028 can0 message data byte 0 register 28 can 1104 c0mdata029 can0 message data byte 0 register 29 can 1104 c0mdata030 can0 message data byte 0 register 30 can 1104 c0mdata031 can0 message data byte 0 register 31 can 1104 c0mdata100 can0 message data byte 1 register 00 can 1104 c0mdata101 can0 message data byte 1 register 01 can 1104 c0mdata102 can0 message data byte 1 register 02 can 1104 c0mdata103 can0 message data byte 1 register 03 can 1104 c0mdata104 can0 message data byte 1 register 04 can 1104 c0mdata105 can0 message data byte 1 register 05 can 1104 c0mdata106 can0 message data byte 1 register 06 can 1104 c0mdata107 can0 message data byte 1 register 07 can 1104 c0mdata108 can0 message data byte 1 register 08 can 1104 c0mdata109 can0 message data byte 1 register 09 can 1104 c0mdata110 can0 message data byte 1 register 10 can 1104 c0mdata111 can0 message data byte 1 register 11 can 1104 c0mdata112 can0 message data byte 1 register 12 can 1104 c0mdata113 can0 message data byte 1 register 13 can 1104 c0mdata114 can0 message data byte 1 register 14 can 1104 c0mdata115 can0 message data byte 1 register 15 can 1104 c0mdata116 can0 message data byte 1 register 16 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1766 of 1817 sep 19, 2011 (6/43) symbol name unit page c0mdata117 can0 message data byte 1 register 17 can 1104 c0mdata118 can0 message data byte 1 register 18 can 1104 c0mdata119 can0 message data byte 1 register 19 can 1104 c0mdata120 can0 message data byte 1 register 20 can 1104 c0mdata121 can0 message data byte 1 register 21 can 1104 c0mdata122 can0 message data byte 1 register 22 can 1104 c0mdata123 can0 message data byte 1 register 23 can 1104 c0mdata124 can0 message data byte 1 register 24 can 1104 c0mdata125 can0 message data byte 1 register 25 can 1104 c0mdata126 can0 message data byte 1 register 26 can 1104 c0mdata127 can0 message data byte 1 register 27 can 1104 c0mdata128 can0 message data byte 1 register 28 can 1104 c0mdata129 can0 message data byte 1 register 29 can 1104 c0mdata130 can0 message data byte 1 register 30 can 1104 c0mdata131 can0 message data byte 1 register 31 can 1104 c0mdata200 can0 message data byte 2 register 00 can 1104 c0mdata201 can0 message data byte 2 register 01 can 1104 c0mdata202 can0 message data byte 2 register 02 can 1104 c0mdata203 can0 message data byte 2 register 03 can 1104 c0mdata204 can0 message data byte 2 register 04 can 1104 c0mdata205 can0 message data byte 2 register 05 can 1104 c0mdata206 can0 message data byte 2 register 06 can 1104 c0mdata207 can0 message data byte 2 register 07 can 1104 c0mdata208 can0 message data byte 2 register 08 can 1104 c0mdata209 can0 message data byte 2 register 09 can 1104 c0mdata210 can0 message data byte 2 register 10 can 1104 c0mdata211 can0 message data byte 2 register 11 can 1104 c0mdata212 can0 message data byte 2 register 12 can 1104 c0mdata213 can0 message data byte 2 register 13 can 1104 c0mdata214 can0 message data byte 2 register 14 can 1104 c0mdata215 can0 message data byte 2 register 15 can 1104 c0mdata216 can0 message data byte 2 register 16 can 1104 c0mdata217 can0 message data byte 2 register 17 can 1104 c0mdata218 can0 message data byte 2 register 18 can 1104 c0mdata219 can0 message data byte 2 register 19 can 1104 c0mdata220 can0 message data byte 2 register 20 can 1104 c0mdata221 can0 message data byte 2 register 21 can 1104 c0mdata222 can0 message data byte 2 register 22 can 1104 c0mdata223 can0 message data byte 2 register 23 can 1104 c0mdata224 can0 message data byte 2 register 24 can 1104 c0mdata225 can0 message data byte 2 register 25 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1767 of 1817 sep 19, 2011 (7/43) symbol name unit page c0mdata226 can0 message data byte 2 register 26 can 1104 c0mdata227 can0 message data byte 2 register 27 can 1104 c0mdata228 can0 message data byte 2 register 28 can 1104 c0mdata229 can0 message data byte 2 register 29 can 1104 c0mdata230 can0 message data byte 2 register 30 can 1104 c0mdata2300 can0 message data byte 23 register 00 can 1104 c0mdata2301 can0 message data byte 23 register 01 can 1104 c0mdata2302 can0 message data byte 23 register 02 can 1104 c0mdata2303 can0 message data byte 23 register 03 can 1104 c0mdata2304 can0 message data byte 23 register 04 can 1104 c0mdata2305 can0 message data byte 23 register 05 can 1104 c0mdata2306 can0 message data byte 23 register 06 can 1104 c0mdata2307 can0 message data byte 23 register 07 can 1104 c0mdata2308 can0 message data byte 23 register 08 can 1104 c0mdata2309 can0 message data byte 23 register 09 can 1104 c0mdata231 can0 message data byte 2 register 31 can 1104 c0mdata2310 can0 message data byte 23 register 10 can 1104 c0mdata2311 can0 message data byte 23 register 11 can 1104 c0mdata2312 can0 message data byte 23 register 12 can 1104 c0mdata2313 can0 message data byte 23 register 13 can 1104 c0mdata2314 can0 message data byte 23 register 14 can 1104 c0mdata2315 can0 message data byte 23 register 15 can 1104 c0mdata2316 can0 message data byte 23 register 16 can 1104 c0mdata2317 can0 message data byte 23 register 17 can 1104 c0mdata2318 can0 message data byte 23 register 18 can 1104 c0mdata2319 can0 message data byte 23 register 19 can 1104 c0mdata2320 can0 message data byte 23 register 20 can 1104 c0mdata2321 can0 message data byte 23 register 21 can 1104 c0mdata2322 can0 message data byte 23 register 22 can 1104 c0mdata2323 can0 message data byte 23 register 23 can 1104 c0mdata2324 can0 message data byte 23 register 24 can 1104 c0mdata2325 can0 message data byte 23 register 25 can 1104 c0mdata2326 can0 message data byte 23 register 26 can 1104 c0mdata2327 can0 message data byte 23 register 27 can 1104 c0mdata2328 can0 message data byte 23 register 28 can 1104 c0mdata2329 can0 message data byte 23 register 29 can 1104 c0mdata2330 can0 message data byte 23 register 30 can 1104 c0mdata2331 can0 message data byte 23 register 31 can 1104 c0mdata300 can0 message data byte 3 register 00 can 1104 c0mdata301 can0 message data byte 3 register 01 can 1104 c0mdata302 can0 message data byte 3 register 02 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1768 of 1817 sep 19, 2011 (8/43) symbol name unit page c0mdata303 can0 message data byte 3 register 03 can 1104 c0mdata304 can0 message data byte 3 register 04 can 1104 c0mdata305 can0 message data byte 3 register 05 can 1104 c0mdata306 can0 message data byte 3 register 06 can 1104 c0mdata307 can0 message data byte 3 register 07 can 1104 c0mdata308 can0 message data byte 3 register 08 can 1104 c0mdata309 can0 message data byte 3 register 09 can 1104 c0mdata310 can0 message data byte 3 register 10 can 1104 c0mdata311 can0 message data byte 3 register 11 can 1104 c0mdata312 can0 message data byte 3 register 12 can 1104 c0mdata313 can0 message data byte 3 register 13 can 1104 c0mdata314 can0 message data byte 3 register 14 can 1104 c0mdata315 can0 message data byte 3 register 15 can 1104 c0mdata316 can0 message data byte 3 register 16 can 1104 c0mdata317 can0 message data byte 3 register 17 can 1104 c0mdata318 can0 message data byte 3 register 18 can 1104 c0mdata319 can0 message data byte 3 register 19 can 1104 c0mdata320 can0 message data byte 3 register 20 can 1104 c0mdata321 can0 message data byte 3 register 21 can 1104 c0mdata322 can0 message data byte 3 register 22 can 1104 c0mdata323 can0 message data byte 3 register 23 can 1104 c0mdata324 can0 message data byte 3 register 24 can 1104 c0mdata325 can0 message data byte 3 register 25 can 1104 c0mdata326 can0 message data byte 3 register 26 can 1104 c0mdata327 can0 message data byte 3 register 27 can 1104 c0mdata328 can0 message data byte 3 register 28 can 1104 c0mdata329 can0 message data byte 3 register 29 can 1104 c0mdata330 can0 message data byte 3 register 30 can 1104 c0mdata331 can0 message data byte 3 register 31 can 1104 c0mdata400 can0 message data byte 4 register 00 can 1104 c0mdata401 can0 message data byte 4 register 01 can 1104 c0mdata402 can0 message data byte 4 register 02 can 1104 c0mdata403 can0 message data byte 4 register 03 can 1104 c0mdata404 can0 message data byte 4 register 04 can 1104 c0mdata405 can0 message data byte 4 register 05 can 1104 c0mdata406 can0 message data byte 4 register 06 can 1104 c0mdata407 can0 message data byte 4 register 07 can 1104 c0mdata408 can0 message data byte 4 register 08 can 1104 c0mdata409 can0 message data byte 4 register 09 can 1104 c0mdata410 can0 message data byte 4 register 10 can 1104 c0mdata411 can0 message data byte 4 register 11 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1769 of 1817 sep 19, 2011 (9/43) symbol name unit page c0mdata412 can0 message data byte 4 register 12 can 1104 c0mdata413 can0 message data byte 4 register 13 can 1104 c0mdata414 can0 message data byte 4 register 14 can 1104 c0mdata415 can0 message data byte 4 register 15 can 1104 c0mdata416 can0 message data byte 4 register 16 can 1104 c0mdata417 can0 message data byte 4 register 17 can 1104 c0mdata418 can0 message data byte 4 register 18 can 1104 c0mdata419 can0 message data byte 4 register 19 can 1104 c0mdata420 can0 message data byte 4 register 20 can 1104 c0mdata421 can0 message data byte 4 register 21 can 1104 c0mdata422 can0 message data byte 4 register 22 can 1104 c0mdata423 can0 message data byte 4 register 23 can 1104 c0mdata424 can0 message data byte 4 register 24 can 1104 c0mdata425 can0 message data byte 4 register 25 can 1104 c0mdata426 can0 message data byte 4 register 26 can 1104 c0mdata427 can0 message data byte 4 register 27 can 1104 c0mdata428 can0 message data byte 4 register 28 can 1104 c0mdata429 can0 message data byte 4 register 29 can 1104 c0mdata430 can0 message data byte 4 register 30 can 1104 c0mdata431 can0 message data byte 4 register 31 can 1104 c0mdata4500 can0 message data byte 45 register 00 can 1104 c0mdata4501 can0 message data byte 45 register 01 can 1104 c0mdata4502 can0 message data byte 45 register 02 can 1104 c0mdata4503 can0 message data byte 45 register 03 can 1104 c0mdata4504 can0 message data byte 45 register 04 can 1104 c0mdata4505 can0 message data byte 45 register 05 can 1104 c0mdata4506 can0 message data byte 45 register 06 can 1104 c0mdata4507 can0 message data byte 45 register 07 can 1104 c0mdata4508 can0 message data byte 45 register 08 can 1104 c0mdata4509 can0 message data byte 45 register 09 can 1104 c0mdata4510 can0 message data byte 45 register 10 can 1104 c0mdata4511 can0 message data byte 45 register 11 can 1104 c0mdata4512 can0 message data byte 45 register 12 can 1104 c0mdata4513 can0 message data byte 45 register 13 can 1104 c0mdata4514 can0 message data byte 45 register 14 can 1104 c0mdata4515 can0 message data byte 45 register 15 can 1104 c0mdata4516 can0 message data byte 45 register 16 can 1104 c0mdata4517 can0 message data byte 45 register 17 can 1104 c0mdata4518 can0 message data byte 45 register 18 can 1104 c0mdata4519 can0 message data byte 45 register 19 can 1104 c0mdata4520 can0 message data byte 45 register 20 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1770 of 1817 sep 19, 2011 (10/43) symbol name unit page c0mdata4521 can0 message data byte 45 register 21 can 1104 c0mdata4522 can0 message data byte 45 register 22 can 1104 c0mdata4523 can0 message data byte 45 register 23 can 1104 c0mdata4524 can0 message data byte 45 register 24 can 1104 c0mdata4525 can0 message data byte 45 register 25 can 1104 c0mdata4526 can0 message data byte 45 register 26 can 1104 c0mdata4527 can0 message data byte 45 register 27 can 1104 c0mdata4528 can0 message data byte 45 register 28 can 1104 c0mdata4529 can0 message data byte 45 register 29 can 1104 c0mdata4530 can0 message data byte 45 register 30 can 1104 c0mdata4531 can0 message data byte 45 register 31 can 1104 c0mdata500 can0 message data byte 5 register 00 can 1104 c0mdata501 can0 message data byte 5 register 01 can 1104 c0mdata502 can0 message data byte 5 register 02 can 1104 c0mdata503 can0 message data byte 5 register 03 can 1104 c0mdata504 can0 message data byte 5 register 04 can 1104 c0mdata505 can0 message data byte 5 register 05 can 1104 c0mdata506 can0 message data byte 5 register 06 can 1104 c0mdata507 can0 message data byte 5 register 07 can 1104 c0mdata508 can0 message data byte 5 register 08 can 1104 c0mdata509 can0 message data byte 5 register 09 can 1104 c0mdata510 can0 message data byte 5 register 10 can 1104 c0mdata511 can0 message data byte 5 register 11 can 1104 c0mdata512 can0 message data byte 5 register 12 can 1104 c0mdata513 can0 message data byte 5 register 13 can 1104 c0mdata514 can0 message data byte 5 register 14 can 1104 c0mdata515 can0 message data byte 5 register 15 can 1104 c0mdata516 can0 message data byte 5 register 16 can 1104 c0mdata517 can0 message data byte 5 register 17 can 1104 c0mdata518 can0 message data byte 5 register 18 can 1104 c0mdata519 can0 message data byte 5 register 19 can 1104 c0mdata520 can0 message data byte 5 register 20 can 1104 c0mdata521 can0 message data byte 5 register 21 can 1104 c0mdata522 can0 message data byte 5 register 22 can 1104 c0mdata523 can0 message data byte 5 register 23 can 1104 c0mdata524 can0 message data byte 5 register 24 can 1104 c0mdata525 can0 message data byte 5 register 25 can 1104 c0mdata526 can0 message data byte 5 register 26 can 1104 c0mdata527 can0 message data byte 5 register 27 can 1104 c0mdata528 can0 message data byte 5 register 28 can 1104 c0mdata529 can0 message data byte 5 register 29 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1771 of 1817 sep 19, 2011 (11/43) symbol name unit page c0mdata530 can0 message data byte 5 register 30 can 1104 c0mdata531 can0 message data byte 5 register 31 can 1104 c0mdata600 can0 message data byte 6 register 00 can 1104 c0mdata601 can0 message data byte 6 register 01 can 1104 c0mdata602 can0 message data byte 6 register 02 can 1104 c0mdata603 can0 message data byte 6 register 03 can 1104 c0mdata604 can0 message data byte 6 register 04 can 1104 c0mdata605 can0 message data byte 6 register 05 can 1104 c0mdata606 can0 message data byte 6 register 06 can 1104 c0mdata607 can0 message data byte 6 register 07 can 1104 c0mdata608 can0 message data byte 6 register 08 can 1104 c0mdata609 can0 message data byte 6 register 09 can 1104 c0mdata610 can0 message data byte 6 register 10 can 1104 c0mdata611 can0 message data byte 6 register 11 can 1104 c0mdata612 can0 message data byte 6 register 12 can 1104 c0mdata613 can0 message data byte 6 register 13 can 1104 c0mdata614 can0 message data byte 6 register 14 can 1104 c0mdata615 can0 message data byte 6 register 15 can 1104 c0mdata616 can0 message data byte 6 register 16 can 1104 c0mdata617 can0 message data byte 6 register 17 can 1104 c0mdata618 can0 message data byte 6 register 18 can 1104 c0mdata619 can0 message data byte 6 register 19 can 1104 c0mdata620 can0 message data byte 6 register 20 can 1104 c0mdata621 can0 message data byte 6 register 21 can 1104 c0mdata622 can0 message data byte 6 register 22 can 1104 c0mdata623 can0 message data byte 6 register 23 can 1104 c0mdata624 can0 message data byte 6 register 24 can 1104 c0mdata625 can0 message data byte 6 register 25 can 1104 c0mdata626 can0 message data byte 6 register 26 can 1104 c0mdata627 can0 message data byte 6 register 27 can 1104 c0mdata628 can0 message data byte 6 register 28 can 1104 c0mdata629 can0 message data byte 6 register 29 can 1104 c0mdata630 can0 message data byte 6 register 30 can 1104 c0mdata631 can0 message data byte 6 register 31 can 1104 c0mdata6700 can0 message data byte 67 register 00 can 1104 c0mdata6701 can0 message data byte 67 register 01 can 1104 c0mdata6702 can0 message data byte 67 register 02 can 1104 c0mdata6703 can0 message data byte 67 register 03 can 1104 c0mdata6704 can0 message data byte 67 register 04 can 1104 c0mdata6705 can0 message data byte 67 register 05 can 1104 c0mdata6706 can0 message data byte 67 register 06 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1772 of 1817 sep 19, 2011 (12/43) symbol name unit page c0mdata6707 can0 message data byte 67 register 07 can 1104 c0mdata6708 can0 message data byte 67 register 08 can 1104 c0mdata6709 can0 message data byte 67 register 09 can 1104 c0mdata6710 can0 message data byte 67 register 10 can 1104 c0mdata6711 can0 message data byte 67 register 11 can 1104 c0mdata6712 can0 message data byte 67 register 12 can 1104 c0mdata6713 can0 message data byte 67 register 13 can 1104 c0mdata6714 can0 message data byte 67 register 14 can 1104 c0mdata6715 can0 message data byte 67 register 15 can 1104 c0mdata6716 can0 message data byte 67 register 16 can 1104 c0mdata6717 can0 message data byte 67 register 17 can 1104 c0mdata6718 can0 message data byte 67 register 18 can 1104 c0mdata6719 can0 message data byte 67 register 19 can 1104 c0mdata6720 can0 message data byte 67 register 20 can 1104 c0mdata6721 can0 message data byte 67 register 21 can 1104 c0mdata6722 can0 message data byte 67 register 22 can 1104 c0mdata6723 can0 message data byte 67 register 23 can 1104 c0mdata6724 can0 message data byte 67 register 24 can 1104 c0mdata6725 can0 message data byte 67 register 25 can 1104 c0mdata6726 can0 message data byte 67 register 26 can 1104 c0mdata6727 can0 message data byte 67 register 27 can 1104 c0mdata6728 can0 message data byte 67 register 28 can 1104 c0mdata6729 can0 message data byte 67 register 29 can 1104 c0mdata6730 can0 message data byte 67 register 30 can 1104 c0mdata6731 can0 message data byte 67 register 31 can 1104 c0mdata700 can0 message data byte 7 register 00 can 1104 c0mdata701 can0 message data byte 7 register 01 can 1104 c0mdata702 can0 message data byte 7 register 02 can 1104 c0mdata703 can0 message data byte 7 register 03 can 1104 c0mdata704 can0 message data byte 7 register 04 can 1104 c0mdata705 can0 message data byte 7 register 05 can 1104 c0mdata706 can0 message data byte 7 register 06 can 1104 c0mdata707 can0 message data byte 7 register 07 can 1104 c0mdata708 can0 message data byte 7 register 08 can 1104 c0mdata709 can0 message data byte 7 register 09 can 1104 c0mdata710 can0 message data byte 7 register 10 can 1104 c0mdata711 can0 message data byte 7 register 11 can 1104 c0mdata712 can0 message data byte 7 register 12 can 1104 c0mdata713 can0 message data byte 7 register 13 can 1104 c0mdata714 can0 message data byte 7 register 14 can 1104 c0mdata715 can0 message data byte 7 register 15 can 1104 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1773 of 1817 sep 19, 2011 (13/43) symbol name unit page c0mdata716 can0 message data byte 7 register 16 can 1104 c0mdata717 can0 message data byte 7 register 17 can 1104 c0mdata718 can0 message data byte 7 register 18 can 1104 c0mdata719 can0 message data byte 7 register 19 can 1104 c0mdata720 can0 message data byte 7 register 20 can 1104 c0mdata721 can0 message data byte 7 register 21 can 1104 c0mdata722 can0 message data byte 7 register 22 can 1104 c0mdata723 can0 message data byte 7 register 23 can 1104 c0mdata724 can0 message data byte 7 register 24 can 1104 c0mdata725 can0 message data byte 7 register 25 can 1104 c0mdata726 can0 message data byte 7 register 26 can 1104 c0mdata727 can0 message data byte 7 register 27 can 1104 c0mdata728 can0 message data byte 7 register 28 can 1104 c0mdata729 can0 message data byte 7 register 29 can 1104 c0mdata730 can0 message data byte 7 register 30 can 1104 c0mdata731 can0 message data byte 7 register 31 can 1104 c0mdlc00 can0 message data length register 00 can 1106 c0mdlc01 can0 message data length register 01 can 1106 c0mdlc02 can0 message data length register 02 can 1106 c0mdlc03 can0 message data length register 03 can 1106 c0mdlc04 can0 message data length register 04 can 1106 c0mdlc05 can0 message data length register 05 can 1106 c0mdlc06 can0 message data length register 06 can 1106 c0mdlc07 can0 message data length register 07 can 1106 c0mdlc08 can0 message data length register 08 can 1106 c0mdlc09 can0 message data length register 09 can 1106 c0mdlc10 can0 message data length register 10 can 1106 c0mdlc11 can0 message data length register 11 can 1106 c0mdlc12 can0 message data length register 12 can 1106 c0mdlc13 can0 message data length register 13 can 1106 c0mdlc14 can0 message data length register 14 can 1106 c0mdlc15 can0 message data length register 15 can 1106 c0mdlc16 can0 message data length register 16 can 1106 c0mdlc17 can0 message data length register 17 can 1106 c0mdlc18 can0 message data length register 18 can 1106 c0mdlc19 can0 message data length register 19 can 1106 c0mdlc20 can0 message data length register 20 can 1106 c0mdlc21 can0 message data length register 21 can 1106 c0mdlc22 can0 message data length register 22 can 1106 c0mdlc23 can0 message data length register 23 can 1106 c0mdlc24 can0 message data length register 24 can 1106 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1774 of 1817 sep 19, 2011 (14/43) symbol name unit page c0mdlc25 can0 message data length register 25 can 1106 c0mdlc26 can0 message data length register 26 can 1106 c0mdlc27 can0 message data length register 27 can 1106 c0mdlc28 can0 message data length register 28 can 1106 c0mdlc29 can0 message data length register 29 can 1106 c0mdlc30 can0 message data length register 30 can 1106 c0mdlc31 can0 message data length register 31 can 1106 c0midh00 can0 message identifier register 00 can 1108 c0midh01 can0 message identifier register 01 can 1108 c0midh02 can0 message identifier register 02 can 1108 c0midh03 can0 message identifier register 03 can 1108 c0midh04 can0 message identifier register 04 can 1108 c0midh05 can0 message identifier register 05 can 1108 c0midh06 can0 message identifier register 06 can 1108 c0midh07 can0 message identifier register 07 can 1108 c0midh08 can0 message identifier register 08 can 1108 c0midh09 can0 message identifier register 09 can 1108 c0midh10 can0 message identifier register 10 can 1108 c0midh11 can0 message identifier register 11 can 1108 c0midh12 can0 message identifier register 12 can 1108 c0midh13 can0 message identifier register 13 can 1108 c0midh14 can0 message identifier register 14 can 1108 c0midh15 can0 message identifier register 15 can 1108 c0midh16 can0 message identifier register 16 can 1108 c0midh17 can0 message identifier register 17 can 1108 c0midh18 can0 message identifier register 18 can 1108 c0midh19 can0 message identifier register 19 can 1108 c0midh20 can0 message identifier register 20 can 1108 c0midh21 can0 message identifier register 21 can 1108 c0midh22 can0 message identifier register 22 can 1108 c0midh23 can0 message identifier register 23 can 1108 c0midh24 can0 message identifier register 24 can 1108 c0midh25 can0 message identifier register 25 can 1108 c0midh26 can0 message identifier register 26 can 1108 c0midh27 can0 message identifier register 27 can 1108 c0midh28 can0 message identifier register 28 can 1108 c0midh29 can0 message identifier register 29 can 1108 c0midh30 can0 message identifier register 30 can 1108 c0midh31 can0 message identifier register 31 can 1108 c0midl00 can0 message identifier register 00 can 1108 c0midl01 can0 message identifier register 01 can 1108 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1775 of 1817 sep 19, 2011 (15/43) symbol name unit page c0midl02 can0 message identifier register 02 can 1108 c0midl03 can0 message identifier register 03 can 1108 c0midl04 can0 message identifier register 04 can 1108 c0midl05 can0 message identifier register 05 can 1108 c0midl06 can0 message identifier register 06 can 1108 c0midl07 can0 message identifier register 07 can 1108 c0midl08 can0 message identifier register 08 can 1108 c0midl09 can0 message identifier register 09 can 1108 c0midl10 can0 message identifier register 10 can 1108 c0midl11 can0 message identifier register 11 can 1108 c0midl12 can0 message identifier register 12 can 1108 c0midl13 can0 message identifier register 13 can 1108 c0midl14 can0 message identifier register 14 can 1108 c0midl15 can0 message identifier register 15 can 1108 c0midl16 can0 message identifier register 16 can 1108 c0midl17 can0 message identifier register 17 can 1108 c0midl18 can0 message identifier register 18 can 1108 c0midl19 can0 message identifier register 19 can 1108 c0midl20 can0 message identifier register 20 can 1108 c0midl21 can0 message identifier register 21 can 1108 c0midl22 can0 message identifier register 22 can 1108 c0midl23 can0 message identifier register 23 can 1108 c0midl24 can0 message identifier register 24 can 1108 c0midl25 can0 message identifier register 25 can 1108 c0midl26 can0 message identifier register 26 can 1108 c0midl27 can0 message identifier register 27 can 1108 c0midl28 can0 message identifier register 28 can 1108 c0midl29 can0 message identifier register 29 can 1108 c0midl30 can0 message identifier register 30 can 1108 c0midl31 can0 message identifier register 31 can 1108 c0rgpt can0 module receive history list register can 1099 c0tgpt can0 module transmit history list register can 1101 c0ts can0 module time stamp register can 1102 cam1 carry mask register 1 ethernet 1397 cam2 carry mask register 2 ethernet 1399 car1 carry register 1 ethernet 1392 car2 carry register 2 ethernet 1394 ccls cpu operation clock status register cg 226 ce0ctl0 csie0 control register 0 csie 849 ce0ctl1 csie0 control register 1 csie 851 ce0ctl2 csie0 control register 2 csie 853 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1776 of 1817 sep 19, 2011 (16/43) symbol name unit page ce0ctl3 csie0 control register 3 csie 854 ce0rx0 csie0 receive data register 0 csie 846 ce0rx0h csie0 receive data register 0h csie 846 ce0rx0l csie0 receive data register 0l csie 846 ce0str csie0 status register csie 855 ce0tic interrupt control register intc 1577 ce0tiofic interrupt control register intc 1577 ce0tx0 csie0 transmit data register csie 847 ce0txh0 csie0 transmit data register h csie 847 ce0txl0 csie0 transmit data register l csie 847 ce1ctl0 csie1 control register 0 csie 849 ce1ctl1 csie1 control register 1 csie 851 ce1ctl2 csie1 control register 2 csie 853 ce1ctl3 csie1 control register 3 csie 854 ce1rx0 csie1 receive data register csie 846 ce1rx0h csie1 receive data register h csie 846 ce1rx0l csie1 receive data register l csie 846 ce1str csie1 status register csie 855 ce1tic interrupt control register intc 1577 ce1tiofic interrupt control register intc 1577 ce1tx0 csie1 transmit data register csie 847 ce1tx0h csie1 transmit data register h csie 847 ce1tx0l csie1 transmit data register l csie 847 cf0ctl0 csif0 control register 0 csif 901 cf0ctl1 csif0 control register 1 csif 904 cf0ctl2 csif0 control register 2 csif 905 cf0ric interrupt control register intc 1577 cf0rx csif0 receive data register csif 900 cf0rxl csif0 receive data register l csif 900 cf0str csif0 status register csif 907 cf0tic interrupt control register intc 1577 cf0tx csif0 transmit data register csif 900 cf0txl csif0 transmit data register l csif 900 cf1ctl0 csif1 control register 0 csif 901 cf1ctl1 csif1 control register 1 csif 904 cf1ctl2 csif1 control register 2 csif 905 cf1ric interrupt control register intc 1577 cf1rx csif1 receive data register csif 900 cf1rxl csif1 receive data register l csif 900 cf1str csif1 status register csif 907 cf1tic interrupt control register intc 1577 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1777 of 1817 sep 19, 2011 (17/43) symbol name unit page cf1tx csif1 transmit data register csif 900 cf1txl csif1 transmit data register l csif 900 cf2ctl0 csif2 control register 0 csif 901 cf2ctl1 csif2 control register 1 csif 904 cf2ctl2 csif2 control register 2 csif 905 cf2ric interrupt control register intc 1577 cf2rx csif2 receive data register csif 900 cf2rxl csif2 receive data register l csif 900 cf2str csif2 status register csif 907 cf2tic interrupt control register intc 1577 cf2tx csif2 transmit data register csif 900 cf2txl csif2 transmit data register l csif 900 cf3ctl0 csif3 control register 0 csif 901 cf3ctl1 csif3 control register 1 csif 904 cf3ctl2 csif3 control register 2 csif 905 cf3ric interrupt control register intc 1577 cf3rx csif3 receive data register csif 900 cf3rxl csif3 receive data register l csif 900 cf3str csif3 status register csif 907 cf3tic interrupt control register intc 1577 cf3tx csif3 transmit data register csif 900 cf3txl csif3 transmit data register l csif 900 cf4ctl0 csif4 control register 0 csif 901 cf4ctl1 csif4 control register 1 csif 904 cf4ctl2 csif4 control register 2 csif 905 cf4ric interrupt control register intc 1577 cf4rx csif4 receive data register csif 900 cf4rxl csif4 receive data register l csif 900 cf4str csif4 status register csif 907 cf4tic interrupt control register intc 1577 cf4tx csif4 transmit data register csif 900 cf4txl csif4 transmit data register l csif 900 cf5ctl0 csif5 control register 0 csif 901 cf5ctl1 csif5 control register 1 csif 904 cf5ctl2 csif5 control register 2 csif 905 cf5ric interrupt control register intc 1577 cf5rx csif5 receive data register csif 900 cf5rxl csif5 receive data register l csif 900 cf5str csif5 status register csif 907 cf5tic interrupt control register intc 1577 cf5tx csif5 transmit data register csif 900 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1778 of 1817 sep 19, 2011 (18/43) symbol name unit page cf5txl csif5 transmit data register l csif 900 cf6ctl0 csif6 control register 0 csif 901 cf6ctl1 csif6 control register 1 csif 904 cf6ctl2 csif6 control register 2 csif 905 cf6ric interrupt control register intc 1577 cf6rx csif6 receive data register csif 900 cf6rxl csif6 receive data register l csif 900 cf6str csif6 status register csif 907 cf6tic interrupt control register intc 1577 cf6tx csif6 transmit data register csif 900 cf6txl csif6 transmit data register l csif 900 ckc clock control register cg 229 clm clock monitor mode register clm 1639 clrt collision register ethernet 1377 cpubctl cpu i/f bus control register usbf 1303 crcd crc data register crc 1650 crcin crc input register crc 1650 ctbp callt base pointer cpu 66 ctpc callt execution status saving registers cpu 65 ctpsw callt execution stat us saving registers cpu 65 dadc0 dma addressing control register 0 dmac 1533 dadc1 dma addressing control register 1 dmac 1533 dadc2 dma addressing control register 2 dmac 1533 dadc3 dma addressing control register 3 dmac 1533 dbc0 dma transfer count register 0 dmac 1532 dbc1 dma transfer count register 1 dmac 1532 dbc2 dma transfer count register 2 dmac 1532 dbc3 dma transfer count register 3 dmac 1532 dbpc exception/debug trap status saving registers cpu 66 dbpsw exception/debug trap status saving registers cpu 66 dchc0 dma channel control register 0 dmac 1534 dchc1 dma channel control register 1 dmac 1534 dchc2 dma channel control register 2 dmac 1534 dchc3 dma channel control register 3 dmac 1534 dda0h dma destination address register 0h dmac 1531 dda0l dma destination address register 0l dmac 1531 dda1h dma destination address register 1h dmac 1531 dda1l dma destination address register 1l dmac 1531 dda2h dma destination address register 2h dmac 1531 dda2l dma destination address register 2l dmac 1531 dda3h dma destination address register 3h dmac 1531 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1779 of 1817 sep 19, 2011 (19/43) symbol name unit page dda3l dma destination address register 3l dmac 1531 dmacm dma controller mode control register ethernet 1473 dmaic0 interrupt control register intc 1577 dmaic1 interrupt control register intc 1577 dmaic2 interrupt control register intc 1577 dmaic3 interrupt control register intc 1577 dsa0h dma source address register 0h dmac 1530 dsa0l dma source address register 0l dmac 1530 dsa1h dma source address register 1h dmac 1530 dsa1l dma source address register 1l dmac 1530 dsa2h dma source address register 2h dmac 1530 dsa2l dma source address register 2l dmac 1530 dsa3h dma source address register 3h dmac 1530 dsa3l dma source address register 3l dmac 1530 dtfr0 dma trigger factor register 0 dmac 1535 dtfr1 dma trigger factor register 1 dmac 1535 dtfr2 dma trigger factor register 2 dmac 1535 dtfr3 dma trigger factor register 3 dmac 1535 dwc0 data wait control register 0 bcu 208 ecr interrupt source register cpu 63 eipc interrupt status saving registers cpu 62 eipsw interrupt status saving registers cpu 62 epcclt epc macro control register usbf 1302 erric0 interrupt control register intc 1577 ethmode core function control register ethernet 1468 exdrqen external dma request enable register dmac 1538 fepc nmi status saving registers cpu 63 fepsw nmi status saving registers cpu 63 flowthresh flow control threshold value register ethernet 1444 fstatus fifo status interrupt register ethernet 1457 fstatus_mask fifo status inte rrupt mask register ethernet 1459 ht1 hash table register 1 ethernet 1390 ht2 hash table register 2 ethernet 1391 hza0ctl0 high impedance output control register 0 motor 605 hza0ctl1 high impedance output control register 1 motor 605 iic0 iic shift register 0 i 2 c 968 iic1 iic shift register 1 i 2 c 968 iic2 iic shift register 2 i 2 c 968 iic3 iic shift register 3 i 2 c 968 iic4 iic shift register 4 i 2 c 968 iicc0 iic control register 0 i 2 c 955 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1780 of 1817 sep 19, 2011 (20/43) symbol name unit page iicc1 iic control register 1 i 2 c 955 iicc2 iic control register 2 i 2 c 955 iicc3 iic control register 3 i 2 c 955 iicc4 iic control register 4 i 2 c 955 iiccl0 iic clock select register 0 i 2 c 965 iiccl1 iic clock select register 1 i 2 c 965 iiccl2 iic clock select register 2 i 2 c 965 iiccl3 iic clock selection register 3 i 2 c 965 iiccl4 iic clock selection register 4 i 2 c 965 iicf0 iic flag register 0 i 2 c 963 iicf1 iic flag register 1 i 2 c 963 iicf2 iic flag register 2 i 2 c 963 iicf3 iic flag register 3 i 2 c 963 iicf4 iic flag register 4 i 2 c 963 iicic0 interrupt control register intc 1577 iicic1 interrupt control register intc 1577 iicic2 interrupt control register intc 1577 iicic3 interrupt control register intc 1577 iicic4 interrupt control register intc 1577 iics0 iic status register 0 i 2 c 960 iics1 iic status register 1 i 2 c 960 iics2 iic status register 2 i 2 c 960 iics3 iic status register 3 i 2 c 960 iics4 iic status register 4 i 2 c 960 iicx0 iic function expansion register 0 i 2 c 966 iicx1 iic function expansion register 1 i 2 c 966 iicx2 iic function expansion register 2 i 2 c 966 iicx3 iic function expansion register 3 i 2 c 966 iicx4 iic function expansion register 4 i 2 c 966 imr0 interrupt mask register 0 intc 1582 imr0h interrupt mask register 0h intc 1582 imr0l interrupt mask register 0l intc 1582 imr1 interrupt mask register 1 intc 1582 imr1h interrupt mask register 1h intc 1582 imr1l interrupt mask register 1l intc 1582 imr2 interrupt mask register 2 intc 1582 imr2h interrupt mask register 2h intc 1582 imr2l interrupt mask register 2l intc 1582 imr3 interrupt mask register 3 intc 1582 imr3h interrupt mask register 3h intc 1582 imr3l interrupt mask register 3l intc 1582 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1781 of 1817 sep 19, 2011 (21/43) symbol name unit page imr4 interrupt mask register 4 intc 1582 imr4h interrupt mask register 4h intc 1582 imr4l interrupt mask register 4l intc 1582 imr5 interrupt mask register 5 intc 1582 imr5h interrupt mask register 5h intc 1582 imr5l interrupt mask register 5l intc 1582 imr6 interrupt mask register 6 intc 1582 imr6h interrupt mask register 6h intc 1582 imr6l interrupt mask register 6l intc 1582 imr7 interrupt mask register 7 intc 1582 imr7l interrupt mask register 7l intc 1582 intf0 external interrupt falling edge specification register 0 intc 1594 intf2 external interrupt falling edge specification register 2 intc 1595 intf3 external interrupt falling edge specification register 3 intc 1596 intf4 external interrupt falling edge specification register 4 intc 1597 intf5 external interrupt falling edge specification register 5 intc 1598 intf5h external interrupt falling edge specification register 5h intc 1598 intf5l external interrupt falling edge specification register 5l intc 1598 intf9 external interrupt falling edge specification register 9 intc 1599 intf9h external interrupt falling edge specification register 9h intc 1599 intf9l external interrupt falling edge specification register 9l intc 1599 intms interrupt register ethernet 1469 intnfc noise elimination control register intc 1600 intr0 external interrupt rising edge specification register 0 intc 1594 intr2 external interrupt rising edge specification register 2 intc 1595 intr3 external interrupt rising edge specification register 3 intc 1596 intr4 external interrupt rising edge specification register 4 intc 1597 intr5 external interrupt rising edge specification register 5 intc 1598 intr5h external interrupt rising edge specification register 5h intc 1598 intr5l external interrupt rising edge specification register 5l intc 1598 intr9 external interrupt rising edge specification register 9 intc 1599 intr9h external interrupt rising edge specification register 9h intc 1599 intr9l external interrupt rising edge specification register 9l intc 1599 ipgr non back-to-back ipg register ethernet 1376 ipgt back-to-back ipg register ethernet 1375 ispr in-service priority register intc 1584 kric interrupt control register intc 1584 krm key return mode register kr 1604 lmax maximum packet length register ethernet 1378 lockr lock register cg 230 lsa1 station address register 1 ethernet 1379 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1782 of 1817 sep 19, 2011 (22/43) symbol name unit page lsa2 station address register 2 ethernet 1380 lstrxdp last reception descript or pointer register ethernet 1475 lsttxdp last transmission descriptor pointer register ethernet 1477 lviic interrupt control register intc 1577 lvim low-voltage detection register lvi 1644 macc1 mac setting register 1 ethernet 1372 macc2 mac setting register 2 ethernet 1374 madr mii address register ethernet 1385 mcmd mii command register ethernet 1384 mffcont fifo controller control register ethernet 1441 miic mii configuration register ethernet 1383 miictl ethernet control register ethernet 1368 mind mii indicator register ethernet 1388 mrdd mii read data register ethernet 1387 mwtd mii write data register ethernet 1386 ocdm on-chip debug mode register dcu 104 ocks0 iic division clock select register 0 i 2 c 968 ocks1 iic division clock select register 1 i 2 c 968 ocks2 iic division clock select register 2 i 2 c 968 osts oscillation stabilization time select register standby 1609 p0 port 0 register port 117 p2 port 2 register port 120 p3 port 3 register port 127 p4 port 4 register port 133 p4h port 4 register h port 133 p4l port 4 register l port 133 p5 port 5 register port 142 p5h port 5 register h port 142 p5l port 5 register l port 142 p7h port 7 register h port 149 p7l port 7 register l port 149 p9 port 9 register port 152 p9h port 9 register h port 152 p9l port 9 register l port 152 pausetm pause timer value register ethernet 1445 pc program counter cpu 60 pcc processor clock control register cg 222 pcm port cm register port 160 pcs port cs register port 163 pct port ct register port 166 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1783 of 1817 sep 19, 2011 (23/43) symbol name unit page pdh port dh register port 169 pdl port dl register port 176 pdlh port dl register h port 176 pdll port dl register l port 176 pf0 port 0 function register port 119 pf2 port 2 function register port 126 pf3 port 3 function register port 131 pf4 port 4 function register port 140 pf4h port 4 function register h port 140 pf4l port 4 function register l port 140 pf5 port 5 function register port 146 pf5h port 5 function register h port 146 pf5l port 5 function register l port 146 pf9 port 9 function register port 159 pf9h port 9 function register h port 159 pf9l port 9 function register l port 159 pfc0 port 0 function control register port 118 pfc2 port 2 function control register port 124 pfc3 port 3 function control register port 129 pfc4 port 4 function control register port 137 pfc4h port 4 function control register h port 137 pfc4l port 4 function control register l port 137 pfc5 port 5 function control register port 146 pfc5h port 5 function control register h port 146 pfc5l port 5 function control register l port 146 pfc9 port 9 function control register port 155 pfc9h port 9 function control register h port 155 pfc9l port 9 function control register l port 155 pfcdh port dh function control register port 173 pfce0 port 0 function control expansion register port 118 pfce2 port 2 function control expansion register port 124 pfce3 port 3 function control expansion register port 129 pfce4l port 4 function control expansion register l port 137 pfce5l port 5 function control expansion register l port 146 pfce9 port 9 function control expansion register port 155 pfce9h port 9 function control expansion register h port 155 pfce9l port 9 function control expansion register l port 155 pfcedh port dh function control expansion register port 173 pic00 interrupt control register intc 1577 pic01 interrupt control register intc 1577 pic02 interrupt control register intc 1577 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1784 of 1817 sep 19, 2011 (24/43) symbol name unit page pic03 interrupt control register intc 1577 pic04 interrupt control register intc 1577 pic05 interrupt control register intc 1577 pic06 interrupt control register intc 1577 pic07 interrupt control register intc 1577 pic08 interrupt control register intc 1577 pic09 interrupt control register intc 1577 pic10 interrupt control register intc 1577 pic11 interrupt control register intc 1577 pic12 interrupt control register intc 1577 pic13 interrupt control register intc 1577 pic14 interrupt control register intc 1577 pic15 interrupt control register intc 1577 pic16 interrupt control register intc 1577 pic17 interrupt control register intc 1577 pic18 interrupt control register intc 1577 pic19 interrupt control register intc 1577 pic20 interrupt control register intc 1577 pic21 interrupt control register intc 1577 pic22 interrupt control register intc 1577 pic23 interrupt control register intc 1577 pic24 interrupt control register intc 1577 pic25 interrupt control register intc 1577 pllctl pll control register cg 228 plls pll lockup time specification register cg 231 pm0 port 0 mode register port 117 pm2 port 2 mode register port 121 pm3 port 3 mode register port 127 pm4 port 4 mode register port 134 pm4h port 4 mode register h port 134 pm4l port 4 mode register l port 134 pm5 port 5 mode register port 143 pm5h port 5 mode register h port 143 pm5l port 5 mode register l port 143 pm7h port 7 mode register h port 150 pm7l port 7 mode register l port 150 pm9 port 9 mode register port 152 pm9h port 9 mode register h port 152 pm9l port 9 mode register l port 152 pmc0 port 0 mode control register port 118 pmc2 port 2 mode control register port 122 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1785 of 1817 sep 19, 2011 (25/43) symbol name unit page pmc3 port 3 mode control register port 128 pmc4 port 4 mode control register port 135 pmc4h port 4 mode control register h port 135 pmc4l port 4 mode control register l port 135 pmc5 port 5 mode control register port 144 pmc5h port 5 mode control register h port 144 pmc5l port 5 mode control register l port 144 pmc9 port 9 mode control register port 153 pmc9h port 9 mode control register h port 153 pmc9l port 9 mode control register l port 153 pmccm port cm mode control register port 162 pmccs port cs mode control register port 165 pmcct port ct mode control register port 167 pmcdh port dh mode control register port 171 pmcdl port dl mode control register port 177 pmcdlh port dl mode control register h port 177 pmcdll port dl mode control register l port 177 pmcm port cm mode register port 161 pmcs port cs mode register port 164 pmct port ct mode register port 166 pmdh port dh mode register port 170 pmdl port dl mode register port 176 pmdlh port dl mode register h port 176 pmdll port dl mode register l port 176 prcmd command register cpu 102 prscm0 prescaler compare register 0 brg 673 prscm1 prescaler compare register 1 brg 944 prscm2 prescaler compare register 2 brg 944 prscm3 prescaler compare register 3 brg 944 prscm4 prescaler compare register 4 brg 944 prsm0 prescaler mode register 0 brg 672 prsm1 prescaler mode register 1 brg 943 prsm2 prescaler mode register 2 brg 943 prsm3 prescaler mode register 3 brg 943 prsm4 prescaler mode register 4 brg 943 psc power save control register cg 1607 psmr power save mode register cg 1608 psw program status word cpu 64 ptvr pause timer value read register ethernet 1381 r0 to r31 general-purpose registers cpu 60 r127 receive 65- to 127-byte frame counter ethernet 1419 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1786 of 1817 sep 19, 2011 (26/43) symbol name unit page r1k receive 512- to 1023-byte frame counter ethernet 1422 r255 receive 128- to 255-byte frame counter ethernet 1420 r511 receive 256- to 511-byte frame counter ethernet 1421 r64 receive 64-byte frame counter ethernet 1418 raln reception alignment error counter ethernet 1410 rams internal ram data status register lvi 1645 rbca reception broadcast packet counter ethernet 1406 rbyt reception byte counter ethernet 1402 rc1alh alarm time set register rtc 670 rc1alm alarm minute set register rtc 670 rc1alw alarm week set register rtc 671 rc1cc0 rtc control register 0 rtc 659 rc1cc1 rtc control register 1 rtc 659 rc1cc2 rtc control register 2 rtc 661 rc1cc3 rtc control register 3 rtc 662 rc1day day count register rtc 666 rc1hour hour count register rtc 664 rc1min minute count register rtc 664 rc1month month count register rtc 668 rc1sec second count register rtc 663 rc1subc sub-count register rtc 663 rc1subu time error correction register rtc 669 rc1week week count register rtc 667 rc1year year count register rtc 668 rcde reception code error counter ethernet 1412 rcm internal oscillation mode register cg 226 recic0 interrupt control register intc 1577 resf reset source flag register reset 1629 rfcr reception false carrier counter ethernet 1413 rfcs reception fcs error frame counter ethernet 1404 rflr reception frame length error counter ethernet 1411 rfrg reception fragment counter ethernet 1416 rjbr reception jabber counter ethernet 1417 rmax receive 1024- to rmax-byte frame counter ethernet 1423 rmca reception multicast packet counter ethernet 1405 rovr reception oversize packet counter ethernet 1415 rpkt reception packet counter ethernet 1403 rstcnt software reset control register ethernet 1443 rtbh0 real-time output buffer register 0h rto 693 rtbl0 real-time output buffer register 0l rto 693 rtc0ic interrupt control register intc 1577 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1787 of 1817 sep 19, 2011 (27/43) symbol name unit page rtc1ic interrupt control register intc 1577 rtc2ic interrupt control register intc 1577 rtpc0 real-time output port control register 0 rto 695 rtpm0 real-time output port mode register 0 rto 694 rund reception undersize packet counter ethernet 1414 rvbt receive valid byte counter ethernet 1424 rxabtcnt reception abort counter ethernet 1467 rxcf reception control frame packet counter ethernet 1407 rxdp reception descriptor pointer register ethernet 1474 rxersel receive error selection register ethernet 1446 rxfinf1 reception status 1 register ethernet 1454 rxfinf2 reception status 2 register ethernet 1455 rxfinf3 reception status 3 register ethernet 1456 rxpf reception pause frame packet counter ethernet 1408 rxstatus reception status interrupt register ethernet 1462 rxstatus_mask reception status in terrupt mask register ethernet 1464 rxstmoni reception status monitor register ethernet 1452 rxuo reception undefined cont rol packet counter ethernet 1409 selcnt0 selector operation control register 0 timer 347 sftrst software reset register ethernet 1472 sva0 slave address register 0 i 2 c 969 sva1 slave address register 1 i 2 c 969 sva2 slave address register 2 i 2 c 969 sva3 slave address register 3 i 2 c 969 sva4 slave address register 4 i 2 c 969 sys system status register cpu 103 taa0ccic0 interrupt control register intc 1577 taa0ccic1 interrupt control register intc 1577 taa0ccr0 taa0 capture/compare register 0 timer 246 taa0ccr1 taa0 capture/compare register 1 timer 248 taa0cnt taa0 counter read buffer register timer 250 taa0ctl0 taa0 control register 0 timer 237 taa0ctl1 taa0 control register 1 timer 238 taa0ioc0 taa0 i/o control register 0 timer 240 taa0ioc1 taa0 i/o control register 1 timer 241 taa0ioc2 taa0 i/o control register 2 timer 242 taa0ioc4 taa0 i/o control register 4 timer 243 taa0opt0 taa0 option register 0 timer 244 taa0opt1 taa0 option register 1 timer 245 taa0ovic interrupt control register intc 1577 taa1ccic0 interrupt control register intc 1577 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1788 of 1817 sep 19, 2011 (28/43) symbol name unit page taa1ccic1 interrupt control register intc 1577 taa1ccr0 taa1 capture/compare register 0 timer 246 taa1ccr1 taa1 capture/compare register 1 timer 248 taa1cnt taa1 counter read buffer register timer 250 taa1ctl0 taa1 control register 0 timer 237 taa1ctl1 taa1 control register 1 timer 238 taa1ioc0 taa1 i/o control register 0 timer 240 taa1ioc1 taa1 i/o control register 1 timer 241 taa1ioc2 taa1 i/o control register 2 timer 242 taa1ioc4 taa1 i/o control register 4 timer 243 taa1opt0 taa1 option register 0 timer 244 taa1ovic interrupt control register intc 1577 taa2ccic0 interrupt control register intc 1577 taa2ccic1 interrupt control register intc 1577 taa2ccr0 taa2 capture/compare register 0 timer 246 taa2ccr1 taa2 capture/compare register 1 timer 248 taa2cnt taa2 counter read buffer register timer 250 taa2ctl0 taa2 control register 0 timer 237 taa2ctl1 taa2 control register 1 timer 238 taa2ioc0 taa2 i/o control register 0 timer 240 taa2ioc1 taa2 i/o control register 1 timer 241 taa2ioc2 taa2 i/o control register 2 timer 242 taa2ioc4 taa2 i/o control register 4 timer 243 taa2opt0 taa2 option register 0 timer 244 taa2opt1 taa2 option register 1 timer 245 taa2ovic interrupt control register intc 1577 taa3ccic0 interrupt control register intc 1577 taa3ccic1 interrupt control register intc 1577 taa3ccr0 taa3 capture/compare register 0 timer 246 taa3ccr1 taa3 capture/compare register 1 timer 248 taa3cnt taa3 counter read buffer register timer 250 taa3ctl0 taa3 control register 0 timer 237 taa3ctl1 taa3 control register 1 timer 238 taa3ioc0 taa3 i/o control register 0 timer 240 taa3ioc1 taa3 i/o control register 1 timer 241 taa3ioc2 taa3 i/o control register 2 timer 242 taa3ioc4 taa3 i/o control register4 timer 243 taa3opt0 taa3 option register 0 timer 244 taa3ovic interrupt control register intc 1577 taa4ccic0 interrupt control register intc 1577 taa4ccic1 interrupt control register intc 1577 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1789 of 1817 sep 19, 2011 (29/43) symbol name unit page taa4ccr0 taa4 capture compare register 0 timer 246 taa4ccr1 taa4 capture compare register 1 timer 248 taa4cnt taa4 counter read buffer register timer 250 taa4ctl0 taa4 control register 0 timer 237 taa4ctl1 taa4 control register 1 timer 238 taa4ioc0 taa4 i/o control register 0 timer 240 taa4ioc1 taa4 i/o control register 1 timer 241 taa4ioc2 taa4 i/o control register 2 timer 242 taa4ioc4 taa4 i/o control register 4 timer 243 taa4opt0 taa4 option register 0 timer 244 taa4ovic interrupt control register intc 1577 taa5ccic0 interrupt control register intc 1577 taa5ccic1 interrupt control register intc 1577 taa5ccr0 taa5 capture/compare register 0 timer 246 taa5ccr1 taa5 capture/compare register 1 timer 248 taa5cnt taa5 counter read buffer register timer 250 taa5ctl0 taa5 control register 0 timer 237 taa5ctl1 taa5 control register 1 timer 238 taa5ioc0 taa5 i/o control register 0 timer 240 taa5ioc1 taa5 i/o control register 1 timer 241 taa5ioc2 taa5 i/o control register 2 timer 242 taa5ioc4 taa5 i/o control register 4 timer 243 taa5opt0 taa5 option register 0 timer 244 taa5ovic interrupt control register intc 1577 tab0ccic0 interrupt control register intc 1577 tab0ccic1 interrupt control register intc 1577 tab0ccic2 interrupt control register intc 1577 tab0ccic3 interrupt control register intc 1577 tab0ccr0 tab0 capture/compare register 0 timer 361 tab0ccr1 tab0 capture/compare register 1 timer 363 tab0ccr2 tab0 capture/compare register 2 timer 365 tab0ccr3 tab0 capture/compare register 3 timer 367 tab0cnt tab0 counter read buffer register timer 369 tab0ctl0 tab0 control register 0 timer 354 tab0ctl1 tab0 control register 1 timer 355 tab0ioc0 tab0 i/o control register 0 timer 356 tab0ioc1 tab0 i/o control register 1 timer 357 tab0ioc2 tab0 i/o control register 2 timer 358 tab0ioc4 tab0 i/o control register 4 timer 359 tab0opt0 tab0 option register 0 timer 360 tab0ovic interrupt control register intc 1577 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1790 of 1817 sep 19, 2011 (30/43) symbol name unit page tab1ccic0 interrupt control register intc 1577 tab1ccic1 interrupt control register intc 1577 tab1ccic2 interrupt control register intc 1577 tab1ccic3 interrupt control register intc 1577 tab1ccr0 tab1 capture/compare register 0 timer 361 tab1ccr1 tab1 capture/compare register 1 timer 363 tab1ccr2 tab1 capture/compare register 2 timer 365 tab1ccr3 tab1 capture/compare register 3 timer 367 tab1cnt tab1 counter read buffer register timer 369 tab1ctl0 tab1 control register 0 timer 354 tab1ctl1 tab1 control register 1 timer 355 tab1dtc tab1 dead time compare register 1 timer 599 tab1ioc0 tab1 i/o control register 0 timer 356 tab1ioc1 tab1 i/o control register 1 timer 357 tab1ioc2 tab1 i/o control register 2 timer 358 tab1ioc3 tab1 i/o control register 3 timer 603 tab1ioc4 tab1 i/o control register 4 timer 359 tab1opt0 tab1 option register 0 timer 360 tab1opt1 tab1 option register 1 timer 600 tab1opt2 tab1 option register 2 timer 601 tab1ovic interrupt control register intc 1577 tanfc0 taa0 noise elimination control register timer 251 tanfc1 taa1 noise elimination control register timer 251 tanfc2 taa2 noise elimination control register timer 251 tanfc3 taa3 noise elimination control register timer 251 tanfc4 taa4 noise elimination control register timer 251 tanfc5 taa5 noise elimination control register timer 251 tbca transmission broadcast packet counter ethernet 1429 tbyt transmission byte counter ethernet 1425 tcse transmission carrier sense error counter ethernet 1439 tdfr transmission delay packet counter ethernet 1432 tfcs transmission fcs error frame counter ethernet 1427 time mac internal error counter ethernet 1440 tlcl transmission late collision packet counter ethernet 1436 tm0cmp0 tmm0 compare register 0 timer 587 tm0ctl0 tmm0 control register 0 timer 588 tm0eqic0 interrupt control register intc 1577 tm1cmp0 tmm1 compare register 0 timer 587 tm1ctl0 tmm1 control register 0 timer 588 tm1eqic0 interrupt control register intc 1577 tm2cmp0 tmm2 compare register 0 timer 587 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1791 of 1817 sep 19, 2011 (31/43) symbol name unit page tm2ctl0 tmm2 control register 0 timer 588 tm2eqic0 interrupt control register intc 1577 tm3cmp0 tmm3 compare register 0 timer 587 tm3ctl0 tmm3 control register 0 timer 588 tm3eqic0 interrupt control register intc 1577 tmca transmission multicast packet counter ethernet 1428 tmcl transmission multiple collision packet counter ethernet 1435 tncl transmission total collision counter ethernet 1438 tpkt transmission packet counter ethernet 1426 transctl transmission control register ethernet 1471 trxic0 interrupt control register intc 1577 tscl transmission single collision packet counter ethernet 1434 tt0ccic0 interrupt control register intc 1577 tt0ccic1 interrupt control register intc 1577 tt0ccr0 tmt0 capture/compare register 0 timer 472 tt0ccr1 tmt0 capture/compare register 1 timer 474 tt0cnt tmt0 counter read buffer register timer 476 tt0ctl0 tmt0 control register 0 timer 458 tt0ctl1 tmt0 control register 1 timer 459 tt0ctl2 tmt0 control register 2 timer 461 tt0iecic interrupt control register intc 1577 tt0ioc0 tmt0 i/o control register 0 timer 463 tt0ioc1 tmt0 i/o control register 1 timer 465 tt0ioc2 tmt0 i/o control register 2 timer 466 tt0ioc3 tmt0 i/o control register 3 timer 467 tt0opt0 tmt0 option register 0 timer 469 tt0opt1 tmt0 option register 1 timer 470 tt0ovic interrupt control register intc 1577 tt0tcw tmt0 counter write register timer 476 ttnfc tmt noise elimination control register timer 477 tuca transmission unicast packet counter ethernet 1430 txabtcnt transmission abort counter ethernet 1466 txcl transmission excessive collision packet counter ethernet 1437 txdf transmission excessive del ay packet counter ethernet 1433 txdp transmission descriptor pointer register ethernet 1476 txfinf1 transmission status 1 register ethernet 1450 txfinf2 transmission status 2 register ethernet 1451 txpf transmission pause cont rol frame counter ethernet 1431 txstatus transmission status interrupt register ethernet 1460 txstatus_mask transmission status in terrupt mask register ethernet 1461 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1792 of 1817 sep 19, 2011 (32/43) symbol name unit page txstmoni1 transmission status monitor 1 register ethernet 1448 txstmoni2 transmission status monitor 2 register ethernet 1449 ub0ctl0 uartb0 control register 0 uartb 742 ub0ctl2 uartb0 control register 2 uartb 747 ub0fic0 uartb0 fifo control register 0 uartb 751 ub0fic1 uartb0 fifo control register 1 uartb 753 ub0fic2 uartb0 fifo control register 2 uartb 754 ub0fic2h uartb0 fifo control register 2h uartb 754 ub0fic2l uartb0 fifo control register 2l uartb 754 ub0fis0 uartb0 status register 0 uartb 756 ub0fis1 uartb0 status register 1 uartb 757 ub0rx uartb0 receive data register uartb 749 ub0rxap uartb0 receive data register ap uartb 749 ub0str uartb0 status register uartb 745 ub0tific interrupt control register intc 1577 ub0tireic interrupt control register intc 1577 ub0tiric interrupt control register intc 1577 ub0titic interrupt control register intc 1577 ub0titoic interrupt control register intc 1577 ub0tx uartb0 transmit data register uartb 748 ub1ctl0 uartb1 control register 0 uartb 742 ub1ctl2 uartb1 control register 2 uartb 747 ub1fic0 uartb1 fifo control register 0 uartb 751 ub1fic1 uartb1 fifo control register 1 uartb 753 ub1fic2 uartb1 fifo control register 2 uartb 754 ub1fic2h uartb1 fifo control register 2h uartb 754 ub1fic2l uartb1 fifo control register 2l uartb 754 ub1fis0 uartb1 status register 0 uartb 756 ub1fis1 uartb1 status register 1 uartb 757 ub1rx uartb1 receive data register uartb 749 ub1rxap uartb1 receive data register ap uartb 749 ub1str uartb1 status register uartb 745 ub1tific interrupt control register intc 1577 ub1tireic interrupt control register intc 1577 ub1tiric interrupt control register intc 1577 ub1titic interrupt control register intc 1577 ub1titoic interrupt control register intc 1577 ub1tx uartb1 transmit data register uartb 748 uc0ctl0 uartc0 control register 0 uartc 806 uc0ctl1 uartc0 control register 1 uartc 833 uc0ctl2 uartc0 control register 2 uartc 834 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1793 of 1817 sep 19, 2011 (33/43) symbol name unit page uc0opt0 uartc0 option control register 0 uartc 808 uc0opt1 uartc0 option control register 1 uartc 810 uc0ric interrupt control register intc 1577 uc0rx uartc0 receive data register uartc 814 uc0rxl uartc0 receive data register l uartc 814 uc0str uartc0 status register uartc 812 uc0tic interrupt control register intc 1577 uc0tx uartc0 transmit data register uartc 815 uc0txl uartc0 transmit data register l uartc 815 uc1ctl0 uartc1 control register 0 uartc 806 uc1ctl1 uartc1 control register 1 uartc 833 uc1ctl2 uartc1 control register 2 uartc 834 uc1opt0 uartc1 option control register 0 uartc 808 uc1opt1 uartc1 option control register 1 uartc 810 uc1ric interrupt control register intc 1577 uc1rx uartc1 receive data register uartc 814 uc1rxl uartc1 receive data register l uartc 814 uc1str uartc1 status register uartc 812 uc1tic interrupt control register intc 1577 uc1tx uartc1 transmit data register uartc 815 uc1txl uartc1 transmit data register l uartc 815 uc2ctl0 uartc2 control register 0 uartc 806 uc2ctl1 uartc2 control register 1 uartc 833 uc2ctl2 uartc2 control register 2 uartc 834 uc2opt0 uartc2 option control register 0 uartc 808 uc2opt1 uartc2 option control register 1 uartc 810 uc2ric interrupt control register intc 1577 uc2rx uartc2 receive data register uartc 814 uc2rxl uartc2 receive data register l uartc 814 uc2str uartc2 status register uartc 812 uc2tic interrupt control register intc 1577 uc2tx uartc2 transmit data register uartc 815 uc2txl uartc2 transmit data register l uartc 815 uc3ctl0 uartc3 control register 0 uartc 806 uc3ctl1 uartc3 control register 1 uartc 833 uc3ctl2 uartc3 control register 2 uartc 834 uc3opt0 uartc3 option control register 0 uartc 808 uc3opt1 uartc3 option control register 1 uartc 810 uc3ric interrupt control register intc 1577 uc3rx uartc3 receive data register uartc 814 uc3rxl uartc3 receive data register l uartc 814 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1794 of 1817 sep 19, 2011 (34/43) symbol name unit page uc3str uartc3 status register uartc 812 uc3tic interrupt control register intc 1577 uc3tx uartc3 transmit data register uartc 815 uc3txl uartc3 transmit data register l uartc 815 uc4ctl0 uartc4 control register 0 uartc 806 uc4ctl1 uartc4 control register 1 uartc 833 uc4ctl2 uartc4 control register 2 uartc 834 uc4opt0 uartc4 option control register 0 uartc 808 uc4opt1 uartc4 option control register 1 uartc 810 uc4ric interrupt control register intc 1577 uc4rx uartc4 receive data register uartc 814 uc4rxl uartc4 receive data register l uartc 814 uc4str uartc4 status register uartc 812 uc4tic interrupt control register intc 1577 uc4tx uartc4 transmit data register uartc 815 uc4txl uartc4 transmit data register l uartc 815 uc5ctl0 uartc5 control register 0 uartc 806 uc5ctl1 uartc5 control register 1 uartc 833 uc5ctl2 uartc5 control register 2 uartc 834 uc5opt0 uartc5 option control register 0 uartc 808 uc5opt1 uartc5 option control register 1 uartc 810 uc5ric interrupt control register intc 1577 uc5rx uartc5 receive data register uartc 814 uc5rxl uartc5 receive data register l uartc 814 uc5str uartc5 status register uartc 812 uc5tic interrupt control register intc 1577 uc5tx uartc5 transmit data register uartc 815 uc5txl uartc5 transmit data register l uartc 815 uc6ctl0 uartc6 control register 0 uartc 806 uc6ctl1 uartc6 control register 1 uartc 833 uc6ctl2 uartc6 control register 2 uartc 834 uc6opt0 uartc6 option control register 0 uartc 808 uc6opt1 uartc6 option control register 1 uartc 810 uc6ric interrupt control register intc 1577 uc6rx uartc6 receive data register uartc 814 uc6rxl uartc6 receive data register l uartc 814 uc6str uartc6 status register uartc 812 uc6tic interrupt control register intc 1577 uc6tx uartc6 transmit data register uartc 815 uc6txl uartc6 transmit data register l uartc 815 uc7ctl0 uartc7 control register 0 uartc 806 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1795 of 1817 sep 19, 2011 (35/43) symbol name unit page uc7ctl1 uartc7 control register 1 uartc 833 uc7ctl2 uartc7 control register 2 uartc 834 uc7opt0 uartc7 option register uartc 808 uc7opt1 uartc7 option control register 1 uartc 810 uc7ric interrupt control register intc 1577 uc7rx uartc7 receive data register uartc 814 uc7rxl uartc7 receive data register l uartc 814 uc7str uartc7 status register uartc 812 uc7tic interrupt control register intc 1577 uc7tx uartc7 transmit data register uartc 815 uc7txl uartc7 transmit data register l uartc 815 ucksel usb clock selection register uartc 1193 uf0aas uf0 active alternative setting register usbf 1255 uf0adrs uf0 address register usbf 1292 uf0aifn uf0 active interface number register usbf 1254 uf0ass uf0 alternative setting status register usbf 1256 uf0bi1 uf0 bulk-in 1 register usbf 1275 uf0bi2 uf0 bulk-in 2 register usbf 1279 uf0bo1 uf0 bulk-out 1 register usbf 1268 uf0bo1l uf0 bulk-out 1 length register usbf 1271 uf0bo2 uf0 bulk-out 2 register usbf 1272 uf0bo2l uf0 bulk-out 2 length register usbf 1275 uf0cie0 uf0 configuration/interface/endp oint descriptor register 0 usbf 1298 uf0cie1 uf0 configuration/interface/endp oint descriptor register 1 usbf 1298 uf0cie10 uf0 configuration/interface/endp oint descriptor register 10 usbf 1298 uf0cie100 uf0 configuration/interface/endp oint descriptor register 100 usbf 1298 uf0cie101 uf0 configuration/interface/endp oint descriptor register 101 usbf 1298 uf0cie102 uf0 configuration/interface/endp oint descriptor register 102 usbf 1298 uf0cie103 uf0 configuration/interface/endp oint descriptor register 103 usbf 1298 uf0cie104 uf0 configuration/interface/endp oint descriptor register 104 usbf 1298 uf0cie105 uf0 configuration/interface/endp oint descriptor register 105 usbf 1298 uf0cie106 uf0 configuration/interface/endp oint descriptor register 106 usbf 1298 uf0cie107 uf0 configuration/interface/endp oint descriptor register 107 usbf 1298 uf0cie108 uf0 configuration/interface/endp oint descriptor register 108 usbf 1298 uf0cie109 uf0 configuration/interface/endp oint descriptor register 109 usbf 1298 uf0cie11 uf0 configuration/interface/endp oint descriptor register 11 usbf 1298 uf0cie110 uf0 configuration/interface/endp oint descriptor register 110 usbf 1298 uf0cie111 uf0 configuration/interface/endp oint descriptor register 111 usbf 1298 uf0cie112 uf0 configuration/interface/endp oint descriptor register 112 usbf 1298 uf0cie113 uf0 configuration/interface/endp oint descriptor register 113 usbf 1298 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1796 of 1817 sep 19, 2011 (36/43) symbol name unit page uf0cie114 uf0 configuration/interface/endp oint descriptor register 114 usbf 1298 uf0cie115 uf0 configuration/interface/endp oint descriptor register 115 usbf 1298 uf0cie116 uf0 configuration/interface/endp oint descriptor register 116 usbf 1298 uf0cie117 uf0 configuration/interface/endp oint descriptor register 117 usbf 1298 uf0cie118 uf0 configuration/interface/endp oint descriptor register 118 usbf 1298 uf0cie119 uf0 configuration/interface/endp oint descriptor register 119 usbf 1298 uf0cie12 uf0 configuration/interface/endp oint descriptor register 12 usbf 1298 uf0cie120 uf0 configuration/interface/endp oint descriptor register 120 usbf 1298 uf0cie121 uf0 configuration/interface/endp oint descriptor register 121 usbf 1298 uf0cie122 uf0 configuration/interface/endp oint descriptor register 122 usbf 1298 uf0cie123 uf0 configuration/interface/endp oint descriptor register 123 usbf 1298 uf0cie124 uf0 configuration/interface/endp oint descriptor register 124 usbf 1298 uf0cie125 uf0 configuration/interface/endp oint descriptor register 125 usbf 1298 uf0cie126 uf0 configuration/interface/endp oint descriptor register 126 usbf 1298 uf0cie127 uf0 configuration/interface/endp oint descriptor register 127 usbf 1298 uf0cie128 uf0 configuration/interface/endp oint descriptor register 128 usbf 1298 uf0cie129 uf0 configuration/interface/endp oint descriptor register 129 usbf 1298 uf0cie13 uf0 configuration/interface/endp oint descriptor register 13 usbf 1298 uf0cie130 uf0 configuration/interface/endp oint descriptor register 130 usbf 1298 uf0cie131 uf0 configuration/interface/endp oint descriptor register 131 usbf 1298 uf0cie132 uf0 configuration/interface/endp oint descriptor register 132 usbf 1298 uf0cie133 uf0 configuration/interface/endp oint descriptor register 133 usbf 1298 uf0cie134 uf0 configuration/interface/endp oint descriptor register 134 usbf 1298 uf0cie135 uf0 configuration/interface/endp oint descriptor register 135 usbf 1298 uf0cie136 uf0 configuration/interface/endp oint descriptor register 136 usbf 1298 uf0cie137 uf0 configuration/interface/endp oint descriptor register 137 usbf 1298 uf0cie138 uf0 configuration/interface/endp oint descriptor register 138 usbf 1298 uf0cie139 uf0 configuration/interface/endp oint descriptor register 139 usbf 1298 uf0cie14 uf0 configuration/interface/endp oint descriptor register 14 usbf 1298 uf0cie140 uf0 configuration/interface/endp oint descriptor register 140 usbf 1298 uf0cie141 uf0 configuration/interface/endp oint descriptor register 141 usbf 1298 uf0cie142 uf0 configuration/interface/endp oint descriptor register 142 usbf 1298 uf0cie143 uf0 configuration/interface/endp oint descriptor register 143 usbf 1298 uf0cie144 uf0 configuration/interface/endp oint descriptor register 144 usbf 1298 uf0cie145 uf0 configuration/interface/endp oint descriptor register 145 usbf 1298 uf0cie146 uf0 configuration/interface/endp oint descriptor register 146 usbf 1298 uf0cie147 uf0 configuration/interface/endp oint descriptor register 147 usbf 1298 uf0cie148 uf0 configuration/interface/endp oint descriptor register 148 usbf 1298 uf0cie149 uf0 configuration/interface/endp oint descriptor register 149 usbf 1298 uf0cie15 uf0 configuration/interface/endp oint descriptor register 15 usbf 1298 uf0cie150 uf0 configuration/interface/endp oint descriptor register 150 usbf 1298 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1797 of 1817 sep 19, 2011 (37/43) symbol name unit page uf0cie151 uf0 configuration/interface/endp oint descriptor register 151 usbf 1298 uf0cie152 uf0 configuration/interface/endp oint descriptor register 152 usbf 1298 uf0cie153 uf0 configuration/interface/endp oint descriptor register 153 usbf 1298 uf0cie154 uf0 configuration/interface/endp oint descriptor register 154 usbf 1298 uf0cie155 uf0 configuration/interface/endp oint descriptor register 155 usbf 1298 uf0cie156 uf0 configuration/interface/endp oint descriptor register 156 usbf 1298 uf0cie157 uf0 configuration/interface/endp oint descriptor register 157 usbf 1298 uf0cie158 uf0 configuration/interface/endp oint descriptor register 158 usbf 1298 uf0cie159 uf0 configuration/interface/endp oint descriptor register 159 usbf 1298 uf0cie16 uf0 configuration/interface/endp oint descriptor register 16 usbf 1298 uf0cie160 uf0 configuration/interface/endp oint descriptor register 160 usbf 1298 uf0cie161 uf0 configuration/interface/endp oint descriptor register 161 usbf 1298 uf0cie162 uf0 configuration/interface/endp oint descriptor register 162 usbf 1298 uf0cie163 uf0 configuration/interface/endp oint descriptor register 163 usbf 1298 uf0cie164 uf0 configuration/interface/endp oint descriptor register 164 usbf 1298 uf0cie165 uf0 configuration/interface/endp oint descriptor register 165 usbf 1298 uf0cie166 uf0 configuration/interface/endp oint descriptor register 166 usbf 1298 uf0cie167 uf0 configuration/interface/endp oint descriptor register 167 usbf 1298 uf0cie168 uf0 configuration/interface/endp oint descriptor register 168 usbf 1298 uf0cie169 uf0 configuration/interface/endp oint descriptor register 169 usbf 1298 uf0cie17 uf0 configuration/interface/endp oint descriptor register 17 usbf 1298 uf0cie170 uf0 configuration/interface/endp oint descriptor register 170 usbf 1298 uf0cie171 uf0 configuration/interface/endp oint descriptor register 171 usbf 1298 uf0cie172 uf0 configuration/interface/endp oint descriptor register 172 usbf 1298 uf0cie173 uf0 configuration/interface/endp oint descriptor register 173 usbf 1298 uf0cie174 uf0 configuration/interface/endp oint descriptor register 174 usbf 1298 uf0cie175 uf0 configuration/interface/endp oint descriptor register 175 usbf 1298 uf0cie176 uf0 configuration/interface/endp oint descriptor register 176 usbf 1298 uf0cie177 uf0 configuration/interface/endp oint descriptor register 177 usbf 1298 uf0cie178 uf0 configuration/interface/endp oint descriptor register 178 usbf 1298 uf0cie179 uf0 configuration/interface/endp oint descriptor register 179 usbf 1298 uf0cie18 uf0 configuration/interface/endp oint descriptor register 18 usbf 1298 uf0cie180 uf0 configuration/interface/endp oint descriptor register 180 usbf 1298 uf0cie181 uf0 configuration/interface/endp oint descriptor register 181 usbf 1298 uf0cie182 uf0 configuration/interface/endp oint descriptor register 182 usbf 1298 uf0cie183 uf0 configuration/interface/endp oint descriptor register 183 usbf 1298 uf0cie184 uf0 configuration/interface/endp oint descriptor register 184 usbf 1298 uf0cie185 uf0 configuration/interface/endp oint descriptor register 185 usbf 1298 uf0cie186 uf0 configuration/interface/endp oint descriptor register 186 usbf 1298 uf0cie187 uf0 configuration/interface/endp oint descriptor register 187 usbf 1298 uf0cie188 uf0 configuration/interface/endp oint descriptor register 188 usbf 1298 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1798 of 1817 sep 19, 2011 (38/43) symbol name unit page uf0cie189 uf0 configuration/interface/endp oint descriptor register 189 usbf 1298 uf0cie19 uf0 configuration/interface/endp oint descriptor register 19 usbf 1298 uf0cie190 uf0 configuration/interface/endp oint descriptor register 190 usbf 1298 uf0cie191 uf0 configuration/interface/endp oint descriptor register 191 usbf 1298 uf0cie192 uf0 configuration/interface/endp oint descriptor register 192 usbf 1298 uf0cie193 uf0 configuration/interface/endp oint descriptor register 193 usbf 1298 uf0cie194 uf0 configuration/interface/endp oint descriptor register 194 usbf 1298 uf0cie195 uf0 configuration/interface/endp oint descriptor register 195 usbf 1298 uf0cie196 uf0 configuration/interface/endp oint descriptor register 196 usbf 1298 uf0cie197 uf0 configuration/interface/endp oint descriptor register 197 usbf 1298 uf0cie198 uf0 configuration/interface/endp oint descriptor register 198 usbf 1298 uf0cie199 uf0 configuration/interface/endp oint descriptor register 199 usbf 1298 uf0cie2 uf0 configuration/interface/endp oint descriptor register 2 usbf 1298 uf0cie20 uf0 configuration/interface/endp oint descriptor register 20 usbf 1298 uf0cie200 uf0 configuration/interface/endp oint descriptor register 200 usbf 1298 uf0cie201 uf0 configuration/interface/endp oint descriptor register 201 usbf 1298 uf0cie202 uf0 configuration/interface/endp oint descriptor register 202 usbf 1298 uf0cie203 uf0 configuration/interface/endp oint descriptor register 203 usbf 1298 uf0cie204 uf0 configuration/interface/endp oint descriptor register 204 usbf 1298 uf0cie205 uf0 configuration/interface/endp oint descriptor register 205 usbf 1298 uf0cie206 uf0 configuration/interface/ endpoint descriptor register 206 usbf 1298 uf0cie207 uf0 configuration/interface/ endpoint descriptor register 207 usbf 1298 uf0cie208 uf0 configuration/interface/ endpoint descriptor register 208 usbf 1298 uf0cie209 uf0 configuration/interface/ endpoint descriptor register 209 usbf 1298 uf0cie210 uf0 configuration/interface/ endpoint descriptor register 210 usbf 1298 uf0cie211 uf0 configuration/interface/ endpoint descriptor register 211 usbf 1298 uf0cie212 uf0 configuration/interface/ endpoint descriptor register 212 usbf 1298 uf0cie213 uf0 configuration/interface/ endpoint descriptor register 213 usbf 1298 uf0cie214 uf0 configuration/interface/ endpoint descriptor register 214 usbf 1298 uf0cie215 uf0 configuration/interface/ endpoint descriptor register 215 usbf 1298 uf0cie216 uf0 configuration/interface/ endpoint descriptor register 216 usbf 1298 uf0cie217 uf0 configuration/interface/ endpoint descriptor register 217 usbf 1298 uf0cie218 uf0 configuration/interface/ endpoint descriptor register 218 usbf 1298 uf0cie219 uf0 configuration/interface/ endpoint descriptor register 219 usbf 1298 uf0cie220 uf0 configuration/interface/ endpoint descriptor register 220 usbf 1298 uf0cie221 uf0 configuration/interface/ endpoint descriptor register 221 usbf 1298 uf0cie222 uf0 configuration/interface/ endpoint descriptor register 222 usbf 1298 uf0cie223 uf0 configuration/interface/ endpoint descriptor register 223 usbf 1298 uf0cie224 uf0 configuration/interface/ endpoint descriptor register 224 usbf 1298 uf0cie225 uf0 configuration/interface/ endpoint descriptor register 225 usbf 1298 uf0cie226 uf0 configuration/interface/ endpoint descriptor register 226 usbf 1298 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1799 of 1817 sep 19, 2011 (39/43) symbol name unit page uf0cie227 uf0 configuration/interface/ endpoint descriptor register 227 usbf 1298 uf0cie228 uf0 configuration/interface/ endpoint descriptor register 228 usbf 1298 uf0cie229 uf0 configuration/interface/ endpoint descriptor register 229 usbf 1298 uf0cie230 uf0 configuration/interface/ endpoint descriptor register 230 usbf 1298 uf0cie231 uf0 configuration/interface/ endpoint descriptor register 231 usbf 1298 uf0cie232 uf0 configuration/interface/ endpoint descriptor register 232 usbf 1298 uf0cie233 uf0 configuration/interface/ endpoint descriptor register 233 usbf 1298 uf0cie234 uf0 configuration/interface/ endpoint descriptor register 234 usbf 1298 uf0cie235 uf0 configuration/interface/ endpoint descriptor register 235 usbf 1298 uf0cie236 uf0 configuration/interface/ endpoint descriptor register 236 usbf 1298 uf0cie237 uf0 configuration/interface/ endpoint descriptor register 237 usbf 1298 uf0cie238 uf0 configuration/interface/ endpoint descriptor register 238 usbf 1298 uf0cie239 uf0 configuration/interface/ endpoint descriptor register 239 usbf 1298 uf0cie240 uf0 configuration/interface/ endpoint descriptor register 240 usbf 1298 uf0cie241 uf0 configuration/interface/ endpoint descriptor register 241 usbf 1298 uf0cie242 uf0 configuration/interface/ endpoint descriptor register 242 usbf 1298 uf0cie243 uf0 configuration/interface/ endpoint descriptor register 243 usbf 1298 uf0cie244 uf0 configuration/interface/ endpoint descriptor register 244 usbf 1298 uf0cie245 uf0 configuration/interface/ endpoint descriptor register 245 usbf 1298 uf0cie246 uf0 configuration/interface/ endpoint descriptor register 246 usbf 1298 uf0cie247 uf0 configuration/interface/ endpoint descriptor register 247 usbf 1298 uf0cie248 uf0 configuration/interface/ endpoint descriptor register 248 usbf 1298 uf0cie249 uf0 configuration/interface/ endpoint descriptor register 249 usbf 1298 uf0cie250 uf0 configuration/interface/ endpoint descriptor register 250 usbf 1298 uf0cie251 uf0 configuration/interface/ endpoint descriptor register 251 usbf 1298 uf0cie252 uf0 configuration/interface/ endpoint descriptor register 252 usbf 1298 uf0cie253 uf0 configuration/interface/ endpoint descriptor register 253 usbf 1298 uf0cie254 uf0 configuration/interface/ endpoint descriptor register 254 usbf 1298 uf0cie255 uf0 configuration/interface/ endpoint descriptor register 255 usbf 1298 uf0cie26 uf0 configuration/interface/endp oint descriptor register 26 usbf 1298 uf0cie27 uf0 configuration/interface/endp oint descriptor register 27 usbf 1298 uf0cie28 uf0 configuration/interface/endp oint descriptor register 28 usbf 1298 uf0cie29 uf0 configuration/interface/endp oint descriptor register 29 usbf 1298 uf0cie3 uf0 configuration/interface/endp oint descriptor register 3 usbf 1298 uf0cie30 uf0 configuration/interface/endp oint descriptor register 30 usbf 1298 uf0cie31 uf0 configuration/interface/endp oint descriptor register 31 usbf 1298 uf0cie32 uf0 configuration/interface/endp oint descriptor register 32 usbf 1298 uf0cie33 uf0 configuration/interface/endp oint descriptor register 33 usbf 1298 uf0cie34 uf0 configuration/interface/endp oint descriptor register 34 usbf 1298 uf0cie35 uf0 configuration/interface/endp oint descriptor register 35 usbf 1298 uf0cie36 uf0 configuration/interface/endp oint descriptor register 36 usbf 1298 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1800 of 1817 sep 19, 2011 (40/43) symbol name unit page uf0cie37 uf0 configuration/interface/endp oint descriptor register 37 usbf 1298 uf0cie38 uf0 configuration/interface/endp oint descriptor register 38 usbf 1298 uf0cie39 uf0 configuration/interface/endp oint descriptor register 39 usbf 1298 uf0cie4 uf0 configuration/interface/endp oint descriptor register 4 usbf 1298 uf0cie40 uf0 configuration/interface/endp oint descriptor register 40 usbf 1298 uf0cie41 uf0 configuration/interface/endp oint descriptor register 41 usbf 1298 uf0cie42 uf0 configuration/interface/endp oint descriptor register 42 usbf 1298 uf0cie43 uf0 configuration/interface/endp oint descriptor register 43 usbf 1298 uf0cie44 uf0 configuration/interface/endp oint descriptor register 44 usbf 1298 uf0cie45 uf0 configuration/interface/endp oint descriptor register 45 usbf 1298 uf0cie46 uf0 configuration/interface/endp oint descriptor register 46 usbf 1298 uf0cie47 uf0 configuration/interface/endp oint descriptor register 47 usbf 1298 uf0cie48 uf0 configuration/interface/endp oint descriptor register 48 usbf 1298 uf0cie49 uf0 configuration/interface/endp oint descriptor register 49 usbf 1298 uf0cie5 uf0 configuration/interface/endp oint descriptor register 5 usbf 1298 uf0cie50 uf0 configuration/interface/endp oint descriptor register 50 usbf 1298 uf0cie51 uf0 configuration/interface/endp oint descriptor register 51 usbf 1298 uf0cie52 uf0 configuration/interface/endp oint descriptor register 52 usbf 1298 uf0cie53 uf0 configuration/interface/endp oint descriptor register 53 usbf 1298 uf0cie54 uf0 configuration/interface/endp oint descriptor register 54 usbf 1298 uf0cie55 uf0 configuration/interface/endp oint descriptor register 55 usbf 1298 uf0cie56 uf0 configuration/interface/endp oint descriptor register 56 usbf 1298 uf0cie57 uf0 configuration/interface/endp oint descriptor register 57 usbf 1298 uf0cie58 uf0 configuration/interface/endp oint descriptor register 58 usbf 1298 uf0cie59 uf0 configuration/interface/endp oint descriptor register 59 usbf 1298 uf0cie6 uf0 configuration/interface/endp oint descriptor register 6 usbf 1298 uf0cie60 uf0 configuration/interface/endp oint descriptor register 60 usbf 1298 uf0cie61 uf0 configuration/interface/endp oint descriptor register 61 usbf 1298 uf0cie62 uf0 configuration/interface/endp oint descriptor register 62 usbf 1298 uf0cie63 uf0 configuration/interface/endp oint descriptor register 63 usbf 1298 uf0cie64 uf0 configuration/interface/endp oint descriptor register 64 usbf 1298 uf0cie65 uf0 configuration/interface/endp oint descriptor register 65 usbf 1298 uf0cie66 uf0 configuration/interface/endp oint descriptor register 66 usbf 1298 uf0cie67 uf0 configuration/interface/endp oint descriptor register 67 usbf 1298 uf0cie68 uf0 configuration/interface/endp oint descriptor register 68 usbf 1298 uf0cie69 uf0 configuration/interface/endp oint descriptor register 69 usbf 1298 uf0cie7 uf0 configuration/interface/endp oint descriptor register 7 usbf 1298 uf0cie70 uf0 configuration/interface/endp oint descriptor register 70 usbf 1298 uf0cie71 uf0 configuration/interface/endp oint descriptor register 71 usbf 1298 uf0cie72 uf0 configuration/interface/endp oint descriptor register 72 usbf 1298 uf0cie73 uf0 configuration/interface/endp oint descriptor register 73 usbf 1298 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1801 of 1817 sep 19, 2011 (41/43) symbol name unit page uf0cie74 uf0 configuration/interface/endp oint descriptor register 74 usbf 1298 uf0cie75 uf0 configuration/interface/endp oint descriptor register 75 usbf 1298 uf0cie76 uf0 configuration/interface/endp oint descriptor register 76 usbf 1298 uf0cie77 uf0 configuration/interface/endp oint descriptor register 77 usbf 1298 uf0cie78 uf0 configuration/interface/endp oint descriptor register 78 usbf 1298 uf0cie79 uf0 configuration/interface/endp oint descriptor register 79 usbf 1298 uf0cie8 uf0 configuration/interface/endp oint descriptor register 8 usbf 1298 uf0cie80 uf0 configuration/interface/endp oint descriptor register 80 usbf 1298 uf0cie81 uf0 configuration/interface/endp oint descriptor register 81 usbf 1298 uf0cie82 uf0 configuration/interface/endp oint descriptor register 82 usbf 1298 uf0cie83 uf0 configuration/interface/endp oint descriptor register 83 usbf 1298 uf0cie84 uf0 configuration/interface/endp oint descriptor register 84 usbf 1298 uf0cie85 uf0 configuration/interface/endp oint descriptor register 85 usbf 1298 uf0cie86 uf0 configuration/interface/endp oint descriptor register 86 usbf 1298 uf0cie87 uf0 configuration/interface/endp oint descriptor register 87 usbf 1298 uf0cie88 uf0 configuration/interface/endp oint descriptor register 88 usbf 1298 uf0cie89 uf0 configuration/interface/endp oint descriptor register 89 usbf 1298 uf0cie9 uf0 configuration/interface/endp oint descriptor register 9 usbf 1298 uf0cie90 uf0 configuration/interface/endp oint descriptor register 90 usbf 1298 uf0cie91 uf0 configuration/interface/endp oint descriptor register 91 usbf 1298 uf0cie92 uf0 configuration/interface/endp oint descriptor register 92 usbf 1298 uf0cie93 uf0 configuration/interface/endp oint descriptor register 93 usbf 1298 uf0cie94 uf0 configuration/interface/endp oint descriptor register 94 usbf 1298 uf0cie95 uf0 configuration/interface/endp oint descriptor register 95 usbf 1298 uf0cie96 uf0 configuration/interface/endp oint descriptor register 96 usbf 1298 uf0cie97 uf0 configuration/interface/endp oint descriptor register 97 usbf 1298 uf0cie98 uf0 configuration/interface/endp oint descriptor register 98 usbf 1298 uf0cie99 uf0 configuration/interface/endp oint descriptor register 99 usbf 1298 uf0clr uf0 clr request register usbf 1219 uf0cnf uf0 configuration register usbf 1293 uf0dd0 uf0 device descriptor register 0 usbf 1297 uf0dd1 uf0 device descriptor register 1 usbf 1297 uf0dd10 uf0 device descriptor register 10 usbf 1297 uf0dd11 uf0 device descriptor register 11 usbf 1297 uf0dd12 uf0 device descriptor register 12 usbf 1297 uf0dd13 uf0 device descriptor register 13 usbf 1297 uf0dd14 uf0 device descriptor register 14 usbf 1297 uf0dd15 uf0 device descriptor register 15 usbf 1297 uf0dd16 uf0 device descriptor register 16 usbf 1297 uf0dd17 uf0 device descriptor register 17 usbf 1297 uf0dd2 uf0 device descriptor register 2 usbf 1297 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1802 of 1817 sep 19, 2011 (42/43) symbol name unit page uf0dd3 uf0 device descriptor register 3 usbf 1297 uf0dd4 uf0 device descriptor register 4 usbf 1297 uf0dd5 uf0 device descriptor register 5 usbf 1297 uf0dd6 uf0 device descriptor register 6 usbf 1297 uf0dd7 uf0 device descriptor register 7 usbf 1297 uf0dd8 uf0 device descriptor register 8 usbf 1297 uf0dd9 uf0 device descriptor register 9 usbf 1297 uf0dend uf0 data end register usbf 1249 uf0dms0 uf0 dma status 0 register usbf 1245 uf0dms1 uf0 dma status 1 register usbf 1246 uf0dscl uf0 descriptor length register usbf 1296 uf0dstl uf0 device status register l usbf 1285 uf0e0l uf0 ep0 length register usbf 1263 uf0e0n uf0 ep0nak register usbf 1210 uf0e0na uf0 ep0nakall register usbf 1212 uf0e0r uf0 ep0 read register usbf 1262 uf0e0sl uf0 ep0 status register l usbf 1286 uf0e0st uf0 ep0 setup register usbf 1264 uf0e0w uf0 ep0 write register usbf 1266 uf0e1dc1 ep1 dma control register 1 usbf 1304 uf0e1dc2 ep1 dma control register 2 usbf 1306 uf0e1im uf0 endpoint 1 interface mapping register usbf 1257 uf0e1sl uf0 ep1 status register l usbf 1287 uf0e2dc1 ep2 dma control register 1 usbf 1304 uf0e2dc2 ep2 dma control register 2 usbf 1306 uf0e2im uf0 endpoint 2 interface mapping register usbf 1258 uf0e2sl uf0 ep2 status register l usbf 1288 uf0e3dc1 ep3 dma control register 1 usbf 1304 uf0e3dc2 ep3 dma control register 2 usbf 1306 uf0e3im uf0 endpoint 3 interface mapping register usbf 1259 uf0e3sl uf0 ep3 status register l usbf 1289 uf0e4dc1 ep4 dma control register 1 usbf 1304 uf0e4dc2 ep4 dma control register 2 usbf 1306 uf0e4im uf0 endpoint 4 interface mapping register usbf 1260 uf0e4sl uf0 ep4 status register l usbf 1290 uf0e7im uf0 endpoint 7 interface mapping register usbf 1261 uf0e7sl uf0 ep7 status register l usbf 1291 uf0en uf0 epnak register usbf 1213 uf0enm uf0 epnak mask register usbf 1217 uf0eps0 uf0 ep status 0 register usbf 1221 uf0eps1 uf0 ep status 1 register usbf 1223 v850es/jh3-e, v850es/jj3-e appendix c register index r01uh0290ej0300 rev.3.00 page 1803 of 1817 sep 19, 2011 (43/43) symbol name unit page uf0eps2 uf0 ep status 2 register usbf 1224 uf0fic0 uf0 fifo clear 0 register usbf 1247 uf0fic1 uf0 fifo clear 1 register usbf 1248 uf0gpr uf0 gpr register usbf 1251 uf0ic0 uf0 int clear 0 register usbf 1238 uf0ic1 uf0 int clear 1 register usbf 1239 uf0ic2 uf0 int clear 2 register usbf 1240 uf0ic3 uf0 int clear 3 register usbf 1241 uf0ic4 uf0 int clear 4 register usbf 1242 uf0idr uf0 int & dmarq register usbf 1243 uf0if0 uf0 interface 0 register usbf 1294 uf0if1 uf0 interface 1 register usbf 1295 uf0if2 uf0 interface 2 register usbf 1295 uf0if3 uf0 interface 3 register usbf 1295 uf0if4 uf0 interface 4 register usbf 1295 uf0im0 uf0 int mask 0 register usbf 1233 uf0im1 uf0 int mask 1 register usbf 1234 uf0im2 uf0 int mask 2 register usbf 1235 uf0im3 uf0 int mask 3 register usbf 1236 uf0im4 uf0 int mask 4 register usbf 1237 uf0int1 uf0 interrupt 1 register usbf 1283 uf0is0 uf0 int status 0 register usbf 1225 uf0is1 uf0 int status 1 register usbf 1227 uf0is2 uf0 int status 2 register usbf 1229 uf0is3 uf0 int status 3 register usbf 1230 uf0is4 uf0 int status 4 register usbf 1232 uf0modc uf0 mode control register usbf 1252 uf0mods uf0 mode status register usbf 1253 uf0sds uf0 sndsie register usbf 128 uf0set uf0 set request register usbf 1220 ufckmsk usb function control register usbf 1193 ufdrqen usbf dma request enable register usbf 1308 ufic0 interrupt control register intc 1577 ufic1 interrupt control register intc 1577 vltp vlan type register ethernet 1382 vswc system wait control register cpu 104 wdte watchdog timer enable register wdt 690 wdtm2 watchdog timer mode register 2 wdt 104 wupic0 interrupt control register intc 1577 v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1804 of 1817 sep 19, 2011 appendix d instruction set list d.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the re mainders of division result s and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1805 of 1817 sep 19, 2011 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency). v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1806 of 1817 sep 19, 2011 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition code (cccc) condition formula explanation 0 0 0 0 ov = 1 overflow 1 0 0 0 ov = 0 no overflow 0 0 0 1 cy = 1 carry lower (less than) 1 0 0 1 cy = 0 no carry not lower (greater than or equal) 0 0 1 0 z = 1 zero 1 0 1 0 z = 0 not zero 0 0 1 1 (cy or z) = 1 not higher (less than or equal) 1 0 1 1 (cy or z) = 0 higher (greater than) 0 1 0 0 s = 1 negative 1 1 0 0 s = 0 positive 0 1 0 1 ? always (unconditional) 1 1 0 1 sat = 1 saturated 0 1 1 0 (s xor ov) = 1 less than signed 1 1 1 0 (s xor ov) = 0 greater than or equal signed 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed 1 1 1 1 ((s xor ov) or z) = 0 greater than signed v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1807 of 1817 sep 19, 2011 d.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 r r r r r 0 1 0 010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 4 4 4 bit#3,disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 r r r r r 1 1 1 111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 r r r r r 0 1 0 011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 3 3 3 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 3 3 3 r r r r r v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1808 of 1817 sep 19, 2011 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 3 3 3 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 2 2 2 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11 v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1809 of 1817 sep 19, 2011 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 r r r r r 0 1 0 000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 r r r r r 0 1 0 111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] note 14 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3 v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1810 of 1817 sep 19, 2011 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) sp sp+4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend (imm5) ep sp/imm n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 3 3 3 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1811 of 1817 sep 19, 2011 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1812 of 1817 sep 19, 2011 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 3 3 3 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (accordi ng to the number of wait stat es. also, if there are no wait states, n is the total number of list12 regist ers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states). v850es/jh3-e, v850es/jj3-e appendix d instruction set list r01uh0290ej0300 rev.3.00 page 1813 of 1817 sep 19, 2011 notes 12. in this instruction, for convenience of mnemonic descrip tion, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. do not specify the same register fo r general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign-expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically-left-shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. v850es/jh3-e, v850es/jj3-e appen dix e revision history r01uh0290ej0300 rev.3.00 page 1814 of 1817 sep 19, 2011 appendix e revision history e.1 major revisions in this edition page description pp.39, 40 addition of 2.1 (1) port pins pp.42 to 50 addition of 2.1 (2) non-port pins p.853 modification of 18.4 (3) csien control register 2 (cenctl2) p.1535 addition of caution 2 to 24.3 (6) dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) p.1663 modification of figure 33-5. communication with dedicated flash programmer (csif0 + hs, csif3 + hs) p.1664 modification of table 33-5. signal connections of dedicated flash programmer (pg-fp5) e.2 revision history of preceding editions edition description chapter addition of note 2 to 5.5.1(1) data wait control register 0 (dwc0) addition of note 2 to 5.5.4(1) address wait control register (awc) addition of note 2 to 5.6(1) bus cycle control register (bcc) chapter 5 bus control function addition of caution 2 to chapter 21 can controler chapter 21 can controler addition of caution to 22.1 overview modification of figure 22-3. example of usb function controller connection modification of 22.4 (2) stopping the usb clock modification of 22.6.1 (2) usb function control register (ufckmsk) addition of caution 2 to 22.9.6 data reception of a bulk transfer by dma mode addition of 22.9.6 (1) initial settings for a bulk transfer (out: ep2, ep4) addition of figure 22-32. dma processing by bulk transfer (out) addition of 22.9.7 (1) initial settings for a bulk transfer (in: ep1, ep3) chapter 22 usb functin controler (usbf) modification of chapter 23 ethernet controler chapter 23 ethernet controler addition of 33.6 creating rom code to place order for previously written product chapter 33 flash memory addition of chapter 35 electrical specifications chapter 35 electrical specifications 2nd addition of chapter 37 recommended soldering conditions chapter 37 recommended soldering conditions v850es/jh3-e, v850es/jj3-e user?s manual: hardware publication date: rev.3.00 sep 19, 2011 published by: renesas electronics corporation http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.1 v850es/jh3-e, v850es/jj3-e r01uh0290ej0300 |
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